220 lines
14 KiB
C
220 lines
14 KiB
C
/*!
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\file gd32f3x0_cmp.h
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\brief definitions for the CMP
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\version 2017-06-06, V1.0.0, firmware for GD32F3x0
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\version 2019-06-01, V2.0.0, firmware for GD32F3x0
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F3X0_CMP_H
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#define GD32F3X0_CMP_H
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#include "gd32f3x0.h"
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/* CMP definitions */
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#define CMP CMP_BASE /*!< CMP base address */
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/* registers definitions */
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#define CMP_CS REG32((CMP) + 0x00000000U) /*!< CMP control and status register */
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/* CMP_CS bits definitions */
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#define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */
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#define CMP_CS_CMP0SW BIT(1) /*!< CMP0 switch */
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#define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */
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#define CMP_CS_CMP0MSEL BITS(4,6) /*!< COMP0_M input selection */
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#define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */
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#define CMP_CS_CMP0PL BIT(11) /*!< polarity of CMP0 output */
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#define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */
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#define CMP_CS_CMP0O BIT(14) /*!< CMP0 output */
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#define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */
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#define CMP_CS_CMP1EN BIT(16) /*!< CMP1 enable */
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#define CMP_CS_CMP1M BITS(18,19) /*!< CMP1 mode */
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#define CMP_CS_CMP1MSEL BITS(20,22) /*!< CMP1_M input selection */
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#define CMP_CS_WNDEN BIT(23) /*!< window mode enable */
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#define CMP_CS_CMP1OSEL BITS(24,26) /*!< CMP1 output selection */
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#define CMP_CS_CMP1PL BIT(27) /*!< polarity of CMP1 output */
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#define CMP_CS_CMP1HST BITS(28,29) /*!< CMP1 hysteresis */
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#define CMP_CS_CMP1O BIT(30) /*!< CMP1 output */
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#define CMP_CS_CMP1LK BIT(31) /*!< CMP1 lock */
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/* consts definitions */
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/* operating mode */
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typedef enum{
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CMP_HIGHSPEED = 0, /*!< high speed mode */
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CMP_MIDDLESPEED, /*!< medium speed mode */
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CMP_LOWSPEED, /*!< low speed mode */
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CMP_VERYLOWSPEED /*!< very-low speed mode */
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}operating_mode_enum;
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/* inverting input */
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typedef enum{
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CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */
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CMP_1_2VREFINT, /*!< VREFINT /2 input */
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CMP_3_4VREFINT, /*!< VREFINT *3/4 input */
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CMP_VREFINT, /*!< VREFINT input */
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CMP_DAC, /*!< PA4 (DAC) input */
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CMP_PA5, /*!< PA5 input */
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CMP_PA_0_2 /*!< PA0 or PA2 input */
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}inverting_input_enum;
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/* hysteresis */
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typedef enum{
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CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */
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CMP_HYSTERESIS_LOW, /*!< output low hysteresis */
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CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */
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CMP_HYSTERESIS_HIGH /*!< output high hysteresis */
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}cmp_hysteresis_enum;
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/* output */
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typedef enum{
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CMP_OUTPUT_NONE = 0, /*!< output no selection */
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CMP_OUTPUT_TIMER0BKIN, /*!< TIMER 0 break input */
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CMP_OUTPUT_TIMER0IC0, /*!< TIMER 0 channel0 input capture */
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CMP_OUTPUT_TIMER0OCPRECLR, /*!< TIMER 0 OCPRE_CLR input */
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CMP_OUTPUT_TIMER1IC3, /*!< TIMER 1 channel3 input capture */
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CMP_OUTPUT_TIMER1OCPRECLR, /*!< TIMER 1 OCPRE_CLR input */
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CMP_OUTPUT_TIMER2IC0, /*!< TIMER 2 channel0 input capture */
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CMP_OUTPUT_TIMER2OCPRECLR /*!< TIMER 2 OCPRE_CLR input */
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}cmp_output_enum;
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/* CMP0 mode */
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#define CS_CMP0M(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
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#define CS_CMP0M_HIGHSPEED CS_CMP0M(0) /*!< CMP0 mode high speed */
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#define CS_CMP0M_MIDDLESPEED CS_CMP0M(1) /*!< CMP0 mode middle speed */
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#define CS_CMP0M_LOWSPEED CS_CMP0M(2) /*!< CMP0 mode low speed */
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#define CS_CMP0M_VERYLOWSPEED CS_CMP0M(3) /*!< CMP0 mode very low speed */
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/* comparator 0 inverting input */
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#define CS_CMP0MSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
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#define CS_CMP0MSEL_1_4VREFINT CS_CMP0MSEL(0) /*!< CMP0 inverting input 1/4 Vrefint */
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#define CS_CMP0MSEL_1_2VREFINT CS_CMP0MSEL(1) /*!< CMP0 inverting input 1/2 Vrefint */
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#define CS_CMP0MSEL_3_4VREFINT CS_CMP0MSEL(2) /*!< CMP0 inverting input 3/4 Vrefint */
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#define CS_CMP0MSEL_VREFINT CS_CMP0MSEL(3) /*!< CMP0 inverting input Vrefint */
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#define CS_CMP0MSEL_DAC CS_CMP0MSEL(4) /*!< CMP0 inverting input DAC*/
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#define CS_CMP0MSEL_PA5 CS_CMP0MSEL(5) /*!< CMP0 inverting input PA5*/
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#define CS_CMP0MSEL_PA0 CS_CMP0MSEL(6) /*!< CMP0 inverting input PA0*/
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/* CMP0 output */
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#define CS_CMP0OSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
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#define CS_CMP0OSEL_OUTPUT_NONE CS_CMP0OSEL(0) /*!< CMP0 output none */
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#define CS_CMP0OSEL_OUTPUT_TIMER0BKIN CS_CMP0OSEL(1) /*!< CMP0 output TIMER 0 break input */
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#define CS_CMP0OSEL_OUTPUT_TIMER0IC0 CS_CMP0OSEL(2) /*!< CMP0 output TIMER 0 channel 0 input capture */
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#define CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP0OSEL(3) /*!< CMP0 output TIMER 0 ocpreclear input */
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#define CS_CMP0OSEL_OUTPUT_TIMER1IC3 CS_CMP0OSEL(4) /*!< CMP0 output TIMER 1 channel 3 input capture */
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#define CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP0OSEL(5) /*!< CMP0 output TIMER 1 ocpreclear input */
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#define CS_CMP0OSEL_OUTPUT_TIMER2IC0 CS_CMP0OSEL(6) /*!< CMP0 output TIMER 2 channle 0 input capture */
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#define CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP0OSEL(7) /*!< CMP0 output TIMER 2 ocpreclear input */
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/* CMP0 hysteresis */
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#define CS_CMP0HST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
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#define CS_CMP0HST_HYSTERESIS_NO CS_CMP0HST(0) /*!< CMP0 output no hysteresis */
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#define CS_CMP0HST_HYSTERESIS_LOW CS_CMP0HST(1) /*!< CMP0 output low hysteresis */
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#define CS_CMP0HST_HYSTERESIS_MIDDLE CS_CMP0HST(2) /*!< CMP0 output middle hysteresis */
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#define CS_CMP0HST_HYSTERESIS_HIGH CS_CMP0HST(3) /*!< CMP0 output high hysteresis */
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/* CMP1 mode */
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#define CS_CMP1M(regval) (BITS(18,19) & ((uint32_t)(regval) << 18))
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#define CS_CMP1M_HIGHSPEED CS_CMP1M(0) /*!< CMP1 mode high speed */
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#define CS_CMP1M_MIDDLESPEED CS_CMP1M(1) /*!< CMP1 mode middle speed */
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#define CS_CMP1M_LOWSPEED CS_CMP1M(2) /*!< CMP1 mode low speed */
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#define CS_CMP1M_VERYLOWSPEED CS_CMP1M(3) /*!< CMP1 mode very low speed */
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/* CMP1 inverting input */
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#define CS_CMP1MSEL(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
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#define CS_CMP1MSEL_1_4VREFINT CS_CMP1MSEL(0) /*!< CMP1 inverting input 1/4 Vrefint */
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#define CS_CMP1MSEL_1_2VREFINT CS_CMP1MSEL(1) /*!< CMP1 inverting input 1/2 Vrefint */
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#define CS_CMP1MSEL_3_4VREFINT CS_CMP1MSEL(2) /*!< CMP1 inverting input 3/4 Vrefint */
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#define CS_CMP1MSEL_VREFINT CS_CMP1MSEL(3) /*!< CMP1 inverting input Vrefint */
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#define CS_CMP1MSEL_DAC CS_CMP1MSEL(4) /*!< CMP1 inverting input DAC */
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#define CS_CMP1MSEL_PA5 CS_CMP1MSEL(5) /*!< CMP1 inverting input PA5 */
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#define CS_CMP1MSEL_PA2 CS_CMP1MSEL(6) /*!< CMP1 inverting input PA2 */
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/* CMP1 output */
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#define CS_CMP1OSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
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#define CS_CMP1OSEL_OUTPUT_NONE CS_CMP1OSEL(0) /*!< CMP1 output none */
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#define CS_CMP1OSEL_OUTPUT_TIMER0BKIN CS_CMP1OSEL(1) /*!< CMP1 output TIMER 0 break input */
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#define CS_CMP1OSEL_OUTPUT_TIMER0IC0 CS_CMP1OSEL(2) /*!< CMP1 output TIMER 0 channel 0 input capture */
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#define CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP1OSEL(3) /*!< CMP1 output TIMER 0 ocpreclear input */
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#define CS_CMP1OSEL_OUTPUT_TIMER1IC3 CS_CMP1OSEL(4) /*!< CMP1 output TIMER 1 channel 3 input capture */
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#define CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP1OSEL(5) /*!< CMP1 output TIMER 1 ocpreclear input */
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#define CS_CMP1OSEL_OUTPUT_TIMER2IC0 CS_CMP1OSEL(6) /*!< CMP1 output TIMER 2 channle 0 input capture */
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#define CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP1OSEL(7) /*!< CMP1 output TIMER 2 ocpreclear input */
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/* CMP1 hysteresis */
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#define CS_CMP1HST(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
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#define CS_CMP1HST_HSTHYSTERESIS_NO CS_CMP1HST(0) /*!< CMP1 output no hysteresis */
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#define CS_CMP1HST_HYSTERESIS_LOW CS_CMP1HST(1) /*!< CMP1 output low hysteresis */
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#define CS_CMP1HST_HYSTERESIS_MIDDLE CS_CMP1HST(2) /*!< CMP1 output middle hysteresis */
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#define CS_CMP1HST_HYSTERESIS_HIGH CS_CMP1HST(3) /*!< CMP1 output high hysteresis */
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/* comparator x definitions */
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#define CMP0 ((uint32_t)0x00000000) /*!< comparator 0 */
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#define CMP1 ((uint32_t)0x00000010) /*!< comparator 1 */
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/* comparator output level */
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#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) /*!< comparator output high */
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#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< comparator output low */
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/* output polarity of comparator */
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#define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001) /*!< output is inverted */
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#define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000) /*!< output is not inverted */
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/* function declarations */
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/* initialization functions */
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/* CMP deinit */
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void cmp_deinit(void);
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/* CMP mode init */
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void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis);
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/* CMP output init */
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void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity);
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/* enable functions */
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/* enable CMP */
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void cmp_enable(uint32_t cmp_periph);
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/* disable CMP */
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void cmp_disable(uint32_t cmp_periph);
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/* enable CMP switch */
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void cmp_switch_enable(void);
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/* disable CMP switch */
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void cmp_switch_disable(void);
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/* enable the window mode */
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void cmp_window_enable(void);
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/* disable the window mode */
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void cmp_window_disable(void);
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/* lock the CMP */
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void cmp_lock_enable(uint32_t cmp_periph);
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/* output functions */
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/* get output level */
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uint32_t cmp_output_level_get(uint32_t cmp_periph);
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#endif /* GD32F3X0_CMP_H */
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