1ef2afbc93
Rewrote the spi driver. Reuse the driver code from https://github.com/sophgo/cvi_alios_open, which is Apache 2.0 licenced. Signed-off-by: flyingcys <flyingcys@163.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
247 lines
8.0 KiB
C
247 lines
8.0 KiB
C
/*
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* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __DW_SPI_HEADER_H__
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#define __DW_SPI_HEADER_H__
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#include "stdint.h"
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#include "stdbool.h"
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#define SPI_REGBASE 0x04180000
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#define SPI_REF_CLK 187500000
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#define MAX_SPI_NUM 4
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#define CVI_DW_SPI_CTRLR0 0x00
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#define CVI_DW_SPI_CTRLR1 0x04
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#define CVI_DW_SPI_SSIENR 0x08
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#define CVI_DW_SPI_MWCR 0x0c
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#define CVI_DW_SPI_SER 0x10
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#define CVI_DW_SPI_BAUDR 0x14
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#define CVI_DW_SPI_TXFTLR 0x18
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#define CVI_DW_SPI_RXFTLR 0x1c
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#define CVI_DW_SPI_TXFLR 0x20
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#define CVI_DW_SPI_RXFLR 0x24
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#define CVI_DW_SPI_SR 0x28
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#define CVI_DW_SPI_IMR 0x2c
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#define CVI_DW_SPI_ISR 0x30
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#define CVI_DW_SPI_RISR 0x34
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#define CVI_DW_SPI_TXOICR 0x38
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#define CVI_DW_SPI_RXOICR 0x3c
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#define CVI_DW_SPI_RXUICR 0x40
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#define CVI_DW_SPI_MSTICR 0x44
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#define CVI_DW_SPI_ICR 0x48
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#define CVI_DW_SPI_DMACR 0x4c
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#define CVI_DW_SPI_DMATDLR 0x50
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#define CVI_DW_SPI_DMARDLR 0x54
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#define CVI_DW_SPI_IDR 0x58
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#define CVI_DW_SPI_VERSION 0x5c
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#define CVI_DW_SPI_DR 0x60
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/* Bit fields in CTRLR0 */
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#define CVI_SPI_DFS_OFFSET 0
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#define CVI_SPI_FRF_OFFSET 4
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#define CVI_SPI_FRF_SPI 0x0
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#define CVI_SPI_FRF_SSP 0x1
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#define CVI_SPI_FRF_MICROWIRE 0x2
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#define CVI_SPI_FRF_RESV 0x3
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#define CVI_SPI_MODE_OFFSET 6
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#define CVI_SPI_SCPH_OFFSET 6
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#define CVI_SPI_SCOL_OFFSET 7
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#define CVI_SPI_TMOD_OFFSET 8
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#define CVI_SPI_TMOD_MASK (0x3 << CVI_SPI_TMOD_OFFSET)
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#define CVI_SPI_TMOD_TR 0x0 /* xmit & recv */
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#define CVI_SPI_TMOD_TO 0x1 /* xmit only */
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#define CVI_SPI_TMOD_RO 0x2 /* recv only */
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#define CVI_SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
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#define CVI_SPI_SLVOE_OFFSET 10
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#define CVI_SPI_SRL_OFFSET 11
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#define CVI_SPI_CFS_OFFSET 12
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/* Bit fields in SR, 7 bits */
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#define CVI_SR_MASK 0x7f
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#define CVI_SR_BUSY (1 << 0)
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#define CVI_SR_TF_NOT_FULL (1 << 1)
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#define CVI_SR_TF_EMPT (1 << 2)
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#define CVI_SR_RF_NOT_EMPT (1 << 3)
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#define CVI_SR_RF_FULL (1 << 4)
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#define CVI_SR_TX_ERR (1 << 5)
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#define SR_DCOL (1 << 6)
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/* Bit fields in ISR, IMR, RISR, 7 bits */
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#define CVI_SPI_INT_TXEI (1 << 0)
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#define CVI_SPI_INT_TXOI (1 << 1)
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#define CVI_SPI_INT_RXUI (1 << 2)
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#define CVI_SPI_INT_RXOI (1 << 3)
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#define CVI_SPI_INT_RXFI (1 << 4)
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#define CVI_SPI_INT_MSTI (1 << 5)
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/* Bit fields in DMACR */
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#define CVI_SPI_DMA_RDMAE (1 << 0)
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#define CVI_SPI_DMA_TDMAE (1 << 1)
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/* TX RX interrupt level threshold, max can be 256 */
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#define CVI_SPI_INT_THRESHOLD 32
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#define BITS_PER_BYTE 8
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#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
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struct dw_spi {
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void *regs;
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int irq;
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int index;
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uint32_t fifo_len; /* depth of the FIFO buffer */
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uint16_t num_cs; /* supported slave numbers */
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uint32_t speed_hz;
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/* Current message transfer state info */
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size_t len;
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const void *tx;
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const void *tx_end;
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void *rx;
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void *rx_end;
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uint32_t rx_len;
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uint32_t tx_len;
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uint8_t n_bytes; /* current is a 1/2 bytes op */
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uint32_t dma_width;
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int (*transfer_handler)(struct dw_spi *dws);
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/* Bus interface info */
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void *priv;
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};
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struct spi_delay {
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#define SPI_DELAY_UNIT_USECS 0
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#define SPI_DELAY_UNIT_NSECS 1
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#define SPI_DELAY_UNIT_SCK 2
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uint16_t value;
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uint8_t unit;
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};
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#define SPI_CPHA 0x01
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#define SPI_CPOL 0x02
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#define SPI_MODE_0 (0|0)
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#define SPI_MODE_1 (0|SPI_CPHA)
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#define SPI_MODE_2 (SPI_CPOL|0)
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#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
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enum transfer_type {
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POLL_TRAN = 0,
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IRQ_TRAN,
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DMA_TRAN,
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};
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enum dw_ssi_type {
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SSI_MOTO_SPI = 0,
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SSI_TI_SSP,
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SSI_NS_MICROWIRE,
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};
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#define SPI_FORMAT_CPOL0_CPHA0 0
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#define SPI_FORMAT_CPOL0_CPHA1 1
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#define SPI_FORMAT_CPOL1_CPHA0 2
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#define SPI_FORMAT_CPOL1_CPHA1 3
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#ifndef BIT
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#define BIT(_n) ( 1 << (_n))
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#endif
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static void dw_writel(struct dw_spi *dws, uint32_t off, uint32_t val)
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{
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writel(val, (dws->regs + off));
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}
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static uint32_t dw_readl(struct dw_spi *dws, uint32_t off)
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{
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return readl(dws->regs + off);
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}
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static inline void spi_enable_chip(struct dw_spi *dws, int enable)
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{
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dw_writel(dws, CVI_DW_SPI_SSIENR, (enable ? 1 : 0));
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}
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static inline void spi_set_clk(struct dw_spi *dws, uint16_t div)
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{
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dw_writel(dws, CVI_DW_SPI_BAUDR, div);
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}
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/* Disable IRQ bits */
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static inline void spi_mask_intr(struct dw_spi *dws, uint32_t mask)
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{
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uint32_t new_mask;
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new_mask = dw_readl(dws, CVI_DW_SPI_IMR) & ~mask;
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dw_writel(dws, CVI_DW_SPI_IMR, new_mask);
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}
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static inline uint32_t spi_get_status(struct dw_spi *dws)
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{
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return dw_readl(dws, CVI_DW_SPI_SR);
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}
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/* Enable IRQ bits */
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static inline void spi_umask_intr(struct dw_spi *dws, uint32_t mask)
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{
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uint32_t new_mask;
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new_mask = dw_readl(dws, CVI_DW_SPI_IMR) | mask;
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dw_writel(dws, CVI_DW_SPI_IMR, new_mask);
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}
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static inline void spi_reset_chip(struct dw_spi *dws)
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{
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spi_enable_chip(dws, 0);
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spi_mask_intr(dws, 0xff);
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dw_readl(dws, CVI_DW_SPI_ICR);
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dw_writel(dws, CVI_DW_SPI_SER, 0);
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spi_enable_chip(dws, 1);
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}
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static inline void spi_enable_dma(struct dw_spi *dws, uint8_t is_tx, uint8_t op)
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{
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/* 1: TDMAE, 0: RDMAE */
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uint32_t val = dw_readl(dws, CVI_DW_SPI_DMACR);
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if (op)
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val |= 1 << (!!is_tx);
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else
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val &= ~(1 << (!!is_tx));
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dw_writel(dws, CVI_DW_SPI_DMACR, val);
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}
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static inline void spi_shutdown_chip(struct dw_spi *dws)
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{
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spi_enable_chip(dws, 0);
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spi_set_clk(dws, 0);
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}
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void spi_hw_init(struct dw_spi *dws);
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void dw_spi_set_controller_mode(struct dw_spi *dws, uint8_t enable_master);
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void dw_spi_set_polarity_and_phase(struct dw_spi *dws, uint8_t format);
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uint32_t dw_spi_set_clock(struct dw_spi *dws, uint32_t clock_in, uint32_t clock_out);
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int dw_spi_set_data_frame_len(struct dw_spi *dws, uint32_t size);
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void dw_spi_set_cs(struct dw_spi *dws, bool enable, uint32_t index);
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void dw_reader(struct dw_spi *dws);
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void dw_writer(struct dw_spi *dws);
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void set_tran_mode(struct dw_spi *dws);
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void dw_spi_show_regs(struct dw_spi *dws);
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int poll_transfer(struct dw_spi *dws);
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int dw_spi_check_status(struct dw_spi *dws, bool raw);
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#endif
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