108 lines
5.1 KiB
C
108 lines
5.1 KiB
C
/*
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* @brief Serial GPIO registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __SGPIO_001_H_
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#define __SGPIO_001_H_
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#include "sys_config.h"
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup IP_SGPIO_001 IP: SGPIO register block and driver
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* @ingroup IP_Drivers
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* Serial GPIO
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* @{
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*/
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/**
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* @brief Serial GPIO register block structure
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*/
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typedef struct { /*!< SGPIO Structure */
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__IO uint32_t OUT_MUX_CFG[16]; /*!< Pin multiplexer configurationregisters. */
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__IO uint32_t SGPIO_MUX_CFG[16]; /*!< SGPIO multiplexer configuration registers. */
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__IO uint32_t SLICE_MUX_CFG[16]; /*!< Slice multiplexer configuration registers. */
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__IO uint32_t REG[16]; /*!< Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
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__IO uint32_t REG_SS[16]; /*!< Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
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__IO uint32_t PRESET[16]; /*!< Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
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__IO uint32_t COUNT[16]; /*!< Down counter, counts down each clock cycle. */
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__IO uint32_t POS[16]; /*!< Each time COUNT0 reaches 0x0 */
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__IO uint32_t MASK_A; /*!< Mask for pattern match function of slice A */
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__IO uint32_t MASK_H; /*!< Mask for pattern match function of slice H */
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__IO uint32_t MASK_I; /*!< Mask for pattern match function of slice I */
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__IO uint32_t MASK_P; /*!< Mask for pattern match function of slice P */
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__I uint32_t GPIO_INREG; /*!< GPIO input status register */
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__IO uint32_t GPIO_OUTREG; /*!< GPIO output control register */
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__IO uint32_t GPIO_OENREG; /*!< GPIO OE control register */
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__IO uint32_t CTRL_ENABLED; /*!< Enables the slice COUNT counter */
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__IO uint32_t CTRL_DISABLED; /*!< Disables the slice COUNT counter */
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__I uint32_t RESERVED0[823];
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__O uint32_t CLR_EN_0; /*!< Shift clock interrupt clear mask */
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__O uint32_t SET_EN_0; /*!< Shift clock interrupt set mask */
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__I uint32_t ENABLE_0; /*!< Shift clock interrupt enable */
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__I uint32_t STATUS_0; /*!< Shift clock interrupt status */
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__O uint32_t CTR_STATUS_0; /*!< Shift clock interrupt clear status */
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__O uint32_t SET_STATUS_0; /*!< Shift clock interrupt set status */
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__I uint32_t RESERVED1[2];
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__O uint32_t CLR_EN_1; /*!< Capture clock interrupt clear mask */
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__O uint32_t SET_EN_1; /*!< Capture clock interrupt set mask */
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__I uint32_t ENABLE_1; /*!< Capture clock interrupt enable */
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__I uint32_t STATUS_1; /*!< Capture clock interrupt status */
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__O uint32_t CTR_STATUS_1; /*!< Capture clock interrupt clear status */
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__O uint32_t SET_STATUS_1; /*!< Capture clock interrupt set status */
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__I uint32_t RESERVED2[2];
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__O uint32_t CLR_EN_2; /*!< Pattern match interrupt clear mask */
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__O uint32_t SET_EN_2; /*!< Pattern match interrupt set mask */
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__I uint32_t ENABLE_2; /*!< Pattern match interrupt enable */
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__I uint32_t STATUS_2; /*!< Pattern match interrupt status */
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__O uint32_t CTR_STATUS_2; /*!< Pattern match interrupt clear status */
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__O uint32_t SET_STATUS_2; /*!< Pattern match interrupt set status */
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__I uint32_t RESERVED3[2];
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__O uint32_t CLR_EN_3; /*!< Input interrupt clear mask */
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__O uint32_t SET_EN_3; /*!< Input bit match interrupt set mask */
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__I uint32_t ENABLE_3; /*!< Input bit match interrupt enable */
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__I uint32_t STATUS_3; /*!< Input bit match interrupt status */
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__O uint32_t CTR_STATUS_3; /*!< Input bit match interrupt clear status */
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__O uint32_t SET_STATUS_3; /*!< Shift clock interrupt set status */
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} IP_SGPIO_001_Type;
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SGPIO_001_H_ */
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