301 lines
8.1 KiB
C
301 lines
8.1 KiB
C
/*
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* @brief SD/SDIO (MCI) registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "sdmmc_001.h"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Initializes the MCI card controller */
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void IP_SDMMC_Init(IP_SDMMC_001_Type *pSDMMC)
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{
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/* Software reset */
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pSDMMC->BMOD = MCI_BMOD_SWR;
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/* reset all blocks */
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pSDMMC->CTRL = MCI_CTRL_RESET | MCI_CTRL_FIFO_RESET | MCI_CTRL_DMA_RESET;
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while (pSDMMC->CTRL & (MCI_CTRL_RESET | MCI_CTRL_FIFO_RESET | MCI_CTRL_DMA_RESET)) {}
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/* Internal DMA setup for control register */
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pSDMMC->CTRL = MCI_CTRL_USE_INT_DMAC | MCI_CTRL_INT_ENABLE;
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pSDMMC->INTMASK = 0;
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/* Clear the interrupts for the host controller */
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pSDMMC->RINTSTS = 0xFFFFFFFF;
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/* Put in max timeout */
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pSDMMC->TMOUT = 0xFFFFFFFF;
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/* FIFO threshold settings for DMA, DMA burst of 4, FIFO watermark at 16 */
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pSDMMC->FIFOTH = MCI_FIFOTH_DMA_MTS_4 | MCI_FIFOTH_RX_WM((SD_FIFO_SZ / 2) - 1) | MCI_FIFOTH_TX_WM(SD_FIFO_SZ / 2);
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/* Enable internal DMA, burst size of 4, fixed burst */
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pSDMMC->BMOD = MCI_BMOD_DE | MCI_BMOD_PBL4 | MCI_BMOD_DSL(4);
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/* disable clock to CIU (needs latch) */
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pSDMMC->CLKENA = 0;
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pSDMMC->CLKSRC = 0;
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}
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/* Close the MCI */
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void IP_SDMMC_DeInit(IP_SDMMC_001_Type *pSDMMC)
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{}
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/* Set block size for transfer */
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void IP_SDMMC_SetBlkSize(IP_SDMMC_001_Type *pSDMMC, uint32_t bytes)
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{
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pSDMMC->BLKSIZ = bytes;
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}
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/* Reset card in slot */
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void IP_SDMMC_Reset(IP_SDMMC_001_Type *pSDMMC, int32_t reset)
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{
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if (reset) {
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pSDMMC->RST_N = 1;
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}
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else {
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pSDMMC->RST_N = 0;
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}
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}
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/* Enable or disable slot power */
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void IP_SDMMC_PowerOnOff(IP_SDMMC_001_Type *pSDMMC, int32_t enable)
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{
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if (enable) {
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pSDMMC->PWREN = 1;
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}
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else {
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pSDMMC->PWREN = 0;
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}
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}
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/* Detect if write protect is enabled */
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int32_t IP_SDMMC_CardWpOn(IP_SDMMC_001_Type *pSDMMC)
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{
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if (pSDMMC->WRTPRT & 1) {
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return 1;
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}
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return 0;
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}
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/* Detect if an SD card is inserted */
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int32_t IP_SDMMC_CardNDetect(IP_SDMMC_001_Type *pSDMMC)
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{
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/* No card = high state in regsiter */
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if (pSDMMC->CDETECT & 1) {
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return 0;
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}
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return 1;
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}
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/* Function to send command to Card interface unit (CIU) */
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int32_t IP_SDMMC_SendCmd(IP_SDMMC_001_Type *pSDMMC, uint32_t cmd, uint32_t arg)
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{
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volatile int32_t tmo = 50;
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volatile int delay;
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/* set command arg reg*/
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pSDMMC->CMDARG = arg;
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pSDMMC->CMD = MCI_CMD_START | cmd;
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/* poll untill command is accepted by the CIU */
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while (--tmo && (pSDMMC->CMD & MCI_CMD_START)) {
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if (tmo & 1) {
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delay = 50;
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}
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else {
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delay = 18000;
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}
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while (--delay > 1) {}
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}
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return (tmo < 1) ? 1 : 0;
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}
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/* Read the response from the last command */
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void IP_SDMMC_GetResponse(IP_SDMMC_001_Type *pSDMMC, uint32_t *resp)
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{
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/* on this chip response is not a fifo so read all 4 regs */
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resp[0] = pSDMMC->RESP0;
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resp[1] = pSDMMC->RESP1;
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resp[2] = pSDMMC->RESP2;
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resp[3] = pSDMMC->RESP3;
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}
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/* Sets the SD bus clock speed */
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void IP_SDMMC_SetClock(IP_SDMMC_001_Type *pSDMMC, uint32_t clk_rate, uint32_t speed)
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{
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/* compute SD/MMC clock dividers */
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uint32_t div;
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div = ((clk_rate / speed) + 2) >> 1;
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if ((div == pSDMMC->CLKDIV) && pSDMMC->CLKENA) {
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return; /* Closest speed is already set */
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}
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/* disable clock */
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pSDMMC->CLKENA = 0;
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/* User divider 0 */
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pSDMMC->CLKSRC = MCI_CLKSRC_CLKDIV0;
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/* inform CIU */
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IP_SDMMC_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0);
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/* set divider 0 to desired value */
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pSDMMC->CLKDIV = MCI_CLOCK_DIVIDER(0, div);
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/* inform CIU */
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IP_SDMMC_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0);
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/* enable clock */
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pSDMMC->CLKENA = MCI_CLKEN_ENABLE;
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/* inform CIU */
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IP_SDMMC_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0);
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}
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/* Function to set card type */
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void IP_SDMMC_SetCardType(IP_SDMMC_001_Type *pSDMMC, uint32_t ctype)
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{
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pSDMMC->CTYPE = ctype;
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}
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/* Function to clear interrupt & FIFOs */
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void IP_SDMMC_SetClearIntFifo(IP_SDMMC_001_Type *pSDMMC)
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{
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/* reset all blocks */
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pSDMMC->CTRL |= MCI_CTRL_FIFO_RESET;
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/* wait till resets clear */
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while (pSDMMC->CTRL & MCI_CTRL_FIFO_RESET) {}
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/* Clear interrupt status */
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pSDMMC->RINTSTS = 0xFFFFFFFF;
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}
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/* Returns the raw SD interface interrupt status */
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uint32_t IP_SDMMC_GetRawIntStatus(IP_SDMMC_001_Type *pSDMMC)
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{
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return pSDMMC->RINTSTS;
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}
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/* Sets the raw SD interface interrupt status */
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void IP_SDMMC_SetRawIntStatus(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal)
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{
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pSDMMC->RINTSTS = iVal;
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}
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/* Sets the SD interface interrupt mask */
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void IP_SDMMC_SetIntMask(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal)
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{
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pSDMMC->INTMASK = iVal;
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}
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/* Setup DMA descriptors */
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void IP_SDMMC_DmaSetup(IP_SDMMC_001_Type *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size)
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{
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int i = 0;
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uint32_t ctrl, maxs;
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/* Reset DMA */
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pSDMMC->CTRL |= MCI_CTRL_DMA_RESET | MCI_CTRL_FIFO_RESET;
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while (pSDMMC->CTRL & MCI_CTRL_DMA_RESET) {}
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/* Build a descriptor list using the chained DMA method */
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while (size > 0) {
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/* Limit size of the transfer to maximum buffer size */
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maxs = size;
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if (maxs > MCI_DMADES1_MAXTR) {
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maxs = MCI_DMADES1_MAXTR;
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}
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size -= maxs;
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/* Set buffer size */
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psdif_dev->mci_dma_dd[i].des1 = MCI_DMADES1_BS1(maxs);
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/* Setup buffer address (chained) */
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psdif_dev->mci_dma_dd[i].des2 = addr + (i * MCI_DMADES1_MAXTR);
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/* Setup basic control */
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ctrl = MCI_DMADES0_OWN | MCI_DMADES0_CH;
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if (i == 0) {
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ctrl |= MCI_DMADES0_FS; /* First DMA buffer */
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}
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/* No more data? Then this is the last descriptor */
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if (!size) {
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ctrl |= MCI_DMADES0_LD;
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}
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else {
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ctrl |= MCI_DMADES0_DIC;
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}
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/* Another descriptor is needed */
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psdif_dev->mci_dma_dd[i].des3 = (uint32_t) &psdif_dev->mci_dma_dd[i + 1];
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psdif_dev->mci_dma_dd[i].des0 = ctrl;
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i++;
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}
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/* Set DMA derscriptor base address */
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pSDMMC->DBADDR = (uint32_t) &psdif_dev->mci_dma_dd[0];
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}
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/**
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* @brief Sets the transfer block size
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @param blk_size : Block Size value
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* @return None
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*/
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void IP_SDMMC_SetBlockSize(IP_SDMMC_001_Type *pSDMMC, uint32_t blk_size)
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{
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/* set block size and byte count */
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pSDMMC->BLKSIZ = blk_size;
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pSDMMC->BYTCNT = blk_size;
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}
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