360 lines
8.2 KiB
C
360 lines
8.2 KiB
C
/**************************************************************************//**
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* @file core_cm3.c
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* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
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* @version V1.40
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* @date 18. February 2010
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*
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* @note
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* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include <stdint.h>
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/* define compiler specific symbols */
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#if defined ( __CC_ARM )
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#define __ASM __asm /*!< asm keyword for ARM Compiler */
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#define __INLINE __inline /*!< inline keyword for ARM Compiler */
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#elif defined ( __ICCARM__ )
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#define __ASM __asm /*!< asm keyword for IAR Compiler */
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
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#elif defined ( __GNUC__ )
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#define __ASM __asm /*!< asm keyword for GNU Compiler */
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#define __INLINE inline /*!< inline keyword for GNU Compiler */
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#elif defined ( __TASKING__ )
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#define __ASM __asm /*!< asm keyword for TASKING Compiler */
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */
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#endif
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/* ########################## Core Instruction Access ######################### */
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#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
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/**
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* @brief Reverse byte order (16 bit)
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in unsigned short value
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*/
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#if (__ARMCC_VERSION < 400677)
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__ASM uint32_t __REV16(uint16_t value)
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{
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rev16 r0, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Reverse byte order in signed short value with sign extension to integer
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in signed short value with sign extension to integer
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*/
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#if (__ARMCC_VERSION < 400677)
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__ASM int32_t __REVSH(int16_t value)
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{
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revsh r0, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Remove the exclusive lock created by ldrex
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*
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* Removes the exclusive lock which is created by ldrex.
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __CLREX(void)
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{
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clrex
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}
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#endif /* __ARMCC_VERSION */
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#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
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/* obsolete */
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#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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/* obsolete */
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#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
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/* obsolete */
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#endif
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/* ########################### Core Function Access ########################### */
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#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
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/**
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* @brief Return the Control Register value
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*
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* @return Control value
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*
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* Return the content of the control register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_CONTROL(void)
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{
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mrs r0, control
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Control Register value
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*
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* @param control Control value
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*
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* Set the control register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_CONTROL(uint32_t control)
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{
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msr control, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Get IPSR Register value
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*
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* @return uint32_t IPSR value
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*
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* return the content of the IPSR register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_IPSR(void)
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{
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mrs r0, ipsr
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Get APSR Register value
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*
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* @return uint32_t APSR value
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*
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* return the content of the APSR register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_APSR(void)
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{
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mrs r0, apsr
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Get xPSR Register value
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*
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* @return uint32_t xPSR value
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*
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* return the content of the xPSR register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_xPSR(void)
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{
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mrs r0, xpsr
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Process Stack Pointer
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*
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* @return ProcessStackPointer
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*
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* Return the actual process stack pointer
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_PSP(void)
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{
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mrs r0, psp
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Process Stack Pointer
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*
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* @param topOfProcStack Process Stack Pointer
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*
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* Assign the value ProcessStackPointer to the MSP
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* (process stack pointer) Cortex processor register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_PSP(uint32_t topOfProcStack)
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{
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msr psp, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Main Stack Pointer
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*
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* @return Main Stack Pointer
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*
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* Return the current value of the MSP (main stack pointer)
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* Cortex processor register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_MSP(void)
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{
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mrs r0, msp
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Main Stack Pointer
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*
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* @param topOfMainStack Main Stack Pointer
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*
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* Assign the value mainStackPointer to the MSP
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* (main stack pointer) Cortex processor register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_MSP(uint32_t mainStackPointer)
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{
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msr msp, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Base Priority value
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*
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* @return BasePriority
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*
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* Return the content of the base priority register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_BASEPRI(void)
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{
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mrs r0, basepri
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Base Priority value
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*
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* @param basePri BasePriority
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*
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* Set the base priority register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_BASEPRI(uint32_t basePri)
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{
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msr basepri, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Priority Mask value
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*
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* @return PriMask
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*
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* Return state of the priority mask bit from the priority mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_PRIMASK(void)
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{
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mrs r0, primask
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Priority Mask value
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*
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* @param priMask PriMask
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*
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* Set the priority mask bit in the priority mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_PRIMASK(uint32_t priMask)
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{
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msr primask, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Fault Mask value
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*
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* @return FaultMask
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*
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* Return the content of the fault mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_FAULTMASK(void)
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{
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mrs r0, faultmask
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Fault Mask value
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*
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* @param faultMask faultMask value
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*
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* Set the fault mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_FAULTMASK(uint32_t faultMask)
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{
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msr faultmask, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the FPSCR value
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*
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* @return FloatingPointStatusControlRegister
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*
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* Return the content of the FPSCR register
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*/
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/**
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* @brief Set the FPSCR value
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*
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* @param fpscr FloatingPointStatusControlRegister
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*
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* Set the FPSCR register
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*/
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#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
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/* obsolete */
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#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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/* obsolete */
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#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
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/* obsolete */
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#endif
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