167 lines
6.4 KiB
C
167 lines
6.4 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-02-08 RT-Thread the first version
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*/
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#ifndef __DRV_SDIO_H__
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#define __DRV_SDIO_H__
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#define MMC0_BASE_ADDR 0x01C0F000
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#define MMC1_BASE_ADDR 0x01C10000
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struct tina_mmc
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{
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volatile rt_uint32_t gctl_reg; /* (0x000) */
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volatile rt_uint32_t ckcr_reg; /* (0x004) */
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volatile rt_uint32_t tmor_reg; /* (0x008) */
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volatile rt_uint32_t bwdr_reg; /* (0x00C) */
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volatile rt_uint32_t bksr_reg; /* (0x010) */
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volatile rt_uint32_t bycr_reg; /* (0x014) */
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volatile rt_uint32_t cmdr_reg; /* (0x018) */
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volatile rt_uint32_t cagr_reg; /* (0x01C) */
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volatile rt_uint32_t resp0_reg; /* (0x020) */
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volatile rt_uint32_t resp1_reg; /* (0x024) */
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volatile rt_uint32_t resp2_reg; /* (0x028) */
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volatile rt_uint32_t resp3_reg; /* (0x02C) */
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volatile rt_uint32_t imkr_reg; /* (0x030) */
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volatile rt_uint32_t misr_reg; /* (0x034) */
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volatile rt_uint32_t risr_reg; /* (0x038) */
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volatile rt_uint32_t star_reg; /* (0x03C) */
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volatile rt_uint32_t fwlr_reg; /* (0x040) */
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volatile rt_uint32_t funs_reg; /* (0x044) */
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volatile rt_uint32_t cbcr_reg; /* (0x048) */
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volatile rt_uint32_t bbcr_reg; /* (0x04C) */
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volatile rt_uint32_t dbgc_reg; /* (0x050) */
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volatile rt_uint32_t reserved0;
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volatile rt_uint32_t a12a_reg; /* (0x058) */
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volatile rt_uint32_t reserved1[7];
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volatile rt_uint32_t hwrst_reg; /* (0x078) */
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volatile rt_uint32_t reserved2;
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volatile rt_uint32_t dmac_reg; /* (0x080) */
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volatile rt_uint32_t dlba_reg; /* (0x084) */
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volatile rt_uint32_t idst_reg; /* (0x088) */
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volatile rt_uint32_t idie_reg; /* (0x08C) */
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volatile rt_uint32_t chda_reg; /* (0x090) */
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volatile rt_uint32_t cbda_reg; /* (0x094) */
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volatile rt_uint32_t reserved3[26];
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volatile rt_uint32_t card_thldc_reg; /* (0x100) */
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volatile rt_uint32_t reserved4[2];
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volatile rt_uint32_t emmc_dsbd_reg; /* (0x10c) */
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volatile rt_uint32_t reserved5[12];
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volatile rt_uint32_t reserved6[48];
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volatile rt_uint32_t fifo_reg; /* (0x200) */
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};
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typedef struct tina_mmc *tina_mmc_t;
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#define MMC0 ((tina_mmc_t)MMC0_BASE_ADDR)
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#define MMC1 ((tina_mmc_t)MMC1_BASE_ADDR)
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#define BIT(x) (1<<(x))
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/* Struct for Intrrrupt Information */
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#define SDXC_RespErr BIT(1) //0x2
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#define SDXC_CmdDone BIT(2) //0x4
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#define SDXC_DataOver BIT(3) //0x8
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#define SDXC_TxDataReq BIT(4) //0x10
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#define SDXC_RxDataReq BIT(5) //0x20
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#define SDXC_RespCRCErr BIT(6) //0x40
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#define SDXC_DataCRCErr BIT(7) //0x80
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#define SDXC_RespTimeout BIT(8) //0x100
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#define SDXC_ACKRcv BIT(8) //0x100
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#define SDXC_DataTimeout BIT(9) //0x200
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#define SDXC_BootStart BIT(9) //0x200
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#define SDXC_DataStarve BIT(10) //0x400
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#define SDXC_VolChgDone BIT(10) //0x400
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#define SDXC_FIFORunErr BIT(11) //0x800
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#define SDXC_HardWLocked BIT(12) //0x1000
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#define SDXC_StartBitErr BIT(13) //0x2000
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#define SDXC_AutoCMDDone BIT(14) //0x4000
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#define SDXC_EndBitErr BIT(15) //0x8000
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#define SDXC_SDIOInt BIT(16) //0x10000
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#define SDXC_CardInsert BIT(30) //0x40000000
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#define SDXC_CardRemove BIT(31) //0x80000000
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#define SDXC_IntErrBit (SDXC_RespErr | SDXC_RespCRCErr | SDXC_DataCRCErr \
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| SDXC_RespTimeout | SDXC_DataTimeout | SDXC_FIFORunErr \
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| SDXC_HardWLocked | SDXC_StartBitErr | SDXC_EndBitErr) //0xbfc2
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/*
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SD CMD reg
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REG[0-5] : Cmd ID
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REG[6] : Has response
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REG[7] : Long response
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REG[8] : Check response CRC
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REG[9] : Has data
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REG[10] : Write
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REG[11] : Steam mode
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REG[12] : Auto stop
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REG[13] : Wait previous over
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REG[14] : About cmd
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REG[15] : Send initialization
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REG[21] : Update clock
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REG[31] : Load cmd
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*/
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#define SDXC_RESPONSE_CMD BIT(6)
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#define SDXC_LONG_RESPONSE_CMD BIT(7)
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#define SDXC_CHECK_CRC_CMD BIT(8)
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#define SDXC_HAS_DATA_CMD BIT(9)
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#define SDXC_WRITE_CMD BIT(10)
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#define SDXC_STEAM_CMD BIT(11)
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#define SDXC_AUTO_STOP_CMD BIT(12)
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#define SDXC_WAIT_OVER_CMD BIT(13)
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#define SDXC_ABOUT_CMD BIT(14)
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#define SDXC_SEND_INIT_CMD BIT(15)
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#define SDXC_UPDATE_CLOCK_CMD BIT(21)
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#define SDXC_LOAD_CMD BIT(31)
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/*
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SD status reg
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REG[0] : FIFO_RX_LEVEL
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REG[1] : FIFO_TX_LEVEL
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REG[2] : FIFO_EMPTY
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REG[3] : FIFO_FULL
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REG[4-7] : FSM_STA
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REG[8] : CARD_PRESENT
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REG[9] : CARD_BUSY
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REG[10] : FSM_BUSY
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REG[11-16]: RESP_IDX
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REG[17-21]: FIFO_LEVEL
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REG[31] : DMA_REQ
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*/
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#define SDXC_FIFO_RX_LEVEL BIT(0)
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#define SDXC_FIFO_TX_LEVEL BIT(1)
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#define SDXC_FIFO_EMPTY BIT(2)
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#define SDXC_FIFO_FULL BIT(3)
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#define SDXC_CARD_PRESENT BIT(8)
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#define SDXC_CARD_BUSY BIT(9)
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#define SDXC_FSM_BUSY BIT(10)
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#define SDXC_DMA_REQ BIT(31)
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struct mmc_des_v4p1
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{
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rt_uint32_t : 1,
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dic : 1, /* disable interrupt on completion */
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last_des : 1, /* 1-this data buffer is the last buffer */
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first_des : 1, /* 1-data buffer is the first buffer,0-data buffer contained in the next descriptor is 1st buffer */
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des_chain : 1, /* 1-the 2nd address in the descriptor is the next descriptor address */
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end_of_ring : 1, /* 1-last descriptor flag when using dual data buffer in descriptor */
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: 24,
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card_err_sum : 1, /* transfer error flag */
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own : 1; /* des owner:1-idma owns it, 0-host owns it */
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#define SDXC_DES_NUM_SHIFT 12 /* smhc2!! */
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#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
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rt_uint32_t data_buf1_sz : 16,
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data_buf2_sz : 16;
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rt_uint32_t buf_addr_ptr1;
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rt_uint32_t buf_addr_ptr2;
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};
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#endif
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