469 lines
24 KiB
C
469 lines
24 KiB
C
/**************************************************************************//**
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* @file
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* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
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* for EFM EFM32GG980F512
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* @author Energy Micro AS
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* @version 3.0.0
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
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******************************************************************************
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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*****************************************************************************/
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#ifndef __EFM32GG980F512_H
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#define __EFM32GG980F512_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**************************************************************************//**
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* @addtogroup Parts
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* @{
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*****************************************************************************/
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/**************************************************************************//**
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* @defgroup EFM32GG980F512 EFM32GG980F512
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* @{
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*****************************************************************************/
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/** Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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/****** EFM32G Peripheral Interrupt Numbers **********************************************/
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DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
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GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
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TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
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USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
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USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
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USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
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ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
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ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
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DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
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I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
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I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
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GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
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TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
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TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
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TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
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USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
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USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
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LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
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USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
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USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
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UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
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UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
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UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
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UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
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LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
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LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
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LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
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PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
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PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
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PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
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RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
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BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
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CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
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VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
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LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
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MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
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AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
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EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
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EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
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} IRQn_Type;
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/**************************************************************************//**
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* @defgroup EFM32GG980F512_Core EFM32GG980F512 Core
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* @{
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* @brief Processor and Core Peripheral Section
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*****************************************************************************/
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#define __MPU_PRESENT 1 /**< Presence of MPU */
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#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
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#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
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/** @} End of group EFM32GG980F512_Core */
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/**************************************************************************//**
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* @defgroup EFM32GG980F512_Part EFM32GG980F512 Part
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* @{
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******************************************************************************/
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/** Part family */
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#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
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/* If part number is not defined as compiler option, define it */
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#if !defined(EFM32GG980F512)
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#define EFM32GG980F512 1 /**< Giant/Leopard Gecko Part */
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#endif
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/** Configure part number */
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#define PART_NUMBER "EFM32GG980F512" /**< Part Number */
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/** Memory Base addresses and limits */
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#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
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#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
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#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
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#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
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#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
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#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
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#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
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#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
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#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
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#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
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#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
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#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
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#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
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#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
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#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
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#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
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#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
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#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
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#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
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#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
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#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
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#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
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#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
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#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
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#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
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#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
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#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
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#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
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#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
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#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
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#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
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#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
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/** Bit banding area */
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#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
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#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
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/** Flash and SRAM limits for EFM32GG980F512 */
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#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
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#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
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#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
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#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
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#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
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#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
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#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
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/* Part number capabilities */
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#define TIMER_PRESENT /**< TIMER is available in this part */
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#define TIMER_COUNT 4 /**< 4 TIMERs available */
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#define USART_PRESENT /**< USART is available in this part */
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#define USART_COUNT 3 /**< 3 USARTs available */
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#define UART_PRESENT /**< UART is available in this part */
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#define UART_COUNT 2 /**< 2 UARTs available */
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#define LEUART_PRESENT /**< LEUART is available in this part */
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#define LEUART_COUNT 2 /**< 2 LEUARTs available */
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#define LETIMER_PRESENT /**< LETIMER is available in this part */
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#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
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#define PCNT_PRESENT /**< PCNT is available in this part */
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#define PCNT_COUNT 3 /**< 3 PCNTs available */
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#define I2C_PRESENT /**< I2C is available in this part */
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#define I2C_COUNT 2 /**< 2 I2Cs available */
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#define ADC_PRESENT /**< ADC is available in this part */
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#define ADC_COUNT 1 /**< 1 ADCs available */
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#define DAC_PRESENT /**< DAC is available in this part */
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#define DAC_COUNT 1 /**< 1 DACs available */
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#define ACMP_PRESENT /**< ACMP is available in this part */
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#define ACMP_COUNT 2 /**< 2 ACMPs available */
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#define LE_PRESENT
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#define LE_COUNT 1
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#define MSC_PRESENT
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#define MSC_COUNT 1
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#define EMU_PRESENT
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#define EMU_COUNT 1
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#define RMU_PRESENT
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#define RMU_COUNT 1
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#define CMU_PRESENT
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#define CMU_COUNT 1
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#define AES_PRESENT
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#define AES_COUNT 1
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#define LESENSE_PRESENT
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#define LESENSE_COUNT 1
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#define EBI_PRESENT
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#define EBI_COUNT 1
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#define GPIO_PRESENT
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#define GPIO_COUNT 1
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#define PRS_PRESENT
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#define PRS_COUNT 1
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#define DMA_PRESENT
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#define DMA_COUNT 1
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#define OPAMP_PRESENT
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#define OPAMP_COUNT 1
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#define USB_PRESENT
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#define USB_COUNT 1
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#define USBC_PRESENT
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#define USBC_COUNT 1
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#define BU_PRESENT
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#define BU_COUNT 1
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#define VCMP_PRESENT
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#define VCMP_COUNT 1
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#define LCD_PRESENT
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#define LCD_COUNT 1
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#define RTC_PRESENT
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#define RTC_COUNT 1
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#define BURTC_PRESENT
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#define BURTC_COUNT 1
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#define HFXTAL_PRESENT
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#define HFXTAL_COUNT 1
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#define LFXTAL_PRESENT
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#define LFXTAL_COUNT 1
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#define WDOG_PRESENT
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#define WDOG_COUNT 1
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#define DBG_PRESENT
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#define DBG_COUNT 1
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#define ETM_PRESENT
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#define ETM_COUNT 1
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#define BOOTLOADER_PRESENT
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#define BOOTLOADER_COUNT 1
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#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
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#include "system_efm32gg.h" /* System Header */
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/** @} End of group EFM32GG980F512_Part */
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/**************************************************************************//**
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* @defgroup EFM32GG980F512_Peripheral_TypeDefs EFM32GG980F512 Peripheral TypeDefs
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* @{
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* @brief Device Specific Peripheral Register Structures
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*****************************************************************************/
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#include "efm32gg_msc.h"
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#include "efm32gg_emu.h"
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#include "efm32gg_rmu.h"
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#include "efm32gg_cmu.h"
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#include "efm32gg_aes.h"
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#include "efm32gg_lesense_st.h"
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#include "efm32gg_lesense_buf.h"
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#include "efm32gg_lesense_ch.h"
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#include "efm32gg_lesense.h"
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#include "efm32gg_ebi.h"
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#include "efm32gg_gpio_p.h"
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#include "efm32gg_gpio.h"
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#include "efm32gg_prs_ch.h"
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#include "efm32gg_prs.h"
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#include "efm32gg_dma_ch.h"
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#include "efm32gg_dma.h"
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#include "efm32gg_timer_cc.h"
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#include "efm32gg_timer.h"
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#include "efm32gg_usart.h"
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#include "efm32gg_leuart.h"
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#include "efm32gg_letimer.h"
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#include "efm32gg_pcnt.h"
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#include "efm32gg_i2c.h"
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#include "efm32gg_adc.h"
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#include "efm32gg_dac.h"
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#include "efm32gg_acmp.h"
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#include "efm32gg_usb_hc.h"
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#include "efm32gg_usb_diep.h"
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#include "efm32gg_usb_doep.h"
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#include "efm32gg_usb.h"
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#include "efm32gg_vcmp.h"
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#include "efm32gg_lcd.h"
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#include "efm32gg_rtc.h"
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#include "efm32gg_burtc_ret.h"
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#include "efm32gg_burtc.h"
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#include "efm32gg_wdog.h"
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#include "efm32gg_etm.h"
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#include "efm32gg_dma_descriptor.h"
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#include "efm32gg_devinfo.h"
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#include "efm32gg_romtable.h"
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#include "efm32gg_calibrate.h"
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/** @} End of group EFM32GG980F512_Peripheral_TypeDefs */
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/**************************************************************************//**
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* @defgroup EFM32GG980F512_Peripheral_Base EFM32GG980F512 Peripheral Memory Map
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* @{
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*****************************************************************************/
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#define MSC_BASE (0x400C0000UL) /**< MSC base address */
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#define EMU_BASE (0x400C6000UL) /**< EMU base address */
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#define RMU_BASE (0x400CA000UL) /**< RMU base address */
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#define CMU_BASE (0x400C8000UL) /**< CMU base address */
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#define AES_BASE (0x400E0000UL) /**< AES base address */
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#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
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#define EBI_BASE (0x40008000UL) /**< EBI base address */
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#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
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#define PRS_BASE (0x400CC000UL) /**< PRS base address */
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#define DMA_BASE (0x400C2000UL) /**< DMA base address */
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#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
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#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
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#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
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#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
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#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
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#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
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#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
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#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
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#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
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#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
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#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
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#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
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#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
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#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
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#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
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#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
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#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
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#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
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#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
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#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
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#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
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#define USB_BASE (0x400C4000UL) /**< USB base address */
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#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
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#define LCD_BASE (0x4008A000UL) /**< LCD base address */
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#define RTC_BASE (0x40080000UL) /**< RTC base address */
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#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
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#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
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#define ETM_BASE (0xE0041000UL) /**< ETM base address */
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#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
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#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
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#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
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/** @} End of group EFM32GG980F512_Peripheral_Base */
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/**************************************************************************//**
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* @defgroup EFM32GG980F512_Peripheral_Declaration EFM32GG980F512 Peripheral Declarations
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* @{
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*****************************************************************************/
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#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
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#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
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#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
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#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
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#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
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#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
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#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
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#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
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#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
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#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
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#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
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#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
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#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
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#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
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#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
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#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
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#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
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#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
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#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
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#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
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#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
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#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
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#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
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#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
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#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
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#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
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#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
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#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
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#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
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#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
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#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
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#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
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#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
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#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
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#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
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#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
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#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
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#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
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#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
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#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
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#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
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/** @} End of group EFM32GG980F512_Peripheral_Declaration */
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/**************************************************************************//**
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* @defgroup EFM32GG980F512_BitFields EFM32GG980F512 Bit Fields
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* @{
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*****************************************************************************/
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#include "efm32gg_prs_signals.h"
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#include "efm32gg_dmareq.h"
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#include "efm32gg_dmactrl.h"
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#include "efm32gg_uart.h"
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/**************************************************************************//**
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* @defgroup EFM32GG980F512_UNLOCK Unlock Codes
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* @{
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|
*****************************************************************************/
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#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
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#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
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#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
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#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
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#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
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#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
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/** @} End of group EFM32GG980F512_UNLOCK */
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|
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/** @} End of group EFM32GG980F512_BitFields */
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|
|
|
/**************************************************************************//**
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|
* @defgroup EFM32GG980F512_Alternate_Function EFM32GG980F512 Alternate Function
|
|
* @{
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|
*****************************************************************************/
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|
|
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#include "efm32gg_af_channels.h"
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|
#include "efm32gg_af_ports.h"
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#include "efm32gg_af_pins.h"
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|
|
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/** @} End of group EFM32GG980F512_Alternate_Function */
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|
|
|
/**************************************************************************//**
|
|
* @brief Set the value of a bit field within a register.
|
|
*
|
|
* @param REG
|
|
* The register to update
|
|
* @param MASK
|
|
* The mask for the bit field to update
|
|
* @param VALUE
|
|
* The value to write to the bit field
|
|
* @param OFFSET
|
|
* The number of bits that the field is offset within the register.
|
|
* 0 (zero) means LSB.
|
|
*****************************************************************************/
|
|
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
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|
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
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|
|
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/** @} End of group EFM32GG980F512 */
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|
|
|
/** @} End of group Parts */
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|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
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|
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#endif /* __EFM32GG980F512_H */
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