184 lines
5.8 KiB
C
184 lines
5.8 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fpl011.h
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* Date: 2021-11-02 14:53:42
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* LastEditTime: 2022-02-18 09:07:38
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* Description: This file is for uart functions
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 huanghe 2021/11/2 first commit
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* 1.1 liushengming 2022/02/18 fix bug
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*/
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#ifndef FPL011_H
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#define FPL011_H
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#include "ftypes.h"
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#include "fassert.h"
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#include "fpl011_hw.h"
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#include "sdkconfig.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FPL011_ERROR_PARAM FT_CODE_ERR(ErrModBsp, ErrBspUart, 0x1u)
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#define FPL011_BAUDRATE 115200U
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/* Config options */
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#define FPL011_OPTION_UARTEN 0x1U
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#define FPL011_OPTION_RXEN 0x2U
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#define FPL011_OPTION_TXEN 0x4U
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#define FPL011_OPTION_FIFOEN 0x8U
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#define FPL011_OPTION_CTS 0x10U
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#define FPL011_OPTION_RTS 0x20U
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#define FPL011_OPTION_DTR 0x40U
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#define FPL011_OPTION_RTSEN 0x80U
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#define FPL011_OPTION_CTSEN 0x100U
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#define FPL011_OPTION_TXDMAEN 0x200U
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#define FPL011_OPTION_RXDMAEN 0x400U
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/* Channel Operational Mode */
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#define FPL011_OPER_MODE_NORMAL (u8)0x00U /* Normal Mode */
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#define FPL011_OPER_MODE_LOCAL_LOOP (u8)0x01U /* Local Loop back Mode */
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/* Data format values */
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#define FPL011_FORMAT_WORDLENGTH_8BIT 0x3
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#define FPL011_FORMAT_WORDLENGTH_7BIT 0x2
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#define FPL011_FORMAT_WORDLENGTH_6BIT 0x1
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#define FPL011_FORMAT_WORDLENGTH_5BIT 0x0
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#define FPL011_FORMAT_NO_PARITY 0U /* No parity */
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#define FPL011_FORMAT_EN_PARITY 1U /* Enable parity */
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#define FPL011_FORMAT_EVEN_PARITY 2U /* Even parity */
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#define FPL011_FORMAT_ODD_PARITY 0U /* Odd parity */
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#define FPL011_FORMAT_EN_STICK_PARITY 4U /* Stick parity */
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#define FPL011_FORMAT_NO_STICK_PARITY 0U /* Stick parity */
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#define FPL011_FORMAT_PARITY_MASK 7U /* Format parity mask */
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#define FPL011_FORMAT_EVEN_PARITY_SHIFT 1U /* Even parity shift */
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#define FPL011_FORMAT_EN_STICK_PARITY_SHIFT 5U /* Stick parity shift */
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#define FPL011_FORMAT_2_STOP_BIT 1U
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#define FPL011_FORMAT_1_STOP_BIT 0U
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/* Callback events */
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#define FPL011_EVENT_RECV_DATA 1U /* Data receiving done */
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#define FPL011_EVENT_RECV_TOUT 2U /* A receive timeout occurred */
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#define FPL011_EVENT_SENT_DATA 3U /* Data transmission done */
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#define FPL011_EVENT_RECV_ERROR 4U /* A receive error detected */
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#define FPL011_EVENT_MODEM 5U /* Modem status changed */
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#define FPL011_EVENT_PARE_FRAME_BRKE 6U /* A receive parity, frame, break \
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* error detected */
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#define FPL011_EVENT_RECV_ORERR 7U /* A receive overrun error detected */
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/**************************** Type Definitions ******************************/
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/**
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* Keep track of data format setting of a device.
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*/
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typedef struct
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{
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u32 baudrate ; /* In bps, ie 1200 */
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u32 data_bits ; /* Number of data bits */
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u32 parity ; /* Parity */
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u8 stopbits ; /* Number of stop bits */
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} FPl011Format ;
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typedef struct
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{
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u32 instance_id; /* Id of device*/
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uintptr base_address;
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u32 ref_clock_hz;
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u32 irq_num;
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u32 baudrate;
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} FPl011Config;
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typedef struct
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{
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u8 *byte_p;
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u32 requested_bytes;
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u32 remaining_bytes;
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} FPl011Buffer;
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typedef void (*FPl011EventHandler)(void *args, u32 event, u32 event_data);
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typedef struct
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{
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FPl011Config config; /* Configuration data structure */
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u32 is_ready; /* Device is ininitialized and ready*/
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FPl011Buffer send_buffer;
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FPl011Buffer receive_buffer;
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FPl011EventHandler handler;
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void *args;
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uint8_t rxbs_error; /* An error occurs during receiving. 0 has no error and 1 has an error */
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} FPl011;
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/************************** Function Prototypes ******************************/
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/* FPl011_uart_sinit.c */
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const FPl011Config *FPl011LookupConfig(u32 instance_id);
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/* FPl011_uart.c */
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FError FPl011CfgInitialize(FPl011 *uart_p, FPl011Config *config);
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void FPl011BlockSend(FPl011 *uart_p, u8 *byte_p, u32 length);
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u32 FPl011Send(FPl011 *uart_p, u8 *byte_p, u32 length);
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u32 FPl011Receive(FPl011 *uart_p, u8 *byte_p, u32 length);
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u8 FPl011BlockReceive(FPl011 *uart_p);
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void FPl011ProgramCtlReg(FPl011 *uart_p, u32 ctrl_reg);
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/* FPl011_uart_options.c */
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void FPl011SetOperMode(FPl011 *uart_p, u8 operation_mode);
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void FPl011SetOptions(FPl011 *uart_p, u32 options);
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void FPl011SetSpecificOptions(FPl011 *uart_p, u32 options);
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void FPl011ClearSpecificOptions(FPl011 *uart_p, u32 options);
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FError FPl011SetBaudRate(FPl011 *uart_p, u32 baudrate) ;
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void FPl011GetDataFormat(FPl011 *uart_p, FPl011Format *format_p) ;
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FError FPl011SetDataFormat(FPl011 *uart_p, FPl011Format *format_p) ;
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void FPl011SetTxFifoThreadHold(FPl011 *uart_p, u8 trigger_level) ;
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void FPl011SetRxFifoThreadhold(FPl011 *uart_p, u8 trigger_level) ;
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/* FPl011_uart_intr.c */
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u32 FPl011GetInterruptMask(FPl011 *uart_p) ;
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void FPl011InterruptHandler(s32 vector, void *param);
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void FPl011SetHandler(FPl011 *uart_p, FPl011EventHandler fun_p, void *args);
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void FPl011SetInterruptMask(FPl011 *uart_p, u32 mask);
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#ifdef __cplusplus
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}
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#endif
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#endif // !
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