145 lines
4.9 KiB
C
145 lines
4.9 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fpwm_hw.h
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-25 11:45:05
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* Description: This file is for pwm register definition.
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 wangxiaodong 2022/4/15 init commit
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*/
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#ifndef FPWM_HW_H
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#define FPWM_HW_H
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#include "fkernel.h"
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#include "ftypes.h"
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#include "fio.h"
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#include "fparameters.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* pwm register definitions */
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#define FPWM_BASE_ADR(n) ((FPWM_BASE_ADDR)+(n<<12)) /* 0<=n<=7 */
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#define FPWM0_BASE_ADR FPWM_BASE_ADR(0) /* PWM 0 base address */
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#define FPWM1_BASE_ADR FPWM_BASE_ADR(1) /* PWM 1 base address */
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#define FPWM2_BASE_ADR FPWM_BASE_ADR(2)
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#define FPWM3_BASE_ADR FPWM_BASE_ADR(3)
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#define FPWM4_BASE_ADR FPWM_BASE_ADR(4)
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#define FPWM5_BASE_ADR FPWM_BASE_ADR(5)
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#define FPWM6_BASE_ADR FPWM_BASE_ADR(6)
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#define FPWM7_BASE_ADR FPWM_BASE_ADR(7)
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/* DB register */
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#define FPWM_DB_CTRL_OFFSET 0x00
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#define FPWM_DB_DLY_OFFSET 0x04
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#define FPWM_OFFSET 0x400
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#define FPWM_TIM_CNT_OFFSET 0x00
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#define FPWM_TIM_CTRL_OFFSET 0x04
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#define FPWM_STATE_OFFSET 0x08
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#define FPWM_PERIOD_OFFSET 0x0C
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#define FPWM_CTRL_OFFSET 0x10
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#define FPWM_CCR_OFFSET 0x14
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#define FPWM_MODE_CHANNEL 2
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#define FPWM_N(x) ((FPWM_OFFSET)*(x))
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#define FPWM_RESET_TIMEOUT 10
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#define NSEC_PER_SEC (1000000000ULL)
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/* pwm db_ctrl field */
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#define FPWM_DB_CTRL_RESET BIT(0)
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#define FPWM_DB_CTRL_IN_MODE BIT(1)
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#define FPWM_DB_CTRL_POLSEL(data) ((data) << 2)
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#define FPWM_DB_CTRL_POLSEL_MASK GENMASK(3, 2)
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#define FPWM_DB_CTRL_POLSEL_GET(data) ((data) >> 2)
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#define FPWM_DB_CTRL_OUT_MODE(data) ((data) << 4)
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#define FPWM_DB_CTRL_OUT_MODE_MASK GENMASK(5, 4)
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#define FPWM_DB_CTRL_OUT_MODE_GET(data) ((data) >> 4)
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/* pwm db_ctrl field */
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#define FPWM_DB_DLY_MAX 1024
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#define FPWM_DB_DLY_RISE_MASK GENMASK(9, 0)
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#define FPWM_DB_DLY_FALL_MASK GENMASK(19, 10)
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#define FPWM_DB_DLY_FALL(data) ((data) << 10)
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#define FPWM_DB_DLY_FALL_GET(data) ((data) >> 10)
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/* pwm tim_ctrl field */
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#define FPWM_TIM_CTRL_DIV_MAX 4096
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#define FPWM_TIM_CTRL_RESET BIT(0)
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#define FPWM_TIM_CTRL_ENABLE BIT(1)
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#define FPWM_TIM_CTRL_MODE_UD BIT(2) /* mode, modulo or up-and-down */
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#define FPWM_TIM_CTRL_OVFIF_ENABLE BIT(4) /* counter-overflow intr enable */
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#define FPWM_TIM_CTRL_GIE BIT(5) /* overall intr enable */
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#define FPWM_TIM_CTRL_DIV(data) ((data) << 16)
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#define FPWM_TIM_CTRL_DIV_MASK GENMASK(27, 16)
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#define FPWM_TIM_CTRL_DIV_GET(data) ((data) >> 16)
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/* pwm_state field */
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#define FPWM_STATE_COUNTER_CLEAR BIT(0)
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#define FPWM_STATE_OVFIF_COUNTER BIT(1)
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#define FPWM_STATE_FIFO_EMPTY BIT(2)
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#define FPWM_STATE_FIFO_FULL BIT(3)
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/* pwm_period field */
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#define FPWM_PERIOD_CCR_MASK GENMASK(15, 0)
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/* pwm_ctrl field */
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#define FPWM_CTRL_MODE_OUTPUT BIT(2)
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#define FPWM_CTRL_INTR_COUNTER_ENABLE BIT(3)
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#define FPWM_CTRL_CMP(data) ((data) << 4)
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#define FPWM_CTRL_CMP_MASK GENMASK(6, 4)
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#define FPWM_CTRL_CMP_GET(data) ((data) >> 4)
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#define FPWM_CTRL_DUTY_SOURCE_FIFO BIT(8)
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#define FPWM_CTRL_INTR_FIFO_EMPTY_ENABLE BIT(9)
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/* pwm_ccr field */
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#define FPWM_CCR_MASK GENMASK(15, 0)
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#define FPWM_CCR_GPIO BIT(16)
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/* pwm lsd cfg, lsd pwm sync control */
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#define FLSD_MIO_PWM_SYN_OFFSET 0x20
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#define FLSD_MIO_PWM_SYN_MASK GENMASK(7, 0)
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/***************** Macros (Inline Functions) Definitions *********************/
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/* 读FPWM寄存器 */
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#define FPWM_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)reg_offset)
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/* 写FPWM寄存器 */
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#define FPWM_WRITE_REG32(addr, reg_offset, reg_value) FtOut32((addr) + (u32)reg_offset, (u32)reg_value)
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#define FPWM_SETBIT(base_addr, reg_offset, data) FtSetBit32((base_addr) + (u32)(reg_offset), (u32)(data))
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#define FPWM_CLEARBIT(base_addr, reg_offset, data) FtClearBit32((base_addr) + (u32)(reg_offset), (u32)(data))
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/* enable pwm lsd syn */
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void FPwmLsdEnable(uintptr lsd_addr, u8 pwm_id);
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/* disable pwm lsd syn */
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void FPwmLsdDisable(uintptr lsd_addr, u8 pwm_id);
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#ifdef __cplusplus
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}
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#endif
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#endif |