834 lines
26 KiB
C
834 lines
26 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fpwm.c
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-04-15 11:45:05
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* Description: This file is for the minimum required function implementations for this driver.
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 wangxiaodong 2022/4/15 init commit
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*/
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#include <string.h>
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#include "fkernel.h"
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#include "ftypes.h"
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#include "ferror_code.h"
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#include "fdebug.h"
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#include "fpwm.h"
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#include "fpwm_hw.h"
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#include "fparameters.h"
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#include "fsleep.h"
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#define FPWM_DEBUG_TAG "PWM"
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#define FPWM_ERROR(format, ...) FT_DEBUG_PRINT_E(FPWM_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FPWM_WARN(format, ...) FT_DEBUG_PRINT_W(FPWM_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FPWM_INFO(format, ...) FT_DEBUG_PRINT_I(FPWM_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FPWM_DEBUG(format, ...) FT_DEBUG_PRINT_D(FPWM_DEBUG_TAG, format, ##__VA_ARGS__)
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/**
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* @name: FPwmReset
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* @msg: reset pwm
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @return err code information, FPWM_SUCCESS indicates success，others indicates failed
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*/
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FError FPwmReset(FPwmCtrl *pctrl, u32 channel)
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{
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FASSERT(pctrl != NULL);
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FASSERT(channel < FPWM_CHANNEL_NUM);
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u32 reg_val = 0;
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int timeout = FPWM_RESET_TIMEOUT;
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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reg_val = FPWM_READ_REG32(base_addr, FPWM_TIM_CTRL_OFFSET);
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reg_val |= FPWM_TIM_CTRL_RESET;
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FPWM_WRITE_REG32(base_addr, FPWM_TIM_CTRL_OFFSET, reg_val);
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/* Check for the reset complete*/
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do
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{
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reg_val = FPWM_READ_REG32(base_addr, FPWM_TIM_CTRL_OFFSET);
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}
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while ((FPWM_TIM_CTRL_RESET & reg_val) && (0 <= --timeout));
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if (0 >= timeout)
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{
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FPWM_ERROR("Time out while waiting for pwm reset to complete");
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return FPWM_ERR_TIMEOUT;
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}
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return FPWM_SUCCESS;
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}
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/**
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* @name: FPwmEnable
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* @msg: enable pwm
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @return
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*/
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void FPwmEnable(FPwmCtrl *pctrl, u32 channel)
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{
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FASSERT(pctrl != NULL);
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FASSERT(channel < FPWM_CHANNEL_NUM);
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u32 reg_val = 0;
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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reg_val = FPWM_READ_REG32(base_addr, FPWM_TIM_CTRL_OFFSET);
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reg_val |= FPWM_TIM_CTRL_ENABLE;
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FPWM_WRITE_REG32(base_addr, FPWM_TIM_CTRL_OFFSET, reg_val);
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pctrl->channel_ctrl_enable[channel] = TRUE;
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}
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/**
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* @name: FPwmDisable
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* @msg: disable pwm
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @return
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*/
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void FPwmDisable(FPwmCtrl *pctrl, u32 channel)
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{
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FASSERT(pctrl != NULL);
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FASSERT(channel < FPWM_CHANNEL_NUM);
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u32 reg_val = 0;
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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reg_val = FPWM_READ_REG32(base_addr, FPWM_TIM_CTRL_OFFSET);
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reg_val &= (~FPWM_TIM_CTRL_ENABLE);
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FPWM_WRITE_REG32(base_addr, FPWM_TIM_CTRL_OFFSET, reg_val);
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pctrl->channel_ctrl_enable[channel] = FALSE;
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}
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/**
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* @name: FPwmTimCtrlModeSet
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* @msg: config pwm timer counter mode.
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @param {FPwmTimCtrlMode} mode, counter mode parameters of FPWM
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* @return
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*/
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static void FPwmTimCtrlModeSet(FPwmCtrl *pctrl, u32 channel, FPwmTimCtrlMode mode)
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{
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FASSERT(pctrl != NULL);
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FASSERT(mode < FPWM_TIM_CTRL_MODE_NUM);
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/* check whether the state is disabled */
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FASSERT(pctrl->channel_ctrl_enable[channel] == FALSE);
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u32 reg_val = 0;
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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reg_val = FPWM_READ_REG32(base_addr, FPWM_TIM_CTRL_OFFSET);
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switch (mode)
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{
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/* modulo */
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case FPWM_MODULO:
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reg_val &= (~FPWM_TIM_CTRL_MODE_UD);
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break;
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/* up-and-down */
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case FPWM_UP_DOWN:
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reg_val |= FPWM_TIM_CTRL_MODE_UD;
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break;
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default:
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break;
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}
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FPWM_WRITE_REG32(base_addr, FPWM_TIM_CTRL_OFFSET, reg_val);
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}
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/**
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* @name: FPwmTimInterruptEnable
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* @msg: enable pwm timer global and counter-overflow interrupt
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @return
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*/
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static void FPwmTimInterruptEnable(FPwmCtrl *pctrl, u32 channel)
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{
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FASSERT(pctrl != NULL);
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u32 reg_val = 0;
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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reg_val = FPWM_READ_REG32(base_addr, FPWM_TIM_CTRL_OFFSET);
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reg_val &= (~(FPWM_TIM_CTRL_OVFIF_ENABLE | FPWM_TIM_CTRL_GIE));
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reg_val |= (FPWM_TIM_CTRL_OVFIF_ENABLE | FPWM_TIM_CTRL_GIE);
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FPWM_WRITE_REG32(base_addr, FPWM_TIM_CTRL_OFFSET, reg_val);
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}
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/**
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* @name: FPwmTimInterruptDisable
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* @msg: disable pwm timer global and counter-overflow interrupt
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @return
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*/
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static void FPwmTimInterruptDisable(FPwmCtrl *pctrl, u32 channel)
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{
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FASSERT(pctrl != NULL);
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u32 reg_val = 0;
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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reg_val = FPWM_READ_REG32(base_addr, FPWM_TIM_CTRL_OFFSET);
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reg_val &= (~(FPWM_TIM_CTRL_OVFIF_ENABLE | FPWM_TIM_CTRL_GIE));
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FPWM_WRITE_REG32(base_addr, FPWM_TIM_CTRL_OFFSET, reg_val);
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}
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/**
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* @name: FPwmDivSet
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* @msg: config pwm div, div range：0~4095, corresponding to 1~4096
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @param {u16} div, div parameters
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* @return
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*/
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static void FPwmDivSet(FPwmCtrl *pctrl, u32 channel, u16 div)
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{
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u32 reg_val = 0;
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FASSERT(pctrl != NULL);
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FASSERT(div < FPWM_TIM_CTRL_DIV_MAX);
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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reg_val = FPWM_READ_REG32(base_addr, FPWM_TIM_CTRL_OFFSET);
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reg_val |= (FPWM_TIM_CTRL_DIV_MASK & FPWM_TIM_CTRL_DIV(div));
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FPWM_WRITE_REG32(base_addr, FPWM_TIM_CTRL_OFFSET, reg_val);
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}
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/**
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* @name: FPwmPeriodSet
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* @msg: config pwm period, range：1~0xffff
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @param {u16} pwm_period, period parameters
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* @return err code information, FPWM_SUCCESS indicates success，others indicates failed
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*/
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static void FPwmPeriodSet(FPwmCtrl *pctrl, u32 channel, u16 pwm_period)
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{
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FASSERT(pctrl != NULL);
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u32 reg_val = 0;
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u64 cycles = 0;
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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reg_val = FPWM_READ_REG32(base_addr, FPWM_PERIOD_OFFSET);
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reg_val &= (~FPWM_PERIOD_CCR_MASK);
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reg_val |= (pwm_period & FPWM_PERIOD_CCR_MASK);
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FPWM_WRITE_REG32(base_addr, FPWM_PERIOD_OFFSET, reg_val);
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}
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/**
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* @name: FPwmDutySourceSet
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* @msg: config pwm duty source, from pwm_ccr register or fifo
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @param {FPwmDutySourceMode} duty_source, duty source parameters
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* @return
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*/
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static void FPwmDutySourceSet(FPwmCtrl *pctrl, u32 channel, FPwmDutySourceMode duty_source)
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{
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FASSERT(pctrl != NULL);
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FASSERT(duty_source < FPWM_DUTY_SEL_MODE_NUM);
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u32 reg_val = 0;
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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reg_val = FPWM_READ_REG32(base_addr, FPWM_CTRL_OFFSET);
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switch (duty_source)
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{
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/* duty from PWM_CCR */
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case FPWM_DUTY_CCR:
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reg_val &= (~FPWM_CTRL_DUTY_SOURCE_FIFO);
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break;
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/* from FIFO */
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case FPWM_DUTY_FIFO:
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reg_val |= FPWM_CTRL_DUTY_SOURCE_FIFO;
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break;
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default:
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break;
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}
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FPWM_WRITE_REG32(base_addr, FPWM_CTRL_OFFSET, reg_val);
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}
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/**
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* @name: FPwmPulseSet
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* @msg: config pwm duty, pwm_ccr is less than pwm_period
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @param {u16} pwm_ccr, pwm_ccr parameters
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* @return err code information, FPWM_SUCCESS indicates success，others indicates failed
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*/
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FError FPwmPulseSet(FPwmCtrl *pctrl, u32 channel, u16 pwm_ccr)
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{
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FASSERT(pctrl != NULL);
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FASSERT(channel < FPWM_CHANNEL_NUM);
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u32 reg_val = 0;
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u64 cycles = 0;
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u32 state = 0;
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u16 pwm_period_ccr = 0;
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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/* Check the pwm_ccr < pwm_period_ccr */
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pwm_period_ccr = (u16)FPWM_READ_REG32(base_addr, FPWM_PERIOD_OFFSET);
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if (pwm_ccr > pwm_period_ccr)
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{
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FPWM_ERROR("The pwm ccr is larger than the period");
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return FPWM_ERR_INVAL_PARM;
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}
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reg_val = FPWM_READ_REG32(base_addr, FPWM_CTRL_OFFSET);
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/* Check the duty source */
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if (reg_val & FPWM_CTRL_DUTY_SOURCE_FIFO)
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{
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/* Check the duty fifo is not full */
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state = FPWM_READ_REG32(base_addr, FPWM_STATE_OFFSET);
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if (state & FPWM_STATE_FIFO_FULL)
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{
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FPWM_ERROR("The fifo of the pwm is full");
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return FPWM_ERR_CMD_FAILED;
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}
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}
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reg_val = FPWM_READ_REG32(base_addr, FPWM_CCR_OFFSET);
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reg_val &= (~FPWM_CCR_MASK);
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reg_val |= (pwm_ccr & FPWM_CCR_MASK);
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FPWM_WRITE_REG32(base_addr, FPWM_CCR_OFFSET, reg_val);
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return FPWM_SUCCESS;
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}
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/**
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* @name: FPwmCtrlModeSet
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* @msg: config pwm mode, currently only support compare output
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @return
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*/
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static void FPwmCtrlModeSet(FPwmCtrl *pctrl, u32 channel)
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{
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FASSERT(pctrl != NULL);
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u32 reg_val = 0;
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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reg_val = FPWM_READ_REG32(base_addr, FPWM_CTRL_OFFSET);
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reg_val |= FPWM_CTRL_MODE_OUTPUT;
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FPWM_WRITE_REG32(base_addr, FPWM_CTRL_OFFSET, reg_val);
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}
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/**
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* @name: FPwmPolaritySet
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* @msg: config pwm compare output polarity
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @param {u32} channel, pwm module's channel, 0/1
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* @param {FPwmPolarity} polarity, compare output polarity parameters
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* @return
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*/
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static void FPwmPolaritySet(FPwmCtrl *pctrl, u32 channel, FPwmPolarity polarity)
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{
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FASSERT(pctrl != NULL);
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FASSERT(polarity < FPWM_POLARITY_NUM);
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/* check whether the state is disabled */
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FASSERT(pctrl->channel_ctrl_enable[channel] == FALSE);
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uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
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u32 reg_val = 0;
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reg_val = FPWM_READ_REG32(base_addr, FPWM_CTRL_OFFSET);
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reg_val &= (~FPWM_CTRL_CMP_MASK);
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reg_val |= FPWM_CTRL_CMP(polarity);
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FPWM_WRITE_REG32(base_addr, FPWM_CTRL_OFFSET, reg_val);
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}
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/**
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* @name: FPwmDbReset
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* @msg: reset pwm db
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
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* @return err code information, FPWM_SUCCESS indicates success，others indicates failed
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*/
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static FError FPwmDbReset(FPwmCtrl *pctrl)
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{
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FASSERT(pctrl != NULL);
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u32 reg_val = 0;
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int timeout = FPWM_RESET_TIMEOUT;
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uintptr base_addr = pctrl->config.db_base_addr;
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reg_val = FPWM_READ_REG32(base_addr, FPWM_DB_CTRL_OFFSET);
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reg_val |= FPWM_DB_CTRL_RESET;
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FPWM_WRITE_REG32(base_addr, FPWM_DB_CTRL_OFFSET, reg_val);
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/* Check for the db reset complete*/
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do
|
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{
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reg_val = FPWM_READ_REG32(base_addr, FPWM_DB_CTRL_OFFSET);
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}
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while ((FPWM_DB_CTRL_RESET & reg_val) && (0 <= --timeout));
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if (0 >= timeout)
|
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{
|
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FPWM_ERROR("Time out while waiting for pwm db reset to complete");
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return FPWM_ERR_TIMEOUT;
|
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}
|
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return FPWM_SUCCESS;
|
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}
|
||
|
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/**
|
||
* @name: FPwmDbPolaritySet
|
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* @msg: config pwm db polarity
|
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* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
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* @param {FPwmDbPolarity} db_polarity, db polarity parameters
|
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* @return err code information, FPWM_SUCCESS indicates success，others indicates failed
|
||
*/
|
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FError FPwmDbPolaritySet(FPwmCtrl *pctrl, FPwmDbPolarity db_polarity)
|
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{
|
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FASSERT(pctrl != NULL);
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FASSERT(db_polarity < FPWM_DB_POLARITY_NUM);
|
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u32 reg_val = 0;
|
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uintptr base_addr = pctrl->config.db_base_addr;
|
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reg_val = FPWM_READ_REG32(base_addr, FPWM_DB_CTRL_OFFSET);
|
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reg_val &= (~FPWM_DB_CTRL_POLSEL_MASK);
|
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reg_val |= FPWM_DB_CTRL_POLSEL(db_polarity);
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FPWM_WRITE_REG32(base_addr, FPWM_DB_CTRL_OFFSET, reg_val);
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return FPWM_SUCCESS;
|
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}
|
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|
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/**
|
||
* @name: FPwmDbFallCycleSet
|
||
* @msg: config pwm db fall cycle
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
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* @param {u16} fall_edge_delay, db fall cycle parameters
|
||
* @return
|
||
*/
|
||
static void FPwmDbFallCycleSet(FPwmCtrl *pctrl, u16 fall_edge_delay)
|
||
{
|
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FASSERT(pctrl != NULL);
|
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FASSERT(fall_edge_delay < FPWM_DB_DLY_MAX);
|
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u32 reg_val = 0;
|
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uintptr pwm_base_addr = pctrl->config.pwm_base_addr;
|
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uintptr db_base_addr = pctrl->config.db_base_addr;
|
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|
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u32 pwm_period = FPWM_READ_REG32(pwm_base_addr, FPWM_PERIOD_OFFSET);
|
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|
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reg_val = FPWM_READ_REG32(db_base_addr, FPWM_DB_DLY_OFFSET);
|
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reg_val &= (~FPWM_DB_DLY_FALL_MASK);
|
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reg_val |= FPWM_DB_DLY_FALL(fall_edge_delay);
|
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FPWM_WRITE_REG32(db_base_addr, FPWM_DB_DLY_OFFSET, reg_val);
|
||
}
|
||
|
||
/**
|
||
* @name: FPwmDbRiseCycleSet
|
||
* @msg: config pwm db rise cycle
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
||
* @param {u16} rise_edge_delay, db rise cycle parameters
|
||
* @return
|
||
*/
|
||
static void FPwmDbRiseCycleSet(FPwmCtrl *pctrl, u16 rise_edge_delay)
|
||
{
|
||
FASSERT(pctrl != NULL);
|
||
FASSERT(rise_edge_delay < FPWM_DB_DLY_MAX);
|
||
u32 reg_val = 0;
|
||
uintptr pwm_base_addr = pctrl->config.pwm_base_addr;
|
||
uintptr db_base_addr = pctrl->config.db_base_addr;
|
||
|
||
u32 pwm_period = FPWM_READ_REG32(pwm_base_addr, FPWM_PERIOD_OFFSET);
|
||
|
||
reg_val = FPWM_READ_REG32(db_base_addr, FPWM_DB_DLY_OFFSET);
|
||
reg_val &= (~FPWM_DB_DLY_RISE_MASK);
|
||
reg_val |= (u32)(rise_edge_delay & FPWM_DB_DLY_RISE_MASK);
|
||
FPWM_WRITE_REG32(db_base_addr, FPWM_DB_DLY_OFFSET, reg_val);
|
||
}
|
||
|
||
/**
|
||
* @name: FPwmDbInModeSet
|
||
* @msg: config pwm db in source mode, pwm0 or pwm1
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
||
* @param {FPwmDbInMode} db_in_mode, db in mode parameters
|
||
* @return void
|
||
*/
|
||
static void FPwmDbInModeSet(FPwmCtrl *pctrl, FPwmDbInMode db_in_mode)
|
||
{
|
||
FASSERT(db_in_mode < FPWM_DB_IN_MODE_NUM);
|
||
u32 reg_val = 0;
|
||
uintptr base_addr = pctrl->config.db_base_addr;
|
||
|
||
reg_val = FPWM_READ_REG32(base_addr, FPWM_DB_CTRL_OFFSET);
|
||
switch (db_in_mode)
|
||
{
|
||
case FPWM_DB_IN_MODE_PWM0:
|
||
reg_val &= (~FPWM_DB_CTRL_IN_MODE);
|
||
break;
|
||
case FPWM_DB_IN_MODE_PWM1:
|
||
reg_val |= FPWM_DB_CTRL_IN_MODE;
|
||
break;
|
||
default:
|
||
break;
|
||
}
|
||
|
||
FPWM_WRITE_REG32(base_addr, FPWM_DB_CTRL_OFFSET, reg_val);
|
||
}
|
||
|
||
static void FPwmDbOutModeSet(FPwmCtrl *pctrl, FPwmDbOutMode db_out_mode)
|
||
{
|
||
FASSERT(db_out_mode < FPWM_DB_OUT_MODE_NUM);
|
||
u32 reg_val = 0;
|
||
uintptr base_addr = pctrl->config.db_base_addr;
|
||
|
||
reg_val = FPWM_READ_REG32(base_addr, FPWM_DB_CTRL_OFFSET);
|
||
reg_val &= (~FPWM_DB_CTRL_OUT_MODE_MASK);
|
||
reg_val |= FPWM_DB_CTRL_OUT_MODE(db_out_mode);
|
||
FPWM_WRITE_REG32(base_addr, FPWM_DB_CTRL_OFFSET, reg_val);
|
||
}
|
||
|
||
/**
|
||
* @name: FPwmInterruptEnable
|
||
* @msg: enable pwm compare output interrupt
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
||
* @param {u32} channel, pwm module's channel, 0/1
|
||
* @param {FPwmIntrEventType} intr_type, pwm interrupt event type
|
||
* @return
|
||
*/
|
||
void FPwmInterruptEnable(FPwmCtrl *pctrl, u32 channel, FPwmIntrEventType intr_type)
|
||
{
|
||
FASSERT(pctrl != NULL);
|
||
FASSERT(channel < FPWM_CHANNEL_NUM);
|
||
u32 reg_val = 0;
|
||
uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
|
||
|
||
reg_val = FPWM_READ_REG32(base_addr, FPWM_CTRL_OFFSET);
|
||
|
||
if (intr_type == FPWM_INTR_EVENT_COUNTER)
|
||
{
|
||
reg_val &= (~FPWM_CTRL_INTR_COUNTER_ENABLE);
|
||
reg_val |= FPWM_CTRL_INTR_COUNTER_ENABLE;
|
||
}
|
||
|
||
if (intr_type == FPWM_INTR_EVENT_FIFO_EMPTY)
|
||
{
|
||
reg_val &= (~FPWM_CTRL_INTR_FIFO_EMPTY_ENABLE);
|
||
reg_val |= FPWM_CTRL_INTR_FIFO_EMPTY_ENABLE;
|
||
}
|
||
|
||
FPWM_WRITE_REG32(base_addr, FPWM_CTRL_OFFSET, reg_val);
|
||
}
|
||
|
||
/**
|
||
* @name: FPwmInterruptDisable
|
||
* @msg: disable pwm compare output interrupt
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
||
* @param {u32} channel, pwm module's channel, 0/1
|
||
* @param {FPwmIntrEventType} intr_type, pwm interrupt event type
|
||
* @return
|
||
*/
|
||
void FPwmInterruptDisable(FPwmCtrl *pctrl, u32 channel, FPwmIntrEventType intr_type)
|
||
{
|
||
FASSERT(pctrl != NULL);
|
||
FASSERT(channel < FPWM_CHANNEL_NUM);
|
||
u32 reg_val = 0;
|
||
uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
|
||
|
||
reg_val = FPWM_READ_REG32(base_addr, FPWM_CTRL_OFFSET);
|
||
|
||
if (intr_type == FPWM_INTR_EVENT_COUNTER)
|
||
{
|
||
reg_val &= (~FPWM_CTRL_INTR_COUNTER_ENABLE);
|
||
}
|
||
|
||
if (intr_type == FPWM_INTR_EVENT_FIFO_EMPTY)
|
||
{
|
||
reg_val &= (~FPWM_CTRL_INTR_FIFO_EMPTY_ENABLE);
|
||
}
|
||
|
||
FPWM_WRITE_REG32(base_addr, FPWM_CTRL_OFFSET, reg_val);
|
||
}
|
||
|
||
/**
|
||
* @name: FPwmDbVariableSet
|
||
* @msg: set pwm db Variable config, users need call this function before
|
||
* FPwmVariableSet if you want to use deadband function.
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
||
* @param {FPwmDbVariableConfig} db_cfg_p, db config parameters, include mode and cycles
|
||
* @return err code information, FPWM_SUCCESS indicates success，others indicates failed
|
||
*/
|
||
FError FPwmDbVariableSet(FPwmCtrl *pctrl, FPwmDbVariableConfig *db_cfg_p)
|
||
{
|
||
FASSERT(pctrl != NULL);
|
||
FASSERT(db_cfg_p != NULL);
|
||
|
||
FError ret = FPWM_SUCCESS;
|
||
|
||
ret = FPwmDbReset(pctrl);
|
||
if (ret != FPWM_SUCCESS)
|
||
{
|
||
FPWM_ERROR("%s ,The FPwmDbReset call failed",__func__);
|
||
return FPWM_ERR_CMD_FAILED;
|
||
}
|
||
|
||
FPwmDbRiseCycleSet(pctrl, db_cfg_p->db_rise_cycle);
|
||
|
||
FPwmDbFallCycleSet(pctrl, db_cfg_p->db_fall_cycle);
|
||
|
||
ret = FPwmDbPolaritySet(pctrl, db_cfg_p->db_polarity_sel);
|
||
if (ret != FPWM_SUCCESS)
|
||
{
|
||
FPWM_ERROR("%s ,The FPwmDbPolaritySet call failed",__func__);
|
||
return FPWM_ERR_CMD_FAILED;
|
||
}
|
||
|
||
FPwmDbInModeSet(pctrl, db_cfg_p->db_in_mode);
|
||
|
||
FPwmDbOutModeSet(pctrl, db_cfg_p->db_out_mode);
|
||
|
||
return ret;
|
||
}
|
||
|
||
/**
|
||
* @name: FPwmDbVariableGet
|
||
* @msg: get pwm deadband variable configuration.
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
||
* @param {FPwmDbVariableConfig} *db_cfg_p, pwm deadband config parameters
|
||
* @return err code information, FPWM_SUCCESS indicates success，others indicates failed
|
||
*/
|
||
FError FPwmDbVariableGet(FPwmCtrl *pctrl, FPwmDbVariableConfig *db_cfg_p)
|
||
{
|
||
FASSERT(pctrl != NULL);
|
||
FASSERT(db_cfg_p != NULL);
|
||
FError ret = FPWM_SUCCESS;
|
||
|
||
uintptr db_base_addr = pctrl->config.db_base_addr;
|
||
|
||
u32 db_ctrl = FPWM_READ_REG32(db_base_addr, FPWM_DB_CTRL_OFFSET);
|
||
/* db input source*/
|
||
db_cfg_p->db_in_mode =
|
||
(db_ctrl & FPWM_DB_CTRL_IN_MODE) ? FPWM_DB_IN_MODE_PWM1 : FPWM_DB_IN_MODE_PWM0;
|
||
|
||
/* db polarity select*/
|
||
db_cfg_p->db_polarity_sel = FPWM_DB_CTRL_POLSEL_GET(db_ctrl & FPWM_DB_CTRL_POLSEL_MASK);
|
||
/* db output mode*/
|
||
db_cfg_p->db_out_mode = FPWM_DB_CTRL_OUT_MODE_GET(db_ctrl & FPWM_DB_CTRL_OUT_MODE_MASK);
|
||
|
||
u32 db_dly = FPWM_READ_REG32(db_base_addr, FPWM_DB_DLY_OFFSET);
|
||
/* db falling edge delay cycle */
|
||
db_cfg_p->db_fall_cycle = FPWM_DB_DLY_FALL_GET(db_dly & FPWM_DB_DLY_FALL_MASK);
|
||
/* db rising edge delay cycle */
|
||
db_cfg_p->db_rise_cycle = (db_dly & FPWM_DB_DLY_RISE_MASK);
|
||
|
||
return ret;
|
||
|
||
}
|
||
|
||
/**
|
||
* @name: FPwmVariableSet
|
||
* @msg: set pwm channel variable configuration, users need call this function after
|
||
* FPwmDbVariableSet if you want to use deadband function.
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
||
* @param {u32} channel, pwm module's channel, 0/1
|
||
* @param {FPwmVariableConfig} pwm_cfg_p, pwm config parameters, include mode and duty
|
||
* @return err code information, FPWM_SUCCESS indicates success，others indicates failed
|
||
*/
|
||
FError FPwmVariableSet(FPwmCtrl *pctrl, u32 channel, FPwmVariableConfig *pwm_cfg_p)
|
||
{
|
||
FASSERT(pctrl != NULL);
|
||
FASSERT(channel < FPWM_CHANNEL_NUM);
|
||
FASSERT(pwm_cfg_p != NULL);
|
||
FError ret = FPWM_SUCCESS;
|
||
|
||
#if defined(FLSD_CONFIG_BASE)
|
||
/* enable lsd pwm syn */
|
||
FPwmLsdEnable(FLSD_CONFIG_BASE, pctrl->config.instance_id);
|
||
#endif
|
||
/* bit[0]:set pwm_tim_ctrl SW_RST */
|
||
ret = FPwmReset(pctrl, channel);
|
||
if (ret != FPWM_SUCCESS)
|
||
{
|
||
FPWM_ERROR("%s ,FPwmReset call failed",__func__);
|
||
return FPWM_ERR_CMD_FAILED;
|
||
}
|
||
|
||
/* pwm timer ctrl disable, before can config */
|
||
FPwmDisable(pctrl, channel);
|
||
|
||
/* bit[2]:set tim_ctrl Mode */
|
||
FPwmTimCtrlModeSet(pctrl, channel, pwm_cfg_p->tim_ctrl_mode);
|
||
|
||
/* bit[4,5]:set tim_ctrl interrput */
|
||
FPwmTimInterruptEnable(pctrl, channel);
|
||
|
||
/*bit[16~27]: set tim_ctrl DIV 0~4095 */
|
||
FPwmDivSet(pctrl, channel, pwm_cfg_p->tim_ctrl_div);
|
||
|
||
/*bit[0~15]: set pwm_period */
|
||
FPwmPeriodSet(pctrl, channel, pwm_cfg_p->pwm_period);
|
||
|
||
/*bit[2]:pwm control mode, input capture or output compare */
|
||
FPwmCtrlModeSet(pctrl, channel);
|
||
|
||
/*bit[3]:pwm control mode irq */
|
||
FPwmInterruptEnable(pctrl, channel, FPWM_INTR_EVENT_COUNTER);
|
||
FPwmInterruptEnable(pctrl, channel, FPWM_INTR_EVENT_FIFO_EMPTY);
|
||
|
||
/*bit[4~6]:pwm ctrl polarity config CMP:0b100*/
|
||
FPwmPolaritySet(pctrl, channel, pwm_cfg_p->pwm_polarity);
|
||
|
||
/*bit[8]:pwm duty source , duty from ccr or fifo */
|
||
FPwmDutySourceSet(pctrl, channel, pwm_cfg_p->pwm_duty_source_mode);
|
||
|
||
/*pwm pulse set, duty */
|
||
ret = FPwmPulseSet(pctrl, channel, pwm_cfg_p->pwm_pulse);
|
||
if (ret != FPWM_SUCCESS)
|
||
{
|
||
FPWM_ERROR("%s , FPwmPulseSet failed",__func__);
|
||
return FPWM_ERR_CMD_FAILED;
|
||
}
|
||
|
||
return ret;
|
||
}
|
||
|
||
/**
|
||
* @name: FPwmVariableGet
|
||
* @msg: get pwm channel variable configuration.
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
||
* @param {u32} channel, pwm module's channel, 0/1
|
||
* @param {FPwmVariableConfig} *pwm_cfg_p, pwm config parameters, include mode and duty
|
||
* @return err code information, FPWM_SUCCESS indicates success，others indicates failed
|
||
*/
|
||
FError FPwmVariableGet(FPwmCtrl *pctrl, u32 channel, FPwmVariableConfig *pwm_cfg_p)
|
||
{
|
||
FASSERT(pctrl != NULL);
|
||
FASSERT(channel < FPWM_CHANNEL_NUM);
|
||
FASSERT(pwm_cfg_p != NULL);
|
||
FError ret = FPWM_SUCCESS;
|
||
|
||
uintptr pwm_base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
|
||
|
||
u32 tim_ctrl = FPWM_READ_REG32(pwm_base_addr, FPWM_TIM_CTRL_OFFSET);
|
||
/* tim_ctrl mode, counter mode */
|
||
pwm_cfg_p->tim_ctrl_mode =
|
||
(tim_ctrl & FPWM_TIM_CTRL_MODE_UD) ? FPWM_UP_DOWN : FPWM_MODULO;
|
||
/* pwm divider */
|
||
pwm_cfg_p->tim_ctrl_div = FPWM_TIM_CTRL_DIV_GET(tim_ctrl & FPWM_TIM_CTRL_DIV_MASK);
|
||
|
||
/* pwm period value */
|
||
u32 pwm_period = FPWM_READ_REG32(pwm_base_addr, FPWM_PERIOD_OFFSET) ;
|
||
pwm_cfg_p->pwm_period = (u16)(pwm_period & FPWM_PERIOD_CCR_MASK);
|
||
|
||
u32 pwm_ctrl = FPWM_READ_REG32(pwm_base_addr, FPWM_CTRL_OFFSET);
|
||
/* pwm mode, compare output */
|
||
pwm_cfg_p->pwm_mode =
|
||
(pwm_ctrl & FPWM_CTRL_MODE_OUTPUT) ? FPWM_OUTPUT_COMPARE : FPWM_NONE_MODE;
|
||
|
||
/* pwm compare output polarity */
|
||
pwm_cfg_p->pwm_polarity = FPWM_CTRL_CMP_GET(pwm_ctrl & FPWM_CTRL_CMP_MASK);
|
||
|
||
/* pwm duty value source */
|
||
pwm_cfg_p->pwm_duty_source_mode =
|
||
(pwm_ctrl & FPWM_CTRL_DUTY_SOURCE_FIFO) ? FPWM_DUTY_FIFO : FPWM_DUTY_CCR;
|
||
|
||
/* pwm pulse value */
|
||
u32 pwm_ccr = FPWM_READ_REG32(pwm_base_addr, FPWM_CCR_OFFSET);
|
||
pwm_cfg_p->pwm_pulse = (u16)(pwm_ccr & FPWM_CCR_MASK);
|
||
|
||
return ret;
|
||
}
|
||
|
||
/**
|
||
* @name: FPwmDeInitialize
|
||
* @msg: DeInitialization function for the device instance
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
||
* @return {*}
|
||
*/
|
||
void FPwmDeInitialize(FPwmCtrl *pctrl)
|
||
{
|
||
FASSERT(pctrl);
|
||
|
||
pctrl->is_ready = 0;
|
||
memset(pctrl, 0, sizeof(*pctrl));
|
||
|
||
return;
|
||
}
|
||
|
||
/**
|
||
* @name: FPwmCfgInitialize
|
||
* @msg: Initializes a specific instance such that it is ready to be used.
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
||
* @param {FPwmConfig} *input_config_p, Configuration parameters of FPWM
|
||
* @return err code information, FPWM_SUCCESS indicates success，others indicates failed
|
||
*/
|
||
FError FPwmCfgInitialize(FPwmCtrl *pctrl, const FPwmConfig *input_config_p)
|
||
{
|
||
FASSERT(pctrl && input_config_p);
|
||
|
||
FError ret = FPWM_SUCCESS;
|
||
/*
|
||
* If the device is started, disallow the initialize and return a Status
|
||
* indicating it is started. This allows the user to de-initialize the device
|
||
* and reinitialize, but prevents a user from inadvertently
|
||
* initializing.
|
||
*/
|
||
if (FT_COMPONENT_IS_READY == pctrl->is_ready)
|
||
{
|
||
FPWM_WARN("The device has been initialized!!!");
|
||
}
|
||
|
||
/*Set default values and configuration data */
|
||
FPwmDeInitialize(pctrl);
|
||
|
||
pctrl->config = *input_config_p;
|
||
#if defined(CONFIG_TARGET_E2000)
|
||
ret = FPwmDbReset(pctrl);
|
||
if (ret != FPWM_SUCCESS)
|
||
{
|
||
FPWM_ERROR("%s ,The FPwmDbReset call failed");
|
||
return FPWM_ERR_CMD_FAILED;
|
||
}
|
||
#endif
|
||
pctrl->is_ready = FT_COMPONENT_IS_READY;
|
||
|
||
return ret;
|
||
}
|
||
|
||
/**
|
||
* @name: FPwmGpioSet
|
||
* @msg: Control gpio output
|
||
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
|
||
* @param {u32} channel, pwm module's channel, 0/1
|
||
* @param {u32} output, set high or low level, 0-low, 1-high
|
||
* @return void
|
||
*/
|
||
void FPwmGpioSet(FPwmCtrl *pctrl, u32 channel, u32 output)
|
||
{
|
||
FASSERT(pctrl != NULL);
|
||
u32 reg_val = 0;
|
||
uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
|
||
|
||
reg_val = FPWM_READ_REG32(base_addr, FPWM_CCR_OFFSET);
|
||
if(output)
|
||
reg_val |= FPWM_CCR_GPIO;
|
||
else
|
||
reg_val &= (~FPWM_CCR_GPIO);
|
||
FPWM_WRITE_REG32(base_addr, FPWM_CCR_OFFSET, reg_val);
|
||
|
||
} |