345 lines
13 KiB
C
345 lines
13 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fgmac_dma.c
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* Date: 2022-04-06 14:46:52
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* LastEditTime: 2022-04-06 14:46:58
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* Description: This file implements dma descriptor ring related functions.
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 huanghe 2021/06/04 first release
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*/
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/***************************** Include Files *********************************/
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#include <string.h>
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#include "fassert.h"
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#include "fkernel.h"
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#include "fcache.h"
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#include "fdebug.h"
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#include "fgmac.h"
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#include "fgmac_hw.h"
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/************************** Constant Definitions *****************************/
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#if defined(__aarch64__)
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#define FGMAC_DMA_IS_64_BIT_MEMORY(addr) (GENMASK_ULL(63, 32) & (uintptr)(addr))
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#else
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#define FGMAC_DMA_IS_64_BIT_MEMORY(addr) (FALSE)
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#endif
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FGMAC_DEBUG_TAG "FGMAC-DMA"
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#define FGMAC_ERROR(format, ...) FT_DEBUG_PRINT_E(FGMAC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FGMAC_WARN(format, ...) FT_DEBUG_PRINT_W(FGMAC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FGMAC_INFO(format, ...) FT_DEBUG_PRINT_I(FGMAC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FGMAC_DEBUG(format, ...) FT_DEBUG_PRINT_D(FGMAC_DEBUG_TAG, format, ##__VA_ARGS__)
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes ******************************/
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/**
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* @name: FGmacSetupTxDescRing
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* @msg: 配置FGMAC的接收DMA描述符和缓冲区
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* @param {FGmac *}instance_p 驱动控制数据
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* {volatile FGmacDmaDesc *} rx_desc_tbl 接收DMA描述符表(数组)
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* {u8} *rx_buf 接收DMA缓冲区(数组，每一个描述符对应一个缓冲区)
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* {const fsize_t} rx_pre_buf_len 单个DMA缓冲区的字节数
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* {const fsize_t} rx_buf_num DMA描述符或者DMA缓存区的数目
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* @return {FError} RX DMA初始化的错误码信息，FGMAC_SUCCESS 表示RX DMA初始化成功，其它返回值表示RX DMA初始化失败
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* @note 传入的rx_desc_tbl和rx_buf必须为32位空间地址
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*/
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FError FGmacSetupRxDescRing(FGmac *instance_p, volatile FGmacDmaDesc *rx_desc_tbl,
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u8 *rx_buf, const fsize_t rx_pre_buf_len, const fsize_t rx_buf_num)
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{
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FASSERT(instance_p && rx_desc_tbl && rx_buf);
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u32 i;
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volatile FGmacDmaDesc *cur_rx_desc;
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FGmacRingDescData *rx_ring_p = &instance_p->rx_ring;
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uintptr base_addr = instance_p->config.base_addr;
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void *desc_end = (void *)(rx_desc_tbl + rx_buf_num * sizeof(FGmacDmaDesc));
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void *buf_end = (void *)(rx_buf + rx_buf_num * rx_pre_buf_len);
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/* check if end address of descriptor or buffer is in 64 bit memory,
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if TRUE, return error because DMA register can only hold 32 bit memory address */
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if ((FGMAC_DMA_IS_64_BIT_MEMORY(desc_end)) || (FGMAC_DMA_IS_64_BIT_MEMORY(buf_end)))
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{
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FGMAC_ERROR("Invalid rx descriptor memory %p or rx dma buf memory %p",
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desc_end, buf_end);
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return FGMAC_ERR_INVALID_DMA_MEM;
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}
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/* init rx dma ring data */
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memset(rx_ring_p, 0, sizeof(*rx_ring_p));
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rx_ring_p->desc_max_num = rx_buf_num; /* total num of rx desc and rx buf */
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rx_ring_p->desc_idx = 0; /* idx of rx desc */
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rx_ring_p->desc_buf_idx = 0; /* idx of rx buf */
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rx_ring_p->desc_buf_base = rx_buf; /* base addr of rx buf */
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/* init rx dma descriptor table */
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memset((void *)rx_desc_tbl, 0, sizeof(FGmacDmaDesc) * rx_buf_num);
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for (i = 0; i < rx_buf_num; i++)
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{
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cur_rx_desc = rx_desc_tbl + i;
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cur_rx_desc->status = FGMAC_DMA_RDES0_OWN;
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cur_rx_desc->ctrl = (FGMAC_DMA_RDES1_BUFFER1_SIZE_MASK & rx_pre_buf_len);
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FCacheDCacheInvalidateRange((uintptr)&rx_buf[i * rx_pre_buf_len], rx_pre_buf_len);
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cur_rx_desc->buf_addr = (u32)((uintptr)&rx_buf[i * rx_pre_buf_len]);
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if ((rx_buf_num - 1) == i)
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{
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cur_rx_desc->ctrl |= FGMAC_DMA_RDES1_END_RING;
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}
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}
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/* flush descriptor */
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instance_p->rx_desc = rx_desc_tbl;
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FCacheDCacheInvalidateRange((uintptr)instance_p->rx_desc, sizeof(FGmacDmaDesc) * rx_buf_num);
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FGMAC_WRITE_REG32(base_addr, FGMAC_DMA_RX_LIST_BASE_OFFSET, (u32)(uintptr)rx_desc_tbl);
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return FGMAC_SUCCESS;
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}
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/**
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* @name: FGmacSetupTxDescRing
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* @msg: 配置FGMAC的发送DMA描述符和缓冲区
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* @param {FGmac *}instance_p 驱动控制数据
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* {volatile FGmacDmaDesc *} tx_desc_tbl 发送DMA描述符表(数组)
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* {u8} *tx_buf 发送DMA缓冲区(数组，每一个描述符对应一个缓冲区)
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* {const fsize_t} tx_pre_buf_len 单个DMA缓冲区的字节数
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* {const fsize_t} tx_buf_num DMA描述符或者DMA缓存区的数目
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* @return {FError} TX DMA初始化的错误码信息，FGMAC_SUCCESS 表示TX DMA初始化成功，其它返回值表示TX DMA初始化失败
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* @note 传入的tx_desc_tbl和tx_buf必须为32位空间地址
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*/
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FError FGmacSetupTxDescRing(FGmac *instance_p, volatile FGmacDmaDesc *tx_desc_tbl,
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u8 *tx_buf, const fsize_t tx_pre_buf_len, const fsize_t tx_buf_num)
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{
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FASSERT(instance_p && tx_desc_tbl && tx_buf);
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u32 i;
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volatile FGmacDmaDesc *cur_tx_desc;
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FGmacRingDescData *tx_ring_p = &instance_p->tx_ring;
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uintptr base_addr = instance_p->config.base_addr;
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void *desc_end = (void *)(tx_desc_tbl + tx_buf_num * sizeof(FGmacDmaDesc));
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void *buf_end = (void *)(tx_buf + tx_buf_num * tx_pre_buf_len);
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/* check if end address of descriptor or buffer is in 64 bit memory,
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if TRUE, return error because DMA register can only hold 32 bit memory address */
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if ((FGMAC_DMA_IS_64_BIT_MEMORY(desc_end)) || (FGMAC_DMA_IS_64_BIT_MEMORY(buf_end)))
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{
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FGMAC_ERROR("Invalid rx descriptor memory %p or rx dma buf memory %p",
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desc_end, buf_end);
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return FGMAC_ERR_INVALID_DMA_MEM;
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}
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/* setup DMA descriptor ring data */
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memset(tx_ring_p, 0, sizeof(*tx_ring_p));
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tx_ring_p->desc_max_num = tx_buf_num;
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tx_ring_p->desc_idx = 0;
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tx_ring_p->desc_buf_idx = 0;
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tx_ring_p->desc_buf_base = tx_buf;
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/* setup DMA descriptor */
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memset((void *)tx_desc_tbl, 0, tx_buf_num * sizeof(FGmacDmaDesc));
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tx_desc_tbl[tx_buf_num - 1].ctrl |= FGMAC_DMA_TDES1_END_RING;
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for (i = 0; i < tx_buf_num; i++)
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{
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cur_tx_desc = tx_desc_tbl + i;
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FCacheDCacheInvalidateRange((uintptr)&tx_buf[i * tx_pre_buf_len], tx_pre_buf_len);
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cur_tx_desc->buf_addr = (u32)((uintptr)&tx_buf[i * tx_pre_buf_len]);
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cur_tx_desc->status = 0;
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}
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/* flush descriptor */
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instance_p->tx_desc = tx_desc_tbl;
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FCacheDCacheInvalidateRange((uintptr)instance_p->tx_desc, tx_buf_num * sizeof(FGmacDmaDesc));
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FGMAC_WRITE_REG32(base_addr, FGMAC_DMA_TX_LIST_BASE_OFFSET, (u32)(uintptr)tx_desc_tbl);
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return FGMAC_SUCCESS;
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}
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/**
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* @name: FGmacStartTrans
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* @msg: 使能FGMAC DMA，使之可以接收/发送数据
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* @return {FError} FGMAC_SUCCESS 表示启动成功，其它返回值表示启动失败
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* @param {FGmac} *instance_p 驱动控制数据
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* @note 调用函数前需要确保FGMAC驱动初始化成功
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*/
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FError FGmacStartTrans(FGmac *instance_p)
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{
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FASSERT(instance_p);
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if (FT_COMPONENT_IS_READY != instance_p->is_ready)
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{
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FGMAC_ERROR("Device is already initialized!!!");
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return FGMAC_ERR_NOT_READY;
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}
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FGmacStartDmaTrans(instance_p->config.base_addr);
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return FGMAC_SUCCESS;
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}
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/**
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* @name: FGmacStopTrans
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* @msg: 去使能FGMAC DMA, 使之不再能接收/发送数据
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* @return {FError} FGMAC_SUCCESS 表示去启动成功，其它返回值表示去启动失败
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* @param {FGmac} *instance_p 驱动控制数据
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* @note 调用函数前需要确保FGMAC驱动初始化成功
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*/
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FError FGmacStopTrans(FGmac *instance_p)
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{
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FASSERT(instance_p);
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if (FT_COMPONENT_IS_READY != instance_p->is_ready)
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{
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FGMAC_ERROR("Device is already initialized!!!");
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return FGMAC_ERR_NOT_READY;
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}
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FGmacStopDmaTrans(instance_p->config.base_addr);
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return FGMAC_SUCCESS;
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}
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/**
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* @name: FGmacRecvFrame
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* @msg: 通过FGMAC接收数据帧
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* @return {FError} FGMAC_SUCCESS 表示接收数据帧成功，其它返回值表示接收数据帧失败
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* @param {FGmac} *instance_p 驱动控制数据
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* @note 调用函数前需要确保FGMAC驱动初始化成功
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*/
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FError FGmacRecvFrame(FGmac *instance_p)
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{
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FASSERT(instance_p);
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FGmacRingDescData *rx_ring = &instance_p->rx_ring;
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volatile FGmacDmaDesc *cur_rx_desc = &instance_p->rx_desc[rx_ring->desc_idx];
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u32 desc_cnt = 0;
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u32 flag = (FGMAC_DMA_RDES0_FIRST_DESCRIPTOR | FGMAC_DMA_RDES0_LAST_DESCRIPTOR);
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while ((0 == (FGMAC_DMA_RDES0_OWN & cur_rx_desc->status)) &&
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(desc_cnt < rx_ring->desc_max_num))
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{
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desc_cnt++;
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if (FGMAC_DMA_RDES0_FIRST_DESCRIPTOR == (flag & cur_rx_desc->status))
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{
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rx_ring->desc_buf_idx = rx_ring->desc_idx;
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FGMAC_DMA_INC_DESC(rx_ring->desc_idx, rx_ring->desc_max_num);
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cur_rx_desc = &instance_p->rx_desc[rx_ring->desc_idx];
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}
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else if (0 == (flag & cur_rx_desc->status))
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{
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FGMAC_DMA_INC_DESC(rx_ring->desc_idx, rx_ring->desc_max_num);
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cur_rx_desc = &instance_p->rx_desc[rx_ring->desc_idx];
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}
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else
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{
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rx_ring->desc_buf_idx = rx_ring->desc_idx;
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FGMAC_DMA_INC_DESC(rx_ring->desc_idx, rx_ring->desc_max_num);
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return FGMAC_SUCCESS;
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}
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}
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return FGMAC_ERR_TRANS_FAILED;
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}
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/**
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* @name: FGmacSendFrame
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* @msg: 通过FGMAC发送数据帧
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* @return {FError} FGMAC_SUCCESS 表示发送数据帧成功，其它返回值表示发送数据帧失败
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* @param {FGmac} *instance_p 驱动控制数据
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* @param {u32} frame_len 数据帧长度
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* @note 调用函数前需要确保FGMAC驱动初始化成功
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*/
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FError FGmacSendFrame(FGmac *instance_p, u32 frame_len)
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{
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FASSERT(instance_p);
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u32 size = 0U;
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u32 i = 0U;
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u32 buf_cnt = 0U;
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FError ret = FGMAC_SUCCESS;
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volatile FGmacDmaDesc *tx_desc;
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FGmacRingDescData *tx_ring = &instance_p->tx_ring;
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const u32 max_packet_size = instance_p->config.max_packet_size;
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if (0U == frame_len)
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{
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return FGMAC_SUCCESS;
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}
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if (max_packet_size < frame_len)
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{
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buf_cnt = frame_len / max_packet_size;
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if (frame_len % max_packet_size)
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{
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buf_cnt++;
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}
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}
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else
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{
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buf_cnt = 1U;
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}
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if (1U == buf_cnt)
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{
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tx_desc = &instance_p->tx_desc[tx_ring->desc_idx];
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/* Set LAST and FIRST segment */
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tx_desc->ctrl |= (FGMAC_DMA_TDES1_FIRST_SEGMENT | FGMAC_DMA_TDES1_LAST_SEGMENT);
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/* Set frame size */
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tx_desc->ctrl &= ~(FGMAC_DMA_TDES1_BUFFER1_SIZE_MASK);
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tx_desc->ctrl |= (frame_len & FGMAC_DMA_TDES1_BUFFER1_SIZE_MASK);
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/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
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tx_desc->status |= FGMAC_DMA_TDES0_OWN;
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FGMAC_DMA_INC_DESC(tx_ring->desc_idx, tx_ring->desc_max_num);
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}
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else
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{
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for (i = 0U; i < buf_cnt; i++)
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{
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tx_desc = &instance_p->tx_desc[tx_ring->desc_idx];
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/* Clear FIRST and LAST segment bits */
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tx_desc->ctrl &= ~(FGMAC_DMA_TDES1_FIRST_SEGMENT | FGMAC_DMA_TDES1_LAST_SEGMENT);
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if (0U == i)
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{
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tx_desc->ctrl |= FGMAC_DMA_TDES1_FIRST_SEGMENT; /* Setting the first segment bit */
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}
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/* Program size */
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tx_desc->ctrl &= ~(FGMAC_DMA_TDES1_BUFFER1_SIZE_MASK);
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tx_desc->ctrl |= (max_packet_size & FGMAC_DMA_TDES1_BUFFER1_SIZE_MASK);
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if ((buf_cnt - 1) == i)
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{
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/* Setting the last segment bit */
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tx_desc->ctrl |= FGMAC_DMA_TDES1_LAST_SEGMENT;
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size = frame_len - (buf_cnt - 1U) * max_packet_size;
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tx_desc->ctrl &= ~(FGMAC_DMA_TDES1_BUFFER1_SIZE_MASK);
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tx_desc->ctrl |= (size & FGMAC_DMA_TDES1_BUFFER1_SIZE_MASK);
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}
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/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
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tx_desc->status |= FGMAC_DMA_TDES0_OWN;
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FGMAC_DMA_INC_DESC(tx_ring->desc_idx, tx_ring->desc_max_num);
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}
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}
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FGmacResumeDmaSend(instance_p->config.base_addr);
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return ret;
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} |