225 lines
11 KiB
C
225 lines
11 KiB
C
//*****************************************************************************
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//
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// hw_i2s.h - Macros for use in accessing the I2S registers.
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//
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// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 8264 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_I2S_H__
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#define __HW_I2S_H__
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//*****************************************************************************
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//
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// The following are defines for the Inter-Integrated Circuit Sound register
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// offsets.
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//
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//*****************************************************************************
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#define I2S_O_TXFIFO 0x00000000 // I2S Transmit FIFO Data
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#define I2S_O_TXFIFOCFG 0x00000004 // I2S Transmit FIFO Configuration
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#define I2S_O_TXCFG 0x00000008 // I2S Transmit Module
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// Configuration
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#define I2S_O_TXLIMIT 0x0000000C // I2S Transmit FIFO Limit
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#define I2S_O_TXISM 0x00000010 // I2S Transmit Interrupt Status
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// and Mask
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#define I2S_O_TXLEV 0x00000018 // I2S Transmit FIFO Level
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#define I2S_O_RXFIFO 0x00000800 // I2S Receive FIFO Data
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#define I2S_O_RXFIFOCFG 0x00000804 // I2S Receive FIFO Configuration
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#define I2S_O_RXCFG 0x00000808 // I2S Receive Module Configuration
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#define I2S_O_RXLIMIT 0x0000080C // I2S Receive FIFO Limit
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#define I2S_O_RXISM 0x00000810 // I2S Receive Interrupt Status and
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// Mask
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#define I2S_O_RXLEV 0x00000818 // I2S Receive FIFO Level
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#define I2S_O_CFG 0x00000C00 // I2S Module Configuration
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#define I2S_O_IM 0x00000C10 // I2S Interrupt Mask
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#define I2S_O_RIS 0x00000C14 // I2S Raw Interrupt Status
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#define I2S_O_MIS 0x00000C18 // I2S Masked Interrupt Status
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#define I2S_O_IC 0x00000C1C // I2S Interrupt Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_TXFIFO register.
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//
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//*****************************************************************************
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#define I2S_TXFIFO_M 0xFFFFFFFF // TX Data
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#define I2S_TXFIFO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_TXFIFOCFG
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// register.
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//
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//*****************************************************************************
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#define I2S_TXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size
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#define I2S_TXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_TXCFG register.
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//
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//*****************************************************************************
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#define I2S_TXCFG_JST 0x20000000 // Justification of Output Data
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#define I2S_TXCFG_DLY 0x10000000 // Data Delay
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#define I2S_TXCFG_SCP 0x08000000 // SCLK Polarity
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#define I2S_TXCFG_LRP 0x04000000 // Left/Right Clock Polarity
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#define I2S_TXCFG_WM_M 0x03000000 // Write Mode
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#define I2S_TXCFG_WM_DUAL 0x00000000 // Stereo mode
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#define I2S_TXCFG_WM_COMPACT 0x01000000 // Compact Stereo mode
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#define I2S_TXCFG_WM_MONO 0x02000000 // Mono mode
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#define I2S_TXCFG_FMT 0x00800000 // FIFO Empty
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#define I2S_TXCFG_MSL 0x00400000 // SCLK Master/Slave
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#define I2S_TXCFG_SSZ_M 0x0000FC00 // Sample Size
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#define I2S_TXCFG_SDSZ_M 0x000003F0 // System Data Size
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#define I2S_TXCFG_SSZ_S 10
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#define I2S_TXCFG_SDSZ_S 4
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_TXLIMIT register.
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//
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//*****************************************************************************
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#define I2S_TXLIMIT_LIMIT_M 0x0000001F // FIFO Limit
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#define I2S_TXLIMIT_LIMIT_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_TXISM register.
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//
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//*****************************************************************************
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#define I2S_TXISM_FFI 0x00010000 // Transmit FIFO Service Request
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// Interrupt
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#define I2S_TXISM_FFM 0x00000001 // FIFO Interrupt Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_TXLEV register.
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//
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//*****************************************************************************
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#define I2S_TXLEV_LEVEL_M 0x0000001F // Number of Audio Samples
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#define I2S_TXLEV_LEVEL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_RXFIFO register.
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//
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//*****************************************************************************
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#define I2S_RXFIFO_M 0xFFFFFFFF // RX Data
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#define I2S_RXFIFO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_RXFIFOCFG
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// register.
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//
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//*****************************************************************************
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#define I2S_RXFIFOCFG_FMM 0x00000004 // FIFO Mono Mode
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#define I2S_RXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size
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#define I2S_RXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_RXCFG register.
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//
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//*****************************************************************************
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#define I2S_RXCFG_JST 0x20000000 // Justification of Input Data
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#define I2S_RXCFG_DLY 0x10000000 // Data Delay
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#define I2S_RXCFG_SCP 0x08000000 // SCLK Polarity
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#define I2S_RXCFG_LRP 0x04000000 // Left/Right Clock Polarity
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#define I2S_RXCFG_RM 0x01000000 // Read Mode
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#define I2S_RXCFG_MSL 0x00400000 // SCLK Master/Slave
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#define I2S_RXCFG_SSZ_M 0x0000FC00 // Sample Size
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#define I2S_RXCFG_SDSZ_M 0x000003F0 // System Data Size
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#define I2S_RXCFG_SSZ_S 10
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#define I2S_RXCFG_SDSZ_S 4
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_RXLIMIT register.
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//
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//*****************************************************************************
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#define I2S_RXLIMIT_LIMIT_M 0x0000001F // FIFO Limit
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#define I2S_RXLIMIT_LIMIT_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_RXISM register.
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//
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//*****************************************************************************
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#define I2S_RXISM_FFI 0x00010000 // Receive FIFO Service Request
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// Interrupt
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#define I2S_RXISM_FFM 0x00000001 // FIFO Interrupt Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_RXLEV register.
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//
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//*****************************************************************************
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#define I2S_RXLEV_LEVEL_M 0x0000001F // Number of Audio Samples
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#define I2S_RXLEV_LEVEL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_CFG register.
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//
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//*****************************************************************************
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#define I2S_CFG_RXSLV 0x00000020 // Use External I2S0RXMCLK
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#define I2S_CFG_TXSLV 0x00000010 // Use External I2S0TXMCLK
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#define I2S_CFG_RXEN 0x00000002 // Serial Receive Engine Enable
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#define I2S_CFG_TXEN 0x00000001 // Serial Transmit Engine Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_IM register.
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//
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//*****************************************************************************
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#define I2S_IM_RXRE 0x00000020 // Receive FIFO Read Error
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#define I2S_IM_RXFSR 0x00000010 // Receive FIFO Service Request
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#define I2S_IM_TXWE 0x00000002 // Transmit FIFO Write Error
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#define I2S_IM_TXFSR 0x00000001 // Transmit FIFO Service Request
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_RIS register.
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//
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//*****************************************************************************
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#define I2S_RIS_RXRE 0x00000020 // Receive FIFO Read Error
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#define I2S_RIS_RXFSR 0x00000010 // Receive FIFO Service Request
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#define I2S_RIS_TXWE 0x00000002 // Transmit FIFO Write Error
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#define I2S_RIS_TXFSR 0x00000001 // Transmit FIFO Service Request
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_MIS register.
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//
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//*****************************************************************************
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#define I2S_MIS_RXRE 0x00000020 // Receive FIFO Read Error
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#define I2S_MIS_RXFSR 0x00000010 // Receive FIFO Service Request
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#define I2S_MIS_TXWE 0x00000002 // Transmit FIFO Write Error
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#define I2S_MIS_TXFSR 0x00000001 // Transmit FIFO Service Request
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2S_O_IC register.
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//
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//*****************************************************************************
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#define I2S_IC_RXRE 0x00000020 // Receive FIFO Read Error
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#define I2S_IC_TXWE 0x00000002 // Transmit FIFO Write Error
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#endif // __HW_I2S_H__
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