854 lines
30 KiB
Plaintext
854 lines
30 KiB
Plaintext
format_version: '2'
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name: SAMC21 LED switcher
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versions:
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api: '1.0'
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backend: 1.8.580
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commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c
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content: unknown
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content_pack_name: unknown
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format: '2'
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frontend: 1.8.580
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packs_version_avr8: 1.0.1463
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packs_version_qtouch: unknown
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packs_version_sam: 1.0.1726
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version_backend: 1.8.580
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version_frontend: ''
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board:
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identifier: SAMC21XplainedPro
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device: SAMC21J18A-AN
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details: null
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application:
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definition: 'Atmel:Application_Examples:0.0.1::Application:RWW_FLASH:'
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configuration: null
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middlewares: {}
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drivers:
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ADC_0:
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user_label: ADC_0
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definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync
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functionality: ADC
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api: HAL:Driver:ADC_Sync
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configuration:
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adc_advanced_settings: true
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adc_arch_adjres: 0
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adc_arch_corren: false
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adc_arch_dbgrun: false
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adc_arch_dualsel: BOTH
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adc_arch_event_settings: false
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adc_arch_flushei: false
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adc_arch_flushinv: false
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adc_arch_gaincorr: 0
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adc_arch_leftadj: false
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adc_arch_offcomp: false
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adc_arch_offsetcorr: 0
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adc_arch_ondemand: false
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adc_arch_r2r: false
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adc_arch_refcomp: false
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adc_arch_resrdyeo: false
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adc_arch_runstdby: false
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adc_arch_samplen: 0
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adc_arch_samplenum: 1 sample
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adc_arch_seqen: 0
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adc_arch_slaveen: false
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adc_arch_startei: false
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adc_arch_startinv: false
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adc_arch_winlt: 0
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adc_arch_winmode: No window mode
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adc_arch_winmoneo: false
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adc_arch_winut: 0
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adc_differential_mode: false
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adc_freerunning_mode: false
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adc_pinmux_negative: I/O ground
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adc_pinmux_positive: ADC AIN0 pin
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adc_prescaler: Peripheral clock divided by 2
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adc_reference: Internal bandgap reference
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adc_resolution: 16-bit (averaging must be enabled)
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optional_signals:
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- identifier: ADC_0:AIN/10
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pad: PA10
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mode: Enabled
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configuration: null
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definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::optional_signal_definition::ADC0.AIN.10
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name: ADC0/AIN/10
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label: AIN/10
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variant: null
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clocks:
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domain_group:
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nodes:
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- name: ADC
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input: Generic clock generator 0
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external: false
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external_frequency: 0
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configuration:
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adc_gclk_selection: Generic clock generator 0
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DMAC:
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user_label: DMAC
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definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
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functionality: System
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api: HAL:HPL:DMAC
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configuration:
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dmac_beatsize_0: 8-bit bus transfer
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dmac_beatsize_1: 8-bit bus transfer
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dmac_beatsize_10: 8-bit bus transfer
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dmac_beatsize_11: 8-bit bus transfer
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dmac_beatsize_12: 8-bit bus transfer
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dmac_beatsize_13: 8-bit bus transfer
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dmac_beatsize_14: 8-bit bus transfer
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dmac_beatsize_15: 8-bit bus transfer
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dmac_beatsize_2: 8-bit bus transfer
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dmac_beatsize_3: 8-bit bus transfer
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dmac_beatsize_4: 8-bit bus transfer
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dmac_beatsize_5: 8-bit bus transfer
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dmac_beatsize_6: 8-bit bus transfer
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dmac_beatsize_7: 8-bit bus transfer
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dmac_beatsize_8: 8-bit bus transfer
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dmac_beatsize_9: 8-bit bus transfer
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dmac_blockact_0: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_1: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_10: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_11: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_12: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_13: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_14: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_15: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_2: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_3: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_4: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_5: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_6: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_7: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_8: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_9: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_channel_0_settings: false
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dmac_channel_10_settings: false
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dmac_channel_11_settings: false
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dmac_channel_12_settings: false
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dmac_channel_13_settings: false
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dmac_channel_14_settings: false
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dmac_channel_15_settings: false
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dmac_channel_1_settings: false
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dmac_channel_2_settings: false
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dmac_channel_3_settings: false
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dmac_channel_4_settings: false
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dmac_channel_5_settings: false
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dmac_channel_6_settings: false
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dmac_channel_7_settings: false
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dmac_channel_8_settings: false
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dmac_channel_9_settings: false
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dmac_dbgrun: false
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dmac_dqos: Background (no sensitive operation)
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dmac_dstinc_0: false
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dmac_dstinc_1: false
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dmac_dstinc_10: false
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dmac_dstinc_11: false
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dmac_dstinc_12: false
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dmac_dstinc_13: false
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dmac_dstinc_14: false
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dmac_dstinc_15: false
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dmac_dstinc_2: false
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dmac_dstinc_3: false
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dmac_dstinc_4: false
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dmac_dstinc_5: false
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dmac_dstinc_6: false
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dmac_dstinc_7: false
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dmac_dstinc_8: false
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dmac_dstinc_9: false
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dmac_enable: false
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dmac_enable_0: false
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dmac_enable_1: false
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dmac_enable_10: false
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dmac_enable_11: false
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dmac_enable_12: false
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dmac_enable_13: false
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dmac_enable_14: false
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dmac_enable_15: false
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dmac_enable_2: false
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dmac_enable_3: false
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dmac_enable_4: false
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dmac_enable_5: false
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dmac_enable_6: false
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dmac_enable_7: false
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dmac_enable_8: false
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dmac_enable_9: false
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dmac_evact_0: No action
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dmac_evact_1: No action
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dmac_evact_10: No action
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dmac_evact_11: No action
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dmac_evact_12: No action
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dmac_evact_13: No action
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dmac_evact_14: No action
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dmac_evact_15: No action
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dmac_evact_2: No action
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dmac_evact_3: No action
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dmac_evact_4: No action
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dmac_evact_5: No action
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dmac_evact_6: No action
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dmac_evact_7: No action
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dmac_evact_8: No action
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dmac_evact_9: No action
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dmac_evie_0: false
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dmac_evie_1: false
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dmac_evie_10: false
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dmac_evie_11: false
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dmac_evie_12: false
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dmac_evie_13: false
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dmac_evie_14: false
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dmac_evie_15: false
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dmac_evie_2: false
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dmac_evie_3: false
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dmac_evie_4: false
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dmac_evie_5: false
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dmac_evie_6: false
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dmac_evie_7: false
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dmac_evie_8: false
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dmac_evie_9: false
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dmac_evoe_0: false
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dmac_evoe_1: false
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dmac_evoe_10: false
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dmac_evoe_11: false
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dmac_evoe_12: false
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dmac_evoe_13: false
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dmac_evoe_14: false
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dmac_evoe_15: false
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dmac_evoe_2: false
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dmac_evoe_3: false
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dmac_evoe_4: false
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dmac_evoe_5: false
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dmac_evoe_6: false
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dmac_evoe_7: false
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dmac_evoe_8: false
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dmac_evoe_9: false
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dmac_evosel_0: Event generation disabled
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dmac_evosel_1: Event generation disabled
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dmac_evosel_10: Event generation disabled
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dmac_evosel_11: Event generation disabled
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dmac_evosel_12: Event generation disabled
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dmac_evosel_13: Event generation disabled
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dmac_evosel_14: Event generation disabled
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dmac_evosel_15: Event generation disabled
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dmac_evosel_2: Event generation disabled
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dmac_evosel_3: Event generation disabled
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dmac_evosel_4: Event generation disabled
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dmac_evosel_5: Event generation disabled
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dmac_evosel_6: Event generation disabled
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dmac_evosel_7: Event generation disabled
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dmac_evosel_8: Event generation disabled
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dmac_evosel_9: Event generation disabled
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dmac_fqos: Background (no sensitive operation)
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dmac_lvl_0: Channel priority 0
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dmac_lvl_1: Channel priority 0
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dmac_lvl_10: Channel priority 0
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dmac_lvl_11: Channel priority 0
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dmac_lvl_12: Channel priority 0
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dmac_lvl_13: Channel priority 0
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dmac_lvl_14: Channel priority 0
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dmac_lvl_15: Channel priority 0
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dmac_lvl_2: Channel priority 0
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dmac_lvl_3: Channel priority 0
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dmac_lvl_4: Channel priority 0
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dmac_lvl_5: Channel priority 0
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dmac_lvl_6: Channel priority 0
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dmac_lvl_7: Channel priority 0
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dmac_lvl_8: Channel priority 0
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dmac_lvl_9: Channel priority 0
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dmac_lvlen0: false
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dmac_lvlen1: false
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dmac_lvlen2: false
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dmac_lvlen3: false
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dmac_lvlpri0: 0
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dmac_lvlpri1: 0
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dmac_lvlpri2: 0
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dmac_lvlpri3: 0
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dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
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dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
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dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
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dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
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dmac_runstdby_0: false
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dmac_runstdby_1: false
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dmac_runstdby_10: false
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dmac_runstdby_11: false
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dmac_runstdby_12: false
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dmac_runstdby_13: false
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dmac_runstdby_14: false
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dmac_runstdby_15: false
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dmac_runstdby_2: false
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dmac_runstdby_3: false
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dmac_runstdby_4: false
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dmac_runstdby_5: false
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dmac_runstdby_6: false
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dmac_runstdby_7: false
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dmac_runstdby_8: false
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dmac_runstdby_9: false
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dmac_srcinc_0: false
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dmac_srcinc_1: false
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dmac_srcinc_10: false
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dmac_srcinc_11: false
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dmac_srcinc_12: false
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dmac_srcinc_13: false
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dmac_srcinc_14: false
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dmac_srcinc_15: false
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dmac_srcinc_2: false
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dmac_srcinc_3: false
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dmac_srcinc_4: false
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dmac_srcinc_5: false
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dmac_srcinc_6: false
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dmac_srcinc_7: false
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dmac_srcinc_8: false
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dmac_srcinc_9: false
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dmac_stepsel_0: Step size settings apply to the destination address
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dmac_stepsel_1: Step size settings apply to the destination address
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dmac_stepsel_10: Step size settings apply to the destination address
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dmac_stepsel_11: Step size settings apply to the destination address
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dmac_stepsel_12: Step size settings apply to the destination address
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dmac_stepsel_13: Step size settings apply to the destination address
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dmac_stepsel_14: Step size settings apply to the destination address
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dmac_stepsel_15: Step size settings apply to the destination address
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dmac_stepsel_2: Step size settings apply to the destination address
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dmac_stepsel_3: Step size settings apply to the destination address
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dmac_stepsel_4: Step size settings apply to the destination address
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dmac_stepsel_5: Step size settings apply to the destination address
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dmac_stepsel_6: Step size settings apply to the destination address
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dmac_stepsel_7: Step size settings apply to the destination address
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dmac_stepsel_8: Step size settings apply to the destination address
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dmac_stepsel_9: Step size settings apply to the destination address
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dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_trifsrc_0: Only software/event triggers
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dmac_trifsrc_1: Only software/event triggers
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dmac_trifsrc_10: Only software/event triggers
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dmac_trifsrc_11: Only software/event triggers
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dmac_trifsrc_12: Only software/event triggers
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dmac_trifsrc_13: Only software/event triggers
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dmac_trifsrc_14: Only software/event triggers
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dmac_trifsrc_15: Only software/event triggers
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dmac_trifsrc_2: Only software/event triggers
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dmac_trifsrc_3: Only software/event triggers
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dmac_trifsrc_4: Only software/event triggers
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dmac_trifsrc_5: Only software/event triggers
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dmac_trifsrc_6: Only software/event triggers
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dmac_trifsrc_7: Only software/event triggers
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dmac_trifsrc_8: Only software/event triggers
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dmac_trifsrc_9: Only software/event triggers
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dmac_trigact_0: One trigger required for each block transfer
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dmac_trigact_1: One trigger required for each block transfer
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dmac_trigact_10: One trigger required for each block transfer
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dmac_trigact_11: One trigger required for each block transfer
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dmac_trigact_12: One trigger required for each block transfer
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dmac_trigact_13: One trigger required for each block transfer
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dmac_trigact_14: One trigger required for each block transfer
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dmac_trigact_15: One trigger required for each block transfer
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dmac_trigact_2: One trigger required for each block transfer
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dmac_trigact_3: One trigger required for each block transfer
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dmac_trigact_4: One trigger required for each block transfer
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dmac_trigact_5: One trigger required for each block transfer
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dmac_trigact_6: One trigger required for each block transfer
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dmac_trigact_7: One trigger required for each block transfer
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dmac_trigact_8: One trigger required for each block transfer
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dmac_trigact_9: One trigger required for each block transfer
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dmac_wrbqos: Background (no sensitive operation)
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optional_signals: []
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variant: null
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clocks:
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domain_group: null
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GCLK:
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user_label: GCLK
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definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
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functionality: System
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api: HAL:HPL:GCLK
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configuration:
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$input: 400000
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$input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
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RESERVED_InputFreq: 400000
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RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
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_$freq_output_Generic clock generator 0: 40001536
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_$freq_output_Generic clock generator 1: 4000000
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_$freq_output_Generic clock generator 2: 400000
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_$freq_output_Generic clock generator 3: 400000
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_$freq_output_Generic clock generator 4: 400000
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_$freq_output_Generic clock generator 5: 400000
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_$freq_output_Generic clock generator 6: 400000
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_$freq_output_Generic clock generator 7: 400000
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enable_gclk_gen_0: true
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enable_gclk_gen_0__externalclock: 1000000
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enable_gclk_gen_1: true
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enable_gclk_gen_1__externalclock: 1000000
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enable_gclk_gen_2: false
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enable_gclk_gen_2__externalclock: 1000000
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enable_gclk_gen_3: false
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enable_gclk_gen_3__externalclock: 1000000
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enable_gclk_gen_4: false
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enable_gclk_gen_4__externalclock: 1000000
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enable_gclk_gen_5: false
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enable_gclk_gen_5__externalclock: 1000000
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enable_gclk_gen_6: false
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enable_gclk_gen_6__externalclock: 1000000
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enable_gclk_gen_7: false
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enable_gclk_gen_7__externalclock: 1000000
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gclk_arch_gen_0_enable: true
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gclk_arch_gen_0_idc: true
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gclk_arch_gen_0_oe: false
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gclk_arch_gen_0_oov: false
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gclk_arch_gen_0_runstdby: false
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gclk_arch_gen_1_enable: true
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gclk_arch_gen_1_idc: true
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gclk_arch_gen_1_oe: false
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gclk_arch_gen_1_oov: false
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gclk_arch_gen_1_runstdby: false
|
|
gclk_arch_gen_2_enable: false
|
|
gclk_arch_gen_2_idc: false
|
|
gclk_arch_gen_2_oe: false
|
|
gclk_arch_gen_2_oov: false
|
|
gclk_arch_gen_2_runstdby: false
|
|
gclk_arch_gen_3_enable: false
|
|
gclk_arch_gen_3_idc: false
|
|
gclk_arch_gen_3_oe: false
|
|
gclk_arch_gen_3_oov: false
|
|
gclk_arch_gen_3_runstdby: false
|
|
gclk_arch_gen_4_enable: false
|
|
gclk_arch_gen_4_idc: false
|
|
gclk_arch_gen_4_oe: false
|
|
gclk_arch_gen_4_oov: false
|
|
gclk_arch_gen_4_runstdby: false
|
|
gclk_arch_gen_5_enable: false
|
|
gclk_arch_gen_5_idc: false
|
|
gclk_arch_gen_5_oe: false
|
|
gclk_arch_gen_5_oov: false
|
|
gclk_arch_gen_5_runstdby: false
|
|
gclk_arch_gen_6_enable: false
|
|
gclk_arch_gen_6_idc: false
|
|
gclk_arch_gen_6_oe: false
|
|
gclk_arch_gen_6_oov: false
|
|
gclk_arch_gen_6_runstdby: false
|
|
gclk_arch_gen_7_enable: false
|
|
gclk_arch_gen_7_idc: false
|
|
gclk_arch_gen_7_oe: false
|
|
gclk_arch_gen_7_oov: false
|
|
gclk_arch_gen_7_runstdby: false
|
|
gclk_gen_0_div: 1
|
|
gclk_gen_0_div_sel: false
|
|
gclk_gen_0_oscillator: Fractional Digital Phase Locked Loop (FDPLL96M)
|
|
gclk_gen_1_div: 1
|
|
gclk_gen_1_div_sel: false
|
|
gclk_gen_1_oscillator: 48MHz Internal Oscillator (OSC48M)
|
|
gclk_gen_2_div: 1
|
|
gclk_gen_2_div_sel: false
|
|
gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
|
|
gclk_gen_3_div: 1
|
|
gclk_gen_3_div_sel: false
|
|
gclk_gen_3_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
|
|
gclk_gen_4_div: 1
|
|
gclk_gen_4_div_sel: false
|
|
gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
|
|
gclk_gen_5_div: 1
|
|
gclk_gen_5_div_sel: false
|
|
gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
|
|
gclk_gen_6_div: 1
|
|
gclk_gen_6_div_sel: false
|
|
gclk_gen_6_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
|
|
gclk_gen_7_div: 1
|
|
gclk_gen_7_div_sel: false
|
|
gclk_gen_7_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
|
|
optional_signals: []
|
|
variant: null
|
|
clocks:
|
|
domain_group: null
|
|
MCLK:
|
|
user_label: MCLK
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
|
|
functionality: System
|
|
api: HAL:HPL:MCLK
|
|
configuration:
|
|
$input: 40001536
|
|
$input_id: Generic clock generator 0
|
|
RESERVED_InputFreq: 40001536
|
|
RESERVED_InputFreq_id: Generic clock generator 0
|
|
_$freq_output_CPU: 40001536
|
|
cpu_clock_source: Generic clock generator 0
|
|
cpu_div: '1'
|
|
enable_cpu_clock: true
|
|
nvm_wait_states: '4'
|
|
optional_signals: []
|
|
variant: null
|
|
clocks:
|
|
domain_group:
|
|
nodes:
|
|
- name: CPU
|
|
input: CPU
|
|
external: false
|
|
external_frequency: 0
|
|
configuration: {}
|
|
FLASH_0:
|
|
user_label: FLASH_0
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::NVMCTRL::driver_config_definition::Flash::HAL:Driver:FLASH
|
|
functionality: Flash
|
|
api: HAL:Driver:FLASH
|
|
configuration:
|
|
nvm_arch_cache: false
|
|
nvm_arch_read_mode: No Miss Penalty
|
|
nvm_arch_sleepprm: Wake On Access
|
|
optional_signals: []
|
|
variant: null
|
|
clocks:
|
|
domain_group: null
|
|
OSC32KCTRL:
|
|
user_label: OSC32KCTRL
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
|
|
functionality: System
|
|
api: HAL:HPL:OSC32KCTRL
|
|
configuration:
|
|
$input: 32768
|
|
$input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
|
RESERVED_InputFreq: 32768
|
|
RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
|
_$freq_output_RTC source: 32768
|
|
enable_osc32k: false
|
|
enable_osculp32k: true
|
|
enable_rtc_source: false
|
|
enable_xosc32k: true
|
|
osc32k_arch_calib: 0
|
|
osc32k_arch_calib_enable: false
|
|
osc32k_arch_en1k: false
|
|
osc32k_arch_en32k: false
|
|
osc32k_arch_enable: false
|
|
osc32k_arch_ondemand: false
|
|
osc32k_arch_runstdby: false
|
|
osc32k_arch_startup: 92us
|
|
osculp32k_calib: 0
|
|
osculp32k_calib_enable: false
|
|
rtc_1khz_selection: false
|
|
rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
|
xosc32k_arch_cfden: false
|
|
xosc32k_arch_cfdeo: false
|
|
xosc32k_arch_en1k: false
|
|
xosc32k_arch_en32k: true
|
|
xosc32k_arch_enable: true
|
|
xosc32k_arch_ondemand: true
|
|
xosc32k_arch_runstdby: true
|
|
xosc32k_arch_startup: 62592us
|
|
xosc32k_arch_swben: false
|
|
xosc32k_arch_xtalen: true
|
|
optional_signals: []
|
|
variant: null
|
|
clocks:
|
|
domain_group: null
|
|
OSCCTRL:
|
|
user_label: OSCCTRL
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
|
|
functionality: System
|
|
api: HAL:HPL:OSCCTRL
|
|
configuration:
|
|
$input: 32768
|
|
$input_id: 32kHz External Crystal Oscillator (XOSC32K)
|
|
RESERVED_InputFreq: 32768
|
|
RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
|
|
_$freq_output_48MHz Internal Oscillator (OSC48M): 4000000
|
|
_$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
|
|
_$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 40001536
|
|
enable_fdpll96m: true
|
|
enable_osc48m: true
|
|
enable_xosc: false
|
|
fdpll96m_arch_enable: true
|
|
fdpll96m_arch_filter: Default filter mode
|
|
fdpll96m_arch_lbypass: false
|
|
fdpll96m_arch_lpen: false
|
|
fdpll96m_arch_ltime: No time-out, automatic lock
|
|
fdpll96m_arch_ondemand: true
|
|
fdpll96m_arch_runstdby: false
|
|
fdpll96m_arch_wuf: false
|
|
fdpll96m_clock_div: 0
|
|
fdpll96m_ldr: 1219
|
|
fdpll96m_ldrfrac: 12
|
|
fdpll96m_presc: '1'
|
|
fdpll96m_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
|
|
osc48m_arch_enable: true
|
|
osc48m_arch_ondemand: true
|
|
osc48m_arch_runstdby: false
|
|
osc48m_arch_startup: 21.333us
|
|
osc48m_div: 11
|
|
xosc_arch_ampgc: false
|
|
xosc_arch_cfden: false
|
|
xosc_arch_cfdeo: false
|
|
xosc_arch_enable: false
|
|
xosc_arch_gain: 2MHz
|
|
xosc_arch_ondemand: true
|
|
xosc_arch_runstdby: false
|
|
xosc_arch_startup: 31us
|
|
xosc_arch_swben: false
|
|
xosc_arch_xtalen: false
|
|
xosc_frequency: 400000
|
|
optional_signals: []
|
|
variant: null
|
|
clocks:
|
|
domain_group: null
|
|
PORT:
|
|
user_label: PORT
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::PORT::driver_config_definition::PORT::HAL:HPL:PORT
|
|
functionality: System
|
|
api: HAL:HPL:PORT
|
|
configuration:
|
|
enable_port_input_event_0: false
|
|
enable_port_input_event_1: false
|
|
enable_port_input_event_2: false
|
|
enable_port_input_event_3: false
|
|
porta_event_action_0: Output register of pin will be set to level of event
|
|
porta_event_action_1: Output register of pin will be set to level of event
|
|
porta_event_action_2: Output register of pin will be set to level of event
|
|
porta_event_action_3: Output register of pin will be set to level of event
|
|
porta_event_pin_identifier_0: 0
|
|
porta_event_pin_identifier_1: 0
|
|
porta_event_pin_identifier_2: 0
|
|
porta_event_pin_identifier_3: 0
|
|
porta_input_event_enable_0: false
|
|
porta_input_event_enable_1: false
|
|
porta_input_event_enable_2: false
|
|
porta_input_event_enable_3: false
|
|
portb_event_action_0: Output register of pin will be set to level of event
|
|
portb_event_action_1: Output register of pin will be set to level of event
|
|
portb_event_action_2: Output register of pin will be set to level of event
|
|
portb_event_action_3: Output register of pin will be set to level of event
|
|
portb_event_pin_identifier_0: 0
|
|
portb_event_pin_identifier_1: 0
|
|
portb_event_pin_identifier_2: 0
|
|
portb_event_pin_identifier_3: 0
|
|
portb_input_event_enable_0: false
|
|
portb_input_event_enable_1: false
|
|
portb_input_event_enable_2: false
|
|
portb_input_event_enable_3: false
|
|
optional_signals: []
|
|
variant: null
|
|
clocks:
|
|
domain_group: null
|
|
I2C_0:
|
|
user_label: I2C_0
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync
|
|
functionality: I2C
|
|
api: HAL:Driver:I2C_Master_Sync
|
|
configuration:
|
|
i2c_master_advanced: true
|
|
i2c_master_arch_dbgstop: Keep running
|
|
i2c_master_arch_inactout: 20-21 SCL cycle time-out(200-210us)
|
|
i2c_master_arch_lowtout: true
|
|
i2c_master_arch_mexttoen: true
|
|
i2c_master_arch_runstdby: false
|
|
i2c_master_arch_sdahold: 300-600ns hold time
|
|
i2c_master_arch_sexttoen: false
|
|
i2c_master_arch_trise: 215
|
|
i2c_master_baud_rate: 100000
|
|
optional_signals: []
|
|
variant:
|
|
specification: SDA=0, SCL=1
|
|
required_signals:
|
|
- name: SERCOM0/PAD/0
|
|
pad: PA08
|
|
label: SDA
|
|
- name: SERCOM0/PAD/1
|
|
pad: PA09
|
|
label: SCL
|
|
clocks:
|
|
domain_group:
|
|
nodes:
|
|
- name: Core
|
|
input: Generic clock generator 0
|
|
external: false
|
|
external_frequency: 0
|
|
- name: Slow
|
|
input: Generic clock generator 1
|
|
external: false
|
|
external_frequency: 0
|
|
configuration:
|
|
core_gclk_selection: Generic clock generator 0
|
|
slow_gclk_selection: Generic clock generator 1
|
|
TARGET_IO:
|
|
user_label: TARGET_IO
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM4::driver_config_definition::UART::HAL:Driver:USART.Async
|
|
functionality: USART
|
|
api: HAL:Driver:USART_Async
|
|
configuration:
|
|
usart_advanced: true
|
|
usart_arch_clock_mode: USART with internal clock
|
|
usart_arch_cloden: false
|
|
usart_arch_dbgstop: Keep running
|
|
usart_arch_dord: LSB is transmitted first
|
|
usart_arch_enc: No encoding
|
|
usart_arch_fractional: 0
|
|
usart_arch_ibon: false
|
|
usart_arch_lin_slave_enable: Disable
|
|
usart_arch_runstdby: false
|
|
usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling)
|
|
usart_arch_sampr: 16x arithmetic
|
|
usart_arch_sfde: false
|
|
usart_baud_rate: 115200
|
|
usart_character_size: 8 bits
|
|
usart_parity: No parity
|
|
usart_rx_enable: true
|
|
usart_stop_bit: One stop bit
|
|
usart_tx_enable: true
|
|
optional_signals: []
|
|
variant:
|
|
specification: TXPO=1, RXPO=3, CMODE=0
|
|
required_signals:
|
|
- name: SERCOM4/PAD/2
|
|
pad: PB10
|
|
label: TX
|
|
- name: SERCOM4/PAD/3
|
|
pad: PB11
|
|
label: RX
|
|
clocks:
|
|
domain_group:
|
|
nodes:
|
|
- name: Core
|
|
input: Generic clock generator 0
|
|
external: false
|
|
external_frequency: 0
|
|
- name: Slow
|
|
input: Generic clock generator 1
|
|
external: false
|
|
external_frequency: 0
|
|
configuration:
|
|
core_gclk_selection: Generic clock generator 0
|
|
slow_gclk_selection: Generic clock generator 1
|
|
CAN_0:
|
|
user_label: CAN_0
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::CAN0::driver_config_definition::CAN::HAL:Driver:CAN.Async
|
|
functionality: CAN
|
|
api: HAL:Driver:CAN_Async
|
|
configuration:
|
|
can_btp_brp: 4
|
|
can_btp_sjw: 10
|
|
can_btp_tseg1: 31
|
|
can_btp_tseg2: 8
|
|
can_cccr_brse: false
|
|
can_cccr_fdoe: false
|
|
can_dbtp_dbrp: 4
|
|
can_dbtp_dsjw: 4
|
|
can_dbtp_dtseg1: 31
|
|
can_dbtp_dtseg2: 8
|
|
can_dbtp_tdc: false
|
|
can_gfc_anfe: Reject
|
|
can_gfc_anfs: Reject
|
|
can_gfc_rrfe: Filter remote frames with 29-bit standard IDs
|
|
can_gfc_rrfs: Filter remote frames with 11-bit standard IDs
|
|
can_ie_bo: true
|
|
can_ie_do: true
|
|
can_ie_ea: true
|
|
can_ie_ep: true
|
|
can_ie_ew: true
|
|
can_mrcfg_dqos: Sensitive latency
|
|
can_mrcfg_runstandby: false
|
|
can_rxesc_f0ds: 8 byte data field.
|
|
can_rxf0c_f0om: blocking mode
|
|
can_rxf0c_f0s: 32
|
|
can_rxf0c_f0wm: 0
|
|
can_sidfc_lss: 128
|
|
can_txbc_tfqs: 32
|
|
can_txefc_efs: 32
|
|
can_txefc_efwm: 0
|
|
can_txesc_tbds: 8 byte data field.
|
|
can_xidam_eidm: 0
|
|
can_xidfc_lss: 64
|
|
optional_signals:
|
|
- identifier: CAN_0:RX
|
|
pad: PA25
|
|
mode: Enabled
|
|
configuration: null
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::optional_signal_definition::CAN0.RX
|
|
name: CAN0/RX
|
|
label: RX
|
|
- identifier: CAN_0:TX
|
|
pad: PA24
|
|
mode: Enabled
|
|
configuration: null
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::optional_signal_definition::CAN0.TX
|
|
name: CAN0/TX
|
|
label: TX
|
|
variant: null
|
|
clocks:
|
|
domain_group:
|
|
nodes:
|
|
- name: CAN
|
|
input: Generic clock generator 0
|
|
external: false
|
|
external_frequency: 0
|
|
configuration:
|
|
can_gclk_selection: Generic clock generator 0
|
|
pads:
|
|
PA08:
|
|
name: PA08
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA08
|
|
mode: I2C
|
|
user_label: PA08
|
|
configuration: null
|
|
PA09:
|
|
name: PA09
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA09
|
|
mode: I2C
|
|
user_label: PA09
|
|
configuration: null
|
|
PA10:
|
|
name: PA10
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA10
|
|
mode: Analog
|
|
user_label: PA10
|
|
configuration: null
|
|
PB10:
|
|
name: PB10
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB10
|
|
mode: Peripheral IO
|
|
user_label: PB10
|
|
configuration: null
|
|
PB11:
|
|
name: PB11
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB11
|
|
mode: Peripheral IO
|
|
user_label: PB11
|
|
configuration: null
|
|
LED0:
|
|
name: PA15
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA15
|
|
mode: Digital output
|
|
user_label: LED0
|
|
configuration: null
|
|
PA24:
|
|
name: PA24
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA24
|
|
mode: Peripheral IO
|
|
user_label: PA24
|
|
configuration: null
|
|
PA25:
|
|
name: PA25
|
|
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA25
|
|
mode: Peripheral IO
|
|
user_label: PA25
|
|
configuration: null
|
|
toolchain_options: []
|
|
static_files: []
|