625 lines
24 KiB
C
625 lines
24 KiB
C
/*
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** ###################################################################
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** Version: rev. 1.1, 2021-08-04
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** Build: b220118
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**
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** Abstract:
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** Chip specific module features.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2022 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2021-04-12)
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** Initial version based on RM DraftF
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** - rev. 1.1 (2021-08-04)
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** Initial version based on RM DraftG
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**
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** ###################################################################
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*/
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#ifndef _LPC55S36_FEATURES_H_
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#define _LPC55S36_FEATURES_H_
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/* SOC module features */
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#if defined(CPU_LPC55S36JBD100)
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/* @brief AOI availability on the SoC. */
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#define FSL_FEATURE_SOC_AOI_COUNT (2)
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/* @brief CACHE64_CTRL availability on the SoC. */
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#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1)
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/* @brief CACHE64_POLSEL availability on the SoC. */
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#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1)
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/* @brief LPC_CAN availability on the SoC. */
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#define FSL_FEATURE_SOC_LPC_CAN_COUNT (1)
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/* @brief CRC availability on the SoC. */
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#define FSL_FEATURE_SOC_CRC_COUNT (1)
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/* @brief CTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
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/* @brief CDOG availability on the SoC. */
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#define FSL_FEATURE_SOC_CDOG_COUNT (1)
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/* @brief DMA availability on the SoC. */
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#define FSL_FEATURE_SOC_DMA_COUNT (2)
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/* @brief DMIC availability on the SoC. */
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#define FSL_FEATURE_SOC_DMIC_COUNT (1)
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/* @brief ENC availability on the SoC. */
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#define FSL_FEATURE_SOC_ENC_COUNT (2)
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/* @brief FLASH availability on the SoC. */
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#define FSL_FEATURE_SOC_FLASH_COUNT (1)
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/* @brief FLEXCOMM availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
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/* @brief FLEXSPI availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
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/* @brief FREQME availability on the SoC. */
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#define FSL_FEATURE_SOC_FREQME_COUNT (1)
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/* @brief GINT availability on the SoC. */
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#define FSL_FEATURE_SOC_GINT_COUNT (2)
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/* @brief GPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_GPIO_COUNT (1)
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/* @brief SECGPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
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/* @brief I2C availability on the SoC. */
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#define FSL_FEATURE_SOC_I2C_COUNT (8)
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/* @brief I3C availability on the SoC. */
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#define FSL_FEATURE_SOC_I3C_COUNT (1)
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/* @brief I2S availability on the SoC. */
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#define FSL_FEATURE_SOC_I2S_COUNT (8)
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/* @brief INPUTMUX availability on the SoC. */
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#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
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/* @brief IOCON availability on the SoC. */
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#define FSL_FEATURE_SOC_IOCON_COUNT (1)
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/* @brief LPADC availability on the SoC. */
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#define FSL_FEATURE_SOC_LPADC_COUNT (2)
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/* @brief LPCMP availability on the SoC. */
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#define FSL_FEATURE_SOC_LPCMP_COUNT (3)
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/* @brief LPDAC availability on the SoC. */
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#define FSL_FEATURE_SOC_LPDAC_COUNT (3)
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/* @brief MAILBOX availability on the SoC. */
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#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
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/* @brief MRT availability on the SoC. */
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#define FSL_FEATURE_SOC_MRT_COUNT (1)
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/* @brief OPAMP availability on the SoC. */
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#define FSL_FEATURE_SOC_OPAMP_COUNT (3)
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/* @brief OSTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
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/* @brief PINT availability on the SoC. */
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#define FSL_FEATURE_SOC_PINT_COUNT (1)
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/* @brief SECPINT availability on the SoC. */
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#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
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/* @brief PMC availability on the SoC. */
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#define FSL_FEATURE_SOC_PMC_COUNT (1)
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/* @brief POWERQUAD availability on the SoC. */
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#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
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/* @brief PWM availability on the SoC. */
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#define FSL_FEATURE_SOC_PWM_COUNT (2)
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/* @brief PUF availability on the SoC. */
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#define FSL_FEATURE_SOC_PUF_COUNT (1)
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/* @brief RTC availability on the SoC. */
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#define FSL_FEATURE_SOC_RTC_COUNT (2)
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/* @brief SCT availability on the SoC. */
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#define FSL_FEATURE_SOC_SCT_COUNT (1)
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/* @brief SPI availability on the SoC. */
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#define FSL_FEATURE_SOC_SPI_COUNT (9)
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/* @brief SYSCON availability on the SoC. */
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#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
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/* @brief USART availability on the SoC. */
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#define FSL_FEATURE_SOC_USART_COUNT (8)
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/* @brief USB availability on the SoC. */
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#define FSL_FEATURE_SOC_USB_COUNT (1)
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/* @brief USBFSH availability on the SoC. */
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#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
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/* @brief UTICK availability on the SoC. */
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#define FSL_FEATURE_SOC_UTICK_COUNT (1)
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/* @brief VREF availability on the SoC. */
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#define FSL_FEATURE_SOC_VREF_COUNT (1)
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/* @brief WWDT availability on the SoC. */
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#define FSL_FEATURE_SOC_WWDT_COUNT (1)
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#elif defined(CPU_LPC55S36JHI48)
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/* @brief AOI availability on the SoC. */
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#define FSL_FEATURE_SOC_AOI_COUNT (2)
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/* @brief CACHE64_CTRL availability on the SoC. */
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#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1)
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/* @brief CACHE64_POLSEL availability on the SoC. */
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#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1)
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/* @brief LPC_CAN availability on the SoC. */
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#define FSL_FEATURE_SOC_LPC_CAN_COUNT (1)
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/* @brief CRC availability on the SoC. */
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#define FSL_FEATURE_SOC_CRC_COUNT (1)
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/* @brief CTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
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/* @brief CDOG availability on the SoC. */
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#define FSL_FEATURE_SOC_CDOG_COUNT (1)
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/* @brief DMA availability on the SoC. */
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#define FSL_FEATURE_SOC_DMA_COUNT (2)
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/* @brief DMIC availability on the SoC. */
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#define FSL_FEATURE_SOC_DMIC_COUNT (1)
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/* @brief ENC availability on the SoC. */
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#define FSL_FEATURE_SOC_ENC_COUNT (2)
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/* @brief FLASH availability on the SoC. */
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#define FSL_FEATURE_SOC_FLASH_COUNT (1)
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/* @brief FLEXCOMM availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
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/* @brief FLEXSPI availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
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/* @brief FREQME availability on the SoC. */
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#define FSL_FEATURE_SOC_FREQME_COUNT (1)
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/* @brief GINT availability on the SoC. */
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#define FSL_FEATURE_SOC_GINT_COUNT (2)
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/* @brief GPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_GPIO_COUNT (1)
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/* @brief SECGPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
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/* @brief I2C availability on the SoC. */
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#define FSL_FEATURE_SOC_I2C_COUNT (8)
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/* @brief I3C availability on the SoC. */
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#define FSL_FEATURE_SOC_I3C_COUNT (1)
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/* @brief I2S availability on the SoC. */
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#define FSL_FEATURE_SOC_I2S_COUNT (8)
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/* @brief INPUTMUX availability on the SoC. */
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#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
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/* @brief IOCON availability on the SoC. */
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#define FSL_FEATURE_SOC_IOCON_COUNT (1)
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/* @brief LPADC availability on the SoC. */
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#define FSL_FEATURE_SOC_LPADC_COUNT (2)
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/* @brief LPCMP availability on the SoC. */
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#define FSL_FEATURE_SOC_LPCMP_COUNT (3)
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/* @brief LPDAC availability on the SoC. */
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#define FSL_FEATURE_SOC_LPDAC_COUNT (3)
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/* @brief MAILBOX availability on the SoC. */
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#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
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/* @brief MRT availability on the SoC. */
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#define FSL_FEATURE_SOC_MRT_COUNT (1)
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/* @brief OPAMP availability on the SoC. */
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#define FSL_FEATURE_SOC_OPAMP_COUNT (3)
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/* @brief OSTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
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/* @brief PINT availability on the SoC. */
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#define FSL_FEATURE_SOC_PINT_COUNT (1)
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/* @brief SECPINT availability on the SoC. */
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#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
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/* @brief PMC availability on the SoC. */
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#define FSL_FEATURE_SOC_PMC_COUNT (1)
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/* @brief POWERQUAD availability on the SoC. */
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#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
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/* @brief PWM availability on the SoC. */
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#define FSL_FEATURE_SOC_PWM_COUNT (2)
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/* @brief PUF availability on the SoC. */
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#define FSL_FEATURE_SOC_PUF_COUNT (1)
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/* @brief RTC availability on the SoC. */
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#define FSL_FEATURE_SOC_RTC_COUNT (2)
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/* @brief SCT availability on the SoC. */
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#define FSL_FEATURE_SOC_SCT_COUNT (1)
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/* @brief SPI availability on the SoC. */
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#define FSL_FEATURE_SOC_SPI_COUNT (9)
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/* @brief SYSCON availability on the SoC. */
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#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
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/* @brief USART availability on the SoC. */
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#define FSL_FEATURE_SOC_USART_COUNT (8)
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/* @brief UTICK availability on the SoC. */
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#define FSL_FEATURE_SOC_UTICK_COUNT (1)
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/* @brief VREF availability on the SoC. */
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#define FSL_FEATURE_SOC_VREF_COUNT (1)
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/* @brief WWDT availability on the SoC. */
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#define FSL_FEATURE_SOC_WWDT_COUNT (1)
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#endif
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/* LPADC module features */
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/* @brief FIFO availability on the SoC. */
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#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
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/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
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/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
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/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
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/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
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/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
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/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
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#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
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/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
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#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
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/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
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/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
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/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
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/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
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/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
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/* @brief Has calibration (bitfield CFG[CALOFS]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
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/* @brief Has offset trim (register OFSTRIM). */
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#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
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/* @brief Has trigger status (register TSTAT). */
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#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
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/* @brief Has internal temperature sensor. */
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#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
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/* @brief Temperature sensor parameter A (slope). */
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#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (768.0f)
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/* @brief Temperature sensor parameter B (offset). */
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#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (292.7f)
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/* @brief Temperature sensor parameter Alpha. */
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#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.7f)
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/* @brief Temperature sensor need calibration. */
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#define FSL_FEATURE_LPADC_TEMP_NEED_CALIBRATION (1)
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/* @brief the address of temperature sensor parameter A (slope) in Flash. */
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#define FSL_FEATURE_FLASH_NMPA_TEMP_SLOPE_ADDRS (0x3FD28U)
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/* @brief the address of temperature sensor parameter B (offset) in Flash. */
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#define FSL_FEATURE_FLASH_NMPA_TEMP_OFFSET_ADDRS (0x3FD2CU)
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/* @brief the buffer size of temperature sensor. */
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#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U)
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/* ANACTRL module features */
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/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */
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#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1)
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/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */
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#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (1)
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/* @brief Has FREQ_ME_CTRL reigster. */
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#define FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL (1)
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/* @brief Has auxiliary bias(register AUX_BIAS). */
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#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (0)
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/* @brief ANACTRL control VDDMAIN. */
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#define FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN (1)
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/* AOI module features */
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/* @brief Maximum value of input mux. */
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#define FSL_FEATURE_AOI_MODULE_INPUTS (4)
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/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
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#define FSL_FEATURE_AOI_EVENT_COUNT (4)
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/* CACHE64_CTRL module features */
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/* @brief Cache Line size in byte. */
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#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32)
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/* CACHE64_POLSEL module features */
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/* No feature definitions */
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/* CAN module features */
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/* @brief Support CANFD or not */
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#define FSL_FEATURE_CAN_SUPPORT_CANFD (1)
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/* CRC module features */
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/* @brief Has data register with name CRC */
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#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
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/* CTIMER module features */
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/* No feature definitions */
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/* LPDAC module features */
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/* @brief FIFO size. */
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#define FSL_FEATURE_LPDAC_FIFO_SIZE (16)
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/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */
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#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1)
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/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */
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#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1)
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/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */
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#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1)
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/* @brief VREF source number. */
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#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3)
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/* @brief Has internal reference current options. */
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#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1)
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/* DMA module features */
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/* @brief Number of channels */
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#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) \
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(((x) == DMA0) ? (52) : \
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(((x) == DMA1) ? (16) : (-1)))
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/* @brief Max channels */
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#define FSL_FEATURE_DMA_MAX_CHANNELS (52)
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/* @brief All channels */
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#define FSL_FEATURE_DMA_ALL_CHANNELS (68U)
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/* @brief Align size of DMA0 descriptor */
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#define FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE (1024)
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/* @brief Align size of DMA1 descriptor */
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#define FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE (256)
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/* @brief Align size of DMA descriptor */
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#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(x) \
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(((x) == DMA0) ? (1024) : \
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(((x) == DMA1) ? (256) : (-1)))
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/* @brief DMA head link descriptor table align size */
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#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
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/* DMIC module features */
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/* @brief Number of channels */
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#define FSL_FEATURE_DMIC_CHANNEL_NUM (2)
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/* @brief DMIC channel FIFO register support sign extended */
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#define FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND (1)
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/* @brief DMIC has no IOCFG register */
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#define FSL_FEATURE_DMIC_HAS_NO_IOCFG (1)
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/* @brief DMIC has decimator reset function */
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#define FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC (1)
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/* @brief DMIC has global channel synchronization function */
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#define FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC (1)
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/* FLEXCOMM module features */
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/* @brief FLEXCOMM0 USART INDEX 0 */
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#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
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/* @brief FLEXCOMM0 SPI INDEX 0 */
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#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
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/* @brief FLEXCOMM0 I2C INDEX 0 */
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#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
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/* @brief FLEXCOMM0 I2S INDEX 0 */
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#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)
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/* @brief FLEXCOMM1 USART INDEX 1 */
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#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
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/* @brief FLEXCOMM1 SPI INDEX 1 */
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#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
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/* @brief FLEXCOMM1 I2C INDEX 1 */
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#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
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/* @brief FLEXCOMM1 I2S INDEX 1 */
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#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)
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/* @brief FLEXCOMM2 USART INDEX 2 */
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#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
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/* @brief FLEXCOMM2 SPI INDEX 2 */
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#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
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/* @brief FLEXCOMM2 I2C INDEX 2 */
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#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
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/* @brief FLEXCOMM2 I2S INDEX 2 */
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#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)
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/* @brief FLEXCOMM3 USART INDEX 3 */
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#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
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/* @brief FLEXCOMM3 SPI INDEX 3 */
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#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
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/* @brief FLEXCOMM3 I2C INDEX 3 */
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#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
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/* @brief FLEXCOMM3 I2S INDEX 3 */
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#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)
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/* @brief FLEXCOMM4 USART INDEX 4 */
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#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
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/* @brief FLEXCOMM4 SPI INDEX 4 */
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#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
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/* @brief FLEXCOMM4 I2C INDEX 4 */
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#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
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/* @brief FLEXCOMM4 I2S INDEX 4 */
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#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4)
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/* @brief FLEXCOMM5 USART INDEX 5 */
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#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
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/* @brief FLEXCOMM5 SPI INDEX 5 */
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#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
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/* @brief FLEXCOMM5 I2C INDEX 5 */
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#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
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/* @brief FLEXCOMM5 I2S INDEX 5 */
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#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5)
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/* @brief FLEXCOMM6 USART INDEX 6 */
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#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
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/* @brief FLEXCOMM6 SPI INDEX 6 */
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#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
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/* @brief FLEXCOMM6 I2C INDEX 6 */
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#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
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/* @brief FLEXCOMM6 I2S INDEX 6 */
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#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6)
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/* @brief FLEXCOMM7 USART INDEX 7 */
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#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
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/* @brief FLEXCOMM7 SPI INDEX 7 */
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#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
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/* @brief FLEXCOMM7 I2C INDEX 7 */
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#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
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/* @brief FLEXCOMM7 I2S INDEX 7 */
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#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7)
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/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */
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#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
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/* @brief I2S has DMIC interconnection */
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#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \
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(((x) == FLEXCOMM0) ? (0) : \
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(((x) == FLEXCOMM1) ? (0) : \
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(((x) == FLEXCOMM2) ? (0) : \
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(((x) == FLEXCOMM3) ? (0) : \
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(((x) == FLEXCOMM4) ? (0) : \
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(((x) == FLEXCOMM5) ? (0) : \
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(((x) == FLEXCOMM6) ? (0) : \
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(((x) == FLEXCOMM7) ? (1) : \
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(((x) == FLEXCOMM8) ? (0) : (-1))))))))))
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/* @brief I2S support dual channel transfer */
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#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \
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(((x) == FLEXCOMM0) ? (0) : \
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(((x) == FLEXCOMM1) ? (0) : \
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(((x) == FLEXCOMM2) ? (0) : \
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(((x) == FLEXCOMM3) ? (0) : \
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(((x) == FLEXCOMM4) ? (0) : \
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(((x) == FLEXCOMM5) ? (0) : \
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(((x) == FLEXCOMM6) ? (1) : \
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(((x) == FLEXCOMM7) ? (1) : \
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(((x) == FLEXCOMM8) ? (0) : (-1))))))))))
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/* FLEXSPI module features */
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/* @brief FlexSPI AHB buffer count */
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#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8)
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/* @brief FlexSPI has no MCR0 ARDFEN bit */
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#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1)
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/* @brief FlexSPI has no MCR0 ATDFEN bit */
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#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1)
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/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */
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#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1)
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/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */
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#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1)
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/* @brief FlexSPI has no IPCR1 IPAREN bit */
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#define FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN (1)
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/* @brief FlexSPI has no AHBCR APAREN bit */
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#define FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN (1)
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/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */
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#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1)
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/* @brief FlexSPI has no FLSHCR4 WMENB bit */
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#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1)
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/* @brief FlexSPI has no STS2 BSLVLOCK bit */
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#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (1)
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/* @brief FlexSPI has no STS2 BREFLOCK bit */
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#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (1)
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/* @brief FlexSPI supports Port A only, do not support Port B. */
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#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (1)
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/* @brief FlexSPI LUTKEY is read only. */
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#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (1)
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/* I2S module features */
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/* @brief I2S support dual channel transfer. */
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#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
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/* @brief I2S has DMIC interconnection. */
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#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1)
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/* I3C module features */
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/* @brief Has TERM bitfile in MERRWARN reigster. */
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#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1)
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/* INPUTMUX module features */
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/* @brief Number of channels */
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#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1)
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/* @brief Inputmux has channel mux control */
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#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0)
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/* IOCON module features */
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/* @brief Func bit field width */
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#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
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/* MRT module features */
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/* @brief number of channels. */
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#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
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/* PINT module features */
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/* @brief Number of connected outputs */
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#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
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/* @brief Number of connected outputs */
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#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
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/* PMC module features */
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/* @brief UTICK does not support PD configure. */
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#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
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/* @brief WDT OSC does not support PD configure. */
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#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
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/* POWERQUAD module features */
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/* @brief Sine and Cossine fix errata */
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#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)
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/* PUF module features */
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/* @brief the shift status value */
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#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
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/* PWM module features */
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/* @brief If (e)FlexPWM has module A channels (outputs). */
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#define FSL_FEATURE_PWM_HAS_CHANNELA (1)
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/* @brief If (e)FlexPWM has module B channels (outputs). */
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#define FSL_FEATURE_PWM_HAS_CHANNELB (1)
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/* @brief If (e)FlexPWM has module X channels (outputs). */
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#define FSL_FEATURE_PWM_HAS_CHANNELX (1)
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/* @brief If (e)FlexPWM has fractional feature. */
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#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1)
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/* @brief If (e)FlexPWM has mux trigger source select bit field. */
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#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1)
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/* @brief Number of submodules in each (e)FlexPWM module. */
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#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
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/* @brief Number of fault channel in each (e)FlexPWM module. */
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#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1)
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/* RTC module features */
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/* @brief Has Tamper Direction Register support. */
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#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0)
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/* @brief Has Tamper Queue Status and Control Register support. */
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#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (1)
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/* @brief Has RTC subsystem. */
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#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1)
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/* @brief Has Reset in system level. */
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#define FSL_FEATURE_RTC_HAS_RESET (1)
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/* @brief Has RTC Tamper 23 Filter Configuration Register support. */
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#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (1)
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/* @brief Has WAKEUP_MODE bitfile in CTRL2 reigster. */
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#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1)
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/* SCT module features */
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/* @brief Number of events */
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#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
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/* @brief Number of states */
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#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
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/* @brief Number of match capture */
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#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
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/* @brief Number of outputs */
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#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
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/* SECPINT module features */
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/* @brief Number of connected outputs */
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#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
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/* SYSCON module features */
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/* @brief Flash page size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
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/* @brief Flash sector size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
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/* @brief Flash size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (251904)
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/* SYSCTL module features */
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/* @brief SYSCTRL has Code Gray feature. */
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#define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1)
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/* USB module features */
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#if defined(CPU_LPC55S36JBD100)
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/* @brief USB version */
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#define FSL_FEATURE_USB_VERSION (200)
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/* @brief Number of the endpoint in USB FS */
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#define FSL_FEATURE_USB_EP_NUM (5)
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#endif /* defined(CPU_LPC55S36JBD100) */
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/* USBFSH module features */
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#if defined(CPU_LPC55S36JBD100)
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/* @brief USBFSH version */
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#define FSL_FEATURE_USBFSH_VERSION (200)
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#endif /* defined(CPU_LPC55S36JBD100) */
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/* VREF module features */
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/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
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#define FSL_FEATURE_VREF_HAS_CHOP_OSC (0)
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/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
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#define FSL_FEATURE_VREF_HAS_COMPENSATION (0)
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/* @brief If high/low buffer mode supported */
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#define FSL_FEATURE_VREF_MODE_LV_TYPE (0)
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/* @brief Module has also low reference (registers VREFL/VREFH) */
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#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
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/* @brief Has VREF_TRM4. */
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#define FSL_FEATURE_VREF_HAS_TRM4 (0)
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/* WWDT module features */
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/* No feature definitions */
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#endif /* _LPC55S36_FEATURES_H_ */
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