nxp.com MIMXRT1176_cm7 1.0 MIMXRT1176DVMAA Copyright 2016-2022 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause CM7 r0p1 little true true true 4 false 8 32 AUDIO_PLL Fractional PLL AUDIO_PLL 0 0 0x80 registers CTRL0 Fractional PLL Control Register 0 32 read-write 0 0xFFFFFFFF DIV_SELECT DIV_SELECT 0 7 read-write ENABLE_ALT ENABLE_ALT 8 1 read-write DISABLE Disable the alternate clock output 0 ENABLE Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed 0x1 HOLD_RING_OFF PLL Start up initialization 13 1 read-write NORMAL Normal operation 0 ENABLE Initialize PLL start up 0x1 POWERUP POWERUP 14 1 read-write PDOWN Power down the PLL 0 PUP Power Up the PLL 0x1 ENABLE ENABLE 15 1 read-write DISABLE Disable the clock output 0 ENABLE Enable the clock output 0x1 BYPASS BYPASS 16 1 read-write NOBYPASS No Bypass 0 BYPASS Bypass the PLL 0x1 DITHER_EN DITHER_EN 17 1 read-write DISABLE Disable Dither 0 ENABLE Enable Dither 0x1 BIAS_TRIM BIAS_TRIM 19 3 read-write PLL_REG_EN PLL_REG_EN 22 1 read-write POST_DIV_SEL Post Divide Select 25 3 read-write DIVIDE1 Divide by 1 0 DIVIDE2 Divide by 2 0x1 DIVIDE4 Divide by 4 0x2 DIVIDE8 Divide by 8 0x3 DIVIDE16 Divide by 16 0x4 DIVIDE32 Divide by 32 0x5 BIAS_SELECT BIAS_SELECT 29 1 read-write BAIS10 Used in SoCs with a bias current of 10uA 0 BAIS2 Used in SoCs with a bias current of 2uA 0x1 CTRL0_SET Fractional PLL Control Register 0x4 32 read-write 0 0xFFFFFFFF oneToSet DIV_SELECT DIV_SELECT 0 7 read-write oneToSet ENABLE_ALT ENABLE_ALT 8 1 read-write oneToSet HOLD_RING_OFF PLL Start up initialization 13 1 read-write oneToSet POWERUP POWERUP 14 1 read-write oneToSet ENABLE ENABLE 15 1 read-write oneToSet BYPASS BYPASS 16 1 read-write oneToSet DITHER_EN DITHER_EN 17 1 read-write oneToSet BIAS_TRIM BIAS_TRIM 19 3 read-write oneToSet PLL_REG_EN PLL_REG_EN 22 1 read-write oneToSet POST_DIV_SEL Post Divide Select 25 3 read-write oneToSet BIAS_SELECT BIAS_SELECT 29 1 read-write oneToSet CTRL0_CLR Fractional PLL Control Register 0x8 32 read-write 0 0xFFFFFFFF oneToClear DIV_SELECT DIV_SELECT 0 7 read-write oneToClear ENABLE_ALT ENABLE_ALT 8 1 read-write oneToClear HOLD_RING_OFF PLL Start up initialization 13 1 read-write oneToClear POWERUP POWERUP 14 1 read-write oneToClear ENABLE ENABLE 15 1 read-write oneToClear BYPASS BYPASS 16 1 read-write oneToClear DITHER_EN DITHER_EN 17 1 read-write oneToClear BIAS_TRIM BIAS_TRIM 19 3 read-write oneToClear PLL_REG_EN PLL_REG_EN 22 1 read-write oneToClear POST_DIV_SEL Post Divide Select 25 3 read-write oneToClear BIAS_SELECT BIAS_SELECT 29 1 read-write oneToClear CTRL0_TOG Fractional PLL Control Register 0xC 32 read-write 0 0xFFFFFFFF oneToToggle DIV_SELECT DIV_SELECT 0 7 read-write oneToToggle ENABLE_ALT ENABLE_ALT 8 1 read-write oneToToggle HOLD_RING_OFF PLL Start up initialization 13 1 read-write oneToToggle POWERUP POWERUP 14 1 read-write oneToToggle ENABLE ENABLE 15 1 read-write oneToToggle BYPASS BYPASS 16 1 read-write oneToToggle DITHER_EN DITHER_EN 17 1 read-write oneToToggle BIAS_TRIM BIAS_TRIM 19 3 read-write oneToToggle PLL_REG_EN PLL_REG_EN 22 1 read-write oneToToggle POST_DIV_SEL Post Divide Select 25 3 read-write oneToToggle BIAS_SELECT BIAS_SELECT 29 1 read-write oneToToggle SPREAD_SPECTRUM Fractional PLL Spread Spectrum Control Register 0x10 32 read-write 0 0xFFFFFFFF STEP Step 0 15 read-write ENABLE Enable 15 1 read-write STOP Stop 16 16 read-write SPREAD_SPECTRUM_SET Fractional PLL Spread Spectrum Control Register 0x14 32 read-write 0 0xFFFFFFFF oneToSet STEP Step 0 15 read-write oneToSet ENABLE Enable 15 1 read-write oneToSet STOP Stop 16 16 read-write oneToSet SPREAD_SPECTRUM_CLR Fractional PLL Spread Spectrum Control Register 0x18 32 read-write 0 0xFFFFFFFF oneToClear STEP Step 0 15 read-write oneToClear ENABLE Enable 15 1 read-write oneToClear STOP Stop 16 16 read-write oneToClear SPREAD_SPECTRUM_TOG Fractional PLL Spread Spectrum Control Register 0x1C 32 read-write 0 0xFFFFFFFF oneToToggle STEP Step 0 15 read-write oneToToggle ENABLE Enable 15 1 read-write oneToToggle STOP Stop 16 16 read-write oneToToggle NUMERATOR Fractional PLL Numerator Control Register 0x20 32 read-write 0 0xFFFFFFFF NUM Numerator 0 30 read-write NUMERATOR_SET Fractional PLL Numerator Control Register 0x24 32 read-write 0 0xFFFFFFFF oneToSet NUM Numerator 0 30 read-write oneToSet NUMERATOR_CLR Fractional PLL Numerator Control Register 0x28 32 read-write 0 0xFFFFFFFF oneToClear NUM Numerator 0 30 read-write oneToClear NUMERATOR_TOG Fractional PLL Numerator Control Register 0x2C 32 read-write 0 0xFFFFFFFF oneToToggle NUM Numerator 0 30 read-write oneToToggle DENOMINATOR Fractional PLL Denominator Control Register 0x30 32 read-write 0 0xFFFFFFFF DENOM Denominator 0 30 read-write DENOMINATOR_SET Fractional PLL Denominator Control Register 0x34 32 read-write 0 0xFFFFFFFF oneToSet DENOM Denominator 0 30 read-write oneToSet DENOMINATOR_CLR Fractional PLL Denominator Control Register 0x38 32 read-write 0 0xFFFFFFFF oneToClear DENOM Denominator 0 30 read-write oneToClear DENOMINATOR_TOG Fractional PLL Denominator Control Register 0x3C 32 read-write 0 0xFFFFFFFF oneToToggle DENOM Denominator 0 30 read-write oneToToggle ETHERNET_PLL Fractional PLL AUDIO_PLL ETHERNET_PLL 0 0 0x80 registers CTRL0 Fractional PLL Control Register 0 32 read-write 0 0xFFFFFFFF DIV_SELECT DIV_SELECT 0 7 read-write ENABLE_ALT ENABLE_ALT 8 1 read-write DISABLE Disable the alternate clock output 0 ENABLE Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed 0x1 HOLD_RING_OFF PLL Start up initialization 13 1 read-write NORMAL Normal operation 0 ENABLE Initialize PLL start up 0x1 POWERUP POWERUP 14 1 read-write PDOWN Power down the PLL 0 PUP Power Up the PLL 0x1 ENABLE ENABLE 15 1 read-write DISABLE Disable the clock output 0 ENABLE Enable the clock output 0x1 BYPASS BYPASS 16 1 read-write NOBYPASS No Bypass 0 BYPASS Bypass the PLL 0x1 DITHER_EN DITHER_EN 17 1 read-write DISABLE Disable Dither 0 ENABLE Enable Dither 0x1 BIAS_TRIM BIAS_TRIM 19 3 read-write PLL_REG_EN PLL_REG_EN 22 1 read-write POST_DIV_SEL Post Divide Select 25 3 read-write DIVIDE1 Divide by 1 0 DIVIDE2 Divide by 2 0x1 DIVIDE4 Divide by 4 0x2 DIVIDE8 Divide by 8 0x3 DIVIDE16 Divide by 16 0x4 DIVIDE32 Divide by 32 0x5 BIAS_SELECT BIAS_SELECT 29 1 read-write BAIS10 Used in SoCs with a bias current of 10uA 0 BAIS2 Used in SoCs with a bias current of 2uA 0x1 CTRL0_SET Fractional PLL Control Register 0x4 32 read-write 0 0xFFFFFFFF oneToSet DIV_SELECT DIV_SELECT 0 7 read-write oneToSet ENABLE_ALT ENABLE_ALT 8 1 read-write oneToSet HOLD_RING_OFF PLL Start up initialization 13 1 read-write oneToSet POWERUP POWERUP 14 1 read-write oneToSet ENABLE ENABLE 15 1 read-write oneToSet BYPASS BYPASS 16 1 read-write oneToSet DITHER_EN DITHER_EN 17 1 read-write oneToSet BIAS_TRIM BIAS_TRIM 19 3 read-write oneToSet PLL_REG_EN PLL_REG_EN 22 1 read-write oneToSet POST_DIV_SEL Post Divide Select 25 3 read-write oneToSet BIAS_SELECT BIAS_SELECT 29 1 read-write oneToSet CTRL0_CLR Fractional PLL Control Register 0x8 32 read-write 0 0xFFFFFFFF oneToClear DIV_SELECT DIV_SELECT 0 7 read-write oneToClear ENABLE_ALT ENABLE_ALT 8 1 read-write oneToClear HOLD_RING_OFF PLL Start up initialization 13 1 read-write oneToClear POWERUP POWERUP 14 1 read-write oneToClear ENABLE ENABLE 15 1 read-write oneToClear BYPASS BYPASS 16 1 read-write oneToClear DITHER_EN DITHER_EN 17 1 read-write oneToClear BIAS_TRIM BIAS_TRIM 19 3 read-write oneToClear PLL_REG_EN PLL_REG_EN 22 1 read-write oneToClear POST_DIV_SEL Post Divide Select 25 3 read-write oneToClear BIAS_SELECT BIAS_SELECT 29 1 read-write oneToClear CTRL0_TOG Fractional PLL Control Register 0xC 32 read-write 0 0xFFFFFFFF oneToToggle DIV_SELECT DIV_SELECT 0 7 read-write oneToToggle ENABLE_ALT ENABLE_ALT 8 1 read-write oneToToggle HOLD_RING_OFF PLL Start up initialization 13 1 read-write oneToToggle POWERUP POWERUP 14 1 read-write oneToToggle ENABLE ENABLE 15 1 read-write oneToToggle BYPASS BYPASS 16 1 read-write oneToToggle DITHER_EN DITHER_EN 17 1 read-write oneToToggle BIAS_TRIM BIAS_TRIM 19 3 read-write oneToToggle PLL_REG_EN PLL_REG_EN 22 1 read-write oneToToggle POST_DIV_SEL Post Divide Select 25 3 read-write oneToToggle BIAS_SELECT BIAS_SELECT 29 1 read-write oneToToggle SPREAD_SPECTRUM Fractional PLL Spread Spectrum Control Register 0x10 32 read-write 0 0xFFFFFFFF STEP Step 0 15 read-write ENABLE Enable 15 1 read-write STOP Stop 16 16 read-write SPREAD_SPECTRUM_SET Fractional PLL Spread Spectrum Control Register 0x14 32 read-write 0 0xFFFFFFFF oneToSet STEP Step 0 15 read-write oneToSet ENABLE Enable 15 1 read-write oneToSet STOP Stop 16 16 read-write oneToSet SPREAD_SPECTRUM_CLR Fractional PLL Spread Spectrum Control Register 0x18 32 read-write 0 0xFFFFFFFF oneToClear STEP Step 0 15 read-write oneToClear ENABLE Enable 15 1 read-write oneToClear STOP Stop 16 16 read-write oneToClear SPREAD_SPECTRUM_TOG Fractional PLL Spread Spectrum Control Register 0x1C 32 read-write 0 0xFFFFFFFF oneToToggle STEP Step 0 15 read-write oneToToggle ENABLE Enable 15 1 read-write oneToToggle STOP Stop 16 16 read-write oneToToggle NUMERATOR Fractional PLL Numerator Control Register 0x20 32 read-write 0 0xFFFFFFFF NUM Numerator 0 30 read-write NUMERATOR_SET Fractional PLL Numerator Control Register 0x24 32 read-write 0 0xFFFFFFFF oneToSet NUM Numerator 0 30 read-write oneToSet NUMERATOR_CLR Fractional PLL Numerator Control Register 0x28 32 read-write 0 0xFFFFFFFF oneToClear NUM Numerator 0 30 read-write oneToClear NUMERATOR_TOG Fractional PLL Numerator Control Register 0x2C 32 read-write 0 0xFFFFFFFF oneToToggle NUM Numerator 0 30 read-write oneToToggle DENOMINATOR Fractional PLL Denominator Control Register 0x30 32 read-write 0 0xFFFFFFFF DENOM Denominator 0 30 read-write DENOMINATOR_SET Fractional PLL Denominator Control Register 0x34 32 read-write 0 0xFFFFFFFF oneToSet DENOM Denominator 0 30 read-write oneToSet DENOMINATOR_CLR Fractional PLL Denominator Control Register 0x38 32 read-write 0 0xFFFFFFFF oneToClear DENOM Denominator 0 30 read-write oneToClear DENOMINATOR_TOG Fractional PLL Denominator Control Register 0x3C 32 read-write 0 0xFFFFFFFF oneToToggle DENOM Denominator 0 30 read-write oneToToggle OSC_RC_400M no description available AUDIO_PLL OSC_RC_400M 0 0 0x80 registers CTRL0 Control Register 0 0 32 read-write 0 0xFFFFFFFF REF_CLK_DIV Divide value for ref_clk to generate slow_clk (used inside this IP) 24 6 read-write CTRL0_SET Control Register 0 0x4 32 read-write 0 0xFFFFFFFF oneToSet REF_CLK_DIV Divide value for ref_clk to generate slow_clk (used inside this IP) 24 6 read-write oneToSet CTRL0_CLR Control Register 0 0x8 32 read-write 0 0xFFFFFFFF oneToClear REF_CLK_DIV Divide value for ref_clk to generate slow_clk (used inside this IP) 24 6 read-write oneToClear CTRL0_TOG Control Register 0 0xC 32 read-write 0 0xFFFFFFFF oneToToggle REF_CLK_DIV Divide value for ref_clk to generate slow_clk (used inside this IP) 24 6 read-write oneToToggle CTRL1 Control Register 1 0x10 32 read-write 0 0xFFFFFFFF HYST_MINUS Negative hysteresis value for the tuned clock 0 4 read-write HYST_PLUS Positive hysteresis value for the tuned clock 8 4 read-write TARGET_COUNT Target count for the fast clock 16 16 read-write CTRL1_SET Control Register 1 0x14 32 read-write 0 0xFFFFFFFF oneToSet HYST_MINUS Negative hysteresis value for the tuned clock 0 4 read-write oneToSet HYST_PLUS Positive hysteresis value for the tuned clock 8 4 read-write oneToSet TARGET_COUNT Target count for the fast clock 16 16 read-write oneToSet CTRL1_CLR Control Register 1 0x18 32 read-write 0 0xFFFFFFFF oneToClear HYST_MINUS Negative hysteresis value for the tuned clock 0 4 read-write oneToClear HYST_PLUS Positive hysteresis value for the tuned clock 8 4 read-write oneToClear TARGET_COUNT Target count for the fast clock 16 16 read-write oneToClear CTRL1_TOG Control Register 1 0x1C 32 read-write 0 0xFFFFFFFF oneToToggle HYST_MINUS Negative hysteresis value for the tuned clock 0 4 read-write oneToToggle HYST_PLUS Positive hysteresis value for the tuned clock 8 4 read-write oneToToggle TARGET_COUNT Target count for the fast clock 16 16 read-write oneToToggle CTRL2 Control Register 2 0x20 32 read-write 0 0xFFFFFFFF TUNE_BYP Bypass the tuning logic 10 1 read-write TUNE_BYP_0 Use the output of tuning logic to run the oscillator 0 TUNE_BYP_1 Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator 0x1 TUNE_EN Freeze/Unfreeze the tuning value 12 1 read-write TUNE_EN_0 Freezes the tuning at the current tuned value. Oscillator runs at the frozen tuning value 0 TUNE_EN_1 Unfreezes and continues the tuning operation 0x1 TUNE_START Start/Stop tuning 14 1 read-write TUNE_START_0 Stop tuning and reset the tuning logic. Oscillator runs using programmed OSC_TUNE_VAL 0 TUNE_START_1 Start tuning 0x1 OSC_TUNE_VAL Program the oscillator frequency 24 8 read-write CTRL2_SET Control Register 2 0x24 32 read-write 0 0xFFFFFFFF oneToSet TUNE_BYP Bypass the tuning logic 10 1 read-write oneToSet TUNE_EN Freeze/Unfreeze the tuning value 12 1 read-write oneToSet TUNE_START Start/Stop tuning 14 1 read-write oneToSet OSC_TUNE_VAL Program the oscillator frequency 24 8 read-write oneToSet CTRL2_CLR Control Register 2 0x28 32 read-write 0 0xFFFFFFFF oneToClear TUNE_BYP Bypass the tuning logic 10 1 read-write oneToClear TUNE_EN Freeze/Unfreeze the tuning value 12 1 read-write oneToClear TUNE_START Start/Stop tuning 14 1 read-write oneToClear OSC_TUNE_VAL Program the oscillator frequency 24 8 read-write oneToClear CTRL2_TOG Control Register 2 0x2C 32 read-write 0 0xFFFFFFFF oneToToggle TUNE_BYP Bypass the tuning logic 10 1 read-write oneToToggle TUNE_EN Freeze/Unfreeze the tuning value 12 1 read-write oneToToggle TUNE_START Start/Stop tuning 14 1 read-write oneToToggle OSC_TUNE_VAL Program the oscillator frequency 24 8 read-write oneToToggle CTRL3 Control Register 3 0x30 32 read-write 0 0xFFFFFFFF CLR_ERR Clear the error flag CLK1M_ERR 0 1 read-write CLR_ERR_0 No effect 0 CLR_ERR_1 Clears the error flag CLK1M_ERR in status register STAT0 0x1 EN_1M_CLK Enable 1MHz output Clock 8 1 read-write EN_1M_CLK_0 Enable the output (clk_1m_out) 0 EN_1M_CLK_1 Disable the output (clk_1m_out) 0x1 MUX_1M_CLK Select free/locked 1MHz output 10 1 read-write MUX_1M_CLK_0 Select free-running 1MHz to be put out on clk_1m_out 0 MUX_1M_CLK_1 Select locked 1MHz to be put out on clk_1m_out 0x1 COUNT_1M_CLK Count for the locked clk_1m_out 16 16 read-write CTRL3_SET Control Register 3 0x34 32 read-write 0 0xFFFFFFFF oneToSet CLR_ERR Clear the error flag CLK1M_ERR 0 1 read-write oneToSet EN_1M_CLK Enable 1MHz output Clock 8 1 read-write oneToSet MUX_1M_CLK Select free/locked 1MHz output 10 1 read-write oneToSet COUNT_1M_CLK Count for the locked clk_1m_out 16 16 read-write oneToSet CTRL3_CLR Control Register 3 0x38 32 read-write 0 0xFFFFFFFF oneToClear CLR_ERR Clear the error flag CLK1M_ERR 0 1 read-write oneToClear EN_1M_CLK Enable 1MHz output Clock 8 1 read-write oneToClear MUX_1M_CLK Select free/locked 1MHz output 10 1 read-write oneToClear COUNT_1M_CLK Count for the locked clk_1m_out 16 16 read-write oneToClear CTRL3_TOG Control Register 3 0x3C 32 read-write 0 0xFFFFFFFF oneToToggle CLR_ERR Clear the error flag CLK1M_ERR 0 1 read-write oneToToggle EN_1M_CLK Enable 1MHz output Clock 8 1 read-write oneToToggle MUX_1M_CLK Select free/locked 1MHz output 10 1 read-write oneToToggle COUNT_1M_CLK Count for the locked clk_1m_out 16 16 read-write oneToToggle STAT0 Status Register 0 0x50 32 read-only 0 0xFFFFFFFF CLK1M_ERR Error flag for clk_1m_locked 0 1 read-only CLK1M_ERR_0 No effect 0 CLK1M_ERR_1 The count value has been reached within one divided ref_clk period 0x1 STAT0_SET Status Register 0 0x54 32 read-only 0 0xFFFFFFFF oneToSet CLK1M_ERR Error flag for clk_1m_locked 0 1 read-only oneToSet STAT0_CLR Status Register 0 0x58 32 read-only 0 0xFFFFFFFF oneToClear CLK1M_ERR Error flag for clk_1m_locked 0 1 read-only oneToClear STAT0_TOG Status Register 0 0x5C 32 read-only 0 0xFFFFFFFF oneToToggle CLK1M_ERR Error flag for clk_1m_locked 0 1 read-only oneToToggle STAT1 Status Register 1 0x60 32 read-only 0 0xFFFFFFFF CURR_COUNT_VAL Current count for the fast clock 16 16 read-only STAT1_SET Status Register 1 0x64 32 read-only 0 0xFFFFFFFF oneToSet CURR_COUNT_VAL Current count for the fast clock 16 16 read-only oneToSet STAT1_CLR Status Register 1 0x68 32 read-only 0 0xFFFFFFFF oneToClear CURR_COUNT_VAL Current count for the fast clock 16 16 read-only oneToClear STAT1_TOG Status Register 1 0x6C 32 read-only 0 0xFFFFFFFF oneToToggle CURR_COUNT_VAL Current count for the fast clock 16 16 read-only oneToToggle STAT2 Status Register 2 0x70 32 read-only 0 0xFFFFFFFF CURR_OSC_TUNE_VAL Current tuning value used by oscillator 24 8 read-only STAT2_SET Status Register 2 0x74 32 read-only 0 0xFFFFFFFF oneToSet CURR_OSC_TUNE_VAL Current tuning value used by oscillator 24 8 read-only oneToSet STAT2_CLR Status Register 2 0x78 32 read-only 0 0xFFFFFFFF oneToClear CURR_OSC_TUNE_VAL Current tuning value used by oscillator 24 8 read-only oneToClear STAT2_TOG Status Register 2 0x7C 32 read-only 0 0xFFFFFFFF oneToToggle CURR_OSC_TUNE_VAL Current tuning value used by oscillator 24 8 read-only oneToToggle PHY_LDO no description available AUDIO_PLL PHY_LDO 0 0 0x80 registers CTRL0 Analog Control Register CTRL0 0 32 read-write 0 0xFFFFFFFF LINREG_EN LinrReg master enable 0 1 read-write LINREG_PWRUPLOAD_DIS LinReg power-up load disable 1 1 read-write LINREG_PWRUPLOAD_DIS_0 Internal pull-down enabled 0 LINREG_PWRUPLOAD_DIS_1 Internal pull-down disabled 0x1 LINREG_ILIMIT_EN LinReg current-limit enable 2 1 read-write LINREG_OUTPUT_TRG LinReg output voltage target setting 4 5 read-write LINREG_OUTPUT_TRG_0 Set output voltage to x.xV 0 LINREG_OUTPUT_TRG_16 Sets output voltage to 1.0V 0x10 LINREG_OUTPUT_TRG_31 Set output voltage to x.xV 0x1F LINREG_PHY_ISO_B Isolation control for attached PHY load 15 1 read-write CTRL0_SET Analog Control Register CTRL0 0x4 32 read-write 0 0xFFFFFFFF oneToSet LINREG_EN LinrReg master enable 0 1 read-write oneToSet LINREG_PWRUPLOAD_DIS LinReg power-up load disable 1 1 read-write oneToSet LINREG_ILIMIT_EN LinReg current-limit enable 2 1 read-write oneToSet LINREG_OUTPUT_TRG LinReg output voltage target setting 4 5 read-write oneToSet LINREG_PHY_ISO_B Isolation control for attached PHY load 15 1 read-write oneToSet CTRL0_CLR Analog Control Register CTRL0 0x8 32 read-write 0 0xFFFFFFFF oneToClear LINREG_EN LinrReg master enable 0 1 read-write oneToClear LINREG_PWRUPLOAD_DIS LinReg power-up load disable 1 1 read-write oneToClear LINREG_ILIMIT_EN LinReg current-limit enable 2 1 read-write oneToClear LINREG_OUTPUT_TRG LinReg output voltage target setting 4 5 read-write oneToClear LINREG_PHY_ISO_B Isolation control for attached PHY load 15 1 read-write oneToClear CTRL0_TOG Analog Control Register CTRL0 0xC 32 read-write 0 0xFFFFFFFF oneToToggle LINREG_EN LinrReg master enable 0 1 read-write oneToToggle LINREG_PWRUPLOAD_DIS LinReg power-up load disable 1 1 read-write oneToToggle LINREG_ILIMIT_EN LinReg current-limit enable 2 1 read-write oneToToggle LINREG_OUTPUT_TRG LinReg output voltage target setting 4 5 read-write oneToToggle LINREG_PHY_ISO_B Isolation control for attached PHY load 15 1 read-write oneToToggle STAT0 Analog Status Register STAT0 0x50 32 read-only 0 0xFFFFFFFF LINREG_STAT LinReg Status Bits 0 4 read-only STAT0_SET Analog Status Register STAT0 0x54 32 read-only 0 0xFFFFFFFF oneToSet LINREG_STAT LinReg Status Bits 0 4 read-only oneToSet STAT0_CLR Analog Status Register STAT0 0x58 32 read-only 0 0xFFFFFFFF oneToClear LINREG_STAT LinReg Status Bits 0 4 read-only oneToClear STAT0_TOG Analog Status Register STAT0 0x5C 32 read-only 0 0xFFFFFFFF oneToToggle LINREG_STAT LinReg Status Bits 0 4 read-only oneToToggle TMPSNS Temperature Sensor Memory Map AUDIO_PLL TMPSNS 0 0 0x10000 registers TMPSNS_INT 83 TMPSNS_LOW_HIGH 84 TMPSNS_PANIC 85 CTRL0 Temperature Sensor Control Register 0 0 32 read-write 0x8020 0xFFFFFFFF SLOPE_CAL Ramp slope calibration control 0 6 read-write V_SEL Voltage Select 8 2 read-write V_SEL_0 Normal temperature measuring mode 0 IBIAS_TRIM Current bias trim value 12 4 read-write CTRL0_SET Temperature Sensor Control Register 0 0x4 32 read-write 0x8020 0xFFFFFFFF oneToSet SLOPE_CAL Ramp slope calibration control 0 6 read-write oneToSet V_SEL Voltage Select 8 2 read-write oneToSet IBIAS_TRIM Current bias trim value 12 4 read-write oneToSet CTRL0_CLR Temperature Sensor Control Register 0 0x8 32 read-write 0x8020 0xFFFFFFFF oneToClear SLOPE_CAL Ramp slope calibration control 0 6 read-write oneToClear V_SEL Voltage Select 8 2 read-write oneToClear IBIAS_TRIM Current bias trim value 12 4 read-write oneToClear CTRL0_TOG Temperature Sensor Control Register 0 0xC 32 read-write 0x8020 0xFFFFFFFF oneToToggle SLOPE_CAL Ramp slope calibration control 0 6 read-write oneToToggle V_SEL Voltage Select 8 2 read-write oneToToggle IBIAS_TRIM Current bias trim value 12 4 read-write oneToToggle CTRL1 Temperature Sensor Control Register 1 0x10 32 read-write 0x800000 0xFFFFFFFF FREQ Temperature Measurement Frequency 0 16 read-write FREQ_0 Single Reading Mode. New reading available every time CTRL1[START] bit is set to 1 from 0. 0 FREQ_1 Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete. 0x1 FREQ_2 Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete. 0x2 FREQ_3 Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete. 0x3 FREQ_4 Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete. 0x4 FREQ_5 Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete. 0x5 FREQ_6 Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete. 0x6 FREQ_7 Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete. 0x7 FREQ_8 Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete. 0x8 FREQ_9 Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete. 0x9 FINISH_IE Measurement finished interrupt enable 16 1 read-write FINISH_IE_0 Interrupt is disabled 0 FINISH_IE_1 Interrupt is enabled 0x1 LOW_TEMP_IE Low temperature interrupt enable 17 1 read-write LOW_TEMP_IE_0 Interrupt is disabled 0 LOW_TEMP_IE_1 Interrupt is enabled 0x1 HIGH_TEMP_IE High temperature interrupt enable 18 1 read-write HIGH_TEMP_IE_0 Interrupt is disabled 0 HIGH_TEMP_IE_1 Interrupt is enabled 0x1 PANIC_TEMP_IE Panic temperature interrupt enable 19 1 read-write PANIC_TEMP_IE_0 Interrupt is disabled 0 PANIC_TEMP_IE_1 Interrupt is enabled 0x1 START Start Temperature Measurement 22 1 read-write START_0 No new temperature reading taken 0 START_1 Initiate a new temperature reading 0x1 PWD Temperature Sensor Power Down 23 1 read-write PWD_0 Sensor is active 0 PWD_1 Sensor is powered down 0x1 RFU Read/Writeable field. Reserved for future use 24 7 read-write PWD_FULL Temperature Sensor Full Power Down 31 1 read-write PWD_FULL_0 Sensor is active 0 PWD_FULL_1 Sensor is powered down 0x1 CTRL1_SET Temperature Sensor Control Register 1 0x14 32 read-write 0x800000 0xFFFFFFFF oneToSet FREQ Temperature Measurement Frequency 0 16 read-write oneToSet FINISH_IE Measurement finished interrupt enable 16 1 read-write oneToSet LOW_TEMP_IE Low temperature interrupt enable 17 1 read-write oneToSet HIGH_TEMP_IE High temperature interrupt enable 18 1 read-write oneToSet PANIC_TEMP_IE Panic temperature interrupt enable 19 1 read-write oneToSet START Start Temperature Measurement 22 1 read-write oneToSet PWD Temperature Sensor Power Down 23 1 read-write oneToSet RFU Read/Writeable field. Reserved for future use 24 7 read-write oneToSet PWD_FULL Temperature Sensor Full Power Down 31 1 read-write oneToSet CTRL1_CLR Temperature Sensor Control Register 1 0x18 32 read-write 0x800000 0xFFFFFFFF oneToClear FREQ Temperature Measurement Frequency 0 16 read-write oneToClear FINISH_IE Measurement finished interrupt enable 16 1 read-write oneToClear LOW_TEMP_IE Low temperature interrupt enable 17 1 read-write oneToClear HIGH_TEMP_IE High temperature interrupt enable 18 1 read-write oneToClear PANIC_TEMP_IE Panic temperature interrupt enable 19 1 read-write oneToClear START Start Temperature Measurement 22 1 read-write oneToClear PWD Temperature Sensor Power Down 23 1 read-write oneToClear RFU Read/Writeable field. Reserved for future use 24 7 read-write oneToClear PWD_FULL Temperature Sensor Full Power Down 31 1 read-write oneToClear CTRL1_TOG Temperature Sensor Control Register 1 0x1C 32 read-write 0x800000 0xFFFFFFFF oneToToggle FREQ Temperature Measurement Frequency 0 16 read-write oneToToggle FINISH_IE Measurement finished interrupt enable 16 1 read-write oneToToggle LOW_TEMP_IE Low temperature interrupt enable 17 1 read-write oneToToggle HIGH_TEMP_IE High temperature interrupt enable 18 1 read-write oneToToggle PANIC_TEMP_IE Panic temperature interrupt enable 19 1 read-write oneToToggle START Start Temperature Measurement 22 1 read-write oneToToggle PWD Temperature Sensor Power Down 23 1 read-write oneToToggle RFU Read/Writeable field. Reserved for future use 24 7 read-write oneToToggle PWD_FULL Temperature Sensor Full Power Down 31 1 read-write oneToToggle RANGE0 Temperature Sensor Range Register 0 0x20 32 read-write 0 0xFFFFFFFF LOW_TEMP_VAL Low temperature threshold value 0 12 read-write HIGH_TEMP_VAL High temperature threshold value 16 12 read-write RANGE0_SET Temperature Sensor Range Register 0 0x24 32 read-write 0 0xFFFFFFFF oneToSet LOW_TEMP_VAL Low temperature threshold value 0 12 read-write oneToSet HIGH_TEMP_VAL High temperature threshold value 16 12 read-write oneToSet RANGE0_CLR Temperature Sensor Range Register 0 0x28 32 read-write 0 0xFFFFFFFF oneToClear LOW_TEMP_VAL Low temperature threshold value 0 12 read-write oneToClear HIGH_TEMP_VAL High temperature threshold value 16 12 read-write oneToClear RANGE0_TOG Temperature Sensor Range Register 0 0x2C 32 read-write 0 0xFFFFFFFF oneToToggle LOW_TEMP_VAL Low temperature threshold value 0 12 read-write oneToToggle HIGH_TEMP_VAL High temperature threshold value 16 12 read-write oneToToggle RANGE1 Temperature Sensor Range Register 1 0x30 32 read-write 0 0xFFFFFFFF PANIC_TEMP_VAL Panic temperature threshold value 0 12 read-write RANGE1_SET Temperature Sensor Range Register 1 0x34 32 read-write 0 0xFFFFFFFF oneToSet PANIC_TEMP_VAL Panic temperature threshold value 0 12 read-write oneToSet RANGE1_CLR Temperature Sensor Range Register 1 0x38 32 read-write 0 0xFFFFFFFF oneToClear PANIC_TEMP_VAL Panic temperature threshold value 0 12 read-write oneToClear RANGE1_TOG Temperature Sensor Range Register 1 0x3C 32 read-write 0 0xFFFFFFFF oneToToggle PANIC_TEMP_VAL Panic temperature threshold value 0 12 read-write oneToToggle STATUS0 Temperature Sensor Status Register 0 0x50 32 read-write 0 0xFFFFFFFF TEMP_VAL Measured temperature value 0 12 read-only FINISH Temperature measurement complete 16 1 read-write oneToClear FINISH_0 Temperature sensor is busy (if CTRL1[START] = 1)or no new reading has been initiated (if CTRL1[START] = 0) 0 FINISH_1 Temperature reading is complete and new temperature value available for reading 0x1 LOW_TEMP Low temperature alarm bit 17 1 read-write oneToClear LOW_TEMP_0 No Low temperature alert 0 LOW_TEMP_1 Low temperature alert 0x1 HIGH_TEMP High temperature alarm bit 18 1 read-write oneToClear HIGH_TEMP_0 No High temperature alert 0 HIGH_TEMP_1 High temperature alert 0x1 PANIC_TEMP Panic temperature alarm bit 19 1 read-write oneToClear PANIC_TEMP_0 No Panic temperature alert 0 PANIC_TEMP_1 Panic temperature alert 0x1 VIDEO_PLL Fractional PLL AUDIO_PLL VIDEO_PLL 0 0 0x80 registers CTRL0 Fractional PLL Control Register 0 32 read-write 0 0xFFFFFFFF DIV_SELECT DIV_SELECT 0 7 read-write ENABLE_ALT ENABLE_ALT 8 1 read-write DISABLE Disable the alternate clock output 0 ENABLE Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed 0x1 HOLD_RING_OFF PLL Start up initialization 13 1 read-write NORMAL Normal operation 0 ENABLE Initialize PLL start up 0x1 POWERUP POWERUP 14 1 read-write PDOWN Power down the PLL 0 PUP Power Up the PLL 0x1 ENABLE ENABLE 15 1 read-write DISABLE Disable the clock output 0 ENABLE Enable the clock output 0x1 BYPASS BYPASS 16 1 read-write NOBYPASS No Bypass 0 BYPASS Bypass the PLL 0x1 DITHER_EN DITHER_EN 17 1 read-write DISABLE Disable Dither 0 ENABLE Enable Dither 0x1 BIAS_TRIM BIAS_TRIM 19 3 read-write PLL_REG_EN PLL_REG_EN 22 1 read-write POST_DIV_SEL Post Divide Select 25 3 read-write DIVIDE1 Divide by 1 0 DIVIDE2 Divide by 2 0x1 DIVIDE4 Divide by 4 0x2 DIVIDE8 Divide by 8 0x3 DIVIDE16 Divide by 16 0x4 DIVIDE32 Divide by 32 0x5 BIAS_SELECT BIAS_SELECT 29 1 read-write BAIS10 Used in SoCs with a bias current of 10uA 0 BAIS2 Used in SoCs with a bias current of 2uA 0x1 CTRL0_SET Fractional PLL Control Register 0x4 32 read-write 0 0xFFFFFFFF oneToSet DIV_SELECT DIV_SELECT 0 7 read-write oneToSet ENABLE_ALT ENABLE_ALT 8 1 read-write oneToSet HOLD_RING_OFF PLL Start up initialization 13 1 read-write oneToSet POWERUP POWERUP 14 1 read-write oneToSet ENABLE ENABLE 15 1 read-write oneToSet BYPASS BYPASS 16 1 read-write oneToSet DITHER_EN DITHER_EN 17 1 read-write oneToSet BIAS_TRIM BIAS_TRIM 19 3 read-write oneToSet PLL_REG_EN PLL_REG_EN 22 1 read-write oneToSet POST_DIV_SEL Post Divide Select 25 3 read-write oneToSet BIAS_SELECT BIAS_SELECT 29 1 read-write oneToSet CTRL0_CLR Fractional PLL Control Register 0x8 32 read-write 0 0xFFFFFFFF oneToClear DIV_SELECT DIV_SELECT 0 7 read-write oneToClear ENABLE_ALT ENABLE_ALT 8 1 read-write oneToClear HOLD_RING_OFF PLL Start up initialization 13 1 read-write oneToClear POWERUP POWERUP 14 1 read-write oneToClear ENABLE ENABLE 15 1 read-write oneToClear BYPASS BYPASS 16 1 read-write oneToClear DITHER_EN DITHER_EN 17 1 read-write oneToClear BIAS_TRIM BIAS_TRIM 19 3 read-write oneToClear PLL_REG_EN PLL_REG_EN 22 1 read-write oneToClear POST_DIV_SEL Post Divide Select 25 3 read-write oneToClear BIAS_SELECT BIAS_SELECT 29 1 read-write oneToClear CTRL0_TOG Fractional PLL Control Register 0xC 32 read-write 0 0xFFFFFFFF oneToToggle DIV_SELECT DIV_SELECT 0 7 read-write oneToToggle ENABLE_ALT ENABLE_ALT 8 1 read-write oneToToggle HOLD_RING_OFF PLL Start up initialization 13 1 read-write oneToToggle POWERUP POWERUP 14 1 read-write oneToToggle ENABLE ENABLE 15 1 read-write oneToToggle BYPASS BYPASS 16 1 read-write oneToToggle DITHER_EN DITHER_EN 17 1 read-write oneToToggle BIAS_TRIM BIAS_TRIM 19 3 read-write oneToToggle PLL_REG_EN PLL_REG_EN 22 1 read-write oneToToggle POST_DIV_SEL Post Divide Select 25 3 read-write oneToToggle BIAS_SELECT BIAS_SELECT 29 1 read-write oneToToggle SPREAD_SPECTRUM Fractional PLL Spread Spectrum Control Register 0x10 32 read-write 0 0xFFFFFFFF STEP Step 0 15 read-write ENABLE Enable 15 1 read-write STOP Stop 16 16 read-write SPREAD_SPECTRUM_SET Fractional PLL Spread Spectrum Control Register 0x14 32 read-write 0 0xFFFFFFFF oneToSet STEP Step 0 15 read-write oneToSet ENABLE Enable 15 1 read-write oneToSet STOP Stop 16 16 read-write oneToSet SPREAD_SPECTRUM_CLR Fractional PLL Spread Spectrum Control Register 0x18 32 read-write 0 0xFFFFFFFF oneToClear STEP Step 0 15 read-write oneToClear ENABLE Enable 15 1 read-write oneToClear STOP Stop 16 16 read-write oneToClear SPREAD_SPECTRUM_TOG Fractional PLL Spread Spectrum Control Register 0x1C 32 read-write 0 0xFFFFFFFF oneToToggle STEP Step 0 15 read-write oneToToggle ENABLE Enable 15 1 read-write oneToToggle STOP Stop 16 16 read-write oneToToggle NUMERATOR Fractional PLL Numerator Control Register 0x20 32 read-write 0 0xFFFFFFFF NUM Numerator 0 30 read-write NUMERATOR_SET Fractional PLL Numerator Control Register 0x24 32 read-write 0 0xFFFFFFFF oneToSet NUM Numerator 0 30 read-write oneToSet NUMERATOR_CLR Fractional PLL Numerator Control Register 0x28 32 read-write 0 0xFFFFFFFF oneToClear NUM Numerator 0 30 read-write oneToClear NUMERATOR_TOG Fractional PLL Numerator Control Register 0x2C 32 read-write 0 0xFFFFFFFF oneToToggle NUM Numerator 0 30 read-write oneToToggle DENOMINATOR Fractional PLL Denominator Control Register 0x30 32 read-write 0 0xFFFFFFFF DENOM Denominator 0 30 read-write DENOMINATOR_SET Fractional PLL Denominator Control Register 0x34 32 read-write 0 0xFFFFFFFF oneToSet DENOM Denominator 0 30 read-write oneToSet DENOMINATOR_CLR Fractional PLL Denominator Control Register 0x38 32 read-write 0 0xFFFFFFFF oneToClear DENOM Denominator 0 30 read-write oneToClear DENOMINATOR_TOG Fractional PLL Denominator Control Register 0x3C 32 read-write 0 0xFFFFFFFF oneToToggle DENOM Denominator 0 30 read-write oneToToggle VMBANDGAP no description available AUDIO_PLL VMBANDGAP 0 0 0x80 registers CTRL0 Analog Control Register CTRL0 0 32 read-write 0 0xFFFFFFFF REFTOP_PWD Master power-down for bandgap module 0 1 read-write REFTOP_LINREGREF_PWD Power-down for bandgap voltage-reference buffer 1 1 read-write REFTOP_PWDVBGUP Power-down VBGUP detector in bandgap 2 1 read-write REFTOP_LOWPOWER Low-power control bit 3 1 read-write REFTOP_SELFBIASOFF bandgap self-bias control bit 4 1 read-write CTRL0_SET Analog Control Register CTRL0 0x4 32 read-write 0 0xFFFFFFFF oneToSet REFTOP_PWD Master power-down for bandgap module 0 1 read-write oneToSet REFTOP_LINREGREF_PWD Power-down for bandgap voltage-reference buffer 1 1 read-write oneToSet REFTOP_PWDVBGUP Power-down VBGUP detector in bandgap 2 1 read-write oneToSet REFTOP_LOWPOWER Low-power control bit 3 1 read-write oneToSet REFTOP_SELFBIASOFF bandgap self-bias control bit 4 1 read-write oneToSet CTRL0_CLR Analog Control Register CTRL0 0x8 32 read-write 0 0xFFFFFFFF oneToClear REFTOP_PWD Master power-down for bandgap module 0 1 read-write oneToClear REFTOP_LINREGREF_PWD Power-down for bandgap voltage-reference buffer 1 1 read-write oneToClear REFTOP_PWDVBGUP Power-down VBGUP detector in bandgap 2 1 read-write oneToClear REFTOP_LOWPOWER Low-power control bit 3 1 read-write oneToClear REFTOP_SELFBIASOFF bandgap self-bias control bit 4 1 read-write oneToClear CTRL0_TOG Analog Control Register CTRL0 0xC 32 read-write 0 0xFFFFFFFF oneToToggle REFTOP_PWD Master power-down for bandgap module 0 1 read-write oneToToggle REFTOP_LINREGREF_PWD Power-down for bandgap voltage-reference buffer 1 1 read-write oneToToggle REFTOP_PWDVBGUP Power-down VBGUP detector in bandgap 2 1 read-write oneToToggle REFTOP_LOWPOWER Low-power control bit 3 1 read-write oneToToggle REFTOP_SELFBIASOFF bandgap self-bias control bit 4 1 read-write oneToToggle STAT0 Analog Status Register STAT0 0x50 32 read-only 0 0xFFFFFFFF REFTOP_VBGUP Brief description here 0 1 read-only VDD1_PORB Brief description here 1 1 read-only VDD2_PORB Brief description here 2 1 read-only VDD3_PORB Brief description here 3 1 read-only STAT0_SET Analog Status Register STAT0 0x54 32 read-only 0 0xFFFFFFFF oneToSet REFTOP_VBGUP Brief description here 0 1 read-only oneToSet VDD1_PORB Brief description here 1 1 read-only oneToSet VDD2_PORB Brief description here 2 1 read-only oneToSet VDD3_PORB Brief description here 3 1 read-only oneToSet STAT0_CLR Analog Status Register STAT0 0x58 32 read-only 0 0xFFFFFFFF oneToClear REFTOP_VBGUP Brief description here 0 1 read-only oneToClear VDD1_PORB Brief description here 1 1 read-only oneToClear VDD2_PORB Brief description here 2 1 read-only oneToClear VDD3_PORB Brief description here 3 1 read-only oneToClear STAT0_TOG Analog Status Register STAT0 0x5C 32 read-only 0 0xFFFFFFFF oneToToggle REFTOP_VBGUP Brief description here 0 1 read-only oneToToggle VDD1_PORB Brief description here 1 1 read-only oneToToggle VDD2_PORB Brief description here 2 1 read-only oneToToggle VDD3_PORB Brief description here 3 1 read-only oneToToggle MECC1 MECC64 MECC MECC 0x40014000 0 0x108 registers MECC1_INT 206 MECC1_FATAL_INT 207 MECC2_FATAL_INT 209 ERR_STATUS Error Interrupt Status Register 0 32 read-write 0 0xFFFFFFFF oneToClear SINGLE_ERR0 Single Bit Error On OCRAM Bank0 0 1 read-write oneToClear SINGLE_ERR0_0 Single bit error does not happen on OCRAM bank0. 0 SINGLE_ERR0_1 Single bit error happens on OCRAM bank0. 0x1 SINGLE_ERR1 Single Bit Error On OCRAM Bank1 1 1 read-write oneToClear SINGLE_ERR1_0 Single bit error does not happen on OCRAM bank1. 0 SINGLE_ERR1_1 Single bit error happens on OCRAM bank1. 0x1 SINGLE_ERR2 Single Bit Error On OCRAM Bank2 2 1 read-write oneToClear SINGLE_ERR2_0 Single bit error does not happen on OCRAM bank2. 0 SINGLE_ERR2_1 Single bit error happens on OCRAM bank2. 0x1 SINGLE_ERR3 Single Bit Error On OCRAM Bank3 3 1 read-write oneToClear SINGLE_ERR3_0 Single bit error does not happen on OCRAM bank3. 0 SINGLE_ERR3_1 Single bit error happens on OCRAM bank3. 0x1 MULTI_ERR0 Multiple Bits Error On OCRAM Bank0 4 1 read-write oneToClear MULTI_ERR0_0 Multiple bits error does not happen on OCRAM bank0. 0 MULTI_ERR0_1 Multiple bits error happens on OCRAM bank0. 0x1 MULTI_ERR1 Multiple Bits Error On OCRAM Bank1 5 1 read-write oneToClear MULTI_ERR1_0 Multiple bits error does not happen on OCRAM bank1. 0 MULTI_ERR1_1 Multiple bits error happens on OCRAM bank1. 0x1 MULTI_ERR2 Multiple Bits Error On OCRAM Bank2 6 1 read-write oneToClear MULTI_ERR2_0 Multiple bits error does not happen on OCRAM bank2. 0 MULTI_ERR2_1 Multiple bits error happens on OCRAM bank2. 0x1 MULTI_ERR3 Multiple Bits Error On OCRAM Bank3 7 1 read-write oneToClear MULTI_ERR3_0 Multiple bits error does not happen on OCRAM bank3. 0 MULTI_ERR3_1 Multiple bits error happens on OCRAM bank3. 0x1 STRB_ERR0 AXI Strobe Error On OCRAM Bank0 8 1 read-write oneToClear STRB_ERR0_0 AXI strobe error does not happen on OCRAM bank0. 0 STRB_ERR0_1 AXI strobe error happens on OCRAM bank0. 0x1 STRB_ERR1 AXI Strobe Error On OCRAM Bank1 9 1 read-write oneToClear STRB_ERR1_0 AXI strobe error does not happen on OCRAM bank1. 0 STRB_ERR1_1 AXI strobe error happens on OCRAM bank1. 0x1 STRB_ERR2 AXI Strobe Error On OCRAM Bank2 10 1 read-write oneToClear STRB_ERR2_0 AXI strobe error does not happen on OCRAM bank2. 0 STRB_ERR2_1 AXI strobe error happens on OCRAM bank2. 0x1 STRB_ERR3 AXI Strobe Error On OCRAM Bank3 11 1 read-write oneToClear STRB_ERR3_0 AXI strobe error does not happen on OCRAM bank3. 0 STRB_ERR3_1 AXI strobe error happens on OCRAM bank3. 0x1 ADDR_ERR0 OCRAM Access Error On Bank0 12 1 read-write oneToClear ADDR_ERR0_0 OCRAM access error does not happen on OCRAM bank0. 0 ADDR_ERR0_1 OCRAM access error happens on OCRAM bank0. 0x1 ADDR_ERR1 OCRAM Access Error On Bank1 13 1 read-write oneToClear ADDR_ERR1_0 OCRAM access error does not happen on OCRAM bank1. 0 ADDR_ERR1_1 OCRAM access error happens on OCRAM bank1. 0x1 ADDR_ERR2 OCRAM Access Error On Bank2 14 1 read-write oneToClear ADDR_ERR2_0 OCRAM access error does not happen on OCRAM bank2. 0 ADDR_ERR2_1 OCRAM access error happens on OCRAM bank2. 0x1 ADDR_ERR3 OCRAM Access Error On Bank3 15 1 read-write oneToClear ADDR_ERR3_0 OCRAM access error does not happen on OCRAM bank3. 0 ADDR_ERR3_1 OCRAM access error happens on OCRAM bank3. 0x1 ERR_STAT_EN Error Interrupt Status Enable Register 0x4 32 read-write 0 0xFFFFFFFF SINGLE_ERR0_STAT_EN Single Bit Error Status Enable On OCRAM Bank0 0 1 read-write SINGLE_ERR0_STAT_EN_0 Disabled 0 SINGLE_ERR0_STAT_EN_1 Enabled 0x1 SINGLE_ERR1_STAT_EN Single Bit Error Status Enable On OCRAM Bank1 1 1 read-write SINGLE_ERR1_STAT_EN_0 Disabled 0 SINGLE_ERR1_STAT_EN_1 Enabled 0x1 SINGLE_ERR2_STAT_EN Single Bit Error Status Enable On OCRAM Bank2 2 1 read-write SINGLE_ERR2_STAT_EN_0 Disabled 0 SINGLE_ERR2_STAT_EN_1 Enabled 0x1 SINGLE_ERR3_STAT_EN Single Bit Error Status Enable On OCRAM Bank3 3 1 read-write SINGLE_ERR3_STAT_EN_0 Disabled 0 SINGLE_ERR3_STAT_EN_1 Enabled 0x1 MULTI_ERR0_STAT_EN Multiple Bits Error Status Enable On OCRAM Bank0 4 1 read-write MULTI_ERR0_STAT_EN_0 Disabled 0 MULTI_ERR0_STAT_EN_1 Enabled 0x1 MULTI_ERR1_STAT_EN Multiple Bits Error Status Enable On OCRAM Bank1 5 1 read-write MULTI_ERR1_STAT_EN_0 Disabled 0 MULTI_ERR1_STAT_EN_1 Enabled 0x1 MULTI_ERR2_STAT_EN Multiple Bits Error Status Enable On OCRAM Bank2 6 1 read-write MULTI_ERR2_STAT_EN_0 Disabled 0 MULTI_ERR2_STAT_EN_1 Enabled 0x1 MULTI_ERR3_STAT_EN Multiple Bits Error Status Enable On OCRAM Bank3 7 1 read-write MULTI_ERR3_STAT_EN_0 Disabled 0 MULTI_ERR3_STAT_EN_1 Enabled 0x1 STRB_ERR0_STAT_EN AXI Strobe Error Status Enable On OCRAM Bank0 8 1 read-write STRB_ERR0_STAT_EN_0 Disabled 0 STRB_ERR0_STAT_EN_1 Enabled 0x1 STRB_ERR1_STAT_EN AXI Strobe Error Status Enable On OCRAM Bank1 9 1 read-write STRB_ERR1_STAT_EN_0 Disabled 0 STRB_ERR1_STAT_EN_1 Enabled 0x1 STRB_ERR2_STAT_EN AXI Strobe Error Status Enable On OCRAM Bank2 10 1 read-write STRB_ERR2_STAT_EN_0 Disabled 0 STRB_ERR2_STAT_EN_1 Enabled 0x1 STRB_ERR3_STAT_EN AXI Strobe Error Status Enable On OCRAM Bank3 11 1 read-write STRB_ERR3_STAT_EN_0 Disabled 0 STRB_ERR3_STAT_EN_1 Enabled 0x1 ADDR_ERR0_STAT_EN OCRAM Access Error Status Enable On Bank0 12 1 read-write ADDR_ERR0_STAT_EN_0 Disabled 0 ADDR_ERR0_STAT_EN_1 Enabled 0x1 ADDR_ERR1_STAT_EN OCRAM Access Error Status Enable On Bank1 13 1 read-write ADDR_ERR1_STAT_EN_0 Disabled 0 ADDR_ERR1_STAT_EN_1 Enabled 0x1 ADDR_ERR2_STAT_EN OCRAM Access Error Status Enable On Bank2 14 1 read-write ADDR_ERR2_STAT_EN_0 Disabled 0 ADDR_ERR2_STAT_EN_1 Enabled 0x1 ADDR_ERR3_STAT_EN OCRAM Access Error Status Enable On Bank3 15 1 read-write ADDR_ERR3_STAT_EN_0 Disabled 0 ADDR_ERR3_STAT_EN_1 Enabled 0x1 ERR_SIG_EN Error Interrupt Enable Register 0x8 32 read-write 0 0xFFFFFFFF SINGLE_ERR0_SIG_EN Single Bit Error Interrupt Enable On OCRAM Bank0 0 1 read-write SINGLE_ERR0_SIG_EN_0 Disabled 0 SINGLE_ERR0_SIG_EN_1 Enabled 0x1 SINGLE_ERR1_SIG_EN Single Bit Error Interrupt Enable On OCRAM Bank1 1 1 read-write SINGLE_ERR1_SIG_EN_0 Disabled 0 SINGLE_ERR1_SIG_EN_1 Enabled 0x1 SINGLE_ERR2_SIG_EN Single Bit Error Interrupt Enable On OCRAM Bank2 2 1 read-write SINGLE_ERR2_SIG_EN_0 Disabled 0 SINGLE_ERR2_SIG_EN_1 Enabled 0x1 SINGLE_ERR3_SIG_EN Single Bit Error Interrupt Enable On OCRAM Bank3 3 1 read-write SINGLE_ERR3_SIG_EN_0 Disabled 0 SINGLE_ERR3_SIG_EN_1 Enabled 0x1 MULTI_ERR0_SIG_EN Multiple Bits Error Interrupt Enable On OCRAM Bank0 4 1 read-write MULTI_ERR0_SIG_EN_0 Disabled 0 MULTI_ERR0_SIG_EN_1 Enabled 0x1 MULTI_ERR1_SIG_EN Multiple Bits Error Interrupt Enable On OCRAM Bank1 5 1 read-write MULTI_ERR1_SIG_EN_0 Disabled 0 MULTI_ERR1_SIG_EN_1 Enabled 0x1 MULTI_ERR2_SIG_EN Multiple Bits Error Interrupt Enable On OCRAM Bank2 6 1 read-write MULTI_ERR2_SIG_EN_0 Disabled 0 MULTI_ERR2_SIG_EN_1 Enabled 0x1 MULTI_ERR3_SIG_EN Multiple Bits Error Interrupt Enable On OCRAM Bank3 7 1 read-write MULTI_ERR3_SIG_EN_0 Disabled 0 MULTI_ERR3_SIG_EN_1 Enabled 0x1 STRB_ERR0_SIG_EN AXI Strobe Error Interrupt Enable On OCRAM Bank0 8 1 read-write STRB_ERR0_SIG_EN_0 Disabled 0 STRB_ERR0_SIG_EN_1 Enabled 0x1 STRB_ERR1_SIG_EN AXI Strobe Error Interrupt Enable On OCRAM Bank1 9 1 read-write STRB_ERR1_SIG_EN_0 Disabled 0 STRB_ERR1_SIG_EN_1 Enabled 0x1 STRB_ERR2_SIG_EN AXI Strobe Error Interrupt Enable On OCRAM Bank2 10 1 read-write STRB_ERR2_SIG_EN_0 Disabled 0 STRB_ERR2_SIG_EN_1 Enabled 0x1 STRB_ERR3_SIG_EN AXI Strobe Error Interrupt Enable On OCRAM Bank3 11 1 read-write STRB_ERR3_SIG_EN_0 Disabled 0 STRB_ERR3_SIG_EN_1 Enabled 0x1 ADDR_ERR0_SIG_EN OCRAM Access Error Interrupt Enable On Bank0 12 1 read-write ADDR_ERR0_SIG_EN_0 Disabled 0 ADDR_ERR0_SIG_EN_1 Enabled 0x1 ADDR_ERR1_SIG_EN OCRAM Access Error Interrupt Enable On Bank1 13 1 read-write ADDR_ERR1_SIG_EN_0 Disabled 0 ADDR_ERR1_SIG_EN_1 Enabled 0x1 ADDR_ERR2_SIG_EN OCRAM Access Error Interrupt Enable On Bank2 14 1 read-write ADDR_ERR2_SIG_EN_0 Disabled 0 ADDR_ERR2_SIG_EN_1 Enabled 0x1 ADDR_ERR3_SIG_EN OCRAM Access Error Interrupt Enable On Bank3 15 1 read-write ADDR_ERR3_SIG_EN_0 Disabled 0 ADDR_ERR3_SIG_EN_1 Enabled 0x1 ERR_DATA_INJ_LOW0 Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data 0xC 32 read-write 0 0xFFFFFFFF ERR_DATA_INJ Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data 0 32 read-write ERR_DATA_INJ_HIGH0 Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data 0x10 32 read-write 0 0xFFFFFFFF ERR_DATA_INJ Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data 0 32 read-write ERR_ECC_INJ0 Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data 0x14 32 read-write 0 0xFFFFFFFF ERR_ECC_INJ Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data 0 8 read-write ERR_DATA_INJ_LOW1 Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data 0x18 32 read-write 0 0xFFFFFFFF ERR_DATA_INJ Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data 0 32 read-write ERR_DATA_INJ_HIGH1 Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data 0x1C 32 read-write 0 0xFFFFFFFF ERR_DATA_INJ Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data 0 32 read-write ERR_ECC_INJ1 Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data 0x20 32 read-write 0 0xFFFFFFFF ERR_ECC_INJ Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data 0 8 read-write ERR_DATA_INJ_LOW2 Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data 0x24 32 read-write 0 0xFFFFFFFF ERR_DATA_INJ Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data 0 32 read-write ERR_DATA_INJ_HIGH2 Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data 0x28 32 read-write 0 0xFFFFFFFF ERR_DATA_INJ Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data 0 32 read-write ERR_ECC_INJ2 Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data 0x2C 32 read-write 0 0xFFFFFFFF ERR_ECC_INJ Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data 0 8 read-write ERR_DATA_INJ_LOW3 Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data 0x30 32 read-write 0 0xFFFFFFFF ERR_DATA_INJ Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data 0 32 read-write ERR_DATA_INJ_HIGH3 Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data 0x34 32 read-write 0 0xFFFFFFFF ERR_DATA_INJ Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data 0 32 read-write ERR_ECC_INJ3 Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data 0x38 32 read-write 0 0xFFFFFFFF ERR_ECC_INJ Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data 0 8 read-write SINGLE_ERR_ADDR_ECC0 Single Error Address And ECC code On OCRAM Bank0 0x3C 32 read-only 0 0xFFFFFFFF SINGLE_ERR_ECC Single Error ECC code On OCRAM Bank0 0 8 read-only SINGLE_ERR_ADDR Single Error Address On OCRAM Bank0 8 19 read-only SINGLE_ERR_DATA_LOW0 LOW 32 Bits Single Error Read Data On OCRAM Bank0 0x40 32 read-only 0 0xFFFFFFFF SINGLE_ERR_DATA LOW 32 Bits Single Error Read Data On OCRAM Bank0 0 32 read-only SINGLE_ERR_DATA_HIGH0 HIGH 32 Bits Single Error Read Data On OCRAM Bank0 0x44 32 read-only 0 0xFFFFFFFF SINGLE_ERR_DATA HIGH 32 Bits Single Error Read Data On OCRAM Bank0 0 32 read-only SINGLE_ERR_POS_LOW0 LOW Single Error Bit Position On OCRAM Bank0 0x48 32 read-only 0 0xFFFFFFFF SINGLE_ERR_POS LOW Single Error Bit Position On OCRAM Bank0 0 32 read-only SINGLE_ERR_POS_HIGH0 HIGH Single Error Bit Position On OCRAM Bank0 0x4C 32 read-only 0 0xFFFFFFFF SINGLE_ERR_POS HIGH Single Error Bit Position On OCRAM Bank0 0 32 read-only SINGLE_ERR_ADDR_ECC1 Single Error Address And ECC code On OCRAM Bank1 0x50 32 read-only 0 0xFFFFFFFF SINGLE_ERR_ECC Single Error ECC code On OCRAM Bank1 0 8 read-only SINGLE_ERR_ADDR Single Error Address On OCRAM Bank1 8 19 read-only SINGLE_ERR_DATA_LOW1 LOW 32 Bits Single Error Read Data On OCRAM Bank1 0x54 32 read-only 0 0xFFFFFFFF SINGLE_ERR_DATA LOW 32 Bits Single Error Read Data On OCRAM Bank1 0 32 read-only SINGLE_ERR_DATA_HIGH1 HIGH 32 Bits Single Error Read Data On OCRAM Bank1 0x58 32 read-only 0 0xFFFFFFFF SINGLE_ERR_DATA HIGH 32 Bits Single Error Read Data On OCRAM Bank1 0 32 read-only SINGLE_ERR_POS_LOW1 LOW Single Error Bit Position On OCRAM Bank1 0x5C 32 read-only 0 0xFFFFFFFF SINGLE_ERR_POS LOW Single Error Bit Position On OCRAM Bank1 0 32 read-only SINGLE_ERR_POS_HIGH1 HIGH Single Error Bit Position On OCRAM Bank1 0x60 32 read-only 0 0xFFFFFFFF SINGLE_ERR_POS HIGH Single Error Bit Position On OCRAM Bank1 0 32 read-only SINGLE_ERR_ADDR_ECC2 Single Error Address And ECC code On OCRAM Bank2 0x64 32 read-only 0 0xFFFFFFFF SINGLE_ERR_ECC Single Error ECC code On OCRAM Bank2 0 8 read-only SINGLE_ERR_ADDR Single Error Address On OCRAM Bank2 8 19 read-only SINGLE_ERR_DATA_LOW2 LOW 32 Bits Single Error Read Data On OCRAM Bank2 0x68 32 read-only 0 0xFFFFFFFF SINGLE_ERR_DATA LOW 32 Bits Single Error Read Data On OCRAM Bank2 0 32 read-only SINGLE_ERR_DATA_HIGH2 HIGH 32 Bits Single Error Read Data On OCRAM Bank2 0x6C 32 read-only 0 0xFFFFFFFF SINGLE_ERR_DATA HIGH 32 Bits Single Error Read Data On OCRAM Bank2 0 32 read-only SINGLE_ERR_POS_LOW2 LOW Single Error Bit Position On OCRAM Bank2 0x70 32 read-only 0 0xFFFFFFFF SINGLE_ERR_POS LOW Single Error Bit Position On OCRAM Bank2 0 32 read-only SINGLE_ERR_POS_HIGH2 HIGH Single Error Bit Position On OCRAM Bank2 0x74 32 read-only 0 0xFFFFFFFF SINGLE_ERR_POS HIGH Single Error Bit Position On OCRAM Bank2 0 32 read-only SINGLE_ERR_ADDR_ECC3 Single Error Address And ECC code On OCRAM Bank3 0x78 32 read-only 0 0xFFFFFFFF SINGLE_ERR_ECC Single Error ECC code On OCRAM Bank3 0 8 read-only SINGLE_ERR_ADDR Single Error Address On OCRAM Bank3 8 19 read-only SINGLE_ERR_DATA_LOW3 LOW 32 Bits Single Error Read Data On OCRAM Bank3 0x7C 32 read-only 0 0xFFFFFFFF SINGLE_ERR_DATA LOW 32 Bits Single Error Read Data On OCRAM Bank3 0 32 read-only SINGLE_ERR_DATA_HIGH3 HIGH 32 Bits Single Error Read Data On OCRAM Bank3 0x80 32 read-only 0 0xFFFFFFFF SINGLE_ERR_DATA HIGH 32 Bits Single Error Read Data On OCRAM Bank3 0 32 read-only SINGLE_ERR_POS_LOW3 LOW Single Error Bit Position On OCRAM Bank3 0x84 32 read-only 0 0xFFFFFFFF SINGLE_ERR_POS LOW Single Error Bit Position On OCRAM Bank3 0 32 read-only SINGLE_ERR_POS_HIGH3 HIGH Single Error Bit Position On OCRAM Bank3 0x88 32 read-only 0 0xFFFFFFFF SINGLE_ERR_POS HIGH Single Error Bit Position On OCRAM Bank3 0 32 read-only MULTI_ERR_ADDR_ECC0 Multiple Error Address And ECC code On OCRAM Bank0 0x8C 32 read-only 0 0xFFFFFFFF MULTI_ERR_ECC Multiple Error ECC code On OCRAM Bank0 0 8 read-only MULTI_ERR_ADDR Multiple Error Address On OCRAM Bank0 8 19 read-only MULTI_ERR_DATA_LOW0 LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 0x90 32 read-only 0 0xFFFFFFFF MULTI_ERR_DATA LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 0 32 read-only MULTI_ERR_DATA_HIGH0 HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 0x94 32 read-only 0 0xFFFFFFFF MULTI_ERR_DATA HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 0 32 read-only MULTI_ERR_ADDR_ECC1 Multiple Error Address And ECC code On OCRAM Bank1 0x98 32 read-only 0 0xFFFFFFFF MULTI_ERR_ECC Multiple Error ECC code On OCRAM Bank1 0 8 read-only MULTI_ERR_ADDR Multiple Error Address On OCRAM Bank1 8 19 read-only MULTI_ERR_DATA_LOW1 LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 0x9C 32 read-only 0 0xFFFFFFFF MULTI_ERR_DATA LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 0 32 read-only MULTI_ERR_DATA_HIGH1 HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 0xA0 32 read-only 0 0xFFFFFFFF MULTI_ERR_DATA HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 0 32 read-only MULTI_ERR_ADDR_ECC2 Multiple Error Address And ECC code On OCRAM Bank2 0xA4 32 read-only 0 0xFFFFFFFF MULTI_ERR_ECC Multiple Error ECC code On OCRAM Bank2 0 8 read-only MULTI_ERR_ADDR Multiple Error Address On OCRAM Bank2 8 19 read-only MULTI_ERR_DATA_LOW2 LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 0xA8 32 read-only 0 0xFFFFFFFF MULTI_ERR_DATA LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 0 32 read-only MULTI_ERR_DATA_HIGH2 HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 0xAC 32 read-only 0 0xFFFFFFFF MULTI_ERR_DATA HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 0 32 read-only MULTI_ERR_ADDR_ECC3 Multiple Error Address And ECC code On OCRAM Bank3 0xB0 32 read-only 0 0xFFFFFFFF MULTI_ERR_ECC Multiple Error ECC code On OCRAM Bank3 0 8 read-only MULTI_ERR_ADDR Multiple Error Address On OCRAM Bank3 8 19 read-only MULTI_ERR_DATA_LOW3 LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 0xB4 32 read-only 0 0xFFFFFFFF MULTI_ERR_DATA LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 0 32 read-only MULTI_ERR_DATA_HIGH3 HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 0xB8 32 read-only 0 0xFFFFFFFF MULTI_ERR_DATA HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 0 32 read-only PIPE_ECC_EN OCRAM Pipeline And ECC Enable 0x100 32 read-write 0 0xFFFFFFFF READ_DATA_WAIT_EN Read Data Wait Enable 0 1 read-write READ_DATA_WAIT_EN_0 Disable. 0 READ_DATA_WAIT_EN_1 Enable. 0x1 READ_ADDR_PIPE_EN Read Address Pipeline Enable 1 1 read-write READ_ADDR_PIPE_EN_0 Disable. 0 READ_ADDR_PIPE_EN_1 Enable. 0x1 WRITE_DATA_PIPE_EN Write Data Pipeline Enable 2 1 read-write WRITE_DATA_PIPE_EN_0 Disable. 0 WRITE_DATA_PIPE_EN_1 Enable. 0x1 WRITE_ADDR_PIPE_EN Write Address Pipeline Enable 3 1 read-write WRITE_ADDR_PIPE_EN_0 Disable. 0 WRITE_ADDR_PIPE_EN_1 Enable. 0x1 ECC_EN ECC Function Enable 4 1 read-write ECC_EN_0 Disable. 0 ECC_EN_1 Enable. 0x1 PENDING_STAT Pending Status 0x104 32 read-only 0 0xFFFFFFFF READ_DATA_WAIT_PENDING Read Data Wait Pending 0 1 read-only READ_DATA_WAIT_PENDING_0 No update pending status for READ_DATA_WAIT_EN. 0 READ_DATA_WAIT_PENDING_1 When READ_DATA_WAIT_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller. 0x1 READ_ADDR_PIPE_PENDING Read Address Pipeline Pending 1 1 read-only READ_ADDR_PIPE_PENDING_0 No update pending status for READ_ADDR_PIPE_EN. 0 READ_ADDR_PIPE_PENDING_1 When READ_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller. 0x1 WRITE_DATA_PIPE_PENDING Write Data Pipeline Pending 2 1 read-only WRITE_DATA_PIPE_PENDING_0 No update pending status for WRITE_DATA_PIPE_EN. 0 WRITE_DATA_PIPE_PENDING_1 When WRITE_DATA_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller. 0x1 WRITE_ADDR_PIPE_PENDING Write Address Pipeline Pending 3 1 read-only WRITE_ADDR_PIPE_PENDING_0 No update pending status for WRITE_ADDR_PIPE_EN. 0 WRITE_ADDR_PIPE_PENDING_1 When WRITE_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller. 0x1 MECC2 MECC64 MECC 0x40018000 0 0x108 registers MECC2_INT 208 XECC_FLEXSPI1 XECC XECC XECC 0x4001C000 0 0x5C registers XECC_FLEXSPI1_INT 210 XECC_FLEXSPI1_FATAL_INT 211 ECC_CTRL ECC Control Register 0 32 read-write 0 0xFFFFFFFF ECC_EN ECC Function Enable 0 1 read-write ECC_EN_0 Disable 0 ECC_EN_1 Enable 0x1 WECC_EN Write ECC Encode Function Enable 1 1 read-write WECC_EN_0 Disable 0 WECC_EN_1 Enable 0x1 RECC_EN Read ECC Function Enable 2 1 read-write RECC_EN_0 Disable 0 RECC_EN_1 Enable 0x1 SWAP_EN Swap Data Enable 3 1 read-write SWAP_EN_0 Disable 0 SWAP_EN_1 Enable 0x1 ERR_STATUS Error Interrupt Status Register 0x4 32 read-write 0 0xFFFFFFFF SINGLE_ERR Single Bit Error 0 1 read-write oneToClear SINGLE_ERR_0 Single bit error does not happen. 0 SINGLE_ERR_1 Single bit error happens. 0x1 MULTI_ERR Multiple Bits Error 1 1 read-write oneToClear MULTI_ERR_0 Multiple bits error does not happen. 0 MULTI_ERR_1 Multiple bits error happens. 0x1 Reserved1 Reserved 2 30 read-only ERR_STAT_EN Error Interrupt Status Enable Register 0x8 32 read-write 0 0xFFFFFFFF SINGLE_ERR_STAT_EN Single Bit Error Status Enable 0 1 read-write SINGLE_ERR_STAT_EN_0 Masked 0 SINGLE_ERR_STAT_EN_1 Enabled 0x1 MULIT_ERR_STAT_EN Multiple Bits Error Status Enable 1 1 read-write MULIT_ERR_STAT_EN_0 Masked 0 MULIT_ERR_STAT_EN_1 Enabled 0x1 Reserved1 Reserved 2 30 read-only ERR_SIG_EN Error Interrupt Enable Register 0xC 32 read-write 0 0xFFFFFFFF SINGLE_ERR_SIG_EN Single Bit Error Interrupt Enable 0 1 read-write SINGLE_ERR_SIG_EN_0 Masked 0 SINGLE_ERR_SIG_EN_1 Enabled 0x1 MULTI_ERR_SIG_EN Multiple Bits Error Interrupt Enable 1 1 read-write MULTI_ERR_SIG_EN_0 Masked 0 MULTI_ERR_SIG_EN_1 Enabled 0x1 Reserved1 Reserved 2 30 read-only ERR_DATA_INJ Error Injection On Write Data 0x10 32 read-write 0 0xFFFFFFFF ERR_DATA_INJ Error Injection On Write Data 0 32 read-write ERR_ECC_INJ Error Injection On ECC Code of Write Data 0x14 32 read-write 0 0xFFFFFFFF ERR_ECC_INJ Error Injection On ECC Code of Write Data 0 32 read-write SINGLE_ERR_ADDR Single Error Address 0x18 32 read-only 0 0xFFFFFFFF SINGLE_ERR_ADDR Single Error Address 0 32 read-only SINGLE_ERR_DATA Single Error Read Data 0x1C 32 read-only 0 0xFFFFFFFF SINGLE_ERR_DATA Single Error Read Data 0 32 read-only SINGLE_ERR_ECC Single Error ECC Code 0x20 32 read-only 0 0xFFFFFFFF SINGLE_ERR_ECC Single Error ECC code 0 32 read-only SINGLE_ERR_POS Single Error Bit Position 0x24 32 read-only 0 0xFFFFFFFF SINGLE_ERR_POS Single Error bit Position 0 32 read-only SINGLE_ERR_BIT_FIELD Single Error Bit Field 0x28 32 read-only 0 0xFFFFFFFF SINGLE_ERR_BIT_FIELD Single Error Bit Field 0 8 read-only Reserved1 Reserved 8 24 read-only MULTI_ERR_ADDR Multiple Error Address 0x2C 32 read-only 0 0xFFFFFFFF MULTI_ERR_ADDR Multiple Error Address 0 32 read-only MULTI_ERR_DATA Multiple Error Read Data 0x30 32 read-only 0 0xFFFFFFFF MULTI_ERR_DATA Multiple Error Read Data 0 32 read-only MULTI_ERR_ECC Multiple Error ECC code 0x34 32 read-only 0 0xFFFFFFFF MULTI_ERR_ECC Multiple Error ECC code 0 32 read-only MULTI_ERR_BIT_FIELD Multiple Error Bit Field 0x38 32 read-only 0 0xFFFFFFFF MULTI_ERR_BIT_FIELD Multiple Error Bit Field 0 8 read-only Reserved1 Reserved 8 24 read-only ECC_BASE_ADDR0 ECC Region 0 Base Address 0x3C 32 read-write 0 0xFFFFFFFF ECC_BASE_ADDR0 ECC Region 0 Base Address 0 32 read-write ECC_END_ADDR0 ECC Region 0 End Address 0x40 32 read-write 0 0xFFFFFFFF ECC_END_ADDR0 ECC Region 0 End Address 0 32 read-write ECC_BASE_ADDR1 ECC Region 1 Base Address 0x44 32 read-write 0 0xFFFFFFFF ECC_BASE_ADDR1 ECC Region 1 Base Address 0 32 read-write ECC_END_ADDR1 ECC Region 1 End Address 0x48 32 read-write 0 0xFFFFFFFF ECC_END_ADDR1 ECC Region 1 End Address 0 32 read-write ECC_BASE_ADDR2 ECC Region 2 Base Address 0x4C 32 read-write 0 0xFFFFFFFF ECC_BASE_ADDR2 ECC Region 2 Base Address 0 32 read-write ECC_END_ADDR2 ECC Region 2 End Address 0x50 32 read-write 0 0xFFFFFFFF ECC_END_ADDR2 ECC Region 2 End Address 0 32 read-write ECC_BASE_ADDR3 ECC Region 3 Base Address 0x54 32 read-write 0 0xFFFFFFFF ECC_BASE_ADDR3 ECC Region 3 Base Address 0 32 read-write ECC_END_ADDR3 ECC Region 3 End Address 0x58 32 read-write 0 0xFFFFFFFF ECC_END_ADDR3 ECC Region 3 End Address 0 32 read-write XECC_FLEXSPI2 XECC XECC 0x40020000 0 0x5C registers XECC_FLEXSPI2_INT 212 XECC_FLEXSPI2_FATAL_INT 213 XECC_SEMC XECC XECC 0x40024000 0 0x5C registers XECC_SEMC_INT 214 XECC_SEMC_FATAL_INT 215 FLEXRAM FLEXRAM FLEXRAM 0x40028000 0 0x110 registers FLEXRAM 50 FLEXRAM_ECC 98 TCM_CTRL TCM CRTL Register 0 32 read-write 0 0xFFFFFFFF TCM_WWAIT_EN TCM Write Wait Mode Enable 0 1 read-write TCM_WWAIT_EN_0 TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. 0 TCM_WWAIT_EN_1 TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. 0x1 TCM_RWAIT_EN TCM Read Wait Mode Enable 1 1 read-write TCM_RWAIT_EN_0 TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. 0 TCM_RWAIT_EN_1 TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. 0x1 FORCE_CLK_ON Force RAM Clock Always On 2 1 read-write Reserved Reserved 3 29 read-only OCRAM_MAGIC_ADDR OCRAM Magic Address Register 0x4 32 read-write 0 0xFFFFFFFF OCRAM_WR_RD_SEL OCRAM Write Read Select 0 1 read-write OCRAM_WR_RD_SEL_0 When OCRAM read access hits magic address, it will generate interrupt. 0 OCRAM_WR_RD_SEL_1 When OCRAM write access hits magic address, it will generate interrupt. 0x1 OCRAM_MAGIC_ADDR OCRAM Magic Address 1 17 read-write Reserved Reserved 18 14 read-only DTCM_MAGIC_ADDR DTCM Magic Address Register 0x8 32 read-write 0 0xFFFFFFFF DTCM_WR_RD_SEL DTCM Write Read Select 0 1 read-write DTCM_WR_RD_SEL_0 When DTCM read access hits magic address, it will generate interrupt. 0 DTCM_WR_RD_SEL_1 When DTCM write access hits magic address, it will generate interrupt. 0x1 DTCM_MAGIC_ADDR DTCM Magic Address 1 16 read-write Reserved Reserved 17 15 read-only ITCM_MAGIC_ADDR ITCM Magic Address Register 0xC 32 read-write 0 0xFFFFFFFF ITCM_WR_RD_SEL ITCM Write Read Select 0 1 read-write ITCM_WR_RD_SEL_0 When ITCM read access hits magic address, it will generate interrupt. 0 ITCM_WR_RD_SEL_1 When ITCM write access hits magic address, it will generate interrupt. 0x1 ITCM_MAGIC_ADDR ITCM Magic Address 1 16 read-write Reserved Reserved 17 15 read-only INT_STATUS Interrupt Status Register 0x10 32 read-write 0 0xFFFFFFFF ITCM_MAM_STATUS ITCM Magic Address Match Status 0 1 read-write oneToClear ITCM_MAM_STATUS_0 ITCM did not access magic address. 0 ITCM_MAM_STATUS_1 ITCM accessed magic address. 0x1 DTCM_MAM_STATUS DTCM Magic Address Match Status 1 1 read-write oneToClear DTCM_MAM_STATUS_0 DTCM did not access magic address. 0 DTCM_MAM_STATUS_1 DTCM accessed magic address. 0x1 OCRAM_MAM_STATUS OCRAM Magic Address Match Status 2 1 read-write oneToClear OCRAM_MAM_STATUS_0 OCRAM did not access magic address. 0 OCRAM_MAM_STATUS_1 OCRAM accessed magic address. 0x1 ITCM_ERR_STATUS ITCM Access Error Status 3 1 read-write oneToClear ITCM_ERR_STATUS_0 ITCM access error does not happen 0 ITCM_ERR_STATUS_1 ITCM access error happens. 0x1 DTCM_ERR_STATUS DTCM Access Error Status 4 1 read-write oneToClear DTCM_ERR_STATUS_0 DTCM access error does not happen 0 DTCM_ERR_STATUS_1 DTCM access error happens. 0x1 OCRAM_ERR_STATUS OCRAM Access Error Status 5 1 read-write oneToClear OCRAM_ERR_STATUS_0 OCRAM access error does not happen 0 OCRAM_ERR_STATUS_1 OCRAM access error happens. 0x1 OCRAM_ECC_ERRM_INT OCRAM access multi-bit ECC Error Interrupt Status 6 1 read-write oneToClear OCRAM_ECC_ERRM_INT_0 OCRAM multi-bit ECC error does not happen 0 OCRAM_ECC_ERRM_INT_1 OCRAM multi-bit ECC error happens. 0x1 OCRAM_ECC_ERRS_INT OCRAM access single-bit ECC Error Interrupt Status 7 1 read-write oneToClear OCRAM_ECC_ERRS_INT_0 OCRAM single-bit ECC error does not happen 0 OCRAM_ECC_ERRS_INT_1 OCRAM single-bit ECC error happens. 0x1 ITCM_ECC_ERRM_INT ITCM Access multi-bit ECC Error Interrupt Status 8 1 read-write oneToClear ITCM_ECC_ERRM_INT_0 ITCM multi-bit ECC error does not happen 0 ITCM_ECC_ERRM_INT_1 ITCM multi-bit ECC error happens. 0x1 ITCM_ECC_ERRS_INT ITCM access single-bit ECC Error Interrupt Status 9 1 read-write oneToClear ITCM_ECC_ERRS_INT_0 ITCM single-bit ECC error does not happen 0 ITCM_ECC_ERRS_INT_1 ITCM single-bit ECC error happens. 0x1 D0TCM_ECC_ERRM_INT D0TCM access multi-bit ECC Error Interrupt Status 10 1 read-write oneToClear D0TCM_ECC_ERRM_INT_0 D0TCM multi-bit ECC error does not happen 0 D0TCM_ECC_ERRM_INT_1 D0TCM multi-bit ECC error happens. 0x1 D0TCM_ECC_ERRS_INT D0TCM access single-bit ECC Error Interrupt Status 11 1 read-write oneToClear D0TCM_ECC_ERRS_INT_0 D0TCM single-bit ECC error does not happen 0 D0TCM_ECC_ERRS_INT_1 D0TCM single-bit ECC error happens. 0x1 D1TCM_ECC_ERRM_INT D1TCM access multi-bit ECC Error Interrupt Status 12 1 read-write oneToClear D1TCM_ECC_ERRM_INT_0 D1TCM multi-bit ECC error does not happen 0 D1TCM_ECC_ERRM_INT_1 D1TCM multi-bit ECC error happens. 0x1 D1TCM_ECC_ERRS_INT D1TCM access single-bit ECC Error Interrupt Status 13 1 read-write oneToClear D1TCM_ECC_ERRS_INT_0 D1TCM single-bit ECC error does not happen 0 D1TCM_ECC_ERRS_INT_1 D1TCM single-bit ECC error happens. 0x1 ITCM_PARTIAL_WR_INT_S ITCM Partial Write Interrupt Status 14 1 read-write oneToClear ITCM_PARTIAL_WR_INT_S_0 ITCM Partial Write does not happen 0 ITCM_PARTIAL_WR_INT_S_1 ITCM Partial Write happens. 0x1 D0TCM_PARTIAL_WR_INT_S D0TCM Partial Write Interrupt Status 15 1 read-write oneToClear D0TCM_PARTIAL_WR_INT_S_0 D0TCM Partial Write does not happen 0 D0TCM_PARTIAL_WR_INT_S_1 D0TCM Partial Write happens. 0x1 D1TCM_PARTIAL_WR_INT_S D1TCM Partial Write Interrupt Status 16 1 read-write oneToClear D1TCM_PARTIAL_WR_INT_S_0 D1TCM Partial Write does not happen 0 D1TCM_PARTIAL_WR_INT_S_1 D1TCM Partial Write happens. 0x1 OCRAM_PARTIAL_WR_INT_S OCRAM Partial Write Interrupt Status 17 1 read-write oneToClear OCRAM_PARTIAL_WR_INT_S_0 OCRAM Partial Write does not happen 0 OCRAM_PARTIAL_WR_INT_S_1 OCRAM Partial Write happens. 0x1 Reserved Reserved 18 14 read-only INT_STAT_EN Interrupt Status Enable Register 0x14 32 read-write 0 0xFFFFFFFF ITCM_MAM_STAT_EN ITCM Magic Address Match Status Enable 0 1 read-write ITCM_MAM_STAT_EN_0 Masked 0 ITCM_MAM_STAT_EN_1 Enabled 0x1 DTCM_MAM_STAT_EN DTCM Magic Address Match Status Enable 1 1 read-write DTCM_MAM_STAT_EN_0 Masked 0 DTCM_MAM_STAT_EN_1 Enabled 0x1 OCRAM_MAM_STAT_EN OCRAM Magic Address Match Status Enable 2 1 read-write OCRAM_MAM_STAT_EN_0 Masked 0 OCRAM_MAM_STAT_EN_1 Enabled 0x1 ITCM_ERR_STAT_EN ITCM Access Error Status Enable 3 1 read-write ITCM_ERR_STAT_EN_0 Masked 0 ITCM_ERR_STAT_EN_1 Enabled 0x1 DTCM_ERR_STAT_EN DTCM Access Error Status Enable 4 1 read-write DTCM_ERR_STAT_EN_0 Masked 0 DTCM_ERR_STAT_EN_1 Enabled 0x1 OCRAM_ERR_STAT_EN OCRAM Access Error Status Enable 5 1 read-write OCRAM_ERR_STAT_EN_0 Masked 0 OCRAM_ERR_STAT_EN_1 Enabled 0x1 OCRAM_ERRM_INT_EN OCRAM Access multi-bit ECC Error Interrupt Status Enable 6 1 read-write OCRAM_ERRM_INT_EN_0 Masked 0 OCRAM_ERRM_INT_EN_1 Enabled 0x1 OCRAM_ERRS_INT_EN OCRAM Access single-bit ECC Error Interrupt Status Enable 7 1 read-write OCRAM_ERRS_INT_EN_0 Masked 0 OCRAM_ERRS_INT_EN_1 Enabled 0x1 ITCM_ERRM_INT_EN ITCM Access multi-bit ECC Error Interrupt Status Enable 8 1 read-write ITCM_ERRM_INT_EN_0 Masked 0 ITCM_ERRM_INT_EN_1 Enabled 0x1 ITCM_ERRS_INT_EN ITCM Access single-bit ECC Error Interrupt Status Enable 9 1 read-write ITCM_ERRS_INT_EN_0 Masked 0 ITCM_ERRS_INT_EN_1 Enabled 0x1 D0TCM_ERRM_INT_EN D0TCM Access multi-bit ECC Error Interrupt Status Enable 10 1 read-write D0TCM_ERRM_INT_EN_0 Masked 0 D0TCM_ERRM_INT_EN_1 Enabled 0x1 D0TCM_ERRS_INT_EN D0TCM Access single-bit ECC Error Interrupt Status Enable 11 1 read-write D0TCM_ERRS_INT_EN_0 Masked 0 D0TCM_ERRS_INT_EN_1 Enabled 0x1 D1TCM_ERRM_INT_EN D1TCM Access multi-bit ECC Error Interrupt Status Enable 12 1 read-write D1TCM_ERRM_INT_EN_0 Masked 0 D1TCM_ERRM_INT_EN_1 Enabled 0x1 D1TCM_ERRS_INT_EN D1TCM Access single-bit ECC Error Interrupt Status Enable 13 1 read-write D1TCM_ERRS_INT_EN_0 Masked 0 D1TCM_ERRS_INT_EN_1 Enabled 0x1 ITCM_PARTIAL_WR_INT_S_EN ITCM Partial Write Interrupt Status Enable 14 1 read-write ITCM_PARTIAL_WR_INT_S_EN_0 Masked 0 ITCM_PARTIAL_WR_INT_S_EN_1 Enabled 0x1 D0TCM_PARTIAL_WR_INT_S_EN D0TCM Partial Write Interrupt Status Enable 15 1 read-write D0TCM_PARTIAL_WR_INT_S_EN_0 Masked 0 D0TCM_PARTIAL_WR_INT_S_EN_1 Enabled 0x1 D1TCM_PARTIAL_WR_INT_S_EN D1TCM Partial Write Interrupt Status EN 16 1 read-write D1TCM_PARTIAL_WR_INT_S_EN_0 Masked 0 D1TCM_PARTIAL_WR_INT_S_EN_1 Enbaled 0x1 OCRAM_PARTIAL_WR_INT_S_EN OCRAM Partial Write Interrupt Status 17 1 read-write OCRAM_PARTIAL_WR_INT_S_EN_0 Masked 0 OCRAM_PARTIAL_WR_INT_S_EN_1 Enabled 0x1 Reserved Reserved 18 14 read-only INT_SIG_EN Interrupt Enable Register 0x18 32 read-write 0 0xFFFFFFFF ITCM_MAM_SIG_EN ITCM Magic Address Match Interrupt Enable 0 1 read-write ITCM_MAM_SIG_EN_0 Masked 0 ITCM_MAM_SIG_EN_1 Enabled 0x1 DTCM_MAM_SIG_EN DTCM Magic Address Match Interrupt Enable 1 1 read-write DTCM_MAM_SIG_EN_0 Masked 0 DTCM_MAM_SIG_EN_1 Enabled 0x1 OCRAM_MAM_SIG_EN OCRAM Magic Address Match Interrupt Enable 2 1 read-write OCRAM_MAM_SIG_EN_0 Masked 0 OCRAM_MAM_SIG_EN_1 Enabled 0x1 ITCM_ERR_SIG_EN ITCM Access Error Interrupt Enable 3 1 read-write ITCM_ERR_SIG_EN_0 Masked 0 ITCM_ERR_SIG_EN_1 Enabled 0x1 DTCM_ERR_SIG_EN DTCM Access Error Interrupt Enable 4 1 read-write DTCM_ERR_SIG_EN_0 Masked 0 DTCM_ERR_SIG_EN_1 Enabled 0x1 OCRAM_ERR_SIG_EN OCRAM Access Error Interrupt Enable 5 1 read-write OCRAM_ERR_SIG_EN_0 Masked 0 OCRAM_ERR_SIG_EN_1 Enabled 0x1 OCRAM_ERRM_INT_SIG_EN OCRAM Access multi-bit ECC Error Interrupt Signal Enable 6 1 read-write OCRAM_ERRM_INT_SIG_EN_0 Masked 0 OCRAM_ERRM_INT_SIG_EN_1 Enabled 0x1 OCRAM_ERRS_INT_SIG_EN OCRAM Access single-bit ECC Error Interrupt Signal Enable 7 1 read-write OCRAM_ERRS_INT_SIG_EN_0 Masked 0 OCRAM_ERRS_INT_SIG_EN_1 Enabled 0x1 ITCM_ERRM_INT_SIG_EN ITCM Access multi-bit ECC Error Interrupt Signal Enable 8 1 read-write ITCM_ERRM_INT_SIG_EN_0 Masked 0 ITCM_ERRM_INT_SIG_EN_1 Enabled 0x1 ITCM_ERRS_INT_SIG_EN ITCM Access single-bit ECC Error Interrupt Signal Enable 9 1 read-write ITCM_ERRS_INT_SIG_EN_0 Masked 0 ITCM_ERRS_INT_SIG_EN_1 Enabled 0x1 D0TCM_ERRM_INT_SIG_EN D0TCM Access multi-bit ECC Error Interrupt Signal Enable 10 1 read-write D0TCM_ERRM_INT_SIG_EN_0 Masked 0 D0TCM_ERRM_INT_SIG_EN_1 Enabled 0x1 D0TCM_ERRS_INT_SIG_EN D0TCM Access single-bit ECC Error Interrupt Signal Enable 11 1 read-write D0TCM_ERRS_INT_SIG_EN_0 Masked 0 D0TCM_ERRS_INT_SIG_EN_1 Enabled 0x1 D1TCM_ERRM_INT_SIG_EN D1TCM Access multi-bit ECC Error Interrupt Signal Enable 12 1 read-write D1TCM_ERRM_INT_SIG_EN_0 Masked 0 D1TCM_ERRM_INT_SIG_EN_1 Enabled 0x1 D1TCM_ERRS_INT_SIG_EN D1TCM Access single-bit ECC Error Interrupt Signal Enable 13 1 read-write D1TCM_ERRS_INT_SIG_EN_0 Masked 0 D1TCM_ERRS_INT_SIG_EN_1 Enabled 0x1 ITCM_PARTIAL_WR_INT_SIG_EN ITCM Partial Write Interrupt Signal Enable Enable 14 1 read-write ITCM_PARTIAL_WR_INT_SIG_EN_0 Masked 0 ITCM_PARTIAL_WR_INT_SIG_EN_1 Enabled 0x1 D0TCM_PARTIAL_WR_INT_SIG_EN D0TCM Partial Write Interrupt Signal Enable Enable 15 1 read-write D0TCM_PARTIAL_WR_INT_SIG_EN_0 Masked 0 D0TCM_PARTIAL_WR_INT_SIG_EN_1 Enabled 0x1 D1TCM_PARTIAL_WR_INT_SIG_EN D1TCM Partial Write Interrupt Signal Enable EN 16 1 read-write D1TCM_PARTIAL_WR_INT_SIG_EN_0 Masked 0 D1TCM_PARTIAL_WR_INT_SIG_EN_1 Enbaled 0x1 OCRAM_PARTIAL_WR_INT_SIG_EN OCRAM Partial Write Interrupt Signal Enable 17 1 read-write OCRAM_PARTIAL_WR_INT_SIG_EN_0 Masked 0 OCRAM_PARTIAL_WR_INT_SIG_EN_1 Enabled 0x1 Reserved Reserved 18 14 read-only OCRAM_ECC_SINGLE_ERROR_INFO OCRAM single-bit ECC Error Information Register 0x1C 32 read-only 0 0xFFFFFFFF OCRAM_ECCS_ERRED_ECC corresponding ECC cipher of OCRAM single-bit ECC error 0 8 read-only OCRAM_ECCS_ERRED_SYN corresponding ECC syndrome of OCRAM single-bit ECC error 8 8 read-only Reserved Reserved 16 16 read-only OCRAM_ECC_SINGLE_ERROR_ADDR OCRAM single-bit ECC Error Address Register 0x20 32 read-only 0 0xFFFFFFFF OCRAM_ECCS_ERRED_ADDR OCRAM single-bit ECC error address 0 32 read-only OCRAM_ECC_SINGLE_ERROR_DATA_LSB OCRAM single-bit ECC Error Data Register 0x24 32 read-only 0 0xFFFFFFFF OCRAM_ECCS_ERRED_DATA_LSB OCRAM single-bit ECC error data [31:0] 0 32 read-only OCRAM_ECC_SINGLE_ERROR_DATA_MSB OCRAM single-bit ECC Error Data Register 0x28 32 read-only 0 0xFFFFFFFF OCRAM_ECCS_ERRED_DATA_MSB OCRAM single-bit ECC error data [63:32] 0 32 read-only OCRAM_ECC_MULTI_ERROR_INFO OCRAM multi-bit ECC Error Information Register 0x2C 32 read-only 0 0xFFFFFFFF OCRAM_ECCM_ERRED_ECC OCRAM multi-bit ECC error corresponding ECC value 0 8 read-only Reserved Reserved 8 24 read-only OCRAM_ECC_MULTI_ERROR_ADDR OCRAM multi-bit ECC Error Address Register 0x30 32 read-only 0 0xFFFFFFFF OCRAM_ECCM_ERRED_ADDR OCRAM multi-bit ECC error address 0 32 read-only OCRAM_ECC_MULTI_ERROR_DATA_LSB OCRAM multi-bit ECC Error Data Register 0x34 32 read-only 0 0xFFFFFFFF OCRAM_ECCM_ERRED_DATA_LSB OCRAM multi-bit ECC error data [31:0] 0 32 read-only OCRAM_ECC_MULTI_ERROR_DATA_MSB OCRAM multi-bit ECC Error Data Register 0x38 32 read-only 0 0xFFFFFFFF OCRAM_ECCM_ERRED_DATA_MSB OCRAM multi-bit ECC error data [63:32] 0 32 read-only ITCM_ECC_SINGLE_ERROR_INFO ITCM single-bit ECC Error Information Register 0x3C 32 read-only 0 0xFFFFFFFF ITCM_ECCS_EFW ITCM single-bit ECC error corresponding TCM_WR value. 0 1 read-only ITCM_ECCS_EFSIZ ITCM single-bit ECC error corresponding TCM size 1 3 read-only ITCM_ECCS_EFMST ITCM single-bit ECC error corresponding TCM_MASTER. 4 4 read-only ITCM_ECCS_EFPRT ITCM single-bit ECC error corresponding TCM_PRIV. 8 4 read-only ITCM_ECCS_EFSYN ITCM single-bit ECC error corresponding syndrome 12 8 read-only Reserved Reserved 20 12 read-only ITCM_ECC_SINGLE_ERROR_ADDR ITCM single-bit ECC Error Address Register 0x40 32 read-only 0 0xFFFFFFFF ITCM_ECCS_ERRED_ADDR ITCM single-bit ECC error address 0 32 read-only ITCM_ECC_SINGLE_ERROR_DATA_LSB ITCM single-bit ECC Error Data Register 0x44 32 read-only 0 0xFFFFFFFF ITCM_ECCS_ERRED_DATA_LSB ITCM single-bit ECC error data [31:0] 0 32 read-only ITCM_ECC_SINGLE_ERROR_DATA_MSB ITCM single-bit ECC Error Data Register 0x48 32 read-only 0 0xFFFFFFFF ITCM_ECCS_ERRED_DATA_MSB ITCM single-bit ECC error data [63:32] 0 32 read-only ITCM_ECC_MULTI_ERROR_INFO ITCM multi-bit ECC Error Information Register 0x4C 32 read-only 0 0xFFFFFFFF ITCM_ECCM_EFW ITCM multi-bit ECC error corresponding TCM_WR value 0 1 read-only ITCM_ECCM_EFSIZ ITCM multi-bit ECC error corresponding tcm access size 1 3 read-only ITCM_ECCM_EFMST ITCM multi-bit ECC error corresponding TCM_MASTER 4 4 read-only ITCM_ECCM_EFPRT ITCM multi-bit ECC error corresponding TCM_PRIV 8 4 read-only ITCM_ECCM_EFSYN ITCM multi-bit ECC error corresponding syndrome 12 8 read-only Reserved Reserved 20 12 read-only ITCM_ECC_MULTI_ERROR_ADDR ITCM multi-bit ECC Error Address Register 0x50 32 read-only 0 0xFFFFFFFF ITCM_ECCM_ERRED_ADDR ITCM multi-bit ECC error address 0 32 read-only ITCM_ECC_MULTI_ERROR_DATA_LSB ITCM multi-bit ECC Error Data Register 0x54 32 read-only 0 0xFFFFFFFF ITCM_ECCM_ERRED_DATA_LSB ITCM multi-bit ECC error data [31:0] 0 32 read-only ITCM_ECC_MULTI_ERROR_DATA_MSB ITCM multi-bit ECC Error Data Register 0x58 32 read-only 0 0xFFFFFFFF ITCM_ECCM_ERRED_DATA_MSB ITCM multi-bit ECC error data [63:32] 0 32 read-only D0TCM_ECC_SINGLE_ERROR_INFO D0TCM single-bit ECC Error Information Register 0x5C 32 read-only 0 0xFFFFFFFF D0TCM_ECCS_EFW D0TCM single-bit ECC error corresponding TCM_WR value 0 1 read-only D0TCM_ECCS_EFSIZ D0TCM single-bit ECC error corresponding tcm access size 1 3 read-only D0TCM_ECCS_EFMST D0TCM single-bit ECC error corresponding TCM_MASTER 4 4 read-only D0TCM_ECCS_EFPRT D0TCM single-bit ECC error corresponding TCM_PRIV 8 4 read-only D0TCM_ECCS_EFSYN D0TCM single-bit ECC error corresponding syndrome 12 7 read-only Reserved Reserved 19 13 read-only D0TCM_ECC_SINGLE_ERROR_ADDR D0TCM single-bit ECC Error Address Register 0x60 32 read-only 0 0xFFFFFFFF D0TCM_ECCS_ERRED_ADDR D0TCM single-bit ECC error address 0 32 read-only D0TCM_ECC_SINGLE_ERROR_DATA D0TCM single-bit ECC Error Data Register 0x64 32 read-only 0 0xFFFFFFFF D0TCM_ECCS_ERRED_DATA D0TCM single-bit ECC error data 0 32 read-only D0TCM_ECC_MULTI_ERROR_INFO D0TCM multi-bit ECC Error Information Register 0x68 32 read-only 0 0xFFFFFFFF D0TCM_ECCM_EFW D0TCM multi-bit ECC error corresponding TCM_WR value 0 1 read-only D0TCM_ECCM_EFSIZ D0TCM multi-bit ECC error corresponding tcm access size 1 3 read-only D0TCM_ECCM_EFMST D0TCM multi-bit ECC error corresponding TCM_MASTER 4 4 read-only D0TCM_ECCM_EFPRT D0TCM multi-bit ECC error corresponding TCM_PRIV 8 4 read-only D0TCM_ECCM_EFSYN D0TCM multi-bit ECC error corresponding syndrome 12 7 read-only Reserved Reserved 19 13 read-only D0TCM_ECC_MULTI_ERROR_ADDR D0TCM multi-bit ECC Error Address Register 0x6C 32 read-only 0 0xFFFFFFFF D0TCM_ECCM_ERRED_ADDR D0TCM multi-bit ECC error address 0 32 read-only D0TCM_ECC_MULTI_ERROR_DATA D0TCM multi-bit ECC Error Data Register 0x70 32 read-only 0 0xFFFFFFFF D0TCM_ECCM_ERRED_DATA D0TCM multi-bit ECC error data 0 32 read-only D1TCM_ECC_SINGLE_ERROR_INFO D1TCM single-bit ECC Error Information Register 0x74 32 read-only 0 0xFFFFFFFF D1TCM_ECCS_EFW D1TCM single-bit ECC error corresponding TCM_WR value 0 1 read-only D1TCM_ECCS_EFSIZ D1TCM single-bit ECC error corresponding tcm access size 1 3 read-only D1TCM_ECCS_EFMST D1TCM single-bit ECC error corresponding TCM_MASTER 4 4 read-only D1TCM_ECCS_EFPRT D1TCM single-bit ECC error corresponding TCM_PRIV 8 4 read-only D1TCM_ECCS_EFSYN D1TCM single-bit ECC error corresponding syndrome 12 7 read-only Reserved Reserved 19 13 read-only D1TCM_ECC_SINGLE_ERROR_ADDR D1TCM single-bit ECC Error Address Register 0x78 32 read-only 0 0xFFFFFFFF D1TCM_ECCS_ERRED_ADDR D1TCM single-bit ECC error address 0 32 read-only D1TCM_ECC_SINGLE_ERROR_DATA D1TCM single-bit ECC Error Data Register 0x7C 32 read-only 0 0xFFFFFFFF D1TCM_ECCS_ERRED_DATA D1TCM single-bit ECC error data 0 32 read-only D1TCM_ECC_MULTI_ERROR_INFO D1TCM multi-bit ECC Error Information Register 0x80 32 read-only 0 0xFFFFFFFF D1TCM_ECCM_EFW D1TCM multi-bit ECC error corresponding TCM_WR value 0 1 read-only D1TCM_ECCM_EFSIZ D1TCM multi-bit ECC error corresponding tcm access size 1 3 read-only D1TCM_ECCM_EFMST D1TCM multi-bit ECC error corresponding TCM_MASTER 4 4 read-only D1TCM_ECCM_EFPRT D1TCM multi-bit ECC error corresponding TCM_PRIV 8 4 read-only D1TCM_ECCM_EFSYN D1TCM multi-bit ECC error corresponding syndrome 12 7 read-only Reserved Reserved 19 13 read-only D1TCM_ECC_MULTI_ERROR_ADDR D1TCM multi-bit ECC Error Address Register 0x84 32 read-only 0 0xFFFFFFFF D1TCM_ECCM_ERRED_ADDR D1TCM multi-bit ECC error address 0 32 read-only D1TCM_ECC_MULTI_ERROR_DATA D1TCM multi-bit ECC Error Data Register 0x88 32 read-only 0 0xFFFFFFFF D1TCM_ECCM_ERRED_DATA D1TCM multi-bit ECC error data 0 32 read-only FLEXRAM_CTRL FlexRAM feature Control register 0x108 32 read-write 0 0xFFFFFFFF OCRAM_RDATA_WAIT_EN Read Data Wait Enable 0 1 read-write OCRAM_RADDR_PIPELINE_EN Read Address Pipeline Enable 1 1 read-write OCRAM_WRDATA_PIPELINE_EN Write Data Pipeline Enable 2 1 read-write OCRAM_WRADDR_PIPELINE_EN Write Address Pipeline Enable 3 1 read-write OCRAM_ECC_EN OCRAM ECC enable 4 1 read-write TCM_ECC_EN TCM ECC enable 5 1 read-write Reserved Reserved 6 26 read-only OCRAM_PIPELINE_STATUS OCRAM Pipeline Status register 0x10C 32 read-only 0 0xFFFFFFFF OCRAM_RDATA_WAIT_EN_UPDATA_PENDING Read Data Wait Enable Pending 0 1 read-only OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING Read Address Pipeline Enable Pending 1 1 read-only OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING Write Data Pipeline Enable Pending 2 1 read-only OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING Write Address Pipeline Enable Pending 3 1 read-only Reserved Reserved 4 28 read-only EWM EWM EWM 0x4002C000 0 0x6 registers EWM 114 CTRL Control Register 0 8 read-write 0 0xFF EWMEN EWM enable. 0 1 read-writeOnce DISABLE EWM module is disabled. 0 ENABLE EWM module is enabled. 0x1 ASSIN EWM_in's Assertion State Select. 1 1 read-writeOnce DISABLE Default assert state of the EWM_in signal. 0 ENABLE Inverts the assert state of EWM_in signal. 0x1 INEN Input Enable. 2 1 read-writeOnce DISABLE EWM_in port is disabled. 0 ENABLE EWM_in port is enabled. 0x1 INTEN Interrupt Enable. 3 1 read-write ZERO Deasserts the interrupt request. 0 INT_REQ Generates an interrupt request, when EWM_OUT_b is asserted. 0x1 SERV Service Register 0x1 8 read-write 0 0xFF SERVICE SERVICE 0 8 read-write CMPL Compare Low Register 0x2 8 read-writeOnce 0 0xFF COMPAREL COMPAREL 0 8 read-writeOnce CMPH Compare High Register 0x3 8 read-writeOnce 0xFF 0xFF COMPAREH COMPAREH 0 8 read-writeOnce CLKCTRL Clock Control Register 0x4 8 read-writeOnce 0 0xFF CLKSEL CLKSEL 0 2 read-writeOnce CLKPRESCALER Clock Prescaler Register 0x5 8 read-writeOnce 0 0xFF CLK_DIV CLK_DIV 0 8 read-writeOnce WDOG1 WDOG WDOG WDOG 0x40030000 0 0xA registers WDOG1 112 WCR Watchdog Control Register 0 16 read-write 0x30 0xFFFF WDZST WDZST 0 1 read-write WDZST_0 Continue timer operation (Default). 0 WDZST_1 Suspend the watchdog timer. 0x1 WDBG WDBG 1 1 read-write WDBG_0 Continue WDOG timer operation (Default). 0 WDBG_1 Suspend the watchdog timer. 0x1 WDE WDE 2 1 read-write WDE_0 Disable the Watchdog (Default). 0 WDE_1 Enable the Watchdog. 0x1 WDT WDT 3 1 read-write WDT_0 No effect on WDOG_B (Default). 0 WDT_1 Assert WDOG_B upon a Watchdog Time-out event. 0x1 SRS SRS 4 1 read-write SRS_0 Assert system reset signal. 0 SRS_1 No effect on the system (Default). 0x1 WDA WDA 5 1 read-write WDA_0 Assert WDOG_B output. 0 WDA_1 No effect on system (Default). 0x1 SRE Software Reset Extension, an optional way to generate software reset 6 1 read-write SRE_0 using original way to generate software reset (default) 0 SRE_1 using new way to generate software reset. 0x1 WDW WDW 7 1 read-write WDW_0 Continue WDOG timer operation (Default). 0 WDW_1 Suspend WDOG timer operation. 0x1 WT WT 8 8 read-write WT_0 - 0.5 Seconds (Default). 0 WT_1 - 1.0 Seconds. 0x1 WT_2 - 1.5 Seconds. 0x2 WT_3 - 2.0 Seconds. 0x3 WT_255 - 128 Seconds. 0xFF WSR Watchdog Service Register 0x2 16 read-write 0 0xFFFF WSR WSR 0 16 read-write WSR_21845 Write to the Watchdog Service Register (WDOG_WSR). 0x5555 WSR_43690 Write to the Watchdog Service Register (WDOG_WSR). 0xAAAA WRSR Watchdog Reset Status Register 0x4 16 read-only 0 0xFFFF SFTW SFTW 0 1 read-only SFTW_0 Reset is not the result of a software reset. 0 SFTW_1 Reset is the result of a software reset. 0x1 TOUT TOUT 1 1 read-only TOUT_0 Reset is not the result of a WDOG timeout. 0 TOUT_1 Reset is the result of a WDOG timeout. 0x1 POR POR 4 1 read-only POR_0 Reset is not the result of a power on reset. 0 POR_1 Reset is the result of a power on reset. 0x1 WICR Watchdog Interrupt Control Register 0x6 16 read-write 0x4 0xFFFF WICT WICT 0 8 read-write WICT_0 WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. 0 WICT_1 WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. 0x1 WICT_4 WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). 0x4 WICT_255 WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. 0xFF WTIS WTIS 14 1 read-write oneToClear WTIS_0 No interrupt has occurred (Default). 0 WTIS_1 Interrupt has occurred 0x1 WIE WIE 15 1 read-write WIE_0 Disable Interrupt (Default). 0 WIE_1 Enable Interrupt. 0x1 WMCR Watchdog Miscellaneous Control Register 0x8 16 read-write 0x1 0xFFFF PDE PDE 0 1 read-write PDE_0 Power Down Counter of WDOG is disabled. 0 PDE_1 Power Down Counter of WDOG is enabled (Default). 0x1 WDOG2 WDOG WDOG 0x40034000 0 0xA registers WDOG2 65 RTWDOG3 WDOG RTWDOG RTWDOG 0x40038000 0 0x10 registers RTWDOG3 113 CS Watchdog Control and Status Register 0 32 read-write 0x2180 0xFFFFFFFF STOP Stop Enable 0 1 read-write STOP_0 Watchdog disabled in chip stop mode. 0 STOP_1 Watchdog enabled in chip stop mode. 0x1 WAIT Wait Enable 1 1 read-write WAIT_0 Watchdog disabled in chip wait mode. 0 WAIT_1 Watchdog enabled in chip wait mode. 0x1 DBG Debug Enable 2 1 read-write DBG_0 Watchdog disabled in chip debug mode. 0 DBG_1 Watchdog enabled in chip debug mode. 0x1 TST Watchdog Test 3 2 read-write TST_0 Watchdog test mode disabled. 0 TST_1 Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. 0x1 TST_2 Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. 0x2 TST_3 Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. 0x3 UPDATE Allow updates 5 1 read-write UPDATE_0 Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 0 UPDATE_1 Updates allowed. Software can modify the watchdog configuration registers within 255 bus clocks after performing the unlock write sequence. 0x1 INT Watchdog Interrupt 6 1 read-write INT_0 Watchdog interrupts are disabled. Watchdog resets are not delayed. 0 INT_1 Watchdog interrupts are enabled. Watchdog resets are delayed by 255 bus clocks from the interrupt vector fetch. 0x1 EN Watchdog Enable 7 1 read-write EN_0 Watchdog disabled. 0 EN_1 Watchdog enabled. 0x1 CLK Watchdog Clock 8 2 read-write RCS Reconfiguration Success 10 1 read-only RCS_0 Reconfiguring WDOG. 0 RCS_1 Reconfiguration is successful. 0x1 ULK Unlock status 11 1 read-only ULK_0 WDOG is locked. 0 ULK_1 WDOG is unlocked. 0x1 PRES Watchdog prescaler 12 1 read-write PRES_0 256 prescaler disabled. 0 PRES_1 256 prescaler enabled. 0x1 CMD32EN Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words 13 1 read-write CMD32EN_0 Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. 0 CMD32EN_1 Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. 0x1 FLG Watchdog Interrupt Flag 14 1 read-write oneToClear FLG_0 No interrupt occurred. 0 FLG_1 An interrupt occurred. 0x1 WIN Watchdog Window 15 1 read-write WIN_0 Window mode disabled. 0 WIN_1 Window mode enabled. 0x1 CNT Watchdog Counter Register 0x4 32 read-write 0 0xFFFFFFFF CNTLOW Low byte of the Watchdog Counter 0 8 read-write CNTHIGH High byte of the Watchdog Counter 8 8 read-write TOVAL Watchdog Timeout Value Register 0x8 32 read-write 0x7D00 0xFFFFFFFF TOVALLOW Low byte of the timeout value 0 8 read-write TOVALHIGH High byte of the timeout value 8 8 read-write WIN Watchdog Window Register 0xC 32 read-write 0 0xFFFFFFFF WINLOW Low byte of Watchdog Window 0 8 read-write WINHIGH High byte of Watchdog Window 8 8 read-write RTWDOG4 WDOG RTWDOG 0x40C10000 0 0x10 registers XBARA1 Crossbar Switch XBARA XBARA1_ 0x4003C000 0 0xB4 registers XBAR1_IRQ_0_1 143 XBAR1_IRQ_2_3 144 SEL0 Crossbar A Select Register 0 0 16 read-write 0 0xFFFF SEL0 Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL1 Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL1 Crossbar A Select Register 1 0x2 16 read-write 0 0xFFFF SEL2 Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL3 Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL2 Crossbar A Select Register 2 0x4 16 read-write 0 0xFFFF SEL4 Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL5 Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL3 Crossbar A Select Register 3 0x6 16 read-write 0 0xFFFF SEL6 Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL7 Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL4 Crossbar A Select Register 4 0x8 16 read-write 0 0xFFFF SEL8 Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL9 Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL5 Crossbar A Select Register 5 0xA 16 read-write 0 0xFFFF SEL10 Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL11 Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL6 Crossbar A Select Register 6 0xC 16 read-write 0 0xFFFF SEL12 Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL13 Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL7 Crossbar A Select Register 7 0xE 16 read-write 0 0xFFFF SEL14 Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL15 Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL8 Crossbar A Select Register 8 0x10 16 read-write 0 0xFFFF SEL16 Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL17 Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL9 Crossbar A Select Register 9 0x12 16 read-write 0 0xFFFF SEL18 Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL19 Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL10 Crossbar A Select Register 10 0x14 16 read-write 0 0xFFFF SEL20 Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL21 Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL11 Crossbar A Select Register 11 0x16 16 read-write 0 0xFFFF SEL22 Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL23 Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL12 Crossbar A Select Register 12 0x18 16 read-write 0 0xFFFF SEL24 Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL25 Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL13 Crossbar A Select Register 13 0x1A 16 read-write 0 0xFFFF SEL26 Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL27 Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL14 Crossbar A Select Register 14 0x1C 16 read-write 0 0xFFFF SEL28 Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL29 Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL15 Crossbar A Select Register 15 0x1E 16 read-write 0 0xFFFF SEL30 Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL31 Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL16 Crossbar A Select Register 16 0x20 16 read-write 0 0xFFFF SEL32 Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL33 Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL17 Crossbar A Select Register 17 0x22 16 read-write 0 0xFFFF SEL34 Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL35 Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL18 Crossbar A Select Register 18 0x24 16 read-write 0 0xFFFF SEL36 Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL37 Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL19 Crossbar A Select Register 19 0x26 16 read-write 0 0xFFFF SEL38 Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL39 Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL20 Crossbar A Select Register 20 0x28 16 read-write 0 0xFFFF SEL40 Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL41 Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL21 Crossbar A Select Register 21 0x2A 16 read-write 0 0xFFFF SEL42 Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL43 Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL22 Crossbar A Select Register 22 0x2C 16 read-write 0 0xFFFF SEL44 Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL45 Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL23 Crossbar A Select Register 23 0x2E 16 read-write 0 0xFFFF SEL46 Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL47 Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL24 Crossbar A Select Register 24 0x30 16 read-write 0 0xFFFF SEL48 Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL49 Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL25 Crossbar A Select Register 25 0x32 16 read-write 0 0xFFFF SEL50 Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL51 Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL26 Crossbar A Select Register 26 0x34 16 read-write 0 0xFFFF SEL52 Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL53 Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL27 Crossbar A Select Register 27 0x36 16 read-write 0 0xFFFF SEL54 Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL55 Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL28 Crossbar A Select Register 28 0x38 16 read-write 0 0xFFFF SEL56 Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL57 Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL29 Crossbar A Select Register 29 0x3A 16 read-write 0 0xFFFF SEL58 Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL59 Input (XBARA_INn) to be muxed to XBARA_OUT59 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL30 Crossbar A Select Register 30 0x3C 16 read-write 0 0xFFFF SEL60 Input (XBARA_INn) to be muxed to XBARA_OUT60 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL61 Input (XBARA_INn) to be muxed to XBARA_OUT61 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL31 Crossbar A Select Register 31 0x3E 16 read-write 0 0xFFFF SEL62 Input (XBARA_INn) to be muxed to XBARA_OUT62 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL63 Input (XBARA_INn) to be muxed to XBARA_OUT63 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL32 Crossbar A Select Register 32 0x40 16 read-write 0 0xFFFF SEL64 Input (XBARA_INn) to be muxed to XBARA_OUT64 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL65 Input (XBARA_INn) to be muxed to XBARA_OUT65 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL33 Crossbar A Select Register 33 0x42 16 read-write 0 0xFFFF SEL66 Input (XBARA_INn) to be muxed to XBARA_OUT66 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL67 Input (XBARA_INn) to be muxed to XBARA_OUT67 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL34 Crossbar A Select Register 34 0x44 16 read-write 0 0xFFFF SEL68 Input (XBARA_INn) to be muxed to XBARA_OUT68 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL69 Input (XBARA_INn) to be muxed to XBARA_OUT69 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL35 Crossbar A Select Register 35 0x46 16 read-write 0 0xFFFF SEL70 Input (XBARA_INn) to be muxed to XBARA_OUT70 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL71 Input (XBARA_INn) to be muxed to XBARA_OUT71 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL36 Crossbar A Select Register 36 0x48 16 read-write 0 0xFFFF SEL72 Input (XBARA_INn) to be muxed to XBARA_OUT72 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL73 Input (XBARA_INn) to be muxed to XBARA_OUT73 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL37 Crossbar A Select Register 37 0x4A 16 read-write 0 0xFFFF SEL74 Input (XBARA_INn) to be muxed to XBARA_OUT74 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL75 Input (XBARA_INn) to be muxed to XBARA_OUT75 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL38 Crossbar A Select Register 38 0x4C 16 read-write 0 0xFFFF SEL76 Input (XBARA_INn) to be muxed to XBARA_OUT76 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL77 Input (XBARA_INn) to be muxed to XBARA_OUT77 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL39 Crossbar A Select Register 39 0x4E 16 read-write 0 0xFFFF SEL78 Input (XBARA_INn) to be muxed to XBARA_OUT78 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL79 Input (XBARA_INn) to be muxed to XBARA_OUT79 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL40 Crossbar A Select Register 40 0x50 16 read-write 0 0xFFFF SEL80 Input (XBARA_INn) to be muxed to XBARA_OUT80 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL81 Input (XBARA_INn) to be muxed to XBARA_OUT81 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL41 Crossbar A Select Register 41 0x52 16 read-write 0 0xFFFF SEL82 Input (XBARA_INn) to be muxed to XBARA_OUT82 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL83 Input (XBARA_INn) to be muxed to XBARA_OUT83 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL42 Crossbar A Select Register 42 0x54 16 read-write 0 0xFFFF SEL84 Input (XBARA_INn) to be muxed to XBARA_OUT84 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL85 Input (XBARA_INn) to be muxed to XBARA_OUT85 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL43 Crossbar A Select Register 43 0x56 16 read-write 0 0xFFFF SEL86 Input (XBARA_INn) to be muxed to XBARA_OUT86 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL87 Input (XBARA_INn) to be muxed to XBARA_OUT87 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL44 Crossbar A Select Register 44 0x58 16 read-write 0 0xFFFF SEL88 Input (XBARA_INn) to be muxed to XBARA_OUT88 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL89 Input (XBARA_INn) to be muxed to XBARA_OUT89 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL45 Crossbar A Select Register 45 0x5A 16 read-write 0 0xFFFF SEL90 Input (XBARA_INn) to be muxed to XBARA_OUT90 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL91 Input (XBARA_INn) to be muxed to XBARA_OUT91 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL46 Crossbar A Select Register 46 0x5C 16 read-write 0 0xFFFF SEL92 Input (XBARA_INn) to be muxed to XBARA_OUT92 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL93 Input (XBARA_INn) to be muxed to XBARA_OUT93 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL47 Crossbar A Select Register 47 0x5E 16 read-write 0 0xFFFF SEL94 Input (XBARA_INn) to be muxed to XBARA_OUT94 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL95 Input (XBARA_INn) to be muxed to XBARA_OUT95 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL48 Crossbar A Select Register 48 0x60 16 read-write 0 0xFFFF SEL96 Input (XBARA_INn) to be muxed to XBARA_OUT96 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL97 Input (XBARA_INn) to be muxed to XBARA_OUT97 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL49 Crossbar A Select Register 49 0x62 16 read-write 0 0xFFFF SEL98 Input (XBARA_INn) to be muxed to XBARA_OUT98 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL99 Input (XBARA_INn) to be muxed to XBARA_OUT99 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL50 Crossbar A Select Register 50 0x64 16 read-write 0 0xFFFF SEL100 Input (XBARA_INn) to be muxed to XBARA_OUT100 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL101 Input (XBARA_INn) to be muxed to XBARA_OUT101 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL51 Crossbar A Select Register 51 0x66 16 read-write 0 0xFFFF SEL102 Input (XBARA_INn) to be muxed to XBARA_OUT102 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL103 Input (XBARA_INn) to be muxed to XBARA_OUT103 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL52 Crossbar A Select Register 52 0x68 16 read-write 0 0xFFFF SEL104 Input (XBARA_INn) to be muxed to XBARA_OUT104 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL105 Input (XBARA_INn) to be muxed to XBARA_OUT105 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL53 Crossbar A Select Register 53 0x6A 16 read-write 0 0xFFFF SEL106 Input (XBARA_INn) to be muxed to XBARA_OUT106 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL107 Input (XBARA_INn) to be muxed to XBARA_OUT107 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL54 Crossbar A Select Register 54 0x6C 16 read-write 0 0xFFFF SEL108 Input (XBARA_INn) to be muxed to XBARA_OUT108 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL109 Input (XBARA_INn) to be muxed to XBARA_OUT109 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL55 Crossbar A Select Register 55 0x6E 16 read-write 0 0xFFFF SEL110 Input (XBARA_INn) to be muxed to XBARA_OUT110 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL111 Input (XBARA_INn) to be muxed to XBARA_OUT111 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL56 Crossbar A Select Register 56 0x70 16 read-write 0 0xFFFF SEL112 Input (XBARA_INn) to be muxed to XBARA_OUT112 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL113 Input (XBARA_INn) to be muxed to XBARA_OUT113 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL57 Crossbar A Select Register 57 0x72 16 read-write 0 0xFFFF SEL114 Input (XBARA_INn) to be muxed to XBARA_OUT114 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL115 Input (XBARA_INn) to be muxed to XBARA_OUT115 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL58 Crossbar A Select Register 58 0x74 16 read-write 0 0xFFFF SEL116 Input (XBARA_INn) to be muxed to XBARA_OUT116 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL117 Input (XBARA_INn) to be muxed to XBARA_OUT117 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL59 Crossbar A Select Register 59 0x76 16 read-write 0 0xFFFF SEL118 Input (XBARA_INn) to be muxed to XBARA_OUT118 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL119 Input (XBARA_INn) to be muxed to XBARA_OUT119 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL60 Crossbar A Select Register 60 0x78 16 read-write 0 0xFFFF SEL120 Input (XBARA_INn) to be muxed to XBARA_OUT120 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL121 Input (XBARA_INn) to be muxed to XBARA_OUT121 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL61 Crossbar A Select Register 61 0x7A 16 read-write 0 0xFFFF SEL122 Input (XBARA_INn) to be muxed to XBARA_OUT122 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL123 Input (XBARA_INn) to be muxed to XBARA_OUT123 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL62 Crossbar A Select Register 62 0x7C 16 read-write 0 0xFFFF SEL124 Input (XBARA_INn) to be muxed to XBARA_OUT124 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL125 Input (XBARA_INn) to be muxed to XBARA_OUT125 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL63 Crossbar A Select Register 63 0x7E 16 read-write 0 0xFFFF SEL126 Input (XBARA_INn) to be muxed to XBARA_OUT126 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL127 Input (XBARA_INn) to be muxed to XBARA_OUT127 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL64 Crossbar A Select Register 64 0x80 16 read-write 0 0xFFFF SEL128 Input (XBARA_INn) to be muxed to XBARA_OUT128 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL129 Input (XBARA_INn) to be muxed to XBARA_OUT129 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL65 Crossbar A Select Register 65 0x82 16 read-write 0 0xFFFF SEL130 Input (XBARA_INn) to be muxed to XBARA_OUT130 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL131 Input (XBARA_INn) to be muxed to XBARA_OUT131 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL66 Crossbar A Select Register 66 0x84 16 read-write 0 0xFFFF SEL132 Input (XBARA_INn) to be muxed to XBARA_OUT132 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL133 Input (XBARA_INn) to be muxed to XBARA_OUT133 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL67 Crossbar A Select Register 67 0x86 16 read-write 0 0xFFFF SEL134 Input (XBARA_INn) to be muxed to XBARA_OUT134 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL135 Input (XBARA_INn) to be muxed to XBARA_OUT135 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL68 Crossbar A Select Register 68 0x88 16 read-write 0 0xFFFF SEL136 Input (XBARA_INn) to be muxed to XBARA_OUT136 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL137 Input (XBARA_INn) to be muxed to XBARA_OUT137 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL69 Crossbar A Select Register 69 0x8A 16 read-write 0 0xFFFF SEL138 Input (XBARA_INn) to be muxed to XBARA_OUT138 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL139 Input (XBARA_INn) to be muxed to XBARA_OUT139 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL70 Crossbar A Select Register 70 0x8C 16 read-write 0 0xFFFF SEL140 Input (XBARA_INn) to be muxed to XBARA_OUT140 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL141 Input (XBARA_INn) to be muxed to XBARA_OUT141 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL71 Crossbar A Select Register 71 0x8E 16 read-write 0 0xFFFF SEL142 Input (XBARA_INn) to be muxed to XBARA_OUT142 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL143 Input (XBARA_INn) to be muxed to XBARA_OUT143 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL72 Crossbar A Select Register 72 0x90 16 read-write 0 0xFFFF SEL144 Input (XBARA_INn) to be muxed to XBARA_OUT144 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL145 Input (XBARA_INn) to be muxed to XBARA_OUT145 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL73 Crossbar A Select Register 73 0x92 16 read-write 0 0xFFFF SEL146 Input (XBARA_INn) to be muxed to XBARA_OUT146 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL147 Input (XBARA_INn) to be muxed to XBARA_OUT147 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL74 Crossbar A Select Register 74 0x94 16 read-write 0 0xFFFF SEL148 Input (XBARA_INn) to be muxed to XBARA_OUT148 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL149 Input (XBARA_INn) to be muxed to XBARA_OUT149 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL75 Crossbar A Select Register 75 0x96 16 read-write 0 0xFFFF SEL150 Input (XBARA_INn) to be muxed to XBARA_OUT150 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL151 Input (XBARA_INn) to be muxed to XBARA_OUT151 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL76 Crossbar A Select Register 76 0x98 16 read-write 0 0xFFFF SEL152 Input (XBARA_INn) to be muxed to XBARA_OUT152 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL153 Input (XBARA_INn) to be muxed to XBARA_OUT153 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL77 Crossbar A Select Register 77 0x9A 16 read-write 0 0xFFFF SEL154 Input (XBARA_INn) to be muxed to XBARA_OUT154 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL155 Input (XBARA_INn) to be muxed to XBARA_OUT155 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL78 Crossbar A Select Register 78 0x9C 16 read-write 0 0xFFFF SEL156 Input (XBARA_INn) to be muxed to XBARA_OUT156 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL157 Input (XBARA_INn) to be muxed to XBARA_OUT157 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL79 Crossbar A Select Register 79 0x9E 16 read-write 0 0xFFFF SEL158 Input (XBARA_INn) to be muxed to XBARA_OUT158 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL159 Input (XBARA_INn) to be muxed to XBARA_OUT159 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL80 Crossbar A Select Register 80 0xA0 16 read-write 0 0xFFFF SEL160 Input (XBARA_INn) to be muxed to XBARA_OUT160 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL161 Input (XBARA_INn) to be muxed to XBARA_OUT161 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL81 Crossbar A Select Register 81 0xA2 16 read-write 0 0xFFFF SEL162 Input (XBARA_INn) to be muxed to XBARA_OUT162 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL163 Input (XBARA_INn) to be muxed to XBARA_OUT163 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL82 Crossbar A Select Register 82 0xA4 16 read-write 0 0xFFFF SEL164 Input (XBARA_INn) to be muxed to XBARA_OUT164 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL165 Input (XBARA_INn) to be muxed to XBARA_OUT165 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL83 Crossbar A Select Register 83 0xA6 16 read-write 0 0xFFFF SEL166 Input (XBARA_INn) to be muxed to XBARA_OUT166 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL167 Input (XBARA_INn) to be muxed to XBARA_OUT167 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL84 Crossbar A Select Register 84 0xA8 16 read-write 0 0xFFFF SEL168 Input (XBARA_INn) to be muxed to XBARA_OUT168 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL169 Input (XBARA_INn) to be muxed to XBARA_OUT169 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL85 Crossbar A Select Register 85 0xAA 16 read-write 0 0xFFFF SEL170 Input (XBARA_INn) to be muxed to XBARA_OUT170 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL171 Input (XBARA_INn) to be muxed to XBARA_OUT171 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL86 Crossbar A Select Register 86 0xAC 16 read-write 0 0xFFFF SEL172 Input (XBARA_INn) to be muxed to XBARA_OUT172 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL173 Input (XBARA_INn) to be muxed to XBARA_OUT173 (refer to Functional Description section for input/output assignment) 8 8 read-write SEL87 Crossbar A Select Register 87 0xAE 16 read-write 0 0xFFFF SEL174 Input (XBARA_INn) to be muxed to XBARA_OUT174 (refer to Functional Description section for input/output assignment) 0 8 read-write SEL175 Input (XBARA_INn) to be muxed to XBARA_OUT175 (refer to Functional Description section for input/output assignment) 8 8 read-write CTRL0 Crossbar A Control Register 0 0xB0 16 read-write 0 0xFFFF DEN0 DMA Enable for XBAR_OUT0 0 1 read-write DEN0_0 DMA disabled 0 DEN0_1 DMA enabled 0x1 IEN0 Interrupt Enable for XBAR_OUT0 1 1 read-write IEN0_0 Interrupt disabled 0 IEN0_1 Interrupt enabled 0x1 EDGE0 Active edge for edge detection on XBAR_OUT0 2 2 read-write EDGE0_0 STS0 never asserts 0 EDGE0_1 STS0 asserts on rising edges of XBAR_OUT0 0x1 EDGE0_2 STS0 asserts on falling edges of XBAR_OUT0 0x2 EDGE0_3 STS0 asserts on rising and falling edges of XBAR_OUT0 0x3 STS0 Edge detection status for XBAR_OUT0 4 1 read-write oneToClear STS0_0 Active edge not yet detected on XBAR_OUT0 0 STS0_1 Active edge detected on XBAR_OUT0 0x1 DEN1 DMA Enable for XBAR_OUT1 8 1 read-write DEN1_0 DMA disabled 0 DEN1_1 DMA enabled 0x1 IEN1 Interrupt Enable for XBAR_OUT1 9 1 read-write IEN1_0 Interrupt disabled 0 IEN1_1 Interrupt enabled 0x1 EDGE1 Active edge for edge detection on XBAR_OUT1 10 2 read-write EDGE1_0 STS1 never asserts 0 EDGE1_1 STS1 asserts on rising edges of XBAR_OUT1 0x1 EDGE1_2 STS1 asserts on falling edges of XBAR_OUT1 0x2 EDGE1_3 STS1 asserts on rising and falling edges of XBAR_OUT1 0x3 STS1 Edge detection status for XBAR_OUT1 12 1 read-write oneToClear STS1_0 Active edge not yet detected on XBAR_OUT1 0 STS1_1 Active edge detected on XBAR_OUT1 0x1 CTRL1 Crossbar A Control Register 1 0xB2 16 read-write 0 0xFFFF DEN2 DMA Enable for XBAR_OUT2 0 1 read-write DEN2_0 DMA disabled 0 DEN2_1 DMA enabled 0x1 IEN2 Interrupt Enable for XBAR_OUT2 1 1 read-write IEN2_0 Interrupt disabled 0 IEN2_1 Interrupt enabled 0x1 EDGE2 Active edge for edge detection on XBAR_OUT2 2 2 read-write EDGE2_0 STS2 never asserts 0 EDGE2_1 STS2 asserts on rising edges of XBAR_OUT2 0x1 EDGE2_2 STS2 asserts on falling edges of XBAR_OUT2 0x2 EDGE2_3 STS2 asserts on rising and falling edges of XBAR_OUT2 0x3 STS2 Edge detection status for XBAR_OUT2 4 1 read-write oneToClear STS2_0 Active edge not yet detected on XBAR_OUT2 0 STS2_1 Active edge detected on XBAR_OUT2 0x1 DEN3 DMA Enable for XBAR_OUT3 8 1 read-write DEN3_0 DMA disabled 0 DEN3_1 DMA enabled 0x1 IEN3 Interrupt Enable for XBAR_OUT3 9 1 read-write IEN3_0 Interrupt disabled 0 IEN3_1 Interrupt enabled 0x1 EDGE3 Active edge for edge detection on XBAR_OUT3 10 2 read-write EDGE3_0 STS3 never asserts 0 EDGE3_1 STS3 asserts on rising edges of XBAR_OUT3 0x1 EDGE3_2 STS3 asserts on falling edges of XBAR_OUT3 0x2 EDGE3_3 STS3 asserts on rising and falling edges of XBAR_OUT3 0x3 STS3 Edge detection status for XBAR_OUT3 12 1 read-write oneToClear STS3_0 Active edge not yet detected on XBAR_OUT3 0 STS3_1 Active edge detected on XBAR_OUT3 0x1 XBARB2 Crossbar Switch XBARA XBARB2_ XBARA 0x40040000 0 0x10 registers SEL0 Crossbar B Select Register 0 0 16 read-write 0 0xFFFF SEL0 Input (XBARB_INn) to be muxed to XBARB_OUT0 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL1 Input (XBARB_INn) to be muxed to XBARB_OUT1 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL1 Crossbar B Select Register 1 0x2 16 read-write 0 0xFFFF SEL2 Input (XBARB_INn) to be muxed to XBARB_OUT2 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL3 Input (XBARB_INn) to be muxed to XBARB_OUT3 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL2 Crossbar B Select Register 2 0x4 16 read-write 0 0xFFFF SEL4 Input (XBARB_INn) to be muxed to XBARB_OUT4 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL5 Input (XBARB_INn) to be muxed to XBARB_OUT5 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL3 Crossbar B Select Register 3 0x6 16 read-write 0 0xFFFF SEL6 Input (XBARB_INn) to be muxed to XBARB_OUT6 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL7 Input (XBARB_INn) to be muxed to XBARB_OUT7 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL4 Crossbar B Select Register 4 0x8 16 read-write 0 0xFFFF SEL8 Input (XBARB_INn) to be muxed to XBARB_OUT8 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL9 Input (XBARB_INn) to be muxed to XBARB_OUT9 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL5 Crossbar B Select Register 5 0xA 16 read-write 0 0xFFFF SEL10 Input (XBARB_INn) to be muxed to XBARB_OUT10 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL11 Input (XBARB_INn) to be muxed to XBARB_OUT11 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL6 Crossbar B Select Register 6 0xC 16 read-write 0 0xFFFF SEL12 Input (XBARB_INn) to be muxed to XBARB_OUT12 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL13 Input (XBARB_INn) to be muxed to XBARB_OUT13 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL7 Crossbar B Select Register 7 0xE 16 read-write 0 0xFFFF SEL14 Input (XBARB_INn) to be muxed to XBARB_OUT14 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL15 Input (XBARB_INn) to be muxed to XBARB_OUT15 (refer to Functional Description section for input/output assignment) 8 7 read-write XBARB3 Crossbar Switch XBARA XBARB3_ 0x40044000 0 0x10 registers ADC_ETC ADC_ETC ADC_ETC 0x40048000 0 0x150 registers ADC_ETC_IRQ0 145 ADC_ETC_IRQ1 146 ADC_ETC_IRQ2 147 ADC_ETC_IRQ3 148 ADC_ETC_ERROR_IRQ 149 CTRL ADC_ETC Global Control Register 0 32 read-write 0x80000000 0xFFFFFFFF TRIG_ENABLE TRIG enable register. 0 8 read-write TRIG_ENABLE_0 disable all 8 external XBAR triggers. 0 TRIG_ENABLE_1 enable external XBAR trigger0. 0x1 TRIG_ENABLE_2 enable external XBAR trigger1. 0x2 TRIG_ENABLE_3 enable external XBAR trigger0 and trigger1. 0x3 TRIG_ENABLE_255 enable all 8 external XBAR triggers. 0xFF PRE_DIVIDER Pre-divider for trig delay and interval 16 8 read-write DMA_MODE_SEL Select the trigger type of the DMA_REQ. 29 1 read-write DMA_MODE_SEL_0 Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. 0 DMA_MODE_SEL_1 Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. 0x1 SOFTRST Software synchronous reset, active high. 31 1 read-write SOFTRST_0 ADC_ETC works normally. 0 SOFTRST_1 All registers inside ADC_ETC will be reset to the default value. 0x1 DONE0_1_IRQ ETC DONE0 and DONE1 IRQ State Register 0x4 32 read-write 0 0xFFFFFFFF oneToClear TRIG0_DONE0 TRIG0 done0 interrupt detection. 0 1 read-write oneToClear TRIG0_DONE0_0 No TRIG0_DONE0 interrupt detected 0 TRIG0_DONE0_1 TRIG0_DONE0 interrupt detected 0x1 TRIG1_DONE0 TRIG1 done0 interrupt detection. 1 1 read-write oneToClear TRIG1_DONE0_0 No TRIG1_DONE0 interrupt detected 0 TRIG1_DONE0_1 TRIG1_DONE0 interrupt detected 0x1 TRIG2_DONE0 TRIG2 done0 interrupt detection. 2 1 read-write oneToClear TRIG2_DONE0_0 No TRIG2_DONE0 interrupt detected 0 TRIG2_DONE0_1 TRIG2_DONE0 interrupt detected 0x1 TRIG3_DONE0 TRIG3 done0 interrupt detection. 3 1 read-write oneToClear TRIG3_DONE0_0 No TRIG3_DONE0 interrupt detected 0 TRIG3_DONE0_1 TRIG3_DONE0 interrupt detected 0x1 TRIG4_DONE0 TRIG4 done0 interrupt detection. 4 1 read-write oneToClear TRIG4_DONE0_0 No TRIG4_DONE0 interrupt detected 0 TRIG4_DONE0_1 TRIG4_DONE0 interrupt detected 0x1 TRIG5_DONE0 TRIG5 done0 interrupt detection. 5 1 read-write oneToClear TRIG5_DONE0_0 No TRIG5_DONE0 interrupt detected 0 TRIG5_DONE0_1 TRIG5_DONE0 interrupt detected 0x1 TRIG6_DONE0 TRIG6 done0 interrupt detection. 6 1 read-write oneToClear TRIG6_DONE0_0 No TRIG6_DONE0 interrupt detected 0 TRIG6_DONE0_1 TRIG6_DONE0 interrupt detected 0x1 TRIG7_DONE0 TRIG7 done0 interrupt detection. 7 1 read-write oneToClear TRIG7_DONE0_0 No TRIG7_DONE0 interrupt detected 0 TRIG7_DONE0_1 TRIG7_DONE0 interrupt detected 0x1 TRIG0_DONE1 TRIG0 done1 interrupt detection. 16 1 read-write oneToClear TRIG0_DONE1_0 No TRIG0_DONE1 interrupt detected 0 TRIG0_DONE1_1 TRIG0_DONE1 interrupt detected 0x1 TRIG1_DONE1 TRIG1 done1 interrupt detection. 17 1 read-write oneToClear TRIG1_DONE1_0 No TRIG1_DONE1 interrupt detected 0 TRIG1_DONE1_1 TRIG1_DONE1 interrupt detected 0x1 TRIG2_DONE1 TRIG2 done1 interrupt detection. 18 1 read-write oneToClear TRIG2_DONE1_0 No TRIG2_DONE1 interrupt detected 0 TRIG2_DONE1_1 TRIG2_DONE1 interrupt detected 0x1 TRIG3_DONE1 TRIG3 done1 interrupt detection. 19 1 read-write oneToClear TRIG3_DONE1_0 No TRIG3_DONE1 interrupt detected 0 TRIG3_DONE1_1 TRIG3_DONE1 interrupt detected 0x1 TRIG4_DONE1 TRIG4 done1 interrupt detection. 20 1 read-write oneToClear TRIG4_DONE1_0 No TRIG4_DONE1 interrupt detected 0 TRIG4_DONE1_1 TRIG4_DONE1 interrupt detected 0x1 TRIG5_DONE1 TRIG5 done1 interrupt detection. 21 1 read-write oneToClear TRIG5_DONE1_0 No TRIG5_DONE1 interrupt detected 0 TRIG5_DONE1_1 TRIG5_DONE1 interrupt detected 0x1 TRIG6_DONE1 TRIG6 done1 interrupt detection. 22 1 read-write oneToClear TRIG6_DONE1_0 No TRIG6_DONE1 interrupt detected 0 TRIG6_DONE1_1 TRIG6_DONE1 interrupt detected 0x1 TRIG7_DONE1 TRIG7 done1 interrupt detection. 23 1 read-write oneToClear TRIG7_DONE1_0 No TRIG7_DONE1 interrupt detected 0 TRIG7_DONE1_1 TRIG7_DONE1 interrupt detected 0x1 DONE2_3_ERR_IRQ ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register 0x8 32 read-write 0 0xFFFFFFFF TRIG0_DONE2 TRIG0 done2 interrupt detection. 0 1 read-write oneToClear TRIG0_DONE2_0 No TRIG0_DONE2 interrupt detected 0 TRIG0_DONE2_1 TRIG0_DONE2 interrupt detected 0x1 TRIG1_DONE2 TRIG1 done2 interrupt detection. 1 1 read-write oneToClear TRIG1_DONE2_0 No TRIG1_DONE2 interrupt detected 0 TRIG1_DONE2_1 TRIG1_DONE2 interrupt detected 0x1 TRIG2_DONE2 TRIG2 done2 interrupt detection. 2 1 read-write oneToClear TRIG2_DONE2_0 No TRIG2_DONE2 interrupt detected 0 TRIG2_DONE2_1 TRIG2_DONE2 interrupt detected 0x1 TRIG3_DONE2 TRIG3 done2 interrupt detection. 3 1 read-write oneToClear TRIG3_DONE2_0 No TRIG3_DONE2 interrupt detected 0 TRIG3_DONE2_1 TRIG3_DONE2 interrupt detected 0x1 TRIG4_DONE2 TRIG4 done2 interrupt detection. 4 1 read-write oneToClear TRIG4_DONE2_0 No TRIG4_DONE2 interrupt detected 0 TRIG4_DONE2_1 TRIG4_DONE2 interrupt detected 0x1 TRIG5_DONE2 TRIG5 done2 interrupt detection. 5 1 read-write oneToClear TRIG5_DONE2_0 No TRIG5_DONE2 interrupt detected 0 TRIG5_DONE2_1 TRIG5_DONE2 interrupt detected 0x1 TRIG6_DONE2 TRIG6 done2 interrupt detection. 6 1 read-write oneToClear TRIG6_DONE2_0 No TRIG6_DONE2 interrupt detected 0 TRIG6_DONE2_1 TRIG6_DONE2 interrupt detected 0x1 TRIG7_DONE2 TRIG7 done2 interrupt detection. 7 1 read-write oneToClear TRIG7_DONE2_0 No TRIG7_DONE2 interrupt detected 0 TRIG7_DONE2_1 TRIG7_DONE2 interrupt detected 0x1 TRIG0_DONE3 TRIG0 done3 interrupt detection. 8 1 read-write oneToClear TRIG0_DONE3_0 No TRIG0_DONE3 interrupt detected 0 TRIG0_DONE3_1 TRIG0_DONE3 interrupt detected 0x1 TRIG1_DONE3 TRIG1 done3 interrupt detection. 9 1 read-write oneToClear TRIG1_DONE3_0 No TRIG1_DONE3 interrupt detected 0 TRIG1_DONE3_1 TRIG1_DONE3 interrupt detected 0x1 TRIG2_DONE3 TRIG2 done3 interrupt detection. 10 1 read-write oneToClear TRIG2_DONE3_0 No TRIG2_DONE3 interrupt detected 0 TRIG2_DONE3_1 TRIG2_DONE3 interrupt detected 0x1 TRIG3_DONE3 TRIG3 done3 interrupt detection. 11 1 read-write oneToClear TRIG3_DONE3_0 No TRIG3_DONE3 interrupt detected 0 TRIG3_DONE3_1 TRIG3_DONE3 interrupt detected 0x1 TRIG4_DONE3 TRIG4 done3 interrupt detection. 12 1 read-write oneToClear TRIG4_DONE3_0 No TRIG4_DONE3 interrupt detected 0 TRIG4_DONE3_1 TRIG4_DONE3 interrupt detected 0x1 TRIG5_DONE3 TRIG5 done3 interrupt detection. 13 1 read-write oneToClear TRIG5_DONE3_0 No TRIG5_DONE3 interrupt detected 0 TRIG5_DONE3_1 TRIG5_DONE3 interrupt detected 0x1 TRIG6_DONE3 TRIG6 done3 interrupt detection. 14 1 read-write oneToClear TRIG6_DONE3_0 No TRIG6_DONE3 interrupt detected 0 TRIG6_DONE3_1 TRIG6_DONE3 interrupt detected 0x1 TRIG7_DONE3 TRIG7 done3 interrupt detection. 15 1 read-write oneToClear TRIG7_DONE3_0 No TRIG7_DONE3 interrupt detected 0 TRIG7_DONE3_1 TRIG7_DONE3 interrupt detected 0x1 TRIG0_ERR TRIG0 error interrupt detection. 16 1 read-write TRIG0_ERR_0 No TRIG0_ERR interrupt detected 0 TRIG0_ERR_1 TRIG0_ERR interrupt detected 0x1 TRIG1_ERR TRIG1 error interrupt detection. 17 1 read-write TRIG1_ERR_0 No TRIG1_ERR interrupt detected 0 TRIG1_ERR_1 TRIG1_ERR interrupt detected 0x1 TRIG2_ERR TRIG2 error interrupt detection. 18 1 read-write TRIG2_ERR_0 No TRIG2_ERR interrupt detected 0 TRIG2_ERR_1 TRIG2_ERR interrupt detected 0x1 TRIG3_ERR TRIG3 error interrupt detection. 19 1 read-write TRIG3_ERR_0 No TRIG3_ERR interrupt detected 0 TRIG3_ERR_1 TRIG3_ERR interrupt detected 0x1 TRIG4_ERR TRIG4 error interrupt detection. 20 1 read-write TRIG4_ERR_0 No TRIG4_ERR interrupt detected 0 TRIG4_ERR_1 TRIG4_ERR interrupt detected 0x1 TRIG5_ERR TRIG5 error interrupt detection. 21 1 read-write TRIG5_ERR_0 No TRIG5_ERR interrupt detected 0 TRIG5_ERR_1 TRIG5_ERR interrupt detected 0x1 TRIG6_ERR TRIG6 error interrupt detection. 22 1 read-write TRIG6_ERR_0 No TRIG6_ERR interrupt detected 0 TRIG6_ERR_1 TRIG6_ERR interrupt detected 0x1 TRIG7_ERR TRIG7 error interrupt detection. 23 1 read-write TRIG7_ERR_0 No TRIG7_ERR interrupt detected 0 TRIG7_ERR_1 TRIG7_ERR interrupt detected 0x1 DMA_CTRL ETC DMA control Register 0xC 32 read-write 0 0xFFFFFFFF TRIG0_ENABLE Enable DMA request when TRIG0 done. 0 1 read-write TRIG0_ENABLE_0 TRIG0 DMA request disabled. 0 TRIG0_ENABLE_1 TRIG0 DMA request enabled. 0x1 TRIG1_ENABLE Enable DMA request when TRIG1 done. 1 1 read-write TRIG1_ENABLE_0 TRIG1 DMA request disabled. 0 TRIG1_ENABLE_1 TRIG1 DMA request enabled. 0x1 TRIG2_ENABLE Enable DMA request when TRIG2 done. 2 1 read-write TRIG2_ENABLE_0 TRIG2 DMA request disabled. 0 TRIG2_ENABLE_1 TRIG2 DMA request enabled. 0x1 TRIG3_ENABLE Enable DMA request when TRIG3 done. 3 1 read-write TRIG3_ENABLE_0 TRIG3 DMA request disabled. 0 TRIG3_ENABLE_1 TRIG3 DMA request enabled. 0x1 TRIG4_ENABLE Enable DMA request when TRIG4 done. 4 1 read-write TRIG4_ENABLE_0 TRIG4 DMA request disabled. 0 TRIG4_ENABLE_1 TRIG4 DMA request enabled. 0x1 TRIG5_ENABLE Enable DMA request when TRIG5 done. 5 1 read-write TRIG5_ENABLE_0 TRIG5 DMA request disabled. 0 TRIG5_ENABLE_1 TRIG5 DMA request enabled. 0x1 TRIG6_ENABLE Enable DMA request when TRIG6 done. 6 1 read-write TRIG6_ENABLE_0 TRIG6 DMA request disabled. 0 TRIG6_ENABLE_1 TRIG6 DMA request enabled. 0x1 TRIG7_ENABLE Enable DMA request when TRIG7 done. 7 1 read-write TRIG7_ENABLE_0 TRIG7 DMA request disabled. 0 TRIG7_ENABLE_1 TRIG7 DMA request enabled. 0x1 TRIG0_REQ Flag bit for DMA request 16 1 read-write oneToClear TRIG0_REQ_0 TRIG0_REQ not detected. 0 TRIG0_REQ_1 TRIG0_REQ detected. 0x1 TRIG1_REQ Flag bit for DMA request 17 1 read-write oneToClear TRIG1_REQ_0 TRIG1_REQ not detected. 0 TRIG1_REQ_1 TRIG1_REQ detected. 0x1 TRIG2_REQ Flag bit for DMA request 18 1 read-write oneToClear TRIG2_REQ_0 TRIG2_REQ not detected. 0 TRIG2_REQ_1 TRIG2_REQ detected. 0x1 TRIG3_REQ Flag bit for DMA request 19 1 read-write oneToClear TRIG3_REQ_0 TRIG3_REQ not detected. 0 TRIG3_REQ_1 TRIG3_REQ detected. 0x1 TRIG4_REQ Flag bit for DMA request 20 1 read-write oneToClear TRIG4_REQ_0 TRIG4_REQ not detected. 0 TRIG4_REQ_1 TRIG4_REQ detected. 0x1 TRIG5_REQ Flag bit for DMA request 21 1 read-write oneToClear TRIG5_REQ_0 TRIG5_REQ not detected. 0 TRIG5_REQ_1 TRIG5_REQ detected. 0x1 TRIG6_REQ Flag bit for DMA request 22 1 read-write oneToClear TRIG6_REQ_0 TRIG6_REQ not detected. 0 TRIG6_REQ_1 TRIG6_REQ detected. 0x1 TRIG7_REQ Flag bit for DMA request 23 1 read-write oneToClear TRIG7_REQ_0 TRIG7_REQ not detected. 0 TRIG7_REQ_1 TRIG7_REQ detected. 0x1 TRIG0_CTRL ETC_TRIG Control Register 0x10 32 read-write 0 0xFFFFFFFF SW_TRIG Software trigger. This field is self-clearing. 0 1 read-write SW_TRIG_0 No software trigger event generated. 0 SW_TRIG_1 Software trigger event generated. 0x1 TRIG_MODE Trigger mode selection. 4 1 read-write TRIG_MODE_0 Hardware trigger. The softerware trigger will be ignored. 0 TRIG_MODE_1 Software trigger. The hardware trigger will be ignored. 0x1 TRIG_CHAIN The number of segments inside the trigger chain of TRIGa. 8 3 read-write TRIG_CHAIN_0 Trigger chain length is 1 0 TRIG_CHAIN_1 Trigger chain length is 2 0x1 TRIG_CHAIN_2 Trigger chain length is 3 0x2 TRIG_CHAIN_3 Trigger chain length is 4 0x3 TRIG_CHAIN_4 Trigger chain length is 5 0x4 TRIG_CHAIN_5 Trigger chain length is 6 0x5 TRIG_CHAIN_6 Trigger chain length is 7 0x6 TRIG_CHAIN_7 Trigger chain length is 8 0x7 TRIG_PRIORITY External trigger priority, 7 is highest priority, while 0 is lowest 12 3 read-write SYNC_MODE Trigger synchronization mode selection 16 1 read-write SYNC_MODE_0 Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. 0 SYNC_MODE_1 Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. 0x1 CHAINx_DONE Segment x done detection 24 8 read-write oneToClear CHAINx_DONE_0 segment x done not detected. 0 CHAINx_DONE_1 segment x done detected. 0x1 TRIG0_COUNTER ETC_TRIG Counter Register 0x14 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG0_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0x18 32 read-write 0 0xFFFFFFFF CSEL0 ADC hardware trigger command selection 0 4 read-write CSEL0_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL0_1 ADC CMD1 selected. 0x1 CSEL0_2 ADC CMD2 selected. 0x2 CSEL0_3 ADC CMD3 selected. 0x3 CSEL0_4 ADC CMD4 selected. 0x4 CSEL0_5 ADC CMD5 selected. 0x5 CSEL0_6 ADC CMD6 selected. 0x6 CSEL0_7 ADC CMD7 selected. 0x7 CSEL0_8 ADC CMD8 selected. 0x8 CSEL0_9 ADC CMD9 selected. 0x9 CSEL0_10 ADC CMD10 selected. 0xA CSEL0_11 ADC CMD11 selected. 0xB CSEL0_12 ADC CMD12 selected. 0xC CSEL0_13 ADC CMD13 selected. 0xD CSEL0_14 ADC CMD14 selected. 0xE CSEL0_15 ADC CMD15 selected. 0xF HWTS0 Segment 0 HWTS ADC hardware trigger selection 4 8 read-write HWTS0_0 no trigger selected 0 HWTS0_1 ADC TRIG0 selected 0x1 HWTS0_2 ADC TRIG1 selected 0x2 HWTS0_4 ADC TRIG2 selected 0x4 HWTS0_8 ADC TRIG3 selected 0x8 HWTS0_16 ADC TRIG4 selected 0x10 HWTS0_32 ADC TRIG5 selected 0x20 HWTS0_64 ADC TRIG6 selected 0x40 HWTS0_128 ADC TRIG7 selected 0x80 B2B0 Segment 0 B2B 12 1 read-write B2B0_0 Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B0_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE0 Segment 0 interrupt enable. (This bit field is meaningful only when IE0_EN is set) 13 2 read-write IE0_0 Generate interrupt on Done0 when segment 0 finish. 0 IE0_1 Generate interrupt on Done1 when segment 0 finish. 0x1 IE0_2 Generate interrupt on Done2 when segment 0 finish. 0x2 IE0_3 Generate interrupt on Done3 when segment 0 finish. 0x3 IE0_EN IRQ enable of segment 0. 15 1 read-write IE0_EN_0 Interrupt DONE disabled. 0 IE0_EN_1 Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0. 0x1 CSEL1 ADC hardware trigger command selection 16 4 read-write CSEL1_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL1_1 ADC CMD1 selected. 0x1 CSEL1_2 ADC CMD2 selected. 0x2 CSEL1_3 ADC CMD3 selected. 0x3 CSEL1_4 ADC CMD4 selected. 0x4 CSEL1_5 ADC CMD5 selected. 0x5 CSEL1_6 ADC CMD6 selected. 0x6 CSEL1_7 ADC CMD7 selected. 0x7 CSEL1_8 ADC CMD8 selected. 0x8 CSEL1_9 ADC CMD9 selected. 0x9 CSEL1_10 ADC CMD10 selected. 0xA CSEL1_11 ADC CMD11 selected. 0xB CSEL1_12 ADC CMD12 selected. 0xC CSEL1_13 ADC CMD13 selected. 0xD CSEL1_14 ADC CMD14 selected. 0xE CSEL1_15 ADC CMD15 selected. 0xF HWTS1 Segment 1 HWTS ADC hardware trigger selection 20 8 read-write HWTS1_0 no trigger selected 0 HWTS1_1 ADC TRIG0 selected 0x1 HWTS1_2 ADC TRIG1 selected 0x2 HWTS1_4 ADC TRIG2 selected 0x4 HWTS1_8 ADC TRIG3 selected 0x8 HWTS1_16 ADC TRIG4 selected 0x10 HWTS1_32 ADC TRIG5 selected 0x20 HWTS1_64 ADC TRIG6 selected 0x40 HWTS1_128 ADC TRIG7 selected 0x80 B2B1 Segment 1 B2B 28 1 read-write B2B1_0 Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B1_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE1 Segment 1 interrupt enable. (This bit field is meaningful only when IE1_EN is set) 29 2 read-write IE1_0 Generate interrupt on Done0 when Segment 1 finish. 0 IE1_1 Generate interrupt on Done1 when Segment 1 finish. 0x1 IE1_2 Generate interrupt on Done2 when Segment 1 finish. 0x2 IE1_3 Generate interrupt on Done3 when Segment 1 finish. 0x3 IE1_EN IRQ enable of segment 1. 31 1 read-write IE1_EN_0 Interrupt DONE disabled. 0 IE1_EN_1 Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1. 0x1 TRIG0_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0x1C 32 read-write 0 0xFFFFFFFF CSEL2 ADC hardware trigger command selection 0 4 read-write CSEL2_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL2_1 ADC CMD1 selected. 0x1 CSEL2_2 ADC CMD2 selected. 0x2 CSEL2_3 ADC CMD3 selected. 0x3 CSEL2_4 ADC CMD4 selected. 0x4 CSEL2_5 ADC CMD5 selected. 0x5 CSEL2_6 ADC CMD6 selected. 0x6 CSEL2_7 ADC CMD7 selected. 0x7 CSEL2_8 ADC CMD8 selected. 0x8 CSEL2_9 ADC CMD9 selected. 0x9 CSEL2_10 ADC CMD10 selected. 0xA CSEL2_11 ADC CMD11 selected. 0xB CSEL2_12 ADC CMD12 selected. 0xC CSEL2_13 ADC CMD13 selected. 0xD CSEL2_14 ADC CMD14 selected. 0xE CSEL2_15 ADC CMD15 selected. 0xF HWTS2 Segment 2 HWTS ADC hardware trigger selection 4 8 read-write HWTS2_0 no trigger selected 0 HWTS2_1 ADC TRIG0 selected 0x1 HWTS2_2 ADC TRIG1 selected 0x2 HWTS2_4 ADC TRIG2 selected 0x4 HWTS2_8 ADC TRIG3 selected 0x8 HWTS2_16 ADC TRIG4 selected 0x10 HWTS2_32 ADC TRIG5 selected 0x20 HWTS2_64 ADC TRIG6 selected 0x40 HWTS2_128 ADC TRIG7 selected 0x80 B2B2 Segment 2 B2B 12 1 read-write B2B2_0 Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B2_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE2 Segment 2 interrupt enable. (This bit field is meaningful only when IE2_EN is set) 13 2 read-write IE2_0 Generate interrupt on Done0 when segment 2 finish. 0 IE2_1 Generate interrupt on Done1 when segment 2 finish. 0x1 IE2_2 Generate interrupt on Done2 when segment 2 finish. 0x2 IE2_3 Generate interrupt on Done3 when segment 2 finish. 0x3 IE2_EN IRQ enable of segment 2. 15 1 read-write IE2_EN_0 Interrupt DONE disabled. 0 IE2_EN_1 Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2. 0x1 CSEL3 ADC hardware trigger command selection 16 4 read-write CSEL3_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL3_1 ADC CMD1 selected. 0x1 CSEL3_2 ADC CMD2 selected. 0x2 CSEL3_3 ADC CMD3 selected. 0x3 CSEL3_4 ADC CMD4 selected. 0x4 CSEL3_5 ADC CMD5 selected. 0x5 CSEL3_6 ADC CMD6 selected. 0x6 CSEL3_7 ADC CMD7 selected. 0x7 CSEL3_8 ADC CMD8 selected. 0x8 CSEL3_9 ADC CMD9 selected. 0x9 CSEL3_10 ADC CMD10 selected. 0xA CSEL3_11 ADC CMD11 selected. 0xB CSEL3_12 ADC CMD12 selected. 0xC CSEL3_13 ADC CMD13 selected. 0xD CSEL3_14 ADC CMD14 selected. 0xE CSEL3_15 ADC CMD15 selected. 0xF HWTS3 Segment 3 HWTS ADC hardware trigger selection 20 8 read-write HWTS3_0 no trigger selected 0 HWTS3_1 ADC TRIG0 selected 0x1 HWTS3_2 ADC TRIG1 selected 0x2 HWTS3_4 ADC TRIG2 selected 0x4 HWTS3_8 ADC TRIG3 selected 0x8 HWTS3_16 ADC TRIG4 selected 0x10 HWTS3_32 ADC TRIG5 selected 0x20 HWTS3_64 ADC TRIG6 selected 0x40 HWTS3_128 ADC TRIG7 selected 0x80 B2B3 Segment 3 B2B 28 1 read-write B2B3_0 Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B3_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE3 Segment 3 interrupt enable. (This bit field is meaningful only when IE3_EN is set) 29 2 read-write IE3_0 Generate interrupt on Done0 when segment 3 finish. 0 IE3_1 Generate interrupt on Done1 when segment 3 finish. 0x1 IE3_2 Generate interrupt on Done2 when segment 3 finish. 0x2 IE3_3 Generate interrupt on Done3 when segment 3 finish. 0x3 IE3_EN IRQ enable of segment 3. 31 1 read-write IE3_EN_0 Interrupt DONE disabled. 0 IE3_EN_1 Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3. 0x1 TRIG0_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0x20 32 read-write 0 0xFFFFFFFF CSEL4 ADC hardware trigger command selection 0 4 read-write CSEL4_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL4_1 ADC CMD1 selected. 0x1 CSEL4_2 ADC CMD2 selected. 0x2 CSEL4_3 ADC CMD3 selected. 0x3 CSEL4_4 ADC CMD4 selected. 0x4 CSEL4_5 ADC CMD5 selected. 0x5 CSEL4_6 ADC CMD6 selected. 0x6 CSEL4_7 ADC CMD7 selected. 0x7 CSEL4_8 ADC CMD8 selected. 0x8 CSEL4_9 ADC CMD9 selected. 0x9 CSEL4_10 ADC CMD10 selected. 0xA CSEL4_11 ADC CMD11 selected. 0xB CSEL4_12 ADC CMD12 selected. 0xC CSEL4_13 ADC CMD13 selected. 0xD CSEL4_14 ADC CMD14 selected. 0xE CSEL4_15 ADC CMD15 selected. 0xF HWTS4 Segment 4 HWTS ADC hardware trigger selection 4 8 read-write HWTS4_0 no trigger selected 0 HWTS4_1 ADC TRIG0 selected 0x1 HWTS4_2 ADC TRIG1 selected 0x2 HWTS4_4 ADC TRIG2 selected 0x4 HWTS4_8 ADC TRIG3 selected 0x8 HWTS4_16 ADC TRIG4 selected 0x10 HWTS4_32 ADC TRIG5 selected 0x20 HWTS4_64 ADC TRIG6 selected 0x40 HWTS4_128 ADC TRIG7 selected 0x80 B2B4 Segment 4 B2B 12 1 read-write B2B4_0 Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B4_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE4 Segment 4 interrupt enable. (This bit field is meaningful only when IE4_EN is set) 13 2 read-write IE4_0 Generate interrupt on Done0 when segment 4 finish. 0 IE4_1 Generate interrupt on Done1 when segment 4 finish. 0x1 IE4_2 Generate interrupt on Done2 when segment 4 finish. 0x2 IE4_3 Generate interrupt on Done3 when segment 4 finish. 0x3 IE4_EN IRQ enable of segment 4. 15 1 read-write IE4_EN_0 Interrupt DONE disabled. 0 IE4_EN_1 Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4. 0x1 CSEL5 ADC hardware trigger command selection 16 4 read-write CSEL5_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL5_1 ADC CMD1 selected. 0x1 CSEL5_2 ADC CMD2 selected. 0x2 CSEL5_3 ADC CMD3 selected. 0x3 CSEL5_4 ADC CMD4 selected. 0x4 CSEL5_5 ADC CMD5 selected. 0x5 CSEL5_6 ADC CMD6 selected. 0x6 CSEL5_7 ADC CMD7 selected. 0x7 CSEL5_8 ADC CMD8 selected. 0x8 CSEL5_9 ADC CMD9 selected. 0x9 CSEL5_10 ADC CMD10 selected. 0xA CSEL5_11 ADC CMD11 selected. 0xB CSEL5_12 ADC CMD12 selected. 0xC CSEL5_13 ADC CMD13 selected. 0xD CSEL5_14 ADC CMD14 selected. 0xE CSEL5_15 ADC CMD15 selected. 0xF HWTS5 Segment 5 HWTS ADC hardware trigger selection 20 8 read-write HWTS5_0 no trigger selected 0 HWTS5_1 ADC TRIG0 selected 0x1 HWTS5_2 ADC TRIG1 selected 0x2 HWTS5_4 ADC TRIG2 selected 0x4 HWTS5_8 ADC TRIG3 selected 0x8 HWTS5_16 ADC TRIG4 selected 0x10 HWTS5_32 ADC TRIG5 selected 0x20 HWTS5_64 ADC TRIG6 selected 0x40 HWTS5_128 ADC TRIG7 selected 0x80 B2B5 Segment 5 B2B 28 1 read-write B2B5_0 Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B5_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE5 Segment 5 interrupt enable. (This bit field is meaningful only when IE5_EN is set) 29 2 read-write IE5_0 Generate interrupt on Done0 when segment 5 finish. 0 IE5_1 Generate interrupt on Done1 when segment 5 finish. 0x1 IE5_2 Generate interrupt on Done2 when segment 5 finish. 0x2 IE5_3 Generate interrupt on Done3 when segment 5 finish. 0x3 IE5_EN IRQ enable of segment 5. 31 1 read-write IE5_EN_0 Interrupt DONE disabled. 0 IE5_EN_1 Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5. 0x1 TRIG0_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0x24 32 read-write 0 0xFFFFFFFF CSEL6 ADC hardware trigger command selection 0 4 read-write CSEL6_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL6_1 ADC CMD1 selected. 0x1 CSEL6_2 ADC CMD2 selected. 0x2 CSEL6_3 ADC CMD3 selected. 0x3 CSEL6_4 ADC CMD4 selected. 0x4 CSEL6_5 ADC CMD5 selected. 0x5 CSEL6_6 ADC CMD6 selected. 0x6 CSEL6_7 ADC CMD7 selected. 0x7 CSEL6_8 ADC CMD8 selected. 0x8 CSEL6_9 ADC CMD9 selected. 0x9 CSEL6_10 ADC CMD10 selected. 0xA CSEL6_11 ADC CMD11 selected. 0xB CSEL6_12 ADC CMD12 selected. 0xC CSEL6_13 ADC CMD13 selected. 0xD CSEL6_14 ADC CMD14 selected. 0xE CSEL6_15 ADC CMD15 selected. 0xF HWTS6 Segment 6 HWTS ADC hardware trigger selection 4 8 read-write HWTS6_0 no trigger selected 0 HWTS6_1 ADC TRIG0 selected 0x1 HWTS6_2 ADC TRIG1 selected 0x2 HWTS6_4 ADC TRIG2 selected 0x4 HWTS6_8 ADC TRIG3 selected 0x8 HWTS6_16 ADC TRIG4 selected 0x10 HWTS6_32 ADC TRIG5 selected 0x20 HWTS6_64 ADC TRIG6 selected 0x40 HWTS6_128 ADC TRIG7 selected 0x80 B2B6 Segment 6 B2B 12 1 read-write B2B6_0 Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B6_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE6 Segment 6 interrupt enable. (This bit field is meaningful only when IE6_EN is set) 13 2 read-write IE6_0 Generate interrupt on Done0 when segment 6 finish. 0 IE6_1 Generate interrupt on Done1 when segment 6 finish. 0x1 IE6_2 Generate interrupt on Done2 when segment 6 finish. 0x2 IE6_3 Generate interrupt on Done3 when segment 6 finish. 0x3 IE6_EN IRQ enable of segment 6. 15 1 read-write IE6_EN_0 Interrupt DONE disabled. 0 IE6_EN_1 Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6. 0x1 CSEL7 ADC hardware trigger command selection 16 4 read-write CSEL7_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL7_1 ADC CMD1 selected. 0x1 CSEL7_2 ADC CMD2 selected. 0x2 CSEL7_3 ADC CMD3 selected. 0x3 CSEL7_4 ADC CMD4 selected. 0x4 CSEL7_5 ADC CMD5 selected. 0x5 CSEL7_6 ADC CMD6 selected. 0x6 CSEL7_7 ADC CMD7 selected. 0x7 CSEL7_8 ADC CMD8 selected. 0x8 CSEL7_9 ADC CMD9 selected. 0x9 CSEL7_10 ADC CMD10 selected. 0xA CSEL7_11 ADC CMD11 selected. 0xB CSEL7_12 ADC CMD12 selected. 0xC CSEL7_13 ADC CMD13 selected. 0xD CSEL7_14 ADC CMD14 selected. 0xE CSEL7_15 ADC CMD15 selected. 0xF HWTS7 Segment 7 HWTS ADC hardware trigger selection 20 8 read-write HWTS7_0 no trigger selected 0 HWTS7_1 ADC TRIG0 selected 0x1 HWTS7_2 ADC TRIG1 selected 0x2 HWTS7_4 ADC TRIG2 selected 0x4 HWTS7_8 ADC TRIG3 selected 0x8 HWTS7_16 ADC TRIG4 selected 0x10 HWTS7_32 ADC TRIG5 selected 0x20 HWTS7_64 ADC TRIG6 selected 0x40 HWTS7_128 ADC TRIG7 selected 0x80 B2B7 Segment 7 B2B 28 1 read-write B2B7_0 Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B7_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE7 Segment 7 interrupt enable. (This bit field is meaningful only when IE7_EN is set) 29 2 read-write IE7_0 Generate interrupt on Done0 when segment 7 finish. 0 IE7_1 Generate interrupt on Done1 when segment 7 finish. 0x1 IE7_2 Generate interrupt on Done2 when segment 7 finish. 0x2 IE7_3 Generate interrupt on Done3 when segment 7 finish. 0x3 IE7_EN IRQ enable of segment 7. 31 1 read-write IE7_EN_0 Interrupt DONE disabled. 0 IE7_EN_1 Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7. 0x1 TRIG0_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0x28 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA1 Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG0_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0x2C 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA3 Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG0_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0x30 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA5 Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG0_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0x34 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA7 Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG1_CTRL ETC_TRIG Control Register 0x38 32 read-write 0 0xFFFFFFFF SW_TRIG Software trigger. This field is self-clearing. 0 1 read-write SW_TRIG_0 No software trigger event generated. 0 SW_TRIG_1 Software trigger event generated. 0x1 TRIG_MODE Trigger mode selection. 4 1 read-write TRIG_MODE_0 Hardware trigger. The softerware trigger will be ignored. 0 TRIG_MODE_1 Software trigger. The hardware trigger will be ignored. 0x1 TRIG_CHAIN The number of segments inside the trigger chain of TRIGa. 8 3 read-write TRIG_CHAIN_0 Trigger chain length is 1 0 TRIG_CHAIN_1 Trigger chain length is 2 0x1 TRIG_CHAIN_2 Trigger chain length is 3 0x2 TRIG_CHAIN_3 Trigger chain length is 4 0x3 TRIG_CHAIN_4 Trigger chain length is 5 0x4 TRIG_CHAIN_5 Trigger chain length is 6 0x5 TRIG_CHAIN_6 Trigger chain length is 7 0x6 TRIG_CHAIN_7 Trigger chain length is 8 0x7 TRIG_PRIORITY External trigger priority, 7 is highest priority, while 0 is lowest 12 3 read-write SYNC_MODE Trigger synchronization mode selection 16 1 read-write SYNC_MODE_0 Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. 0 SYNC_MODE_1 Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. 0x1 CHAINx_DONE Segment x done detection 24 8 read-write oneToClear CHAINx_DONE_0 segment x done not detected. 0 CHAINx_DONE_1 segment x done detected. 0x1 TRIG1_COUNTER ETC_TRIG Counter Register 0x3C 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG1_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0x40 32 read-write 0 0xFFFFFFFF CSEL0 ADC hardware trigger command selection 0 4 read-write CSEL0_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL0_1 ADC CMD1 selected. 0x1 CSEL0_2 ADC CMD2 selected. 0x2 CSEL0_3 ADC CMD3 selected. 0x3 CSEL0_4 ADC CMD4 selected. 0x4 CSEL0_5 ADC CMD5 selected. 0x5 CSEL0_6 ADC CMD6 selected. 0x6 CSEL0_7 ADC CMD7 selected. 0x7 CSEL0_8 ADC CMD8 selected. 0x8 CSEL0_9 ADC CMD9 selected. 0x9 CSEL0_10 ADC CMD10 selected. 0xA CSEL0_11 ADC CMD11 selected. 0xB CSEL0_12 ADC CMD12 selected. 0xC CSEL0_13 ADC CMD13 selected. 0xD CSEL0_14 ADC CMD14 selected. 0xE CSEL0_15 ADC CMD15 selected. 0xF HWTS0 Segment 0 HWTS ADC hardware trigger selection 4 8 read-write HWTS0_0 no trigger selected 0 HWTS0_1 ADC TRIG0 selected 0x1 HWTS0_2 ADC TRIG1 selected 0x2 HWTS0_4 ADC TRIG2 selected 0x4 HWTS0_8 ADC TRIG3 selected 0x8 HWTS0_16 ADC TRIG4 selected 0x10 HWTS0_32 ADC TRIG5 selected 0x20 HWTS0_64 ADC TRIG6 selected 0x40 HWTS0_128 ADC TRIG7 selected 0x80 B2B0 Segment 0 B2B 12 1 read-write B2B0_0 Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B0_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE0 Segment 0 interrupt enable. (This bit field is meaningful only when IE0_EN is set) 13 2 read-write IE0_0 Generate interrupt on Done0 when segment 0 finish. 0 IE0_1 Generate interrupt on Done1 when segment 0 finish. 0x1 IE0_2 Generate interrupt on Done2 when segment 0 finish. 0x2 IE0_3 Generate interrupt on Done3 when segment 0 finish. 0x3 IE0_EN IRQ enable of segment 0. 15 1 read-write IE0_EN_0 Interrupt DONE disabled. 0 IE0_EN_1 Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0. 0x1 CSEL1 ADC hardware trigger command selection 16 4 read-write CSEL1_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL1_1 ADC CMD1 selected. 0x1 CSEL1_2 ADC CMD2 selected. 0x2 CSEL1_3 ADC CMD3 selected. 0x3 CSEL1_4 ADC CMD4 selected. 0x4 CSEL1_5 ADC CMD5 selected. 0x5 CSEL1_6 ADC CMD6 selected. 0x6 CSEL1_7 ADC CMD7 selected. 0x7 CSEL1_8 ADC CMD8 selected. 0x8 CSEL1_9 ADC CMD9 selected. 0x9 CSEL1_10 ADC CMD10 selected. 0xA CSEL1_11 ADC CMD11 selected. 0xB CSEL1_12 ADC CMD12 selected. 0xC CSEL1_13 ADC CMD13 selected. 0xD CSEL1_14 ADC CMD14 selected. 0xE CSEL1_15 ADC CMD15 selected. 0xF HWTS1 Segment 1 HWTS ADC hardware trigger selection 20 8 read-write HWTS1_0 no trigger selected 0 HWTS1_1 ADC TRIG0 selected 0x1 HWTS1_2 ADC TRIG1 selected 0x2 HWTS1_4 ADC TRIG2 selected 0x4 HWTS1_8 ADC TRIG3 selected 0x8 HWTS1_16 ADC TRIG4 selected 0x10 HWTS1_32 ADC TRIG5 selected 0x20 HWTS1_64 ADC TRIG6 selected 0x40 HWTS1_128 ADC TRIG7 selected 0x80 B2B1 Segment 1 B2B 28 1 read-write B2B1_0 Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B1_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE1 Segment 1 interrupt enable. (This bit field is meaningful only when IE1_EN is set) 29 2 read-write IE1_0 Generate interrupt on Done0 when Segment 1 finish. 0 IE1_1 Generate interrupt on Done1 when Segment 1 finish. 0x1 IE1_2 Generate interrupt on Done2 when Segment 1 finish. 0x2 IE1_3 Generate interrupt on Done3 when Segment 1 finish. 0x3 IE1_EN IRQ enable of segment 1. 31 1 read-write IE1_EN_0 Interrupt DONE disabled. 0 IE1_EN_1 Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1. 0x1 TRIG1_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0x44 32 read-write 0 0xFFFFFFFF CSEL2 ADC hardware trigger command selection 0 4 read-write CSEL2_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL2_1 ADC CMD1 selected. 0x1 CSEL2_2 ADC CMD2 selected. 0x2 CSEL2_3 ADC CMD3 selected. 0x3 CSEL2_4 ADC CMD4 selected. 0x4 CSEL2_5 ADC CMD5 selected. 0x5 CSEL2_6 ADC CMD6 selected. 0x6 CSEL2_7 ADC CMD7 selected. 0x7 CSEL2_8 ADC CMD8 selected. 0x8 CSEL2_9 ADC CMD9 selected. 0x9 CSEL2_10 ADC CMD10 selected. 0xA CSEL2_11 ADC CMD11 selected. 0xB CSEL2_12 ADC CMD12 selected. 0xC CSEL2_13 ADC CMD13 selected. 0xD CSEL2_14 ADC CMD14 selected. 0xE CSEL2_15 ADC CMD15 selected. 0xF HWTS2 Segment 2 HWTS ADC hardware trigger selection 4 8 read-write HWTS2_0 no trigger selected 0 HWTS2_1 ADC TRIG0 selected 0x1 HWTS2_2 ADC TRIG1 selected 0x2 HWTS2_4 ADC TRIG2 selected 0x4 HWTS2_8 ADC TRIG3 selected 0x8 HWTS2_16 ADC TRIG4 selected 0x10 HWTS2_32 ADC TRIG5 selected 0x20 HWTS2_64 ADC TRIG6 selected 0x40 HWTS2_128 ADC TRIG7 selected 0x80 B2B2 Segment 2 B2B 12 1 read-write B2B2_0 Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B2_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE2 Segment 2 interrupt enable. (This bit field is meaningful only when IE2_EN is set) 13 2 read-write IE2_0 Generate interrupt on Done0 when segment 2 finish. 0 IE2_1 Generate interrupt on Done1 when segment 2 finish. 0x1 IE2_2 Generate interrupt on Done2 when segment 2 finish. 0x2 IE2_3 Generate interrupt on Done3 when segment 2 finish. 0x3 IE2_EN IRQ enable of segment 2. 15 1 read-write IE2_EN_0 Interrupt DONE disabled. 0 IE2_EN_1 Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2. 0x1 CSEL3 ADC hardware trigger command selection 16 4 read-write CSEL3_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL3_1 ADC CMD1 selected. 0x1 CSEL3_2 ADC CMD2 selected. 0x2 CSEL3_3 ADC CMD3 selected. 0x3 CSEL3_4 ADC CMD4 selected. 0x4 CSEL3_5 ADC CMD5 selected. 0x5 CSEL3_6 ADC CMD6 selected. 0x6 CSEL3_7 ADC CMD7 selected. 0x7 CSEL3_8 ADC CMD8 selected. 0x8 CSEL3_9 ADC CMD9 selected. 0x9 CSEL3_10 ADC CMD10 selected. 0xA CSEL3_11 ADC CMD11 selected. 0xB CSEL3_12 ADC CMD12 selected. 0xC CSEL3_13 ADC CMD13 selected. 0xD CSEL3_14 ADC CMD14 selected. 0xE CSEL3_15 ADC CMD15 selected. 0xF HWTS3 Segment 3 HWTS ADC hardware trigger selection 20 8 read-write HWTS3_0 no trigger selected 0 HWTS3_1 ADC TRIG0 selected 0x1 HWTS3_2 ADC TRIG1 selected 0x2 HWTS3_4 ADC TRIG2 selected 0x4 HWTS3_8 ADC TRIG3 selected 0x8 HWTS3_16 ADC TRIG4 selected 0x10 HWTS3_32 ADC TRIG5 selected 0x20 HWTS3_64 ADC TRIG6 selected 0x40 HWTS3_128 ADC TRIG7 selected 0x80 B2B3 Segment 3 B2B 28 1 read-write B2B3_0 Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B3_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE3 Segment 3 interrupt enable. (This bit field is meaningful only when IE3_EN is set) 29 2 read-write IE3_0 Generate interrupt on Done0 when segment 3 finish. 0 IE3_1 Generate interrupt on Done1 when segment 3 finish. 0x1 IE3_2 Generate interrupt on Done2 when segment 3 finish. 0x2 IE3_3 Generate interrupt on Done3 when segment 3 finish. 0x3 IE3_EN IRQ enable of segment 3. 31 1 read-write IE3_EN_0 Interrupt DONE disabled. 0 IE3_EN_1 Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3. 0x1 TRIG1_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0x48 32 read-write 0 0xFFFFFFFF CSEL4 ADC hardware trigger command selection 0 4 read-write CSEL4_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL4_1 ADC CMD1 selected. 0x1 CSEL4_2 ADC CMD2 selected. 0x2 CSEL4_3 ADC CMD3 selected. 0x3 CSEL4_4 ADC CMD4 selected. 0x4 CSEL4_5 ADC CMD5 selected. 0x5 CSEL4_6 ADC CMD6 selected. 0x6 CSEL4_7 ADC CMD7 selected. 0x7 CSEL4_8 ADC CMD8 selected. 0x8 CSEL4_9 ADC CMD9 selected. 0x9 CSEL4_10 ADC CMD10 selected. 0xA CSEL4_11 ADC CMD11 selected. 0xB CSEL4_12 ADC CMD12 selected. 0xC CSEL4_13 ADC CMD13 selected. 0xD CSEL4_14 ADC CMD14 selected. 0xE CSEL4_15 ADC CMD15 selected. 0xF HWTS4 Segment 4 HWTS ADC hardware trigger selection 4 8 read-write HWTS4_0 no trigger selected 0 HWTS4_1 ADC TRIG0 selected 0x1 HWTS4_2 ADC TRIG1 selected 0x2 HWTS4_4 ADC TRIG2 selected 0x4 HWTS4_8 ADC TRIG3 selected 0x8 HWTS4_16 ADC TRIG4 selected 0x10 HWTS4_32 ADC TRIG5 selected 0x20 HWTS4_64 ADC TRIG6 selected 0x40 HWTS4_128 ADC TRIG7 selected 0x80 B2B4 Segment 4 B2B 12 1 read-write B2B4_0 Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B4_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE4 Segment 4 interrupt enable. (This bit field is meaningful only when IE4_EN is set) 13 2 read-write IE4_0 Generate interrupt on Done0 when segment 4 finish. 0 IE4_1 Generate interrupt on Done1 when segment 4 finish. 0x1 IE4_2 Generate interrupt on Done2 when segment 4 finish. 0x2 IE4_3 Generate interrupt on Done3 when segment 4 finish. 0x3 IE4_EN IRQ enable of segment 4. 15 1 read-write IE4_EN_0 Interrupt DONE disabled. 0 IE4_EN_1 Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4. 0x1 CSEL5 ADC hardware trigger command selection 16 4 read-write CSEL5_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL5_1 ADC CMD1 selected. 0x1 CSEL5_2 ADC CMD2 selected. 0x2 CSEL5_3 ADC CMD3 selected. 0x3 CSEL5_4 ADC CMD4 selected. 0x4 CSEL5_5 ADC CMD5 selected. 0x5 CSEL5_6 ADC CMD6 selected. 0x6 CSEL5_7 ADC CMD7 selected. 0x7 CSEL5_8 ADC CMD8 selected. 0x8 CSEL5_9 ADC CMD9 selected. 0x9 CSEL5_10 ADC CMD10 selected. 0xA CSEL5_11 ADC CMD11 selected. 0xB CSEL5_12 ADC CMD12 selected. 0xC CSEL5_13 ADC CMD13 selected. 0xD CSEL5_14 ADC CMD14 selected. 0xE CSEL5_15 ADC CMD15 selected. 0xF HWTS5 Segment 5 HWTS ADC hardware trigger selection 20 8 read-write HWTS5_0 no trigger selected 0 HWTS5_1 ADC TRIG0 selected 0x1 HWTS5_2 ADC TRIG1 selected 0x2 HWTS5_4 ADC TRIG2 selected 0x4 HWTS5_8 ADC TRIG3 selected 0x8 HWTS5_16 ADC TRIG4 selected 0x10 HWTS5_32 ADC TRIG5 selected 0x20 HWTS5_64 ADC TRIG6 selected 0x40 HWTS5_128 ADC TRIG7 selected 0x80 B2B5 Segment 5 B2B 28 1 read-write B2B5_0 Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B5_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE5 Segment 5 interrupt enable. (This bit field is meaningful only when IE5_EN is set) 29 2 read-write IE5_0 Generate interrupt on Done0 when segment 5 finish. 0 IE5_1 Generate interrupt on Done1 when segment 5 finish. 0x1 IE5_2 Generate interrupt on Done2 when segment 5 finish. 0x2 IE5_3 Generate interrupt on Done3 when segment 5 finish. 0x3 IE5_EN IRQ enable of segment 5. 31 1 read-write IE5_EN_0 Interrupt DONE disabled. 0 IE5_EN_1 Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5. 0x1 TRIG1_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0x4C 32 read-write 0 0xFFFFFFFF CSEL6 ADC hardware trigger command selection 0 4 read-write CSEL6_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL6_1 ADC CMD1 selected. 0x1 CSEL6_2 ADC CMD2 selected. 0x2 CSEL6_3 ADC CMD3 selected. 0x3 CSEL6_4 ADC CMD4 selected. 0x4 CSEL6_5 ADC CMD5 selected. 0x5 CSEL6_6 ADC CMD6 selected. 0x6 CSEL6_7 ADC CMD7 selected. 0x7 CSEL6_8 ADC CMD8 selected. 0x8 CSEL6_9 ADC CMD9 selected. 0x9 CSEL6_10 ADC CMD10 selected. 0xA CSEL6_11 ADC CMD11 selected. 0xB CSEL6_12 ADC CMD12 selected. 0xC CSEL6_13 ADC CMD13 selected. 0xD CSEL6_14 ADC CMD14 selected. 0xE CSEL6_15 ADC CMD15 selected. 0xF HWTS6 Segment 6 HWTS ADC hardware trigger selection 4 8 read-write HWTS6_0 no trigger selected 0 HWTS6_1 ADC TRIG0 selected 0x1 HWTS6_2 ADC TRIG1 selected 0x2 HWTS6_4 ADC TRIG2 selected 0x4 HWTS6_8 ADC TRIG3 selected 0x8 HWTS6_16 ADC TRIG4 selected 0x10 HWTS6_32 ADC TRIG5 selected 0x20 HWTS6_64 ADC TRIG6 selected 0x40 HWTS6_128 ADC TRIG7 selected 0x80 B2B6 Segment 6 B2B 12 1 read-write B2B6_0 Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B6_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE6 Segment 6 interrupt enable. (This bit field is meaningful only when IE6_EN is set) 13 2 read-write IE6_0 Generate interrupt on Done0 when segment 6 finish. 0 IE6_1 Generate interrupt on Done1 when segment 6 finish. 0x1 IE6_2 Generate interrupt on Done2 when segment 6 finish. 0x2 IE6_3 Generate interrupt on Done3 when segment 6 finish. 0x3 IE6_EN IRQ enable of segment 6. 15 1 read-write IE6_EN_0 Interrupt DONE disabled. 0 IE6_EN_1 Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6. 0x1 CSEL7 ADC hardware trigger command selection 16 4 read-write CSEL7_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL7_1 ADC CMD1 selected. 0x1 CSEL7_2 ADC CMD2 selected. 0x2 CSEL7_3 ADC CMD3 selected. 0x3 CSEL7_4 ADC CMD4 selected. 0x4 CSEL7_5 ADC CMD5 selected. 0x5 CSEL7_6 ADC CMD6 selected. 0x6 CSEL7_7 ADC CMD7 selected. 0x7 CSEL7_8 ADC CMD8 selected. 0x8 CSEL7_9 ADC CMD9 selected. 0x9 CSEL7_10 ADC CMD10 selected. 0xA CSEL7_11 ADC CMD11 selected. 0xB CSEL7_12 ADC CMD12 selected. 0xC CSEL7_13 ADC CMD13 selected. 0xD CSEL7_14 ADC CMD14 selected. 0xE CSEL7_15 ADC CMD15 selected. 0xF HWTS7 Segment 7 HWTS ADC hardware trigger selection 20 8 read-write HWTS7_0 no trigger selected 0 HWTS7_1 ADC TRIG0 selected 0x1 HWTS7_2 ADC TRIG1 selected 0x2 HWTS7_4 ADC TRIG2 selected 0x4 HWTS7_8 ADC TRIG3 selected 0x8 HWTS7_16 ADC TRIG4 selected 0x10 HWTS7_32 ADC TRIG5 selected 0x20 HWTS7_64 ADC TRIG6 selected 0x40 HWTS7_128 ADC TRIG7 selected 0x80 B2B7 Segment 7 B2B 28 1 read-write B2B7_0 Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B7_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE7 Segment 7 interrupt enable. (This bit field is meaningful only when IE7_EN is set) 29 2 read-write IE7_0 Generate interrupt on Done0 when segment 7 finish. 0 IE7_1 Generate interrupt on Done1 when segment 7 finish. 0x1 IE7_2 Generate interrupt on Done2 when segment 7 finish. 0x2 IE7_3 Generate interrupt on Done3 when segment 7 finish. 0x3 IE7_EN IRQ enable of segment 7. 31 1 read-write IE7_EN_0 Interrupt DONE disabled. 0 IE7_EN_1 Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7. 0x1 TRIG1_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0x50 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA1 Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG1_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0x54 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA3 Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG1_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0x58 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA5 Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG1_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0x5C 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA7 Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG2_CTRL ETC_TRIG Control Register 0x60 32 read-write 0 0xFFFFFFFF SW_TRIG Software trigger. This field is self-clearing. 0 1 read-write SW_TRIG_0 No software trigger event generated. 0 SW_TRIG_1 Software trigger event generated. 0x1 TRIG_MODE Trigger mode selection. 4 1 read-write TRIG_MODE_0 Hardware trigger. The softerware trigger will be ignored. 0 TRIG_MODE_1 Software trigger. The hardware trigger will be ignored. 0x1 TRIG_CHAIN The number of segments inside the trigger chain of TRIGa. 8 3 read-write TRIG_CHAIN_0 Trigger chain length is 1 0 TRIG_CHAIN_1 Trigger chain length is 2 0x1 TRIG_CHAIN_2 Trigger chain length is 3 0x2 TRIG_CHAIN_3 Trigger chain length is 4 0x3 TRIG_CHAIN_4 Trigger chain length is 5 0x4 TRIG_CHAIN_5 Trigger chain length is 6 0x5 TRIG_CHAIN_6 Trigger chain length is 7 0x6 TRIG_CHAIN_7 Trigger chain length is 8 0x7 TRIG_PRIORITY External trigger priority, 7 is highest priority, while 0 is lowest 12 3 read-write SYNC_MODE Trigger synchronization mode selection 16 1 read-write SYNC_MODE_0 Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. 0 SYNC_MODE_1 Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. 0x1 CHAINx_DONE Segment x done detection 24 8 read-write oneToClear CHAINx_DONE_0 segment x done not detected. 0 CHAINx_DONE_1 segment x done detected. 0x1 TRIG2_COUNTER ETC_TRIG Counter Register 0x64 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG2_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0x68 32 read-write 0 0xFFFFFFFF CSEL0 ADC hardware trigger command selection 0 4 read-write CSEL0_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL0_1 ADC CMD1 selected. 0x1 CSEL0_2 ADC CMD2 selected. 0x2 CSEL0_3 ADC CMD3 selected. 0x3 CSEL0_4 ADC CMD4 selected. 0x4 CSEL0_5 ADC CMD5 selected. 0x5 CSEL0_6 ADC CMD6 selected. 0x6 CSEL0_7 ADC CMD7 selected. 0x7 CSEL0_8 ADC CMD8 selected. 0x8 CSEL0_9 ADC CMD9 selected. 0x9 CSEL0_10 ADC CMD10 selected. 0xA CSEL0_11 ADC CMD11 selected. 0xB CSEL0_12 ADC CMD12 selected. 0xC CSEL0_13 ADC CMD13 selected. 0xD CSEL0_14 ADC CMD14 selected. 0xE CSEL0_15 ADC CMD15 selected. 0xF HWTS0 Segment 0 HWTS ADC hardware trigger selection 4 8 read-write HWTS0_0 no trigger selected 0 HWTS0_1 ADC TRIG0 selected 0x1 HWTS0_2 ADC TRIG1 selected 0x2 HWTS0_4 ADC TRIG2 selected 0x4 HWTS0_8 ADC TRIG3 selected 0x8 HWTS0_16 ADC TRIG4 selected 0x10 HWTS0_32 ADC TRIG5 selected 0x20 HWTS0_64 ADC TRIG6 selected 0x40 HWTS0_128 ADC TRIG7 selected 0x80 B2B0 Segment 0 B2B 12 1 read-write B2B0_0 Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B0_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE0 Segment 0 interrupt enable. (This bit field is meaningful only when IE0_EN is set) 13 2 read-write IE0_0 Generate interrupt on Done0 when segment 0 finish. 0 IE0_1 Generate interrupt on Done1 when segment 0 finish. 0x1 IE0_2 Generate interrupt on Done2 when segment 0 finish. 0x2 IE0_3 Generate interrupt on Done3 when segment 0 finish. 0x3 IE0_EN IRQ enable of segment 0. 15 1 read-write IE0_EN_0 Interrupt DONE disabled. 0 IE0_EN_1 Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0. 0x1 CSEL1 ADC hardware trigger command selection 16 4 read-write CSEL1_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL1_1 ADC CMD1 selected. 0x1 CSEL1_2 ADC CMD2 selected. 0x2 CSEL1_3 ADC CMD3 selected. 0x3 CSEL1_4 ADC CMD4 selected. 0x4 CSEL1_5 ADC CMD5 selected. 0x5 CSEL1_6 ADC CMD6 selected. 0x6 CSEL1_7 ADC CMD7 selected. 0x7 CSEL1_8 ADC CMD8 selected. 0x8 CSEL1_9 ADC CMD9 selected. 0x9 CSEL1_10 ADC CMD10 selected. 0xA CSEL1_11 ADC CMD11 selected. 0xB CSEL1_12 ADC CMD12 selected. 0xC CSEL1_13 ADC CMD13 selected. 0xD CSEL1_14 ADC CMD14 selected. 0xE CSEL1_15 ADC CMD15 selected. 0xF HWTS1 Segment 1 HWTS ADC hardware trigger selection 20 8 read-write HWTS1_0 no trigger selected 0 HWTS1_1 ADC TRIG0 selected 0x1 HWTS1_2 ADC TRIG1 selected 0x2 HWTS1_4 ADC TRIG2 selected 0x4 HWTS1_8 ADC TRIG3 selected 0x8 HWTS1_16 ADC TRIG4 selected 0x10 HWTS1_32 ADC TRIG5 selected 0x20 HWTS1_64 ADC TRIG6 selected 0x40 HWTS1_128 ADC TRIG7 selected 0x80 B2B1 Segment 1 B2B 28 1 read-write B2B1_0 Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B1_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE1 Segment 1 interrupt enable. (This bit field is meaningful only when IE1_EN is set) 29 2 read-write IE1_0 Generate interrupt on Done0 when Segment 1 finish. 0 IE1_1 Generate interrupt on Done1 when Segment 1 finish. 0x1 IE1_2 Generate interrupt on Done2 when Segment 1 finish. 0x2 IE1_3 Generate interrupt on Done3 when Segment 1 finish. 0x3 IE1_EN IRQ enable of segment 1. 31 1 read-write IE1_EN_0 Interrupt DONE disabled. 0 IE1_EN_1 Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1. 0x1 TRIG2_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0x6C 32 read-write 0 0xFFFFFFFF CSEL2 ADC hardware trigger command selection 0 4 read-write CSEL2_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL2_1 ADC CMD1 selected. 0x1 CSEL2_2 ADC CMD2 selected. 0x2 CSEL2_3 ADC CMD3 selected. 0x3 CSEL2_4 ADC CMD4 selected. 0x4 CSEL2_5 ADC CMD5 selected. 0x5 CSEL2_6 ADC CMD6 selected. 0x6 CSEL2_7 ADC CMD7 selected. 0x7 CSEL2_8 ADC CMD8 selected. 0x8 CSEL2_9 ADC CMD9 selected. 0x9 CSEL2_10 ADC CMD10 selected. 0xA CSEL2_11 ADC CMD11 selected. 0xB CSEL2_12 ADC CMD12 selected. 0xC CSEL2_13 ADC CMD13 selected. 0xD CSEL2_14 ADC CMD14 selected. 0xE CSEL2_15 ADC CMD15 selected. 0xF HWTS2 Segment 2 HWTS ADC hardware trigger selection 4 8 read-write HWTS2_0 no trigger selected 0 HWTS2_1 ADC TRIG0 selected 0x1 HWTS2_2 ADC TRIG1 selected 0x2 HWTS2_4 ADC TRIG2 selected 0x4 HWTS2_8 ADC TRIG3 selected 0x8 HWTS2_16 ADC TRIG4 selected 0x10 HWTS2_32 ADC TRIG5 selected 0x20 HWTS2_64 ADC TRIG6 selected 0x40 HWTS2_128 ADC TRIG7 selected 0x80 B2B2 Segment 2 B2B 12 1 read-write B2B2_0 Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B2_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE2 Segment 2 interrupt enable. (This bit field is meaningful only when IE2_EN is set) 13 2 read-write IE2_0 Generate interrupt on Done0 when segment 2 finish. 0 IE2_1 Generate interrupt on Done1 when segment 2 finish. 0x1 IE2_2 Generate interrupt on Done2 when segment 2 finish. 0x2 IE2_3 Generate interrupt on Done3 when segment 2 finish. 0x3 IE2_EN IRQ enable of segment 2. 15 1 read-write IE2_EN_0 Interrupt DONE disabled. 0 IE2_EN_1 Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2. 0x1 CSEL3 ADC hardware trigger command selection 16 4 read-write CSEL3_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL3_1 ADC CMD1 selected. 0x1 CSEL3_2 ADC CMD2 selected. 0x2 CSEL3_3 ADC CMD3 selected. 0x3 CSEL3_4 ADC CMD4 selected. 0x4 CSEL3_5 ADC CMD5 selected. 0x5 CSEL3_6 ADC CMD6 selected. 0x6 CSEL3_7 ADC CMD7 selected. 0x7 CSEL3_8 ADC CMD8 selected. 0x8 CSEL3_9 ADC CMD9 selected. 0x9 CSEL3_10 ADC CMD10 selected. 0xA CSEL3_11 ADC CMD11 selected. 0xB CSEL3_12 ADC CMD12 selected. 0xC CSEL3_13 ADC CMD13 selected. 0xD CSEL3_14 ADC CMD14 selected. 0xE CSEL3_15 ADC CMD15 selected. 0xF HWTS3 Segment 3 HWTS ADC hardware trigger selection 20 8 read-write HWTS3_0 no trigger selected 0 HWTS3_1 ADC TRIG0 selected 0x1 HWTS3_2 ADC TRIG1 selected 0x2 HWTS3_4 ADC TRIG2 selected 0x4 HWTS3_8 ADC TRIG3 selected 0x8 HWTS3_16 ADC TRIG4 selected 0x10 HWTS3_32 ADC TRIG5 selected 0x20 HWTS3_64 ADC TRIG6 selected 0x40 HWTS3_128 ADC TRIG7 selected 0x80 B2B3 Segment 3 B2B 28 1 read-write B2B3_0 Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B3_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE3 Segment 3 interrupt enable. (This bit field is meaningful only when IE3_EN is set) 29 2 read-write IE3_0 Generate interrupt on Done0 when segment 3 finish. 0 IE3_1 Generate interrupt on Done1 when segment 3 finish. 0x1 IE3_2 Generate interrupt on Done2 when segment 3 finish. 0x2 IE3_3 Generate interrupt on Done3 when segment 3 finish. 0x3 IE3_EN IRQ enable of segment 3. 31 1 read-write IE3_EN_0 Interrupt DONE disabled. 0 IE3_EN_1 Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3. 0x1 TRIG2_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0x70 32 read-write 0 0xFFFFFFFF CSEL4 ADC hardware trigger command selection 0 4 read-write CSEL4_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL4_1 ADC CMD1 selected. 0x1 CSEL4_2 ADC CMD2 selected. 0x2 CSEL4_3 ADC CMD3 selected. 0x3 CSEL4_4 ADC CMD4 selected. 0x4 CSEL4_5 ADC CMD5 selected. 0x5 CSEL4_6 ADC CMD6 selected. 0x6 CSEL4_7 ADC CMD7 selected. 0x7 CSEL4_8 ADC CMD8 selected. 0x8 CSEL4_9 ADC CMD9 selected. 0x9 CSEL4_10 ADC CMD10 selected. 0xA CSEL4_11 ADC CMD11 selected. 0xB CSEL4_12 ADC CMD12 selected. 0xC CSEL4_13 ADC CMD13 selected. 0xD CSEL4_14 ADC CMD14 selected. 0xE CSEL4_15 ADC CMD15 selected. 0xF HWTS4 Segment 4 HWTS ADC hardware trigger selection 4 8 read-write HWTS4_0 no trigger selected 0 HWTS4_1 ADC TRIG0 selected 0x1 HWTS4_2 ADC TRIG1 selected 0x2 HWTS4_4 ADC TRIG2 selected 0x4 HWTS4_8 ADC TRIG3 selected 0x8 HWTS4_16 ADC TRIG4 selected 0x10 HWTS4_32 ADC TRIG5 selected 0x20 HWTS4_64 ADC TRIG6 selected 0x40 HWTS4_128 ADC TRIG7 selected 0x80 B2B4 Segment 4 B2B 12 1 read-write B2B4_0 Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B4_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE4 Segment 4 interrupt enable. (This bit field is meaningful only when IE4_EN is set) 13 2 read-write IE4_0 Generate interrupt on Done0 when segment 4 finish. 0 IE4_1 Generate interrupt on Done1 when segment 4 finish. 0x1 IE4_2 Generate interrupt on Done2 when segment 4 finish. 0x2 IE4_3 Generate interrupt on Done3 when segment 4 finish. 0x3 IE4_EN IRQ enable of segment 4. 15 1 read-write IE4_EN_0 Interrupt DONE disabled. 0 IE4_EN_1 Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4. 0x1 CSEL5 ADC hardware trigger command selection 16 4 read-write CSEL5_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL5_1 ADC CMD1 selected. 0x1 CSEL5_2 ADC CMD2 selected. 0x2 CSEL5_3 ADC CMD3 selected. 0x3 CSEL5_4 ADC CMD4 selected. 0x4 CSEL5_5 ADC CMD5 selected. 0x5 CSEL5_6 ADC CMD6 selected. 0x6 CSEL5_7 ADC CMD7 selected. 0x7 CSEL5_8 ADC CMD8 selected. 0x8 CSEL5_9 ADC CMD9 selected. 0x9 CSEL5_10 ADC CMD10 selected. 0xA CSEL5_11 ADC CMD11 selected. 0xB CSEL5_12 ADC CMD12 selected. 0xC CSEL5_13 ADC CMD13 selected. 0xD CSEL5_14 ADC CMD14 selected. 0xE CSEL5_15 ADC CMD15 selected. 0xF HWTS5 Segment 5 HWTS ADC hardware trigger selection 20 8 read-write HWTS5_0 no trigger selected 0 HWTS5_1 ADC TRIG0 selected 0x1 HWTS5_2 ADC TRIG1 selected 0x2 HWTS5_4 ADC TRIG2 selected 0x4 HWTS5_8 ADC TRIG3 selected 0x8 HWTS5_16 ADC TRIG4 selected 0x10 HWTS5_32 ADC TRIG5 selected 0x20 HWTS5_64 ADC TRIG6 selected 0x40 HWTS5_128 ADC TRIG7 selected 0x80 B2B5 Segment 5 B2B 28 1 read-write B2B5_0 Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B5_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE5 Segment 5 interrupt enable. (This bit field is meaningful only when IE5_EN is set) 29 2 read-write IE5_0 Generate interrupt on Done0 when segment 5 finish. 0 IE5_1 Generate interrupt on Done1 when segment 5 finish. 0x1 IE5_2 Generate interrupt on Done2 when segment 5 finish. 0x2 IE5_3 Generate interrupt on Done3 when segment 5 finish. 0x3 IE5_EN IRQ enable of segment 5. 31 1 read-write IE5_EN_0 Interrupt DONE disabled. 0 IE5_EN_1 Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5. 0x1 TRIG2_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0x74 32 read-write 0 0xFFFFFFFF CSEL6 ADC hardware trigger command selection 0 4 read-write CSEL6_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL6_1 ADC CMD1 selected. 0x1 CSEL6_2 ADC CMD2 selected. 0x2 CSEL6_3 ADC CMD3 selected. 0x3 CSEL6_4 ADC CMD4 selected. 0x4 CSEL6_5 ADC CMD5 selected. 0x5 CSEL6_6 ADC CMD6 selected. 0x6 CSEL6_7 ADC CMD7 selected. 0x7 CSEL6_8 ADC CMD8 selected. 0x8 CSEL6_9 ADC CMD9 selected. 0x9 CSEL6_10 ADC CMD10 selected. 0xA CSEL6_11 ADC CMD11 selected. 0xB CSEL6_12 ADC CMD12 selected. 0xC CSEL6_13 ADC CMD13 selected. 0xD CSEL6_14 ADC CMD14 selected. 0xE CSEL6_15 ADC CMD15 selected. 0xF HWTS6 Segment 6 HWTS ADC hardware trigger selection 4 8 read-write HWTS6_0 no trigger selected 0 HWTS6_1 ADC TRIG0 selected 0x1 HWTS6_2 ADC TRIG1 selected 0x2 HWTS6_4 ADC TRIG2 selected 0x4 HWTS6_8 ADC TRIG3 selected 0x8 HWTS6_16 ADC TRIG4 selected 0x10 HWTS6_32 ADC TRIG5 selected 0x20 HWTS6_64 ADC TRIG6 selected 0x40 HWTS6_128 ADC TRIG7 selected 0x80 B2B6 Segment 6 B2B 12 1 read-write B2B6_0 Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B6_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE6 Segment 6 interrupt enable. (This bit field is meaningful only when IE6_EN is set) 13 2 read-write IE6_0 Generate interrupt on Done0 when segment 6 finish. 0 IE6_1 Generate interrupt on Done1 when segment 6 finish. 0x1 IE6_2 Generate interrupt on Done2 when segment 6 finish. 0x2 IE6_3 Generate interrupt on Done3 when segment 6 finish. 0x3 IE6_EN IRQ enable of segment 6. 15 1 read-write IE6_EN_0 Interrupt DONE disabled. 0 IE6_EN_1 Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6. 0x1 CSEL7 ADC hardware trigger command selection 16 4 read-write CSEL7_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL7_1 ADC CMD1 selected. 0x1 CSEL7_2 ADC CMD2 selected. 0x2 CSEL7_3 ADC CMD3 selected. 0x3 CSEL7_4 ADC CMD4 selected. 0x4 CSEL7_5 ADC CMD5 selected. 0x5 CSEL7_6 ADC CMD6 selected. 0x6 CSEL7_7 ADC CMD7 selected. 0x7 CSEL7_8 ADC CMD8 selected. 0x8 CSEL7_9 ADC CMD9 selected. 0x9 CSEL7_10 ADC CMD10 selected. 0xA CSEL7_11 ADC CMD11 selected. 0xB CSEL7_12 ADC CMD12 selected. 0xC CSEL7_13 ADC CMD13 selected. 0xD CSEL7_14 ADC CMD14 selected. 0xE CSEL7_15 ADC CMD15 selected. 0xF HWTS7 Segment 7 HWTS ADC hardware trigger selection 20 8 read-write HWTS7_0 no trigger selected 0 HWTS7_1 ADC TRIG0 selected 0x1 HWTS7_2 ADC TRIG1 selected 0x2 HWTS7_4 ADC TRIG2 selected 0x4 HWTS7_8 ADC TRIG3 selected 0x8 HWTS7_16 ADC TRIG4 selected 0x10 HWTS7_32 ADC TRIG5 selected 0x20 HWTS7_64 ADC TRIG6 selected 0x40 HWTS7_128 ADC TRIG7 selected 0x80 B2B7 Segment 7 B2B 28 1 read-write B2B7_0 Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B7_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE7 Segment 7 interrupt enable. (This bit field is meaningful only when IE7_EN is set) 29 2 read-write IE7_0 Generate interrupt on Done0 when segment 7 finish. 0 IE7_1 Generate interrupt on Done1 when segment 7 finish. 0x1 IE7_2 Generate interrupt on Done2 when segment 7 finish. 0x2 IE7_3 Generate interrupt on Done3 when segment 7 finish. 0x3 IE7_EN IRQ enable of segment 7. 31 1 read-write IE7_EN_0 Interrupt DONE disabled. 0 IE7_EN_1 Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7. 0x1 TRIG2_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0x78 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA1 Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG2_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0x7C 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA3 Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG2_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0x80 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA5 Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG2_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0x84 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA7 Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG3_CTRL ETC_TRIG Control Register 0x88 32 read-write 0 0xFFFFFFFF SW_TRIG Software trigger. This field is self-clearing. 0 1 read-write SW_TRIG_0 No software trigger event generated. 0 SW_TRIG_1 Software trigger event generated. 0x1 TRIG_MODE Trigger mode selection. 4 1 read-write TRIG_MODE_0 Hardware trigger. The softerware trigger will be ignored. 0 TRIG_MODE_1 Software trigger. The hardware trigger will be ignored. 0x1 TRIG_CHAIN The number of segments inside the trigger chain of TRIGa. 8 3 read-write TRIG_CHAIN_0 Trigger chain length is 1 0 TRIG_CHAIN_1 Trigger chain length is 2 0x1 TRIG_CHAIN_2 Trigger chain length is 3 0x2 TRIG_CHAIN_3 Trigger chain length is 4 0x3 TRIG_CHAIN_4 Trigger chain length is 5 0x4 TRIG_CHAIN_5 Trigger chain length is 6 0x5 TRIG_CHAIN_6 Trigger chain length is 7 0x6 TRIG_CHAIN_7 Trigger chain length is 8 0x7 TRIG_PRIORITY External trigger priority, 7 is highest priority, while 0 is lowest 12 3 read-write SYNC_MODE Trigger synchronization mode selection 16 1 read-write SYNC_MODE_0 Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. 0 SYNC_MODE_1 Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. 0x1 CHAINx_DONE Segment x done detection 24 8 read-write oneToClear CHAINx_DONE_0 segment x done not detected. 0 CHAINx_DONE_1 segment x done detected. 0x1 TRIG3_COUNTER ETC_TRIG Counter Register 0x8C 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG3_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0x90 32 read-write 0 0xFFFFFFFF CSEL0 ADC hardware trigger command selection 0 4 read-write CSEL0_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL0_1 ADC CMD1 selected. 0x1 CSEL0_2 ADC CMD2 selected. 0x2 CSEL0_3 ADC CMD3 selected. 0x3 CSEL0_4 ADC CMD4 selected. 0x4 CSEL0_5 ADC CMD5 selected. 0x5 CSEL0_6 ADC CMD6 selected. 0x6 CSEL0_7 ADC CMD7 selected. 0x7 CSEL0_8 ADC CMD8 selected. 0x8 CSEL0_9 ADC CMD9 selected. 0x9 CSEL0_10 ADC CMD10 selected. 0xA CSEL0_11 ADC CMD11 selected. 0xB CSEL0_12 ADC CMD12 selected. 0xC CSEL0_13 ADC CMD13 selected. 0xD CSEL0_14 ADC CMD14 selected. 0xE CSEL0_15 ADC CMD15 selected. 0xF HWTS0 Segment 0 HWTS ADC hardware trigger selection 4 8 read-write HWTS0_0 no trigger selected 0 HWTS0_1 ADC TRIG0 selected 0x1 HWTS0_2 ADC TRIG1 selected 0x2 HWTS0_4 ADC TRIG2 selected 0x4 HWTS0_8 ADC TRIG3 selected 0x8 HWTS0_16 ADC TRIG4 selected 0x10 HWTS0_32 ADC TRIG5 selected 0x20 HWTS0_64 ADC TRIG6 selected 0x40 HWTS0_128 ADC TRIG7 selected 0x80 B2B0 Segment 0 B2B 12 1 read-write B2B0_0 Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B0_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE0 Segment 0 interrupt enable. (This bit field is meaningful only when IE0_EN is set) 13 2 read-write IE0_0 Generate interrupt on Done0 when segment 0 finish. 0 IE0_1 Generate interrupt on Done1 when segment 0 finish. 0x1 IE0_2 Generate interrupt on Done2 when segment 0 finish. 0x2 IE0_3 Generate interrupt on Done3 when segment 0 finish. 0x3 IE0_EN IRQ enable of segment 0. 15 1 read-write IE0_EN_0 Interrupt DONE disabled. 0 IE0_EN_1 Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0. 0x1 CSEL1 ADC hardware trigger command selection 16 4 read-write CSEL1_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL1_1 ADC CMD1 selected. 0x1 CSEL1_2 ADC CMD2 selected. 0x2 CSEL1_3 ADC CMD3 selected. 0x3 CSEL1_4 ADC CMD4 selected. 0x4 CSEL1_5 ADC CMD5 selected. 0x5 CSEL1_6 ADC CMD6 selected. 0x6 CSEL1_7 ADC CMD7 selected. 0x7 CSEL1_8 ADC CMD8 selected. 0x8 CSEL1_9 ADC CMD9 selected. 0x9 CSEL1_10 ADC CMD10 selected. 0xA CSEL1_11 ADC CMD11 selected. 0xB CSEL1_12 ADC CMD12 selected. 0xC CSEL1_13 ADC CMD13 selected. 0xD CSEL1_14 ADC CMD14 selected. 0xE CSEL1_15 ADC CMD15 selected. 0xF HWTS1 Segment 1 HWTS ADC hardware trigger selection 20 8 read-write HWTS1_0 no trigger selected 0 HWTS1_1 ADC TRIG0 selected 0x1 HWTS1_2 ADC TRIG1 selected 0x2 HWTS1_4 ADC TRIG2 selected 0x4 HWTS1_8 ADC TRIG3 selected 0x8 HWTS1_16 ADC TRIG4 selected 0x10 HWTS1_32 ADC TRIG5 selected 0x20 HWTS1_64 ADC TRIG6 selected 0x40 HWTS1_128 ADC TRIG7 selected 0x80 B2B1 Segment 1 B2B 28 1 read-write B2B1_0 Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B1_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE1 Segment 1 interrupt enable. (This bit field is meaningful only when IE1_EN is set) 29 2 read-write IE1_0 Generate interrupt on Done0 when Segment 1 finish. 0 IE1_1 Generate interrupt on Done1 when Segment 1 finish. 0x1 IE1_2 Generate interrupt on Done2 when Segment 1 finish. 0x2 IE1_3 Generate interrupt on Done3 when Segment 1 finish. 0x3 IE1_EN IRQ enable of segment 1. 31 1 read-write IE1_EN_0 Interrupt DONE disabled. 0 IE1_EN_1 Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1. 0x1 TRIG3_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0x94 32 read-write 0 0xFFFFFFFF CSEL2 ADC hardware trigger command selection 0 4 read-write CSEL2_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL2_1 ADC CMD1 selected. 0x1 CSEL2_2 ADC CMD2 selected. 0x2 CSEL2_3 ADC CMD3 selected. 0x3 CSEL2_4 ADC CMD4 selected. 0x4 CSEL2_5 ADC CMD5 selected. 0x5 CSEL2_6 ADC CMD6 selected. 0x6 CSEL2_7 ADC CMD7 selected. 0x7 CSEL2_8 ADC CMD8 selected. 0x8 CSEL2_9 ADC CMD9 selected. 0x9 CSEL2_10 ADC CMD10 selected. 0xA CSEL2_11 ADC CMD11 selected. 0xB CSEL2_12 ADC CMD12 selected. 0xC CSEL2_13 ADC CMD13 selected. 0xD CSEL2_14 ADC CMD14 selected. 0xE CSEL2_15 ADC CMD15 selected. 0xF HWTS2 Segment 2 HWTS ADC hardware trigger selection 4 8 read-write HWTS2_0 no trigger selected 0 HWTS2_1 ADC TRIG0 selected 0x1 HWTS2_2 ADC TRIG1 selected 0x2 HWTS2_4 ADC TRIG2 selected 0x4 HWTS2_8 ADC TRIG3 selected 0x8 HWTS2_16 ADC TRIG4 selected 0x10 HWTS2_32 ADC TRIG5 selected 0x20 HWTS2_64 ADC TRIG6 selected 0x40 HWTS2_128 ADC TRIG7 selected 0x80 B2B2 Segment 2 B2B 12 1 read-write B2B2_0 Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B2_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE2 Segment 2 interrupt enable. (This bit field is meaningful only when IE2_EN is set) 13 2 read-write IE2_0 Generate interrupt on Done0 when segment 2 finish. 0 IE2_1 Generate interrupt on Done1 when segment 2 finish. 0x1 IE2_2 Generate interrupt on Done2 when segment 2 finish. 0x2 IE2_3 Generate interrupt on Done3 when segment 2 finish. 0x3 IE2_EN IRQ enable of segment 2. 15 1 read-write IE2_EN_0 Interrupt DONE disabled. 0 IE2_EN_1 Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2. 0x1 CSEL3 ADC hardware trigger command selection 16 4 read-write CSEL3_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL3_1 ADC CMD1 selected. 0x1 CSEL3_2 ADC CMD2 selected. 0x2 CSEL3_3 ADC CMD3 selected. 0x3 CSEL3_4 ADC CMD4 selected. 0x4 CSEL3_5 ADC CMD5 selected. 0x5 CSEL3_6 ADC CMD6 selected. 0x6 CSEL3_7 ADC CMD7 selected. 0x7 CSEL3_8 ADC CMD8 selected. 0x8 CSEL3_9 ADC CMD9 selected. 0x9 CSEL3_10 ADC CMD10 selected. 0xA CSEL3_11 ADC CMD11 selected. 0xB CSEL3_12 ADC CMD12 selected. 0xC CSEL3_13 ADC CMD13 selected. 0xD CSEL3_14 ADC CMD14 selected. 0xE CSEL3_15 ADC CMD15 selected. 0xF HWTS3 Segment 3 HWTS ADC hardware trigger selection 20 8 read-write HWTS3_0 no trigger selected 0 HWTS3_1 ADC TRIG0 selected 0x1 HWTS3_2 ADC TRIG1 selected 0x2 HWTS3_4 ADC TRIG2 selected 0x4 HWTS3_8 ADC TRIG3 selected 0x8 HWTS3_16 ADC TRIG4 selected 0x10 HWTS3_32 ADC TRIG5 selected 0x20 HWTS3_64 ADC TRIG6 selected 0x40 HWTS3_128 ADC TRIG7 selected 0x80 B2B3 Segment 3 B2B 28 1 read-write B2B3_0 Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B3_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE3 Segment 3 interrupt enable. (This bit field is meaningful only when IE3_EN is set) 29 2 read-write IE3_0 Generate interrupt on Done0 when segment 3 finish. 0 IE3_1 Generate interrupt on Done1 when segment 3 finish. 0x1 IE3_2 Generate interrupt on Done2 when segment 3 finish. 0x2 IE3_3 Generate interrupt on Done3 when segment 3 finish. 0x3 IE3_EN IRQ enable of segment 3. 31 1 read-write IE3_EN_0 Interrupt DONE disabled. 0 IE3_EN_1 Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3. 0x1 TRIG3_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0x98 32 read-write 0 0xFFFFFFFF CSEL4 ADC hardware trigger command selection 0 4 read-write CSEL4_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL4_1 ADC CMD1 selected. 0x1 CSEL4_2 ADC CMD2 selected. 0x2 CSEL4_3 ADC CMD3 selected. 0x3 CSEL4_4 ADC CMD4 selected. 0x4 CSEL4_5 ADC CMD5 selected. 0x5 CSEL4_6 ADC CMD6 selected. 0x6 CSEL4_7 ADC CMD7 selected. 0x7 CSEL4_8 ADC CMD8 selected. 0x8 CSEL4_9 ADC CMD9 selected. 0x9 CSEL4_10 ADC CMD10 selected. 0xA CSEL4_11 ADC CMD11 selected. 0xB CSEL4_12 ADC CMD12 selected. 0xC CSEL4_13 ADC CMD13 selected. 0xD CSEL4_14 ADC CMD14 selected. 0xE CSEL4_15 ADC CMD15 selected. 0xF HWTS4 Segment 4 HWTS ADC hardware trigger selection 4 8 read-write HWTS4_0 no trigger selected 0 HWTS4_1 ADC TRIG0 selected 0x1 HWTS4_2 ADC TRIG1 selected 0x2 HWTS4_4 ADC TRIG2 selected 0x4 HWTS4_8 ADC TRIG3 selected 0x8 HWTS4_16 ADC TRIG4 selected 0x10 HWTS4_32 ADC TRIG5 selected 0x20 HWTS4_64 ADC TRIG6 selected 0x40 HWTS4_128 ADC TRIG7 selected 0x80 B2B4 Segment 4 B2B 12 1 read-write B2B4_0 Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B4_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE4 Segment 4 interrupt enable. (This bit field is meaningful only when IE4_EN is set) 13 2 read-write IE4_0 Generate interrupt on Done0 when segment 4 finish. 0 IE4_1 Generate interrupt on Done1 when segment 4 finish. 0x1 IE4_2 Generate interrupt on Done2 when segment 4 finish. 0x2 IE4_3 Generate interrupt on Done3 when segment 4 finish. 0x3 IE4_EN IRQ enable of segment 4. 15 1 read-write IE4_EN_0 Interrupt DONE disabled. 0 IE4_EN_1 Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4. 0x1 CSEL5 ADC hardware trigger command selection 16 4 read-write CSEL5_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL5_1 ADC CMD1 selected. 0x1 CSEL5_2 ADC CMD2 selected. 0x2 CSEL5_3 ADC CMD3 selected. 0x3 CSEL5_4 ADC CMD4 selected. 0x4 CSEL5_5 ADC CMD5 selected. 0x5 CSEL5_6 ADC CMD6 selected. 0x6 CSEL5_7 ADC CMD7 selected. 0x7 CSEL5_8 ADC CMD8 selected. 0x8 CSEL5_9 ADC CMD9 selected. 0x9 CSEL5_10 ADC CMD10 selected. 0xA CSEL5_11 ADC CMD11 selected. 0xB CSEL5_12 ADC CMD12 selected. 0xC CSEL5_13 ADC CMD13 selected. 0xD CSEL5_14 ADC CMD14 selected. 0xE CSEL5_15 ADC CMD15 selected. 0xF HWTS5 Segment 5 HWTS ADC hardware trigger selection 20 8 read-write HWTS5_0 no trigger selected 0 HWTS5_1 ADC TRIG0 selected 0x1 HWTS5_2 ADC TRIG1 selected 0x2 HWTS5_4 ADC TRIG2 selected 0x4 HWTS5_8 ADC TRIG3 selected 0x8 HWTS5_16 ADC TRIG4 selected 0x10 HWTS5_32 ADC TRIG5 selected 0x20 HWTS5_64 ADC TRIG6 selected 0x40 HWTS5_128 ADC TRIG7 selected 0x80 B2B5 Segment 5 B2B 28 1 read-write B2B5_0 Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B5_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE5 Segment 5 interrupt enable. (This bit field is meaningful only when IE5_EN is set) 29 2 read-write IE5_0 Generate interrupt on Done0 when segment 5 finish. 0 IE5_1 Generate interrupt on Done1 when segment 5 finish. 0x1 IE5_2 Generate interrupt on Done2 when segment 5 finish. 0x2 IE5_3 Generate interrupt on Done3 when segment 5 finish. 0x3 IE5_EN IRQ enable of segment 5. 31 1 read-write IE5_EN_0 Interrupt DONE disabled. 0 IE5_EN_1 Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5. 0x1 TRIG3_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0x9C 32 read-write 0 0xFFFFFFFF CSEL6 ADC hardware trigger command selection 0 4 read-write CSEL6_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL6_1 ADC CMD1 selected. 0x1 CSEL6_2 ADC CMD2 selected. 0x2 CSEL6_3 ADC CMD3 selected. 0x3 CSEL6_4 ADC CMD4 selected. 0x4 CSEL6_5 ADC CMD5 selected. 0x5 CSEL6_6 ADC CMD6 selected. 0x6 CSEL6_7 ADC CMD7 selected. 0x7 CSEL6_8 ADC CMD8 selected. 0x8 CSEL6_9 ADC CMD9 selected. 0x9 CSEL6_10 ADC CMD10 selected. 0xA CSEL6_11 ADC CMD11 selected. 0xB CSEL6_12 ADC CMD12 selected. 0xC CSEL6_13 ADC CMD13 selected. 0xD CSEL6_14 ADC CMD14 selected. 0xE CSEL6_15 ADC CMD15 selected. 0xF HWTS6 Segment 6 HWTS ADC hardware trigger selection 4 8 read-write HWTS6_0 no trigger selected 0 HWTS6_1 ADC TRIG0 selected 0x1 HWTS6_2 ADC TRIG1 selected 0x2 HWTS6_4 ADC TRIG2 selected 0x4 HWTS6_8 ADC TRIG3 selected 0x8 HWTS6_16 ADC TRIG4 selected 0x10 HWTS6_32 ADC TRIG5 selected 0x20 HWTS6_64 ADC TRIG6 selected 0x40 HWTS6_128 ADC TRIG7 selected 0x80 B2B6 Segment 6 B2B 12 1 read-write B2B6_0 Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B6_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE6 Segment 6 interrupt enable. (This bit field is meaningful only when IE6_EN is set) 13 2 read-write IE6_0 Generate interrupt on Done0 when segment 6 finish. 0 IE6_1 Generate interrupt on Done1 when segment 6 finish. 0x1 IE6_2 Generate interrupt on Done2 when segment 6 finish. 0x2 IE6_3 Generate interrupt on Done3 when segment 6 finish. 0x3 IE6_EN IRQ enable of segment 6. 15 1 read-write IE6_EN_0 Interrupt DONE disabled. 0 IE6_EN_1 Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6. 0x1 CSEL7 ADC hardware trigger command selection 16 4 read-write CSEL7_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL7_1 ADC CMD1 selected. 0x1 CSEL7_2 ADC CMD2 selected. 0x2 CSEL7_3 ADC CMD3 selected. 0x3 CSEL7_4 ADC CMD4 selected. 0x4 CSEL7_5 ADC CMD5 selected. 0x5 CSEL7_6 ADC CMD6 selected. 0x6 CSEL7_7 ADC CMD7 selected. 0x7 CSEL7_8 ADC CMD8 selected. 0x8 CSEL7_9 ADC CMD9 selected. 0x9 CSEL7_10 ADC CMD10 selected. 0xA CSEL7_11 ADC CMD11 selected. 0xB CSEL7_12 ADC CMD12 selected. 0xC CSEL7_13 ADC CMD13 selected. 0xD CSEL7_14 ADC CMD14 selected. 0xE CSEL7_15 ADC CMD15 selected. 0xF HWTS7 Segment 7 HWTS ADC hardware trigger selection 20 8 read-write HWTS7_0 no trigger selected 0 HWTS7_1 ADC TRIG0 selected 0x1 HWTS7_2 ADC TRIG1 selected 0x2 HWTS7_4 ADC TRIG2 selected 0x4 HWTS7_8 ADC TRIG3 selected 0x8 HWTS7_16 ADC TRIG4 selected 0x10 HWTS7_32 ADC TRIG5 selected 0x20 HWTS7_64 ADC TRIG6 selected 0x40 HWTS7_128 ADC TRIG7 selected 0x80 B2B7 Segment 7 B2B 28 1 read-write B2B7_0 Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B7_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE7 Segment 7 interrupt enable. (This bit field is meaningful only when IE7_EN is set) 29 2 read-write IE7_0 Generate interrupt on Done0 when segment 7 finish. 0 IE7_1 Generate interrupt on Done1 when segment 7 finish. 0x1 IE7_2 Generate interrupt on Done2 when segment 7 finish. 0x2 IE7_3 Generate interrupt on Done3 when segment 7 finish. 0x3 IE7_EN IRQ enable of segment 7. 31 1 read-write IE7_EN_0 Interrupt DONE disabled. 0 IE7_EN_1 Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7. 0x1 TRIG3_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0xA0 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA1 Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG3_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0xA4 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA3 Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG3_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0xA8 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA5 Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG3_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0xAC 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA7 Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG4_CTRL ETC_TRIG Control Register 0xB0 32 read-write 0 0xFFFFFFFF SW_TRIG Software trigger. This field is self-clearing. 0 1 read-write SW_TRIG_0 No software trigger event generated. 0 SW_TRIG_1 Software trigger event generated. 0x1 TRIG_MODE Trigger mode selection. 4 1 read-write TRIG_MODE_0 Hardware trigger. The softerware trigger will be ignored. 0 TRIG_MODE_1 Software trigger. The hardware trigger will be ignored. 0x1 TRIG_CHAIN The number of segments inside the trigger chain of TRIGa. 8 3 read-write TRIG_CHAIN_0 Trigger chain length is 1 0 TRIG_CHAIN_1 Trigger chain length is 2 0x1 TRIG_CHAIN_2 Trigger chain length is 3 0x2 TRIG_CHAIN_3 Trigger chain length is 4 0x3 TRIG_CHAIN_4 Trigger chain length is 5 0x4 TRIG_CHAIN_5 Trigger chain length is 6 0x5 TRIG_CHAIN_6 Trigger chain length is 7 0x6 TRIG_CHAIN_7 Trigger chain length is 8 0x7 TRIG_PRIORITY External trigger priority, 7 is highest priority, while 0 is lowest 12 3 read-write SYNC_MODE Trigger synchronization mode selection 16 1 read-write SYNC_MODE_0 Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. 0 SYNC_MODE_1 Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. 0x1 CHAINx_DONE Segment x done detection 24 8 read-write oneToClear CHAINx_DONE_0 segment x done not detected. 0 CHAINx_DONE_1 segment x done detected. 0x1 TRIG4_COUNTER ETC_TRIG Counter Register 0xB4 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG4_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0xB8 32 read-write 0 0xFFFFFFFF CSEL0 ADC hardware trigger command selection 0 4 read-write CSEL0_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL0_1 ADC CMD1 selected. 0x1 CSEL0_2 ADC CMD2 selected. 0x2 CSEL0_3 ADC CMD3 selected. 0x3 CSEL0_4 ADC CMD4 selected. 0x4 CSEL0_5 ADC CMD5 selected. 0x5 CSEL0_6 ADC CMD6 selected. 0x6 CSEL0_7 ADC CMD7 selected. 0x7 CSEL0_8 ADC CMD8 selected. 0x8 CSEL0_9 ADC CMD9 selected. 0x9 CSEL0_10 ADC CMD10 selected. 0xA CSEL0_11 ADC CMD11 selected. 0xB CSEL0_12 ADC CMD12 selected. 0xC CSEL0_13 ADC CMD13 selected. 0xD CSEL0_14 ADC CMD14 selected. 0xE CSEL0_15 ADC CMD15 selected. 0xF HWTS0 Segment 0 HWTS ADC hardware trigger selection 4 8 read-write HWTS0_0 no trigger selected 0 HWTS0_1 ADC TRIG0 selected 0x1 HWTS0_2 ADC TRIG1 selected 0x2 HWTS0_4 ADC TRIG2 selected 0x4 HWTS0_8 ADC TRIG3 selected 0x8 HWTS0_16 ADC TRIG4 selected 0x10 HWTS0_32 ADC TRIG5 selected 0x20 HWTS0_64 ADC TRIG6 selected 0x40 HWTS0_128 ADC TRIG7 selected 0x80 B2B0 Segment 0 B2B 12 1 read-write B2B0_0 Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B0_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE0 Segment 0 interrupt enable. (This bit field is meaningful only when IE0_EN is set) 13 2 read-write IE0_0 Generate interrupt on Done0 when segment 0 finish. 0 IE0_1 Generate interrupt on Done1 when segment 0 finish. 0x1 IE0_2 Generate interrupt on Done2 when segment 0 finish. 0x2 IE0_3 Generate interrupt on Done3 when segment 0 finish. 0x3 IE0_EN IRQ enable of segment 0. 15 1 read-write IE0_EN_0 Interrupt DONE disabled. 0 IE0_EN_1 Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0. 0x1 CSEL1 ADC hardware trigger command selection 16 4 read-write CSEL1_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL1_1 ADC CMD1 selected. 0x1 CSEL1_2 ADC CMD2 selected. 0x2 CSEL1_3 ADC CMD3 selected. 0x3 CSEL1_4 ADC CMD4 selected. 0x4 CSEL1_5 ADC CMD5 selected. 0x5 CSEL1_6 ADC CMD6 selected. 0x6 CSEL1_7 ADC CMD7 selected. 0x7 CSEL1_8 ADC CMD8 selected. 0x8 CSEL1_9 ADC CMD9 selected. 0x9 CSEL1_10 ADC CMD10 selected. 0xA CSEL1_11 ADC CMD11 selected. 0xB CSEL1_12 ADC CMD12 selected. 0xC CSEL1_13 ADC CMD13 selected. 0xD CSEL1_14 ADC CMD14 selected. 0xE CSEL1_15 ADC CMD15 selected. 0xF HWTS1 Segment 1 HWTS ADC hardware trigger selection 20 8 read-write HWTS1_0 no trigger selected 0 HWTS1_1 ADC TRIG0 selected 0x1 HWTS1_2 ADC TRIG1 selected 0x2 HWTS1_4 ADC TRIG2 selected 0x4 HWTS1_8 ADC TRIG3 selected 0x8 HWTS1_16 ADC TRIG4 selected 0x10 HWTS1_32 ADC TRIG5 selected 0x20 HWTS1_64 ADC TRIG6 selected 0x40 HWTS1_128 ADC TRIG7 selected 0x80 B2B1 Segment 1 B2B 28 1 read-write B2B1_0 Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B1_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE1 Segment 1 interrupt enable. (This bit field is meaningful only when IE1_EN is set) 29 2 read-write IE1_0 Generate interrupt on Done0 when Segment 1 finish. 0 IE1_1 Generate interrupt on Done1 when Segment 1 finish. 0x1 IE1_2 Generate interrupt on Done2 when Segment 1 finish. 0x2 IE1_3 Generate interrupt on Done3 when Segment 1 finish. 0x3 IE1_EN IRQ enable of segment 1. 31 1 read-write IE1_EN_0 Interrupt DONE disabled. 0 IE1_EN_1 Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1. 0x1 TRIG4_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0xBC 32 read-write 0 0xFFFFFFFF CSEL2 ADC hardware trigger command selection 0 4 read-write CSEL2_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL2_1 ADC CMD1 selected. 0x1 CSEL2_2 ADC CMD2 selected. 0x2 CSEL2_3 ADC CMD3 selected. 0x3 CSEL2_4 ADC CMD4 selected. 0x4 CSEL2_5 ADC CMD5 selected. 0x5 CSEL2_6 ADC CMD6 selected. 0x6 CSEL2_7 ADC CMD7 selected. 0x7 CSEL2_8 ADC CMD8 selected. 0x8 CSEL2_9 ADC CMD9 selected. 0x9 CSEL2_10 ADC CMD10 selected. 0xA CSEL2_11 ADC CMD11 selected. 0xB CSEL2_12 ADC CMD12 selected. 0xC CSEL2_13 ADC CMD13 selected. 0xD CSEL2_14 ADC CMD14 selected. 0xE CSEL2_15 ADC CMD15 selected. 0xF HWTS2 Segment 2 HWTS ADC hardware trigger selection 4 8 read-write HWTS2_0 no trigger selected 0 HWTS2_1 ADC TRIG0 selected 0x1 HWTS2_2 ADC TRIG1 selected 0x2 HWTS2_4 ADC TRIG2 selected 0x4 HWTS2_8 ADC TRIG3 selected 0x8 HWTS2_16 ADC TRIG4 selected 0x10 HWTS2_32 ADC TRIG5 selected 0x20 HWTS2_64 ADC TRIG6 selected 0x40 HWTS2_128 ADC TRIG7 selected 0x80 B2B2 Segment 2 B2B 12 1 read-write B2B2_0 Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B2_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE2 Segment 2 interrupt enable. (This bit field is meaningful only when IE2_EN is set) 13 2 read-write IE2_0 Generate interrupt on Done0 when segment 2 finish. 0 IE2_1 Generate interrupt on Done1 when segment 2 finish. 0x1 IE2_2 Generate interrupt on Done2 when segment 2 finish. 0x2 IE2_3 Generate interrupt on Done3 when segment 2 finish. 0x3 IE2_EN IRQ enable of segment 2. 15 1 read-write IE2_EN_0 Interrupt DONE disabled. 0 IE2_EN_1 Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2. 0x1 CSEL3 ADC hardware trigger command selection 16 4 read-write CSEL3_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL3_1 ADC CMD1 selected. 0x1 CSEL3_2 ADC CMD2 selected. 0x2 CSEL3_3 ADC CMD3 selected. 0x3 CSEL3_4 ADC CMD4 selected. 0x4 CSEL3_5 ADC CMD5 selected. 0x5 CSEL3_6 ADC CMD6 selected. 0x6 CSEL3_7 ADC CMD7 selected. 0x7 CSEL3_8 ADC CMD8 selected. 0x8 CSEL3_9 ADC CMD9 selected. 0x9 CSEL3_10 ADC CMD10 selected. 0xA CSEL3_11 ADC CMD11 selected. 0xB CSEL3_12 ADC CMD12 selected. 0xC CSEL3_13 ADC CMD13 selected. 0xD CSEL3_14 ADC CMD14 selected. 0xE CSEL3_15 ADC CMD15 selected. 0xF HWTS3 Segment 3 HWTS ADC hardware trigger selection 20 8 read-write HWTS3_0 no trigger selected 0 HWTS3_1 ADC TRIG0 selected 0x1 HWTS3_2 ADC TRIG1 selected 0x2 HWTS3_4 ADC TRIG2 selected 0x4 HWTS3_8 ADC TRIG3 selected 0x8 HWTS3_16 ADC TRIG4 selected 0x10 HWTS3_32 ADC TRIG5 selected 0x20 HWTS3_64 ADC TRIG6 selected 0x40 HWTS3_128 ADC TRIG7 selected 0x80 B2B3 Segment 3 B2B 28 1 read-write B2B3_0 Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B3_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE3 Segment 3 interrupt enable. (This bit field is meaningful only when IE3_EN is set) 29 2 read-write IE3_0 Generate interrupt on Done0 when segment 3 finish. 0 IE3_1 Generate interrupt on Done1 when segment 3 finish. 0x1 IE3_2 Generate interrupt on Done2 when segment 3 finish. 0x2 IE3_3 Generate interrupt on Done3 when segment 3 finish. 0x3 IE3_EN IRQ enable of segment 3. 31 1 read-write IE3_EN_0 Interrupt DONE disabled. 0 IE3_EN_1 Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3. 0x1 TRIG4_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0xC0 32 read-write 0 0xFFFFFFFF CSEL4 ADC hardware trigger command selection 0 4 read-write CSEL4_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL4_1 ADC CMD1 selected. 0x1 CSEL4_2 ADC CMD2 selected. 0x2 CSEL4_3 ADC CMD3 selected. 0x3 CSEL4_4 ADC CMD4 selected. 0x4 CSEL4_5 ADC CMD5 selected. 0x5 CSEL4_6 ADC CMD6 selected. 0x6 CSEL4_7 ADC CMD7 selected. 0x7 CSEL4_8 ADC CMD8 selected. 0x8 CSEL4_9 ADC CMD9 selected. 0x9 CSEL4_10 ADC CMD10 selected. 0xA CSEL4_11 ADC CMD11 selected. 0xB CSEL4_12 ADC CMD12 selected. 0xC CSEL4_13 ADC CMD13 selected. 0xD CSEL4_14 ADC CMD14 selected. 0xE CSEL4_15 ADC CMD15 selected. 0xF HWTS4 Segment 4 HWTS ADC hardware trigger selection 4 8 read-write HWTS4_0 no trigger selected 0 HWTS4_1 ADC TRIG0 selected 0x1 HWTS4_2 ADC TRIG1 selected 0x2 HWTS4_4 ADC TRIG2 selected 0x4 HWTS4_8 ADC TRIG3 selected 0x8 HWTS4_16 ADC TRIG4 selected 0x10 HWTS4_32 ADC TRIG5 selected 0x20 HWTS4_64 ADC TRIG6 selected 0x40 HWTS4_128 ADC TRIG7 selected 0x80 B2B4 Segment 4 B2B 12 1 read-write B2B4_0 Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B4_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE4 Segment 4 interrupt enable. (This bit field is meaningful only when IE4_EN is set) 13 2 read-write IE4_0 Generate interrupt on Done0 when segment 4 finish. 0 IE4_1 Generate interrupt on Done1 when segment 4 finish. 0x1 IE4_2 Generate interrupt on Done2 when segment 4 finish. 0x2 IE4_3 Generate interrupt on Done3 when segment 4 finish. 0x3 IE4_EN IRQ enable of segment 4. 15 1 read-write IE4_EN_0 Interrupt DONE disabled. 0 IE4_EN_1 Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4. 0x1 CSEL5 ADC hardware trigger command selection 16 4 read-write CSEL5_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL5_1 ADC CMD1 selected. 0x1 CSEL5_2 ADC CMD2 selected. 0x2 CSEL5_3 ADC CMD3 selected. 0x3 CSEL5_4 ADC CMD4 selected. 0x4 CSEL5_5 ADC CMD5 selected. 0x5 CSEL5_6 ADC CMD6 selected. 0x6 CSEL5_7 ADC CMD7 selected. 0x7 CSEL5_8 ADC CMD8 selected. 0x8 CSEL5_9 ADC CMD9 selected. 0x9 CSEL5_10 ADC CMD10 selected. 0xA CSEL5_11 ADC CMD11 selected. 0xB CSEL5_12 ADC CMD12 selected. 0xC CSEL5_13 ADC CMD13 selected. 0xD CSEL5_14 ADC CMD14 selected. 0xE CSEL5_15 ADC CMD15 selected. 0xF HWTS5 Segment 5 HWTS ADC hardware trigger selection 20 8 read-write HWTS5_0 no trigger selected 0 HWTS5_1 ADC TRIG0 selected 0x1 HWTS5_2 ADC TRIG1 selected 0x2 HWTS5_4 ADC TRIG2 selected 0x4 HWTS5_8 ADC TRIG3 selected 0x8 HWTS5_16 ADC TRIG4 selected 0x10 HWTS5_32 ADC TRIG5 selected 0x20 HWTS5_64 ADC TRIG6 selected 0x40 HWTS5_128 ADC TRIG7 selected 0x80 B2B5 Segment 5 B2B 28 1 read-write B2B5_0 Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B5_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE5 Segment 5 interrupt enable. (This bit field is meaningful only when IE5_EN is set) 29 2 read-write IE5_0 Generate interrupt on Done0 when segment 5 finish. 0 IE5_1 Generate interrupt on Done1 when segment 5 finish. 0x1 IE5_2 Generate interrupt on Done2 when segment 5 finish. 0x2 IE5_3 Generate interrupt on Done3 when segment 5 finish. 0x3 IE5_EN IRQ enable of segment 5. 31 1 read-write IE5_EN_0 Interrupt DONE disabled. 0 IE5_EN_1 Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5. 0x1 TRIG4_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0xC4 32 read-write 0 0xFFFFFFFF CSEL6 ADC hardware trigger command selection 0 4 read-write CSEL6_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL6_1 ADC CMD1 selected. 0x1 CSEL6_2 ADC CMD2 selected. 0x2 CSEL6_3 ADC CMD3 selected. 0x3 CSEL6_4 ADC CMD4 selected. 0x4 CSEL6_5 ADC CMD5 selected. 0x5 CSEL6_6 ADC CMD6 selected. 0x6 CSEL6_7 ADC CMD7 selected. 0x7 CSEL6_8 ADC CMD8 selected. 0x8 CSEL6_9 ADC CMD9 selected. 0x9 CSEL6_10 ADC CMD10 selected. 0xA CSEL6_11 ADC CMD11 selected. 0xB CSEL6_12 ADC CMD12 selected. 0xC CSEL6_13 ADC CMD13 selected. 0xD CSEL6_14 ADC CMD14 selected. 0xE CSEL6_15 ADC CMD15 selected. 0xF HWTS6 Segment 6 HWTS ADC hardware trigger selection 4 8 read-write HWTS6_0 no trigger selected 0 HWTS6_1 ADC TRIG0 selected 0x1 HWTS6_2 ADC TRIG1 selected 0x2 HWTS6_4 ADC TRIG2 selected 0x4 HWTS6_8 ADC TRIG3 selected 0x8 HWTS6_16 ADC TRIG4 selected 0x10 HWTS6_32 ADC TRIG5 selected 0x20 HWTS6_64 ADC TRIG6 selected 0x40 HWTS6_128 ADC TRIG7 selected 0x80 B2B6 Segment 6 B2B 12 1 read-write B2B6_0 Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B6_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE6 Segment 6 interrupt enable. (This bit field is meaningful only when IE6_EN is set) 13 2 read-write IE6_0 Generate interrupt on Done0 when segment 6 finish. 0 IE6_1 Generate interrupt on Done1 when segment 6 finish. 0x1 IE6_2 Generate interrupt on Done2 when segment 6 finish. 0x2 IE6_3 Generate interrupt on Done3 when segment 6 finish. 0x3 IE6_EN IRQ enable of segment 6. 15 1 read-write IE6_EN_0 Interrupt DONE disabled. 0 IE6_EN_1 Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6. 0x1 CSEL7 ADC hardware trigger command selection 16 4 read-write CSEL7_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL7_1 ADC CMD1 selected. 0x1 CSEL7_2 ADC CMD2 selected. 0x2 CSEL7_3 ADC CMD3 selected. 0x3 CSEL7_4 ADC CMD4 selected. 0x4 CSEL7_5 ADC CMD5 selected. 0x5 CSEL7_6 ADC CMD6 selected. 0x6 CSEL7_7 ADC CMD7 selected. 0x7 CSEL7_8 ADC CMD8 selected. 0x8 CSEL7_9 ADC CMD9 selected. 0x9 CSEL7_10 ADC CMD10 selected. 0xA CSEL7_11 ADC CMD11 selected. 0xB CSEL7_12 ADC CMD12 selected. 0xC CSEL7_13 ADC CMD13 selected. 0xD CSEL7_14 ADC CMD14 selected. 0xE CSEL7_15 ADC CMD15 selected. 0xF HWTS7 Segment 7 HWTS ADC hardware trigger selection 20 8 read-write HWTS7_0 no trigger selected 0 HWTS7_1 ADC TRIG0 selected 0x1 HWTS7_2 ADC TRIG1 selected 0x2 HWTS7_4 ADC TRIG2 selected 0x4 HWTS7_8 ADC TRIG3 selected 0x8 HWTS7_16 ADC TRIG4 selected 0x10 HWTS7_32 ADC TRIG5 selected 0x20 HWTS7_64 ADC TRIG6 selected 0x40 HWTS7_128 ADC TRIG7 selected 0x80 B2B7 Segment 7 B2B 28 1 read-write B2B7_0 Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B7_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE7 Segment 7 interrupt enable. (This bit field is meaningful only when IE7_EN is set) 29 2 read-write IE7_0 Generate interrupt on Done0 when segment 7 finish. 0 IE7_1 Generate interrupt on Done1 when segment 7 finish. 0x1 IE7_2 Generate interrupt on Done2 when segment 7 finish. 0x2 IE7_3 Generate interrupt on Done3 when segment 7 finish. 0x3 IE7_EN IRQ enable of segment 7. 31 1 read-write IE7_EN_0 Interrupt DONE disabled. 0 IE7_EN_1 Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7. 0x1 TRIG4_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0xC8 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA1 Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG4_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0xCC 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA3 Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG4_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0xD0 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA5 Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG4_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0xD4 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA7 Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG5_CTRL ETC_TRIG Control Register 0xD8 32 read-write 0 0xFFFFFFFF SW_TRIG Software trigger. This field is self-clearing. 0 1 read-write SW_TRIG_0 No software trigger event generated. 0 SW_TRIG_1 Software trigger event generated. 0x1 TRIG_MODE Trigger mode selection. 4 1 read-write TRIG_MODE_0 Hardware trigger. The softerware trigger will be ignored. 0 TRIG_MODE_1 Software trigger. The hardware trigger will be ignored. 0x1 TRIG_CHAIN The number of segments inside the trigger chain of TRIGa. 8 3 read-write TRIG_CHAIN_0 Trigger chain length is 1 0 TRIG_CHAIN_1 Trigger chain length is 2 0x1 TRIG_CHAIN_2 Trigger chain length is 3 0x2 TRIG_CHAIN_3 Trigger chain length is 4 0x3 TRIG_CHAIN_4 Trigger chain length is 5 0x4 TRIG_CHAIN_5 Trigger chain length is 6 0x5 TRIG_CHAIN_6 Trigger chain length is 7 0x6 TRIG_CHAIN_7 Trigger chain length is 8 0x7 TRIG_PRIORITY External trigger priority, 7 is highest priority, while 0 is lowest 12 3 read-write SYNC_MODE Trigger synchronization mode selection 16 1 read-write SYNC_MODE_0 Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. 0 SYNC_MODE_1 Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. 0x1 CHAINx_DONE Segment x done detection 24 8 read-write oneToClear CHAINx_DONE_0 segment x done not detected. 0 CHAINx_DONE_1 segment x done detected. 0x1 TRIG5_COUNTER ETC_TRIG Counter Register 0xDC 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG5_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0xE0 32 read-write 0 0xFFFFFFFF CSEL0 ADC hardware trigger command selection 0 4 read-write CSEL0_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL0_1 ADC CMD1 selected. 0x1 CSEL0_2 ADC CMD2 selected. 0x2 CSEL0_3 ADC CMD3 selected. 0x3 CSEL0_4 ADC CMD4 selected. 0x4 CSEL0_5 ADC CMD5 selected. 0x5 CSEL0_6 ADC CMD6 selected. 0x6 CSEL0_7 ADC CMD7 selected. 0x7 CSEL0_8 ADC CMD8 selected. 0x8 CSEL0_9 ADC CMD9 selected. 0x9 CSEL0_10 ADC CMD10 selected. 0xA CSEL0_11 ADC CMD11 selected. 0xB CSEL0_12 ADC CMD12 selected. 0xC CSEL0_13 ADC CMD13 selected. 0xD CSEL0_14 ADC CMD14 selected. 0xE CSEL0_15 ADC CMD15 selected. 0xF HWTS0 Segment 0 HWTS ADC hardware trigger selection 4 8 read-write HWTS0_0 no trigger selected 0 HWTS0_1 ADC TRIG0 selected 0x1 HWTS0_2 ADC TRIG1 selected 0x2 HWTS0_4 ADC TRIG2 selected 0x4 HWTS0_8 ADC TRIG3 selected 0x8 HWTS0_16 ADC TRIG4 selected 0x10 HWTS0_32 ADC TRIG5 selected 0x20 HWTS0_64 ADC TRIG6 selected 0x40 HWTS0_128 ADC TRIG7 selected 0x80 B2B0 Segment 0 B2B 12 1 read-write B2B0_0 Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B0_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE0 Segment 0 interrupt enable. (This bit field is meaningful only when IE0_EN is set) 13 2 read-write IE0_0 Generate interrupt on Done0 when segment 0 finish. 0 IE0_1 Generate interrupt on Done1 when segment 0 finish. 0x1 IE0_2 Generate interrupt on Done2 when segment 0 finish. 0x2 IE0_3 Generate interrupt on Done3 when segment 0 finish. 0x3 IE0_EN IRQ enable of segment 0. 15 1 read-write IE0_EN_0 Interrupt DONE disabled. 0 IE0_EN_1 Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0. 0x1 CSEL1 ADC hardware trigger command selection 16 4 read-write CSEL1_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL1_1 ADC CMD1 selected. 0x1 CSEL1_2 ADC CMD2 selected. 0x2 CSEL1_3 ADC CMD3 selected. 0x3 CSEL1_4 ADC CMD4 selected. 0x4 CSEL1_5 ADC CMD5 selected. 0x5 CSEL1_6 ADC CMD6 selected. 0x6 CSEL1_7 ADC CMD7 selected. 0x7 CSEL1_8 ADC CMD8 selected. 0x8 CSEL1_9 ADC CMD9 selected. 0x9 CSEL1_10 ADC CMD10 selected. 0xA CSEL1_11 ADC CMD11 selected. 0xB CSEL1_12 ADC CMD12 selected. 0xC CSEL1_13 ADC CMD13 selected. 0xD CSEL1_14 ADC CMD14 selected. 0xE CSEL1_15 ADC CMD15 selected. 0xF HWTS1 Segment 1 HWTS ADC hardware trigger selection 20 8 read-write HWTS1_0 no trigger selected 0 HWTS1_1 ADC TRIG0 selected 0x1 HWTS1_2 ADC TRIG1 selected 0x2 HWTS1_4 ADC TRIG2 selected 0x4 HWTS1_8 ADC TRIG3 selected 0x8 HWTS1_16 ADC TRIG4 selected 0x10 HWTS1_32 ADC TRIG5 selected 0x20 HWTS1_64 ADC TRIG6 selected 0x40 HWTS1_128 ADC TRIG7 selected 0x80 B2B1 Segment 1 B2B 28 1 read-write B2B1_0 Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B1_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE1 Segment 1 interrupt enable. (This bit field is meaningful only when IE1_EN is set) 29 2 read-write IE1_0 Generate interrupt on Done0 when Segment 1 finish. 0 IE1_1 Generate interrupt on Done1 when Segment 1 finish. 0x1 IE1_2 Generate interrupt on Done2 when Segment 1 finish. 0x2 IE1_3 Generate interrupt on Done3 when Segment 1 finish. 0x3 IE1_EN IRQ enable of segment 1. 31 1 read-write IE1_EN_0 Interrupt DONE disabled. 0 IE1_EN_1 Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1. 0x1 TRIG5_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0xE4 32 read-write 0 0xFFFFFFFF CSEL2 ADC hardware trigger command selection 0 4 read-write CSEL2_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL2_1 ADC CMD1 selected. 0x1 CSEL2_2 ADC CMD2 selected. 0x2 CSEL2_3 ADC CMD3 selected. 0x3 CSEL2_4 ADC CMD4 selected. 0x4 CSEL2_5 ADC CMD5 selected. 0x5 CSEL2_6 ADC CMD6 selected. 0x6 CSEL2_7 ADC CMD7 selected. 0x7 CSEL2_8 ADC CMD8 selected. 0x8 CSEL2_9 ADC CMD9 selected. 0x9 CSEL2_10 ADC CMD10 selected. 0xA CSEL2_11 ADC CMD11 selected. 0xB CSEL2_12 ADC CMD12 selected. 0xC CSEL2_13 ADC CMD13 selected. 0xD CSEL2_14 ADC CMD14 selected. 0xE CSEL2_15 ADC CMD15 selected. 0xF HWTS2 Segment 2 HWTS ADC hardware trigger selection 4 8 read-write HWTS2_0 no trigger selected 0 HWTS2_1 ADC TRIG0 selected 0x1 HWTS2_2 ADC TRIG1 selected 0x2 HWTS2_4 ADC TRIG2 selected 0x4 HWTS2_8 ADC TRIG3 selected 0x8 HWTS2_16 ADC TRIG4 selected 0x10 HWTS2_32 ADC TRIG5 selected 0x20 HWTS2_64 ADC TRIG6 selected 0x40 HWTS2_128 ADC TRIG7 selected 0x80 B2B2 Segment 2 B2B 12 1 read-write B2B2_0 Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B2_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE2 Segment 2 interrupt enable. (This bit field is meaningful only when IE2_EN is set) 13 2 read-write IE2_0 Generate interrupt on Done0 when segment 2 finish. 0 IE2_1 Generate interrupt on Done1 when segment 2 finish. 0x1 IE2_2 Generate interrupt on Done2 when segment 2 finish. 0x2 IE2_3 Generate interrupt on Done3 when segment 2 finish. 0x3 IE2_EN IRQ enable of segment 2. 15 1 read-write IE2_EN_0 Interrupt DONE disabled. 0 IE2_EN_1 Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2. 0x1 CSEL3 ADC hardware trigger command selection 16 4 read-write CSEL3_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL3_1 ADC CMD1 selected. 0x1 CSEL3_2 ADC CMD2 selected. 0x2 CSEL3_3 ADC CMD3 selected. 0x3 CSEL3_4 ADC CMD4 selected. 0x4 CSEL3_5 ADC CMD5 selected. 0x5 CSEL3_6 ADC CMD6 selected. 0x6 CSEL3_7 ADC CMD7 selected. 0x7 CSEL3_8 ADC CMD8 selected. 0x8 CSEL3_9 ADC CMD9 selected. 0x9 CSEL3_10 ADC CMD10 selected. 0xA CSEL3_11 ADC CMD11 selected. 0xB CSEL3_12 ADC CMD12 selected. 0xC CSEL3_13 ADC CMD13 selected. 0xD CSEL3_14 ADC CMD14 selected. 0xE CSEL3_15 ADC CMD15 selected. 0xF HWTS3 Segment 3 HWTS ADC hardware trigger selection 20 8 read-write HWTS3_0 no trigger selected 0 HWTS3_1 ADC TRIG0 selected 0x1 HWTS3_2 ADC TRIG1 selected 0x2 HWTS3_4 ADC TRIG2 selected 0x4 HWTS3_8 ADC TRIG3 selected 0x8 HWTS3_16 ADC TRIG4 selected 0x10 HWTS3_32 ADC TRIG5 selected 0x20 HWTS3_64 ADC TRIG6 selected 0x40 HWTS3_128 ADC TRIG7 selected 0x80 B2B3 Segment 3 B2B 28 1 read-write B2B3_0 Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B3_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE3 Segment 3 interrupt enable. (This bit field is meaningful only when IE3_EN is set) 29 2 read-write IE3_0 Generate interrupt on Done0 when segment 3 finish. 0 IE3_1 Generate interrupt on Done1 when segment 3 finish. 0x1 IE3_2 Generate interrupt on Done2 when segment 3 finish. 0x2 IE3_3 Generate interrupt on Done3 when segment 3 finish. 0x3 IE3_EN IRQ enable of segment 3. 31 1 read-write IE3_EN_0 Interrupt DONE disabled. 0 IE3_EN_1 Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3. 0x1 TRIG5_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0xE8 32 read-write 0 0xFFFFFFFF CSEL4 ADC hardware trigger command selection 0 4 read-write CSEL4_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL4_1 ADC CMD1 selected. 0x1 CSEL4_2 ADC CMD2 selected. 0x2 CSEL4_3 ADC CMD3 selected. 0x3 CSEL4_4 ADC CMD4 selected. 0x4 CSEL4_5 ADC CMD5 selected. 0x5 CSEL4_6 ADC CMD6 selected. 0x6 CSEL4_7 ADC CMD7 selected. 0x7 CSEL4_8 ADC CMD8 selected. 0x8 CSEL4_9 ADC CMD9 selected. 0x9 CSEL4_10 ADC CMD10 selected. 0xA CSEL4_11 ADC CMD11 selected. 0xB CSEL4_12 ADC CMD12 selected. 0xC CSEL4_13 ADC CMD13 selected. 0xD CSEL4_14 ADC CMD14 selected. 0xE CSEL4_15 ADC CMD15 selected. 0xF HWTS4 Segment 4 HWTS ADC hardware trigger selection 4 8 read-write HWTS4_0 no trigger selected 0 HWTS4_1 ADC TRIG0 selected 0x1 HWTS4_2 ADC TRIG1 selected 0x2 HWTS4_4 ADC TRIG2 selected 0x4 HWTS4_8 ADC TRIG3 selected 0x8 HWTS4_16 ADC TRIG4 selected 0x10 HWTS4_32 ADC TRIG5 selected 0x20 HWTS4_64 ADC TRIG6 selected 0x40 HWTS4_128 ADC TRIG7 selected 0x80 B2B4 Segment 4 B2B 12 1 read-write B2B4_0 Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B4_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE4 Segment 4 interrupt enable. (This bit field is meaningful only when IE4_EN is set) 13 2 read-write IE4_0 Generate interrupt on Done0 when segment 4 finish. 0 IE4_1 Generate interrupt on Done1 when segment 4 finish. 0x1 IE4_2 Generate interrupt on Done2 when segment 4 finish. 0x2 IE4_3 Generate interrupt on Done3 when segment 4 finish. 0x3 IE4_EN IRQ enable of segment 4. 15 1 read-write IE4_EN_0 Interrupt DONE disabled. 0 IE4_EN_1 Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4. 0x1 CSEL5 ADC hardware trigger command selection 16 4 read-write CSEL5_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL5_1 ADC CMD1 selected. 0x1 CSEL5_2 ADC CMD2 selected. 0x2 CSEL5_3 ADC CMD3 selected. 0x3 CSEL5_4 ADC CMD4 selected. 0x4 CSEL5_5 ADC CMD5 selected. 0x5 CSEL5_6 ADC CMD6 selected. 0x6 CSEL5_7 ADC CMD7 selected. 0x7 CSEL5_8 ADC CMD8 selected. 0x8 CSEL5_9 ADC CMD9 selected. 0x9 CSEL5_10 ADC CMD10 selected. 0xA CSEL5_11 ADC CMD11 selected. 0xB CSEL5_12 ADC CMD12 selected. 0xC CSEL5_13 ADC CMD13 selected. 0xD CSEL5_14 ADC CMD14 selected. 0xE CSEL5_15 ADC CMD15 selected. 0xF HWTS5 Segment 5 HWTS ADC hardware trigger selection 20 8 read-write HWTS5_0 no trigger selected 0 HWTS5_1 ADC TRIG0 selected 0x1 HWTS5_2 ADC TRIG1 selected 0x2 HWTS5_4 ADC TRIG2 selected 0x4 HWTS5_8 ADC TRIG3 selected 0x8 HWTS5_16 ADC TRIG4 selected 0x10 HWTS5_32 ADC TRIG5 selected 0x20 HWTS5_64 ADC TRIG6 selected 0x40 HWTS5_128 ADC TRIG7 selected 0x80 B2B5 Segment 5 B2B 28 1 read-write B2B5_0 Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B5_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE5 Segment 5 interrupt enable. (This bit field is meaningful only when IE5_EN is set) 29 2 read-write IE5_0 Generate interrupt on Done0 when segment 5 finish. 0 IE5_1 Generate interrupt on Done1 when segment 5 finish. 0x1 IE5_2 Generate interrupt on Done2 when segment 5 finish. 0x2 IE5_3 Generate interrupt on Done3 when segment 5 finish. 0x3 IE5_EN IRQ enable of segment 5. 31 1 read-write IE5_EN_0 Interrupt DONE disabled. 0 IE5_EN_1 Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5. 0x1 TRIG5_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0xEC 32 read-write 0 0xFFFFFFFF CSEL6 ADC hardware trigger command selection 0 4 read-write CSEL6_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL6_1 ADC CMD1 selected. 0x1 CSEL6_2 ADC CMD2 selected. 0x2 CSEL6_3 ADC CMD3 selected. 0x3 CSEL6_4 ADC CMD4 selected. 0x4 CSEL6_5 ADC CMD5 selected. 0x5 CSEL6_6 ADC CMD6 selected. 0x6 CSEL6_7 ADC CMD7 selected. 0x7 CSEL6_8 ADC CMD8 selected. 0x8 CSEL6_9 ADC CMD9 selected. 0x9 CSEL6_10 ADC CMD10 selected. 0xA CSEL6_11 ADC CMD11 selected. 0xB CSEL6_12 ADC CMD12 selected. 0xC CSEL6_13 ADC CMD13 selected. 0xD CSEL6_14 ADC CMD14 selected. 0xE CSEL6_15 ADC CMD15 selected. 0xF HWTS6 Segment 6 HWTS ADC hardware trigger selection 4 8 read-write HWTS6_0 no trigger selected 0 HWTS6_1 ADC TRIG0 selected 0x1 HWTS6_2 ADC TRIG1 selected 0x2 HWTS6_4 ADC TRIG2 selected 0x4 HWTS6_8 ADC TRIG3 selected 0x8 HWTS6_16 ADC TRIG4 selected 0x10 HWTS6_32 ADC TRIG5 selected 0x20 HWTS6_64 ADC TRIG6 selected 0x40 HWTS6_128 ADC TRIG7 selected 0x80 B2B6 Segment 6 B2B 12 1 read-write B2B6_0 Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B6_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE6 Segment 6 interrupt enable. (This bit field is meaningful only when IE6_EN is set) 13 2 read-write IE6_0 Generate interrupt on Done0 when segment 6 finish. 0 IE6_1 Generate interrupt on Done1 when segment 6 finish. 0x1 IE6_2 Generate interrupt on Done2 when segment 6 finish. 0x2 IE6_3 Generate interrupt on Done3 when segment 6 finish. 0x3 IE6_EN IRQ enable of segment 6. 15 1 read-write IE6_EN_0 Interrupt DONE disabled. 0 IE6_EN_1 Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6. 0x1 CSEL7 ADC hardware trigger command selection 16 4 read-write CSEL7_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL7_1 ADC CMD1 selected. 0x1 CSEL7_2 ADC CMD2 selected. 0x2 CSEL7_3 ADC CMD3 selected. 0x3 CSEL7_4 ADC CMD4 selected. 0x4 CSEL7_5 ADC CMD5 selected. 0x5 CSEL7_6 ADC CMD6 selected. 0x6 CSEL7_7 ADC CMD7 selected. 0x7 CSEL7_8 ADC CMD8 selected. 0x8 CSEL7_9 ADC CMD9 selected. 0x9 CSEL7_10 ADC CMD10 selected. 0xA CSEL7_11 ADC CMD11 selected. 0xB CSEL7_12 ADC CMD12 selected. 0xC CSEL7_13 ADC CMD13 selected. 0xD CSEL7_14 ADC CMD14 selected. 0xE CSEL7_15 ADC CMD15 selected. 0xF HWTS7 Segment 7 HWTS ADC hardware trigger selection 20 8 read-write HWTS7_0 no trigger selected 0 HWTS7_1 ADC TRIG0 selected 0x1 HWTS7_2 ADC TRIG1 selected 0x2 HWTS7_4 ADC TRIG2 selected 0x4 HWTS7_8 ADC TRIG3 selected 0x8 HWTS7_16 ADC TRIG4 selected 0x10 HWTS7_32 ADC TRIG5 selected 0x20 HWTS7_64 ADC TRIG6 selected 0x40 HWTS7_128 ADC TRIG7 selected 0x80 B2B7 Segment 7 B2B 28 1 read-write B2B7_0 Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B7_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE7 Segment 7 interrupt enable. (This bit field is meaningful only when IE7_EN is set) 29 2 read-write IE7_0 Generate interrupt on Done0 when segment 7 finish. 0 IE7_1 Generate interrupt on Done1 when segment 7 finish. 0x1 IE7_2 Generate interrupt on Done2 when segment 7 finish. 0x2 IE7_3 Generate interrupt on Done3 when segment 7 finish. 0x3 IE7_EN IRQ enable of segment 7. 31 1 read-write IE7_EN_0 Interrupt DONE disabled. 0 IE7_EN_1 Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7. 0x1 TRIG5_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0xF0 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA1 Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG5_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0xF4 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA3 Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG5_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0xF8 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA5 Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG5_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0xFC 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA7 Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG6_CTRL ETC_TRIG Control Register 0x100 32 read-write 0 0xFFFFFFFF SW_TRIG Software trigger. This field is self-clearing. 0 1 read-write SW_TRIG_0 No software trigger event generated. 0 SW_TRIG_1 Software trigger event generated. 0x1 TRIG_MODE Trigger mode selection. 4 1 read-write TRIG_MODE_0 Hardware trigger. The softerware trigger will be ignored. 0 TRIG_MODE_1 Software trigger. The hardware trigger will be ignored. 0x1 TRIG_CHAIN The number of segments inside the trigger chain of TRIGa. 8 3 read-write TRIG_CHAIN_0 Trigger chain length is 1 0 TRIG_CHAIN_1 Trigger chain length is 2 0x1 TRIG_CHAIN_2 Trigger chain length is 3 0x2 TRIG_CHAIN_3 Trigger chain length is 4 0x3 TRIG_CHAIN_4 Trigger chain length is 5 0x4 TRIG_CHAIN_5 Trigger chain length is 6 0x5 TRIG_CHAIN_6 Trigger chain length is 7 0x6 TRIG_CHAIN_7 Trigger chain length is 8 0x7 TRIG_PRIORITY External trigger priority, 7 is highest priority, while 0 is lowest 12 3 read-write SYNC_MODE Trigger synchronization mode selection 16 1 read-write SYNC_MODE_0 Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. 0 SYNC_MODE_1 Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. 0x1 CHAINx_DONE Segment x done detection 24 8 read-write oneToClear CHAINx_DONE_0 segment x done not detected. 0 CHAINx_DONE_1 segment x done detected. 0x1 TRIG6_COUNTER ETC_TRIG Counter Register 0x104 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG6_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0x108 32 read-write 0 0xFFFFFFFF CSEL0 ADC hardware trigger command selection 0 4 read-write CSEL0_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL0_1 ADC CMD1 selected. 0x1 CSEL0_2 ADC CMD2 selected. 0x2 CSEL0_3 ADC CMD3 selected. 0x3 CSEL0_4 ADC CMD4 selected. 0x4 CSEL0_5 ADC CMD5 selected. 0x5 CSEL0_6 ADC CMD6 selected. 0x6 CSEL0_7 ADC CMD7 selected. 0x7 CSEL0_8 ADC CMD8 selected. 0x8 CSEL0_9 ADC CMD9 selected. 0x9 CSEL0_10 ADC CMD10 selected. 0xA CSEL0_11 ADC CMD11 selected. 0xB CSEL0_12 ADC CMD12 selected. 0xC CSEL0_13 ADC CMD13 selected. 0xD CSEL0_14 ADC CMD14 selected. 0xE CSEL0_15 ADC CMD15 selected. 0xF HWTS0 Segment 0 HWTS ADC hardware trigger selection 4 8 read-write HWTS0_0 no trigger selected 0 HWTS0_1 ADC TRIG0 selected 0x1 HWTS0_2 ADC TRIG1 selected 0x2 HWTS0_4 ADC TRIG2 selected 0x4 HWTS0_8 ADC TRIG3 selected 0x8 HWTS0_16 ADC TRIG4 selected 0x10 HWTS0_32 ADC TRIG5 selected 0x20 HWTS0_64 ADC TRIG6 selected 0x40 HWTS0_128 ADC TRIG7 selected 0x80 B2B0 Segment 0 B2B 12 1 read-write B2B0_0 Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B0_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE0 Segment 0 interrupt enable. (This bit field is meaningful only when IE0_EN is set) 13 2 read-write IE0_0 Generate interrupt on Done0 when segment 0 finish. 0 IE0_1 Generate interrupt on Done1 when segment 0 finish. 0x1 IE0_2 Generate interrupt on Done2 when segment 0 finish. 0x2 IE0_3 Generate interrupt on Done3 when segment 0 finish. 0x3 IE0_EN IRQ enable of segment 0. 15 1 read-write IE0_EN_0 Interrupt DONE disabled. 0 IE0_EN_1 Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0. 0x1 CSEL1 ADC hardware trigger command selection 16 4 read-write CSEL1_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL1_1 ADC CMD1 selected. 0x1 CSEL1_2 ADC CMD2 selected. 0x2 CSEL1_3 ADC CMD3 selected. 0x3 CSEL1_4 ADC CMD4 selected. 0x4 CSEL1_5 ADC CMD5 selected. 0x5 CSEL1_6 ADC CMD6 selected. 0x6 CSEL1_7 ADC CMD7 selected. 0x7 CSEL1_8 ADC CMD8 selected. 0x8 CSEL1_9 ADC CMD9 selected. 0x9 CSEL1_10 ADC CMD10 selected. 0xA CSEL1_11 ADC CMD11 selected. 0xB CSEL1_12 ADC CMD12 selected. 0xC CSEL1_13 ADC CMD13 selected. 0xD CSEL1_14 ADC CMD14 selected. 0xE CSEL1_15 ADC CMD15 selected. 0xF HWTS1 Segment 1 HWTS ADC hardware trigger selection 20 8 read-write HWTS1_0 no trigger selected 0 HWTS1_1 ADC TRIG0 selected 0x1 HWTS1_2 ADC TRIG1 selected 0x2 HWTS1_4 ADC TRIG2 selected 0x4 HWTS1_8 ADC TRIG3 selected 0x8 HWTS1_16 ADC TRIG4 selected 0x10 HWTS1_32 ADC TRIG5 selected 0x20 HWTS1_64 ADC TRIG6 selected 0x40 HWTS1_128 ADC TRIG7 selected 0x80 B2B1 Segment 1 B2B 28 1 read-write B2B1_0 Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B1_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE1 Segment 1 interrupt enable. (This bit field is meaningful only when IE1_EN is set) 29 2 read-write IE1_0 Generate interrupt on Done0 when Segment 1 finish. 0 IE1_1 Generate interrupt on Done1 when Segment 1 finish. 0x1 IE1_2 Generate interrupt on Done2 when Segment 1 finish. 0x2 IE1_3 Generate interrupt on Done3 when Segment 1 finish. 0x3 IE1_EN IRQ enable of segment 1. 31 1 read-write IE1_EN_0 Interrupt DONE disabled. 0 IE1_EN_1 Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1. 0x1 TRIG6_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0x10C 32 read-write 0 0xFFFFFFFF CSEL2 ADC hardware trigger command selection 0 4 read-write CSEL2_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL2_1 ADC CMD1 selected. 0x1 CSEL2_2 ADC CMD2 selected. 0x2 CSEL2_3 ADC CMD3 selected. 0x3 CSEL2_4 ADC CMD4 selected. 0x4 CSEL2_5 ADC CMD5 selected. 0x5 CSEL2_6 ADC CMD6 selected. 0x6 CSEL2_7 ADC CMD7 selected. 0x7 CSEL2_8 ADC CMD8 selected. 0x8 CSEL2_9 ADC CMD9 selected. 0x9 CSEL2_10 ADC CMD10 selected. 0xA CSEL2_11 ADC CMD11 selected. 0xB CSEL2_12 ADC CMD12 selected. 0xC CSEL2_13 ADC CMD13 selected. 0xD CSEL2_14 ADC CMD14 selected. 0xE CSEL2_15 ADC CMD15 selected. 0xF HWTS2 Segment 2 HWTS ADC hardware trigger selection 4 8 read-write HWTS2_0 no trigger selected 0 HWTS2_1 ADC TRIG0 selected 0x1 HWTS2_2 ADC TRIG1 selected 0x2 HWTS2_4 ADC TRIG2 selected 0x4 HWTS2_8 ADC TRIG3 selected 0x8 HWTS2_16 ADC TRIG4 selected 0x10 HWTS2_32 ADC TRIG5 selected 0x20 HWTS2_64 ADC TRIG6 selected 0x40 HWTS2_128 ADC TRIG7 selected 0x80 B2B2 Segment 2 B2B 12 1 read-write B2B2_0 Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B2_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE2 Segment 2 interrupt enable. (This bit field is meaningful only when IE2_EN is set) 13 2 read-write IE2_0 Generate interrupt on Done0 when segment 2 finish. 0 IE2_1 Generate interrupt on Done1 when segment 2 finish. 0x1 IE2_2 Generate interrupt on Done2 when segment 2 finish. 0x2 IE2_3 Generate interrupt on Done3 when segment 2 finish. 0x3 IE2_EN IRQ enable of segment 2. 15 1 read-write IE2_EN_0 Interrupt DONE disabled. 0 IE2_EN_1 Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2. 0x1 CSEL3 ADC hardware trigger command selection 16 4 read-write CSEL3_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL3_1 ADC CMD1 selected. 0x1 CSEL3_2 ADC CMD2 selected. 0x2 CSEL3_3 ADC CMD3 selected. 0x3 CSEL3_4 ADC CMD4 selected. 0x4 CSEL3_5 ADC CMD5 selected. 0x5 CSEL3_6 ADC CMD6 selected. 0x6 CSEL3_7 ADC CMD7 selected. 0x7 CSEL3_8 ADC CMD8 selected. 0x8 CSEL3_9 ADC CMD9 selected. 0x9 CSEL3_10 ADC CMD10 selected. 0xA CSEL3_11 ADC CMD11 selected. 0xB CSEL3_12 ADC CMD12 selected. 0xC CSEL3_13 ADC CMD13 selected. 0xD CSEL3_14 ADC CMD14 selected. 0xE CSEL3_15 ADC CMD15 selected. 0xF HWTS3 Segment 3 HWTS ADC hardware trigger selection 20 8 read-write HWTS3_0 no trigger selected 0 HWTS3_1 ADC TRIG0 selected 0x1 HWTS3_2 ADC TRIG1 selected 0x2 HWTS3_4 ADC TRIG2 selected 0x4 HWTS3_8 ADC TRIG3 selected 0x8 HWTS3_16 ADC TRIG4 selected 0x10 HWTS3_32 ADC TRIG5 selected 0x20 HWTS3_64 ADC TRIG6 selected 0x40 HWTS3_128 ADC TRIG7 selected 0x80 B2B3 Segment 3 B2B 28 1 read-write B2B3_0 Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B3_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE3 Segment 3 interrupt enable. (This bit field is meaningful only when IE3_EN is set) 29 2 read-write IE3_0 Generate interrupt on Done0 when segment 3 finish. 0 IE3_1 Generate interrupt on Done1 when segment 3 finish. 0x1 IE3_2 Generate interrupt on Done2 when segment 3 finish. 0x2 IE3_3 Generate interrupt on Done3 when segment 3 finish. 0x3 IE3_EN IRQ enable of segment 3. 31 1 read-write IE3_EN_0 Interrupt DONE disabled. 0 IE3_EN_1 Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3. 0x1 TRIG6_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0x110 32 read-write 0 0xFFFFFFFF CSEL4 ADC hardware trigger command selection 0 4 read-write CSEL4_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL4_1 ADC CMD1 selected. 0x1 CSEL4_2 ADC CMD2 selected. 0x2 CSEL4_3 ADC CMD3 selected. 0x3 CSEL4_4 ADC CMD4 selected. 0x4 CSEL4_5 ADC CMD5 selected. 0x5 CSEL4_6 ADC CMD6 selected. 0x6 CSEL4_7 ADC CMD7 selected. 0x7 CSEL4_8 ADC CMD8 selected. 0x8 CSEL4_9 ADC CMD9 selected. 0x9 CSEL4_10 ADC CMD10 selected. 0xA CSEL4_11 ADC CMD11 selected. 0xB CSEL4_12 ADC CMD12 selected. 0xC CSEL4_13 ADC CMD13 selected. 0xD CSEL4_14 ADC CMD14 selected. 0xE CSEL4_15 ADC CMD15 selected. 0xF HWTS4 Segment 4 HWTS ADC hardware trigger selection 4 8 read-write HWTS4_0 no trigger selected 0 HWTS4_1 ADC TRIG0 selected 0x1 HWTS4_2 ADC TRIG1 selected 0x2 HWTS4_4 ADC TRIG2 selected 0x4 HWTS4_8 ADC TRIG3 selected 0x8 HWTS4_16 ADC TRIG4 selected 0x10 HWTS4_32 ADC TRIG5 selected 0x20 HWTS4_64 ADC TRIG6 selected 0x40 HWTS4_128 ADC TRIG7 selected 0x80 B2B4 Segment 4 B2B 12 1 read-write B2B4_0 Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B4_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE4 Segment 4 interrupt enable. (This bit field is meaningful only when IE4_EN is set) 13 2 read-write IE4_0 Generate interrupt on Done0 when segment 4 finish. 0 IE4_1 Generate interrupt on Done1 when segment 4 finish. 0x1 IE4_2 Generate interrupt on Done2 when segment 4 finish. 0x2 IE4_3 Generate interrupt on Done3 when segment 4 finish. 0x3 IE4_EN IRQ enable of segment 4. 15 1 read-write IE4_EN_0 Interrupt DONE disabled. 0 IE4_EN_1 Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4. 0x1 CSEL5 ADC hardware trigger command selection 16 4 read-write CSEL5_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL5_1 ADC CMD1 selected. 0x1 CSEL5_2 ADC CMD2 selected. 0x2 CSEL5_3 ADC CMD3 selected. 0x3 CSEL5_4 ADC CMD4 selected. 0x4 CSEL5_5 ADC CMD5 selected. 0x5 CSEL5_6 ADC CMD6 selected. 0x6 CSEL5_7 ADC CMD7 selected. 0x7 CSEL5_8 ADC CMD8 selected. 0x8 CSEL5_9 ADC CMD9 selected. 0x9 CSEL5_10 ADC CMD10 selected. 0xA CSEL5_11 ADC CMD11 selected. 0xB CSEL5_12 ADC CMD12 selected. 0xC CSEL5_13 ADC CMD13 selected. 0xD CSEL5_14 ADC CMD14 selected. 0xE CSEL5_15 ADC CMD15 selected. 0xF HWTS5 Segment 5 HWTS ADC hardware trigger selection 20 8 read-write HWTS5_0 no trigger selected 0 HWTS5_1 ADC TRIG0 selected 0x1 HWTS5_2 ADC TRIG1 selected 0x2 HWTS5_4 ADC TRIG2 selected 0x4 HWTS5_8 ADC TRIG3 selected 0x8 HWTS5_16 ADC TRIG4 selected 0x10 HWTS5_32 ADC TRIG5 selected 0x20 HWTS5_64 ADC TRIG6 selected 0x40 HWTS5_128 ADC TRIG7 selected 0x80 B2B5 Segment 5 B2B 28 1 read-write B2B5_0 Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B5_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE5 Segment 5 interrupt enable. (This bit field is meaningful only when IE5_EN is set) 29 2 read-write IE5_0 Generate interrupt on Done0 when segment 5 finish. 0 IE5_1 Generate interrupt on Done1 when segment 5 finish. 0x1 IE5_2 Generate interrupt on Done2 when segment 5 finish. 0x2 IE5_3 Generate interrupt on Done3 when segment 5 finish. 0x3 IE5_EN IRQ enable of segment 5. 31 1 read-write IE5_EN_0 Interrupt DONE disabled. 0 IE5_EN_1 Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5. 0x1 TRIG6_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0x114 32 read-write 0 0xFFFFFFFF CSEL6 ADC hardware trigger command selection 0 4 read-write CSEL6_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL6_1 ADC CMD1 selected. 0x1 CSEL6_2 ADC CMD2 selected. 0x2 CSEL6_3 ADC CMD3 selected. 0x3 CSEL6_4 ADC CMD4 selected. 0x4 CSEL6_5 ADC CMD5 selected. 0x5 CSEL6_6 ADC CMD6 selected. 0x6 CSEL6_7 ADC CMD7 selected. 0x7 CSEL6_8 ADC CMD8 selected. 0x8 CSEL6_9 ADC CMD9 selected. 0x9 CSEL6_10 ADC CMD10 selected. 0xA CSEL6_11 ADC CMD11 selected. 0xB CSEL6_12 ADC CMD12 selected. 0xC CSEL6_13 ADC CMD13 selected. 0xD CSEL6_14 ADC CMD14 selected. 0xE CSEL6_15 ADC CMD15 selected. 0xF HWTS6 Segment 6 HWTS ADC hardware trigger selection 4 8 read-write HWTS6_0 no trigger selected 0 HWTS6_1 ADC TRIG0 selected 0x1 HWTS6_2 ADC TRIG1 selected 0x2 HWTS6_4 ADC TRIG2 selected 0x4 HWTS6_8 ADC TRIG3 selected 0x8 HWTS6_16 ADC TRIG4 selected 0x10 HWTS6_32 ADC TRIG5 selected 0x20 HWTS6_64 ADC TRIG6 selected 0x40 HWTS6_128 ADC TRIG7 selected 0x80 B2B6 Segment 6 B2B 12 1 read-write B2B6_0 Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B6_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE6 Segment 6 interrupt enable. (This bit field is meaningful only when IE6_EN is set) 13 2 read-write IE6_0 Generate interrupt on Done0 when segment 6 finish. 0 IE6_1 Generate interrupt on Done1 when segment 6 finish. 0x1 IE6_2 Generate interrupt on Done2 when segment 6 finish. 0x2 IE6_3 Generate interrupt on Done3 when segment 6 finish. 0x3 IE6_EN IRQ enable of segment 6. 15 1 read-write IE6_EN_0 Interrupt DONE disabled. 0 IE6_EN_1 Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6. 0x1 CSEL7 ADC hardware trigger command selection 16 4 read-write CSEL7_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL7_1 ADC CMD1 selected. 0x1 CSEL7_2 ADC CMD2 selected. 0x2 CSEL7_3 ADC CMD3 selected. 0x3 CSEL7_4 ADC CMD4 selected. 0x4 CSEL7_5 ADC CMD5 selected. 0x5 CSEL7_6 ADC CMD6 selected. 0x6 CSEL7_7 ADC CMD7 selected. 0x7 CSEL7_8 ADC CMD8 selected. 0x8 CSEL7_9 ADC CMD9 selected. 0x9 CSEL7_10 ADC CMD10 selected. 0xA CSEL7_11 ADC CMD11 selected. 0xB CSEL7_12 ADC CMD12 selected. 0xC CSEL7_13 ADC CMD13 selected. 0xD CSEL7_14 ADC CMD14 selected. 0xE CSEL7_15 ADC CMD15 selected. 0xF HWTS7 Segment 7 HWTS ADC hardware trigger selection 20 8 read-write HWTS7_0 no trigger selected 0 HWTS7_1 ADC TRIG0 selected 0x1 HWTS7_2 ADC TRIG1 selected 0x2 HWTS7_4 ADC TRIG2 selected 0x4 HWTS7_8 ADC TRIG3 selected 0x8 HWTS7_16 ADC TRIG4 selected 0x10 HWTS7_32 ADC TRIG5 selected 0x20 HWTS7_64 ADC TRIG6 selected 0x40 HWTS7_128 ADC TRIG7 selected 0x80 B2B7 Segment 7 B2B 28 1 read-write B2B7_0 Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B7_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE7 Segment 7 interrupt enable. (This bit field is meaningful only when IE7_EN is set) 29 2 read-write IE7_0 Generate interrupt on Done0 when segment 7 finish. 0 IE7_1 Generate interrupt on Done1 when segment 7 finish. 0x1 IE7_2 Generate interrupt on Done2 when segment 7 finish. 0x2 IE7_3 Generate interrupt on Done3 when segment 7 finish. 0x3 IE7_EN IRQ enable of segment 7. 31 1 read-write IE7_EN_0 Interrupt DONE disabled. 0 IE7_EN_1 Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7. 0x1 TRIG6_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0x118 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA1 Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG6_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0x11C 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA3 Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG6_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0x120 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA5 Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG6_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0x124 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA7 Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG7_CTRL ETC_TRIG Control Register 0x128 32 read-write 0 0xFFFFFFFF SW_TRIG Software trigger. This field is self-clearing. 0 1 read-write SW_TRIG_0 No software trigger event generated. 0 SW_TRIG_1 Software trigger event generated. 0x1 TRIG_MODE Trigger mode selection. 4 1 read-write TRIG_MODE_0 Hardware trigger. The softerware trigger will be ignored. 0 TRIG_MODE_1 Software trigger. The hardware trigger will be ignored. 0x1 TRIG_CHAIN The number of segments inside the trigger chain of TRIGa. 8 3 read-write TRIG_CHAIN_0 Trigger chain length is 1 0 TRIG_CHAIN_1 Trigger chain length is 2 0x1 TRIG_CHAIN_2 Trigger chain length is 3 0x2 TRIG_CHAIN_3 Trigger chain length is 4 0x3 TRIG_CHAIN_4 Trigger chain length is 5 0x4 TRIG_CHAIN_5 Trigger chain length is 6 0x5 TRIG_CHAIN_6 Trigger chain length is 7 0x6 TRIG_CHAIN_7 Trigger chain length is 8 0x7 TRIG_PRIORITY External trigger priority, 7 is highest priority, while 0 is lowest 12 3 read-write SYNC_MODE Trigger synchronization mode selection 16 1 read-write SYNC_MODE_0 Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. 0 SYNC_MODE_1 Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. 0x1 CHAINx_DONE Segment x done detection 24 8 read-write oneToClear CHAINx_DONE_0 segment x done not detected. 0 CHAINx_DONE_1 segment x done detected. 0x1 TRIG7_COUNTER ETC_TRIG Counter Register 0x12C 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG7_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0x130 32 read-write 0 0xFFFFFFFF CSEL0 ADC hardware trigger command selection 0 4 read-write CSEL0_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL0_1 ADC CMD1 selected. 0x1 CSEL0_2 ADC CMD2 selected. 0x2 CSEL0_3 ADC CMD3 selected. 0x3 CSEL0_4 ADC CMD4 selected. 0x4 CSEL0_5 ADC CMD5 selected. 0x5 CSEL0_6 ADC CMD6 selected. 0x6 CSEL0_7 ADC CMD7 selected. 0x7 CSEL0_8 ADC CMD8 selected. 0x8 CSEL0_9 ADC CMD9 selected. 0x9 CSEL0_10 ADC CMD10 selected. 0xA CSEL0_11 ADC CMD11 selected. 0xB CSEL0_12 ADC CMD12 selected. 0xC CSEL0_13 ADC CMD13 selected. 0xD CSEL0_14 ADC CMD14 selected. 0xE CSEL0_15 ADC CMD15 selected. 0xF HWTS0 Segment 0 HWTS ADC hardware trigger selection 4 8 read-write HWTS0_0 no trigger selected 0 HWTS0_1 ADC TRIG0 selected 0x1 HWTS0_2 ADC TRIG1 selected 0x2 HWTS0_4 ADC TRIG2 selected 0x4 HWTS0_8 ADC TRIG3 selected 0x8 HWTS0_16 ADC TRIG4 selected 0x10 HWTS0_32 ADC TRIG5 selected 0x20 HWTS0_64 ADC TRIG6 selected 0x40 HWTS0_128 ADC TRIG7 selected 0x80 B2B0 Segment 0 B2B 12 1 read-write B2B0_0 Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B0_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE0 Segment 0 interrupt enable. (This bit field is meaningful only when IE0_EN is set) 13 2 read-write IE0_0 Generate interrupt on Done0 when segment 0 finish. 0 IE0_1 Generate interrupt on Done1 when segment 0 finish. 0x1 IE0_2 Generate interrupt on Done2 when segment 0 finish. 0x2 IE0_3 Generate interrupt on Done3 when segment 0 finish. 0x3 IE0_EN IRQ enable of segment 0. 15 1 read-write IE0_EN_0 Interrupt DONE disabled. 0 IE0_EN_1 Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0. 0x1 CSEL1 ADC hardware trigger command selection 16 4 read-write CSEL1_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL1_1 ADC CMD1 selected. 0x1 CSEL1_2 ADC CMD2 selected. 0x2 CSEL1_3 ADC CMD3 selected. 0x3 CSEL1_4 ADC CMD4 selected. 0x4 CSEL1_5 ADC CMD5 selected. 0x5 CSEL1_6 ADC CMD6 selected. 0x6 CSEL1_7 ADC CMD7 selected. 0x7 CSEL1_8 ADC CMD8 selected. 0x8 CSEL1_9 ADC CMD9 selected. 0x9 CSEL1_10 ADC CMD10 selected. 0xA CSEL1_11 ADC CMD11 selected. 0xB CSEL1_12 ADC CMD12 selected. 0xC CSEL1_13 ADC CMD13 selected. 0xD CSEL1_14 ADC CMD14 selected. 0xE CSEL1_15 ADC CMD15 selected. 0xF HWTS1 Segment 1 HWTS ADC hardware trigger selection 20 8 read-write HWTS1_0 no trigger selected 0 HWTS1_1 ADC TRIG0 selected 0x1 HWTS1_2 ADC TRIG1 selected 0x2 HWTS1_4 ADC TRIG2 selected 0x4 HWTS1_8 ADC TRIG3 selected 0x8 HWTS1_16 ADC TRIG4 selected 0x10 HWTS1_32 ADC TRIG5 selected 0x20 HWTS1_64 ADC TRIG6 selected 0x40 HWTS1_128 ADC TRIG7 selected 0x80 B2B1 Segment 1 B2B 28 1 read-write B2B1_0 Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B1_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE1 Segment 1 interrupt enable. (This bit field is meaningful only when IE1_EN is set) 29 2 read-write IE1_0 Generate interrupt on Done0 when Segment 1 finish. 0 IE1_1 Generate interrupt on Done1 when Segment 1 finish. 0x1 IE1_2 Generate interrupt on Done2 when Segment 1 finish. 0x2 IE1_3 Generate interrupt on Done3 when Segment 1 finish. 0x3 IE1_EN IRQ enable of segment 1. 31 1 read-write IE1_EN_0 Interrupt DONE disabled. 0 IE1_EN_1 Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1. 0x1 TRIG7_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0x134 32 read-write 0 0xFFFFFFFF CSEL2 ADC hardware trigger command selection 0 4 read-write CSEL2_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL2_1 ADC CMD1 selected. 0x1 CSEL2_2 ADC CMD2 selected. 0x2 CSEL2_3 ADC CMD3 selected. 0x3 CSEL2_4 ADC CMD4 selected. 0x4 CSEL2_5 ADC CMD5 selected. 0x5 CSEL2_6 ADC CMD6 selected. 0x6 CSEL2_7 ADC CMD7 selected. 0x7 CSEL2_8 ADC CMD8 selected. 0x8 CSEL2_9 ADC CMD9 selected. 0x9 CSEL2_10 ADC CMD10 selected. 0xA CSEL2_11 ADC CMD11 selected. 0xB CSEL2_12 ADC CMD12 selected. 0xC CSEL2_13 ADC CMD13 selected. 0xD CSEL2_14 ADC CMD14 selected. 0xE CSEL2_15 ADC CMD15 selected. 0xF HWTS2 Segment 2 HWTS ADC hardware trigger selection 4 8 read-write HWTS2_0 no trigger selected 0 HWTS2_1 ADC TRIG0 selected 0x1 HWTS2_2 ADC TRIG1 selected 0x2 HWTS2_4 ADC TRIG2 selected 0x4 HWTS2_8 ADC TRIG3 selected 0x8 HWTS2_16 ADC TRIG4 selected 0x10 HWTS2_32 ADC TRIG5 selected 0x20 HWTS2_64 ADC TRIG6 selected 0x40 HWTS2_128 ADC TRIG7 selected 0x80 B2B2 Segment 2 B2B 12 1 read-write B2B2_0 Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B2_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE2 Segment 2 interrupt enable. (This bit field is meaningful only when IE2_EN is set) 13 2 read-write IE2_0 Generate interrupt on Done0 when segment 2 finish. 0 IE2_1 Generate interrupt on Done1 when segment 2 finish. 0x1 IE2_2 Generate interrupt on Done2 when segment 2 finish. 0x2 IE2_3 Generate interrupt on Done3 when segment 2 finish. 0x3 IE2_EN IRQ enable of segment 2. 15 1 read-write IE2_EN_0 Interrupt DONE disabled. 0 IE2_EN_1 Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2. 0x1 CSEL3 ADC hardware trigger command selection 16 4 read-write CSEL3_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL3_1 ADC CMD1 selected. 0x1 CSEL3_2 ADC CMD2 selected. 0x2 CSEL3_3 ADC CMD3 selected. 0x3 CSEL3_4 ADC CMD4 selected. 0x4 CSEL3_5 ADC CMD5 selected. 0x5 CSEL3_6 ADC CMD6 selected. 0x6 CSEL3_7 ADC CMD7 selected. 0x7 CSEL3_8 ADC CMD8 selected. 0x8 CSEL3_9 ADC CMD9 selected. 0x9 CSEL3_10 ADC CMD10 selected. 0xA CSEL3_11 ADC CMD11 selected. 0xB CSEL3_12 ADC CMD12 selected. 0xC CSEL3_13 ADC CMD13 selected. 0xD CSEL3_14 ADC CMD14 selected. 0xE CSEL3_15 ADC CMD15 selected. 0xF HWTS3 Segment 3 HWTS ADC hardware trigger selection 20 8 read-write HWTS3_0 no trigger selected 0 HWTS3_1 ADC TRIG0 selected 0x1 HWTS3_2 ADC TRIG1 selected 0x2 HWTS3_4 ADC TRIG2 selected 0x4 HWTS3_8 ADC TRIG3 selected 0x8 HWTS3_16 ADC TRIG4 selected 0x10 HWTS3_32 ADC TRIG5 selected 0x20 HWTS3_64 ADC TRIG6 selected 0x40 HWTS3_128 ADC TRIG7 selected 0x80 B2B3 Segment 3 B2B 28 1 read-write B2B3_0 Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B3_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE3 Segment 3 interrupt enable. (This bit field is meaningful only when IE3_EN is set) 29 2 read-write IE3_0 Generate interrupt on Done0 when segment 3 finish. 0 IE3_1 Generate interrupt on Done1 when segment 3 finish. 0x1 IE3_2 Generate interrupt on Done2 when segment 3 finish. 0x2 IE3_3 Generate interrupt on Done3 when segment 3 finish. 0x3 IE3_EN IRQ enable of segment 3. 31 1 read-write IE3_EN_0 Interrupt DONE disabled. 0 IE3_EN_1 Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3. 0x1 TRIG7_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0x138 32 read-write 0 0xFFFFFFFF CSEL4 ADC hardware trigger command selection 0 4 read-write CSEL4_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL4_1 ADC CMD1 selected. 0x1 CSEL4_2 ADC CMD2 selected. 0x2 CSEL4_3 ADC CMD3 selected. 0x3 CSEL4_4 ADC CMD4 selected. 0x4 CSEL4_5 ADC CMD5 selected. 0x5 CSEL4_6 ADC CMD6 selected. 0x6 CSEL4_7 ADC CMD7 selected. 0x7 CSEL4_8 ADC CMD8 selected. 0x8 CSEL4_9 ADC CMD9 selected. 0x9 CSEL4_10 ADC CMD10 selected. 0xA CSEL4_11 ADC CMD11 selected. 0xB CSEL4_12 ADC CMD12 selected. 0xC CSEL4_13 ADC CMD13 selected. 0xD CSEL4_14 ADC CMD14 selected. 0xE CSEL4_15 ADC CMD15 selected. 0xF HWTS4 Segment 4 HWTS ADC hardware trigger selection 4 8 read-write HWTS4_0 no trigger selected 0 HWTS4_1 ADC TRIG0 selected 0x1 HWTS4_2 ADC TRIG1 selected 0x2 HWTS4_4 ADC TRIG2 selected 0x4 HWTS4_8 ADC TRIG3 selected 0x8 HWTS4_16 ADC TRIG4 selected 0x10 HWTS4_32 ADC TRIG5 selected 0x20 HWTS4_64 ADC TRIG6 selected 0x40 HWTS4_128 ADC TRIG7 selected 0x80 B2B4 Segment 4 B2B 12 1 read-write B2B4_0 Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B4_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE4 Segment 4 interrupt enable. (This bit field is meaningful only when IE4_EN is set) 13 2 read-write IE4_0 Generate interrupt on Done0 when segment 4 finish. 0 IE4_1 Generate interrupt on Done1 when segment 4 finish. 0x1 IE4_2 Generate interrupt on Done2 when segment 4 finish. 0x2 IE4_3 Generate interrupt on Done3 when segment 4 finish. 0x3 IE4_EN IRQ enable of segment 4. 15 1 read-write IE4_EN_0 Interrupt DONE disabled. 0 IE4_EN_1 Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4. 0x1 CSEL5 ADC hardware trigger command selection 16 4 read-write CSEL5_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL5_1 ADC CMD1 selected. 0x1 CSEL5_2 ADC CMD2 selected. 0x2 CSEL5_3 ADC CMD3 selected. 0x3 CSEL5_4 ADC CMD4 selected. 0x4 CSEL5_5 ADC CMD5 selected. 0x5 CSEL5_6 ADC CMD6 selected. 0x6 CSEL5_7 ADC CMD7 selected. 0x7 CSEL5_8 ADC CMD8 selected. 0x8 CSEL5_9 ADC CMD9 selected. 0x9 CSEL5_10 ADC CMD10 selected. 0xA CSEL5_11 ADC CMD11 selected. 0xB CSEL5_12 ADC CMD12 selected. 0xC CSEL5_13 ADC CMD13 selected. 0xD CSEL5_14 ADC CMD14 selected. 0xE CSEL5_15 ADC CMD15 selected. 0xF HWTS5 Segment 5 HWTS ADC hardware trigger selection 20 8 read-write HWTS5_0 no trigger selected 0 HWTS5_1 ADC TRIG0 selected 0x1 HWTS5_2 ADC TRIG1 selected 0x2 HWTS5_4 ADC TRIG2 selected 0x4 HWTS5_8 ADC TRIG3 selected 0x8 HWTS5_16 ADC TRIG4 selected 0x10 HWTS5_32 ADC TRIG5 selected 0x20 HWTS5_64 ADC TRIG6 selected 0x40 HWTS5_128 ADC TRIG7 selected 0x80 B2B5 Segment 5 B2B 28 1 read-write B2B5_0 Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B5_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE5 Segment 5 interrupt enable. (This bit field is meaningful only when IE5_EN is set) 29 2 read-write IE5_0 Generate interrupt on Done0 when segment 5 finish. 0 IE5_1 Generate interrupt on Done1 when segment 5 finish. 0x1 IE5_2 Generate interrupt on Done2 when segment 5 finish. 0x2 IE5_3 Generate interrupt on Done3 when segment 5 finish. 0x3 IE5_EN IRQ enable of segment 5. 31 1 read-write IE5_EN_0 Interrupt DONE disabled. 0 IE5_EN_1 Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5. 0x1 TRIG7_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0x13C 32 read-write 0 0xFFFFFFFF CSEL6 ADC hardware trigger command selection 0 4 read-write CSEL6_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL6_1 ADC CMD1 selected. 0x1 CSEL6_2 ADC CMD2 selected. 0x2 CSEL6_3 ADC CMD3 selected. 0x3 CSEL6_4 ADC CMD4 selected. 0x4 CSEL6_5 ADC CMD5 selected. 0x5 CSEL6_6 ADC CMD6 selected. 0x6 CSEL6_7 ADC CMD7 selected. 0x7 CSEL6_8 ADC CMD8 selected. 0x8 CSEL6_9 ADC CMD9 selected. 0x9 CSEL6_10 ADC CMD10 selected. 0xA CSEL6_11 ADC CMD11 selected. 0xB CSEL6_12 ADC CMD12 selected. 0xC CSEL6_13 ADC CMD13 selected. 0xD CSEL6_14 ADC CMD14 selected. 0xE CSEL6_15 ADC CMD15 selected. 0xF HWTS6 Segment 6 HWTS ADC hardware trigger selection 4 8 read-write HWTS6_0 no trigger selected 0 HWTS6_1 ADC TRIG0 selected 0x1 HWTS6_2 ADC TRIG1 selected 0x2 HWTS6_4 ADC TRIG2 selected 0x4 HWTS6_8 ADC TRIG3 selected 0x8 HWTS6_16 ADC TRIG4 selected 0x10 HWTS6_32 ADC TRIG5 selected 0x20 HWTS6_64 ADC TRIG6 selected 0x40 HWTS6_128 ADC TRIG7 selected 0x80 B2B6 Segment 6 B2B 12 1 read-write B2B6_0 Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B6_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE6 Segment 6 interrupt enable. (This bit field is meaningful only when IE6_EN is set) 13 2 read-write IE6_0 Generate interrupt on Done0 when segment 6 finish. 0 IE6_1 Generate interrupt on Done1 when segment 6 finish. 0x1 IE6_2 Generate interrupt on Done2 when segment 6 finish. 0x2 IE6_3 Generate interrupt on Done3 when segment 6 finish. 0x3 IE6_EN IRQ enable of segment 6. 15 1 read-write IE6_EN_0 Interrupt DONE disabled. 0 IE6_EN_1 Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6. 0x1 CSEL7 ADC hardware trigger command selection 16 4 read-write CSEL7_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 CSEL7_1 ADC CMD1 selected. 0x1 CSEL7_2 ADC CMD2 selected. 0x2 CSEL7_3 ADC CMD3 selected. 0x3 CSEL7_4 ADC CMD4 selected. 0x4 CSEL7_5 ADC CMD5 selected. 0x5 CSEL7_6 ADC CMD6 selected. 0x6 CSEL7_7 ADC CMD7 selected. 0x7 CSEL7_8 ADC CMD8 selected. 0x8 CSEL7_9 ADC CMD9 selected. 0x9 CSEL7_10 ADC CMD10 selected. 0xA CSEL7_11 ADC CMD11 selected. 0xB CSEL7_12 ADC CMD12 selected. 0xC CSEL7_13 ADC CMD13 selected. 0xD CSEL7_14 ADC CMD14 selected. 0xE CSEL7_15 ADC CMD15 selected. 0xF HWTS7 Segment 7 HWTS ADC hardware trigger selection 20 8 read-write HWTS7_0 no trigger selected 0 HWTS7_1 ADC TRIG0 selected 0x1 HWTS7_2 ADC TRIG1 selected 0x2 HWTS7_4 ADC TRIG2 selected 0x4 HWTS7_8 ADC TRIG3 selected 0x8 HWTS7_16 ADC TRIG4 selected 0x10 HWTS7_32 ADC TRIG5 selected 0x20 HWTS7_64 ADC TRIG6 selected 0x40 HWTS7_128 ADC TRIG7 selected 0x80 B2B7 Segment 7 B2B 28 1 read-write B2B7_0 Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached 0 B2B7_1 Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. 0x1 IE7 Segment 7 interrupt enable. (This bit field is meaningful only when IE7_EN is set) 29 2 read-write IE7_0 Generate interrupt on Done0 when segment 7 finish. 0 IE7_1 Generate interrupt on Done1 when segment 7 finish. 0x1 IE7_2 Generate interrupt on Done2 when segment 7 finish. 0x2 IE7_3 Generate interrupt on Done3 when segment 7 finish. 0x3 IE7_EN IRQ enable of segment 7. 31 1 read-write IE7_EN_0 Interrupt DONE disabled. 0 IE7_EN_1 Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7. 0x1 TRIG7_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0x140 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA1 Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG7_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0x144 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA3 Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG7_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0x148 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA5 Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only TRIG7_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0x14C 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 0 12 read-only DATA7 Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module 16 12 read-only LPADC1 LPADC ADC ADC 0x40050000 0 0x304 registers ADC1 88 VERID Version ID Register 0 32 read-only 0x100001A 0xFFFFFFFF RES Resolution 0 1 read-only RES_0 Up to 13-bit differential/12-bit single ended resolution supported. 0 RES_1 Up to 16-bit differential/15-bit single ended resolution supported. 0x1 DIFFEN Differential Supported 1 1 read-only DIFFEN_0 Differential operation not supported. 0 DIFFEN_1 Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented. 0x1 MVI Multi Vref Implemented 3 1 read-only MVI_0 Single voltage reference input supported. 0 MVI_1 Multiple voltage reference inputs supported. 0x1 CSW Channel Scale Width 4 3 read-only CSW_0 Channel scaling not supported. 0 CSW_1 Channel scaling supported. 1-bit CSCALE control field. 0x1 CSW_6 Channel scaling supported. 6-bit CSCALE control field. 0x6 VR1RNGI Voltage Reference 1 Range Control Bit Implemented 8 1 read-only VR1RNGI_0 Range control not required. CFG[VREF1RNG] is not implemented. 0 VR1RNGI_1 Range control required. CFG[VREF1RNG] is implemented. 0x1 IADCKI Internal LPADC Clock implemented 9 1 read-only IADCKI_0 Internal clock source not implemented. 0 IADCKI_1 Internal clock source (and CFG[ADCKEN]) implemented. 0x1 CALOFSI Calibration Offset Function Implemented 10 1 read-only CALOFSI_0 Offset calibration and offset trimming not implemented. 0 CALOFSI_1 Offset calibration and offset trimming implemented. 0x1 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0xF041008 0xFFFFFFFF TRIG_NUM Trigger Number 0 8 read-only TRIG_NUM_8 8 hardware triggers implemented 0x8 FIFOSIZE Result FIFO Depth 8 8 read-only FIFOSIZE_16 Result FIFO depth = 16 datawords. 0x10 CV_NUM Compare Value Number 16 8 read-only CV_NUM_4 4 compare value registers implemented 0x4 CMD_NUM Command Buffer Number 24 8 read-only CMD_NUM_15 15 command buffers implemented 0xF CTRL LPADC Control Register 0x10 32 read-write 0 0xFFFFFFFF ADCEN LPADC Enable 0 1 read-write ADCEN_0 LPADC is disabled. 0 ADCEN_1 LPADC is enabled. 0x1 RST Software Reset 1 1 read-write RST_0 LPADC logic is not reset. 0 RST_1 LPADC logic is reset. 0x1 DOZEN Doze Enable 2 1 read-write DOZEN_0 LPADC is enabled in Doze mode. 0 DOZEN_1 LPADC is disabled in Doze mode. 0x1 TRIG_SRC Hardware trigger source selection 3 2 read-write TRIG_SRC_0 ADC_ETC hw trigger , and HW trigger are enabled 0 TRIG_SRC_1 ADC_ETC hw trigger is enabled 0x1 TRIG_SRC_2 HW trigger is enabled 0x2 RSTFIFO Reset FIFO 8 1 read-write RSTFIFO_0 No effect. 0 RSTFIFO_1 FIFO is reset. 0x1 STAT LPADC Status Register 0x14 32 read-write 0 0xFFFFFFFF RDY Result FIFO Ready Flag 0 1 read-only RDY_0 Result FIFO data level not above watermark level. 0 RDY_1 Result FIFO holding data above watermark level. 0x1 FOF Result FIFO Overflow Flag 1 1 read-write oneToClear FOF_0 No result FIFO overflow has occurred since the last time the flag was cleared. 0 FOF_1 At least one result FIFO overflow has occurred since the last time the flag was cleared. 0x1 ADC_ACTIVE ADC Active 8 1 read-only ADC_ACTIVE_0 The LPADC is IDLE. There are no pending triggers to service and no active commands are being processed. 0 ADC_ACTIVE_1 The LPADC is processing a conversion, running through the power up delay, or servicing a trigger. 0x1 TRGACT Trigger Active 16 3 read-only TRGACT_0 Command (sequence) associated with Trigger 0 currently being executed. 0 TRGACT_1 Command (sequence) associated with Trigger 1 currently being executed. 0x1 TRGACT_2 Command (sequence) associated with Trigger 2 currently being executed. 0x2 TRGACT_3 Command (sequence) from the associated Trigger number is currently being executed. 0x3 TRGACT_4 Command (sequence) from the associated Trigger number is currently being executed. 0x4 TRGACT_5 Command (sequence) from the associated Trigger number is currently being executed. 0x5 TRGACT_6 Command (sequence) from the associated Trigger number is currently being executed. 0x6 TRGACT_7 Command (sequence) from the associated Trigger number is currently being executed. 0x7 CMDACT Command Active 24 4 read-only CMDACT_0 No command is currently in progress. 0 CMDACT_1 Command 1 currently being executed. 0x1 CMDACT_2 Command 2 currently being executed. 0x2 CMDACT_3 Associated command number is currently being executed. 0x3 CMDACT_4 Associated command number is currently being executed. 0x4 CMDACT_5 Associated command number is currently being executed. 0x5 CMDACT_6 Associated command number is currently being executed. 0x6 CMDACT_7 Associated command number is currently being executed. 0x7 CMDACT_8 Associated command number is currently being executed. 0x8 CMDACT_9 Associated command number is currently being executed. 0x9 IE Interrupt Enable Register 0x18 32 read-write 0 0xFFFFFFFF FWMIE FIFO Watermark Interrupt Enable 0 1 read-write FWMIE_0 FIFO watermark interrupts are not enabled. 0 FWMIE_1 FIFO watermark interrupts are enabled. 0x1 FOFIE Result FIFO Overflow Interrupt Enable 1 1 read-write FOFIE_0 FIFO overflow interrupts are not enabled. 0 FOFIE_1 FIFO overflow interrupts are enabled. 0x1 DE DMA Enable Register 0x1C 32 read-write 0 0xFFFFFFFF FWMDE FIFO Watermark DMA Enable 0 1 read-write FWMDE_0 DMA request disabled. 0 FWMDE_1 DMA request enabled. 0x1 CFG LPADC Configuration Register 0x20 32 read-write 0x800000 0xFFFFFFFF TPRICTRL LPADC trigger priority control 0 1 read-write TPRICTRL_0 If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. 0 TPRICTRL_1 If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true conversion. 0x1 PWRSEL Power Configuration Select 4 2 read-write PWRSEL_0 Level 1 (Lowest power setting) 0 PWRSEL_1 Level 2 0x1 PWRSEL_2 Level 3 0x2 PWRSEL_3 Level 4 (Highest power setting) 0x3 REFSEL Voltage Reference Selection 6 2 read-write REFSEL_0 (Default) Option 1 setting. 0 REFSEL_1 Option 2 setting. 0x1 REFSEL_2 Option 3 setting. 0x2 PUDLY Power Up Delay 16 8 read-write PWREN LPADC Analog Pre-Enable 28 1 read-write PWREN_0 LPADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. 0 PWREN_1 LPADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed. 0x1 PAUSE LPADC Pause Register 0x24 32 read-write 0 0xFFFFFFFF PAUSEDLY Pause Delay 0 9 read-write PAUSEEN PAUSE Option Enable 31 1 read-write PAUSEEN_0 Pause operation disabled 0 PAUSEEN_1 Pause operation enabled 0x1 FCTRL LPADC FIFO Control Register 0x30 32 read-write 0 0xFFFFFFFF FCOUNT Result FIFO counter 0 5 read-only FCOUNT_0 No data stored in FIFO 0 FCOUNT_1 1 dataword stored in FIFO 0x1 FCOUNT_2 2 datawords stored in FIFO 0x2 FCOUNT_4 4 datawords stored in FIFO 0x4 FCOUNT_8 8 datawords stored in FIFO 0x8 FCOUNT_16 16 datawords stored in FIFO 0x10 FWMARK Watermark level selection 16 4 read-write FWMARK_0 Generates STAT[RDY] flag after 1st successful conversion - single conversion 0 FWMARK_1 Generates STAT[RDY] flag after 2nd successful conversion 0x1 FWMARK_2 Generates STAT[RDY] flag after 3rd successful conversion 0x2 FWMARK_3 Generates STAT[RDY] flag after 4th successful conversion 0x3 FWMARK_4 Generates STAT[RDY] flag after 5th successful conversion 0x4 FWMARK_5 Generates STAT[RDY] flag after 6th successful conversion 0x5 FWMARK_6 Generates STAT[RDY] flag after 7th successful conversion 0x6 FWMARK_7 Generates STAT[RDY] flag after 8th successful conversion 0x7 FWMARK_8 Generates STAT[RDY] flag after 9th successful conversion 0x8 FWMARK_9 Generates STAT[RDY] flag after 10th successful conversion 0x9 FWMARK_10 Generates STAT[RDY] flag after 11th successful conversion 0xA FWMARK_11 Generates STAT[RDY] flag after 12th successful conversion 0xB FWMARK_12 Generates STAT[RDY] flag after 13th successful conversion 0xC FWMARK_13 Generates STAT[RDY] flag after 14th successful conversion 0xD FWMARK_14 Generates STAT[RDY] flag after 15th successful conversion 0xE FWMARK_15 Generates STAT[RDY] flag after 16th successful conversion 0xF SWTRIG Software Trigger Register 0x34 32 read-write 0 0xFFFFFFFF SWT0 Software trigger 0 event 0 1 read-write SWT0_0 No trigger 0 event generated. 0 SWT0_1 Trigger 0 event generated. 0x1 SWT1 Software trigger 1 event 1 1 read-write SWT1_0 No trigger 1 event generated. 0 SWT1_1 Trigger 1 event generated. 0x1 SWT2 Software trigger 2 event 2 1 read-write SWT2_0 No trigger 2 event generated. 0 SWT2_1 Trigger 2 event generated. 0x1 SWT3 Software trigger 3 event 3 1 read-write SWT3_0 No trigger 3 event generated. 0 SWT3_1 Trigger 3 event generated. 0x1 SWT4 Software trigger 4 event 4 1 read-write SWT4_0 No trigger 4 event generated. 0 SWT4_1 Trigger 4 event generated. 0x1 SWT5 Software trigger 5 event 5 1 read-write SWT5_0 No trigger 5 event generated. 0 SWT5_1 Trigger 5 event generated. 0x1 SWT6 Software trigger 6 event 6 1 read-write SWT6_0 No trigger 6 event generated. 0 SWT6_1 Trigger 6 event generated. 0x1 SWT7 Software trigger 7 event 7 1 read-write SWT7_0 No trigger 7 event generated. 0 SWT7_1 Trigger 7 event generated. 0x1 8 0x4 TCTRL[%s] Trigger Control Register 0xC0 32 read-write 0 0xFFFFFFFF HTEN Trigger enable 0 1 read-write HTEN_0 Hardware trigger source disabled 0 HTEN_1 Hardware trigger source enabled 0x1 CMD_SEL The command number is selected by software TCMD or hardware tcmd signal 1 1 read-write CMD_SEL_0 TCTRLa[TCMD] will determine the command 0 CMD_SEL_1 Software TCDM is bypassed , and hardware TCMD from ADC_ETC module will be used. The trigger command is then defined by ADC hardware trigger command selection field in ADC_ETC->TRIGx_CHAINy_z_n[CSEL]. 0x1 TPRI Trigger priority setting 8 3 read-write TPRI_0 Set to highest priority, Level 1 0 TPRI_1 Set to corresponding priority level 0x1 TPRI_2 Set to corresponding priority level 0x2 TPRI_3 Set to corresponding priority level 0x3 TPRI_4 Set to corresponding priority level 0x4 TPRI_5 Set to corresponding priority level 0x5 TPRI_6 Set to corresponding priority level 0x6 TPRI_7 Set to lowest priority, Level 8 0x7 TDLY Trigger delay select 16 4 read-write TCMD Trigger command select 24 4 read-write TCMD_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 TCMD_1 CMD1 is executed 0x1 TCMD_2 Corresponding CMD is executed 0x2 TCMD_3 Corresponding CMD is executed 0x3 TCMD_4 Corresponding CMD is executed 0x4 TCMD_5 Corresponding CMD is executed 0x5 TCMD_6 Corresponding CMD is executed 0x6 TCMD_7 Corresponding CMD is executed 0x7 TCMD_8 Corresponding CMD is executed 0x8 TCMD_9 Corresponding CMD is executed 0x9 TCMD_15 CMD15 is executed 0xF CMDL1 LPADC Command Low Buffer Register 0x100 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH1 LPADC Command High Buffer Register 0x104 32 read-write 0 0xFFFFFFFF CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL2 LPADC Command Low Buffer Register 0x108 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH2 LPADC Command High Buffer Register 0x10C 32 read-write 0 0xFFFFFFFF CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL3 LPADC Command Low Buffer Register 0x110 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH3 LPADC Command High Buffer Register 0x114 32 read-write 0 0xFFFFFFFF CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL4 LPADC Command Low Buffer Register 0x118 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH4 LPADC Command High Buffer Register 0x11C 32 read-write 0 0xFFFFFFFF CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL5 LPADC Command Low Buffer Register 0x120 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH5 LPADC Command High Buffer Register 0x124 32 read-write 0 0xFFFFFFFF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL6 LPADC Command Low Buffer Register 0x128 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH6 LPADC Command High Buffer Register 0x12C 32 read-write 0 0xFFFFFFFF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL7 LPADC Command Low Buffer Register 0x130 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH7 LPADC Command High Buffer Register 0x134 32 read-write 0 0xFFFFFFFF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL8 LPADC Command Low Buffer Register 0x138 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH8 LPADC Command High Buffer Register 0x13C 32 read-write 0 0xFFFFFFFF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL9 LPADC Command Low Buffer Register 0x140 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH9 LPADC Command High Buffer Register 0x144 32 read-write 0 0xFFFFFFFF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL10 LPADC Command Low Buffer Register 0x148 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH10 LPADC Command High Buffer Register 0x14C 32 read-write 0 0xFFFFFFFF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL11 LPADC Command Low Buffer Register 0x150 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH11 LPADC Command High Buffer Register 0x154 32 read-write 0 0xFFFFFFFF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL12 LPADC Command Low Buffer Register 0x158 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH12 LPADC Command High Buffer Register 0x15C 32 read-write 0 0xFFFFFFFF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL13 LPADC Command Low Buffer Register 0x160 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH13 LPADC Command High Buffer Register 0x164 32 read-write 0 0xFFFFFFFF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL14 LPADC Command Low Buffer Register 0x168 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH14 LPADC Command High Buffer Register 0x16C 32 read-write 0 0xFFFFFFFF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL15 LPADC Command Low Buffer Register 0x170 32 read-write 0x2000 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0 ABSEL_1 When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). 0x1 DIFF Differential Mode Enable 6 1 read-write DIFF_0 Single-ended mode. 0 DIFF_1 Differential mode. 0x1 CSCALE Channel Scale 13 1 read-write CSCALE_0 Scale selected analog channel (Factor of 30/64) 0 CSCALE_1 (Default) Full scale (Factor of 1) 0x1 CMDH15 LPADC Command High Buffer Register 0x174 32 read-write 0 0xFFFFFFFF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF 4 0x4 1,2,3,4 CV%s Compare Value Register 0x200 32 read-write 0 0xFFFFFFFF CVL Compare Value Low 0 16 read-write CVH Compare Value High. 16 16 read-write RESFIFO LPADC Data Result FIFO Register 0x300 32 read-only 0 0xFFFFFFFF D Data result 0 16 read-only TSRC Trigger Source 16 3 read-only TSRC_0 Trigger source 0 initiated this conversion. 0 TSRC_1 Trigger source 1 initiated this conversion. 0x1 TSRC_2 Corresponding trigger source initiated this conversion. 0x2 TSRC_3 Corresponding trigger source initiated this conversion. 0x3 TSRC_4 Corresponding trigger source initiated this conversion. 0x4 TSRC_5 Corresponding trigger source initiated this conversion. 0x5 TSRC_6 Corresponding trigger source initiated this conversion. 0x6 TSRC_7 Trigger source 7 initiated this conversion. 0x7 LOOPCNT Loop count value 20 4 read-only LOOPCNT_0 Result is from initial conversion in command. 0 LOOPCNT_1 Result is from second conversion in command. 0x1 LOOPCNT_2 Result is from LOOPCNT+1 conversion in command. 0x2 LOOPCNT_3 Result is from LOOPCNT+1 conversion in command. 0x3 LOOPCNT_4 Result is from LOOPCNT+1 conversion in command. 0x4 LOOPCNT_5 Result is from LOOPCNT+1 conversion in command. 0x5 LOOPCNT_6 Result is from LOOPCNT+1 conversion in command. 0x6 LOOPCNT_7 Result is from LOOPCNT+1 conversion in command. 0x7 LOOPCNT_8 Result is from LOOPCNT+1 conversion in command. 0x8 LOOPCNT_9 Result is from LOOPCNT+1 conversion in command. 0x9 LOOPCNT_15 Result is from 16th conversion in command. 0xF CMDSRC Command Buffer Source 24 4 read-only CMDSRC_0 Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. 0 CMDSRC_1 CMD1 buffer used as control settings for this conversion. 0x1 CMDSRC_2 Corresponding command buffer used as control settings for this conversion. 0x2 CMDSRC_3 Corresponding command buffer used as control settings for this conversion. 0x3 CMDSRC_4 Corresponding command buffer used as control settings for this conversion. 0x4 CMDSRC_5 Corresponding command buffer used as control settings for this conversion. 0x5 CMDSRC_6 Corresponding command buffer used as control settings for this conversion. 0x6 CMDSRC_7 Corresponding command buffer used as control settings for this conversion. 0x7 CMDSRC_8 Corresponding command buffer used as control settings for this conversion. 0x8 CMDSRC_9 Corresponding command buffer used as control settings for this conversion. 0x9 CMDSRC_15 CMD15 buffer used as control settings for this conversion. 0xF VALID FIFO entry is valid 31 1 read-only VALID_0 FIFO is empty. Discard any read from RESFIFO. 0 VALID_1 FIFO record read from RESFIFO is valid. 0x1 LPADC2 LPADC ADC 0x40054000 0 0x304 registers ADC2 89 DAC DAC DAC 0x40064000 0 0x18 registers DAC 63 VERID Version Identifier Register 0 32 read-only 0x1000000 0xFFFFFFFF FEATURE Feature Identification Number 0 16 read-only FEATURE_0 Standard feature set 0 FEATURE_1 C40 feature set 0x1 FEATURE_2 5V DAC feature set 0x2 FEATURE_4 ADC BIST feature set 0x4 MINOR Minor version number 16 8 read-only MAJOR Major version number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x3 0xFFFFFFFF FIFOSZ FIFO size 0 3 read-only FIFOSZ_0 FIFO depth is 2 0 FIFOSZ_1 FIFO depth is 4 0x1 FIFOSZ_2 FIFO depth is 8 0x2 FIFOSZ_3 FIFO depth is 16 0x3 FIFOSZ_4 FIFO depth is 32 0x4 FIFOSZ_5 FIFO depth is 64 0x5 FIFOSZ_6 FIFO depth is 128 0x6 FIFOSZ_7 FIFO depth is 256 0x7 DATA DAC Data Register 0x8 32 write-only 0 0xFFFFFFFF DATA0 FIFO DATA0 0 12 write-only CR DAC Status and Control Register 0xC 32 read-write 0x2 0xFFFFFFFF FULLF Full Flag 0 1 read-write FULLF_0 FIFO is not full. 0 FULLF_1 FIFO is full. 0x1 NEMPTF Nearly Empty Flag 1 1 read-write NEMPTF_0 More than one data is available in the FIFO. 0 NEMPTF_1 One data is available in the FIFO. 0x1 WMF FIFO Watermark Status Flag 2 1 read-write WMF_0 The DAC buffer read pointer has not reached the watermark level. 0 WMF_1 The DAC buffer read pointer has reached the watermark level. 0x1 UDFF Underflow Flag 3 1 read-write UDFF_0 No underflow has occurred since the last time the flag was cleared. 0 UDFF_1 At least one trigger underflow has occurred since the last time the flag was cleared. 0x1 OVFF Overflow Flag 4 1 read-write OVFF_0 No overflow has occurred since the last time the flag was cleared. 0 OVFF_1 At least one FIFO overflow has occurred since the last time the flag was cleared. 0x1 FULLIE Full Interrupt Enable 8 1 read-write FULLIE_0 FIFO Full interrupt is disabled. 0 FULLIE_1 FIFO Full interrupt is enabled. 0x1 EMPTIE Nearly Empty Interrupt Enable 9 1 read-write EMPTIE_0 FIFO Nearly Empty interrupt is disabled. 0 EMPTIE_1 FIFO Nearly Empty interrupt is enabled. 0x1 WTMIE Watermark Interrupt Enable 10 1 read-write WTMIE_0 Watermark interrupt is disabled. 0 WTMIE_1 Watermark interrupt is enabled. 0x1 SWTRG DAC Software Trigger 12 1 read-write SWTRG_0 The DAC soft trigger is not valid. 0 SWTRG_1 The DAC soft trigger is valid. 0x1 TRGSEL DAC Trigger Select 13 1 read-write TRGSEL_0 The DAC hardware trigger is selected. 0 TRGSEL_1 The DAC software trigger is selected. 0x1 DACRFS DAC Reference Select 14 1 read-write DACRFS_0 The DAC selects DACREF_1 as the reference voltage. 0 DACRFS_1 The DAC selects DACREF_2 as the reference voltage. 0x1 DACEN DAC Enable 15 1 read-write DACEN_0 The DAC system is disabled. 0 DACEN_1 The DAC system is enabled. 0x1 FIFOEN FIFO Enable 16 1 read-write FIFOEN_0 FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion. 0 FIFOEN_1 FIFO is enabled. Data will first read from FIFO to buffer then go to conversion. 0x1 SWMD DAC FIFO Mode Select 17 1 read-write SWMD_0 Normal mode 0 SWMD_1 Swing back mode 0x1 UVIE Underflow and overflow interrupt enable 18 1 read-write UVIE_0 Underflow and overflow interrupt is disabled. 0 UVIE_1 Underflow and overflow interrupt is enabled. 0x1 FIFORST FIFO Reset 21 1 read-write FIFORST_0 No effect 0 FIFORST_1 FIFO reset 0x1 SWRST Software reset 22 1 read-write DMAEN DMA Enable Select 23 1 read-write DMAEN_0 DMA is disabled. 0 DMAEN_1 DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. 0x1 WML Watermark Level Select 24 8 read-write PTR DAC FIFO Pointer Register 0x10 32 read-only 0 0xFFFFFFFF DACWFP DACWFP 0 8 read-only DACRFP DACRFP 16 8 read-only CR2 DAC Status and Control Register 2 0x14 32 read-write 0 0xFFFFFFFF BFEN Buffer Enable 0 1 read-write BFEN_0 Opamp is not used as buffer 0 BFEN_1 Opamp is used as buffer 0x1 OEN Optional Enable 1 1 read-write OEN_0 Output buffer is not bypassed 0 OEN_1 Output buffer is bypassed 0x1 BFMS Buffer Middle Speed Select 2 1 read-write BFMS_0 Buffer middle speed not selected 0 BFMS_1 Buffer middle speed selected 0x1 BFHS Buffer High Speed Select 3 1 read-write BFHS_0 Buffer high speed not selected 0 BFHS_1 Buffer high speed selected 0x1 IREF2 Internal PTAT (Proportional To Absolute Temperature) Current Reference Select 4 1 read-write IREF2_0 Internal PTAT Current Reference not selected 0 IREF2_1 Internal PTAT Current Reference selected 0x1 IREF1 Internal ZTC (Zero Temperature Coefficient) Current Reference Select 5 1 read-write IREF1_0 Internal ZTC Current Reference not selected 0 IREF1_1 Internal ZTC Current Reference selected 0x1 IREF Internal Current Reference Select 6 1 read-write IREF_0 Internal Current Reference not selected 0 IREF_1 Internal Current Reference selected 0x1 IEE_APC IEE_APC IEE_APC 0x40068000 0 0x80 registers REGION0_TOP_ADDR End address of IEE region (n) 0 32 read-write 0 0xFFFFFFFF TOP_ADDR End address of IEE region 0 29 read-write REGION0_BOT_ADDR Start address of IEE region (n) 0x4 32 read-write 0 0xFFFFFFFF BOT_ADDR Start address of IEE region 0 29 read-write REGION0_RDC_D0 Region control of core domain 0 for region (n) 0x8 32 read-write 0 0xFFFFFFFF RDC_D0_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D0_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION0_RDC_D1 Region control of core domain 1 for region (n) 0xC 32 read-write 0 0xFFFFFFFF RDC_D1_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D1_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION1_TOP_ADDR End address of IEE region (n) 0x10 32 read-write 0 0xFFFFFFFF TOP_ADDR End address of IEE region 0 29 read-write REGION1_BOT_ADDR Start address of IEE region (n) 0x14 32 read-write 0 0xFFFFFFFF BOT_ADDR Start address of IEE region 0 29 read-write REGION1_RDC_D0 Region control of core domain 0 for region (n) 0x18 32 read-write 0 0xFFFFFFFF RDC_D0_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D0_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION1_RDC_D1 Region control of core domain 1 for region (n) 0x1C 32 read-write 0 0xFFFFFFFF RDC_D1_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D1_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION2_TOP_ADDR End address of IEE region (n) 0x20 32 read-write 0 0xFFFFFFFF TOP_ADDR End address of IEE region 0 29 read-write REGION2_BOT_ADDR Start address of IEE region (n) 0x24 32 read-write 0 0xFFFFFFFF BOT_ADDR Start address of IEE region 0 29 read-write REGION2_RDC_D0 Region control of core domain 0 for region (n) 0x28 32 read-write 0 0xFFFFFFFF RDC_D0_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D0_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION2_RDC_D1 Region control of core domain 1 for region (n) 0x2C 32 read-write 0 0xFFFFFFFF RDC_D1_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D1_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION3_TOP_ADDR End address of IEE region (n) 0x30 32 read-write 0 0xFFFFFFFF TOP_ADDR End address of IEE region 0 29 read-write REGION3_BOT_ADDR Start address of IEE region (n) 0x34 32 read-write 0 0xFFFFFFFF BOT_ADDR Start address of IEE region 0 29 read-write REGION3_RDC_D0 Region control of core domain 0 for region (n) 0x38 32 read-write 0 0xFFFFFFFF RDC_D0_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D0_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION3_RDC_D1 Region control of core domain 1 for region (n) 0x3C 32 read-write 0 0xFFFFFFFF RDC_D1_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D1_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION4_TOP_ADDR End address of IEE region (n) 0x40 32 read-write 0 0xFFFFFFFF TOP_ADDR End address of IEE region 0 29 read-write REGION4_BOT_ADDR Start address of IEE region (n) 0x44 32 read-write 0 0xFFFFFFFF BOT_ADDR Start address of IEE region 0 29 read-write REGION4_RDC_D0 Region control of core domain 0 for region (n) 0x48 32 read-write 0 0xFFFFFFFF RDC_D0_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D0_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION4_RDC_D1 Region control of core domain 1 for region (n) 0x4C 32 read-write 0 0xFFFFFFFF RDC_D1_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D1_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION5_TOP_ADDR End address of IEE region (n) 0x50 32 read-write 0 0xFFFFFFFF TOP_ADDR End address of IEE region 0 29 read-write REGION5_BOT_ADDR Start address of IEE region (n) 0x54 32 read-write 0 0xFFFFFFFF BOT_ADDR Start address of IEE region 0 29 read-write REGION5_RDC_D0 Region control of core domain 0 for region (n) 0x58 32 read-write 0 0xFFFFFFFF RDC_D0_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D0_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION5_RDC_D1 Region control of core domain 1 for region (n) 0x5C 32 read-write 0 0xFFFFFFFF RDC_D1_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D1_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION6_TOP_ADDR End address of IEE region (n) 0x60 32 read-write 0 0xFFFFFFFF TOP_ADDR End address of IEE region 0 29 read-write REGION6_BOT_ADDR Start address of IEE region (n) 0x64 32 read-write 0 0xFFFFFFFF BOT_ADDR Start address of IEE region 0 29 read-write REGION6_RDC_D0 Region control of core domain 0 for region (n) 0x68 32 read-write 0 0xFFFFFFFF RDC_D0_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D0_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION6_RDC_D1 Region control of core domain 1 for region (n) 0x6C 32 read-write 0 0xFFFFFFFF RDC_D1_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D1_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION7_TOP_ADDR End address of IEE region (n) 0x70 32 read-write 0 0xFFFFFFFF TOP_ADDR End address of IEE region 0 29 read-write REGION7_BOT_ADDR Start address of IEE region (n) 0x74 32 read-write 0 0xFFFFFFFF BOT_ADDR Start address of IEE region 0 29 read-write REGION7_RDC_D0 Region control of core domain 0 for region (n) 0x78 32 read-write 0 0xFFFFFFFF RDC_D0_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D0_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 REGION7_RDC_D1 Region control of core domain 1 for region (n) 0x7C 32 read-write 0 0xFFFFFFFF RDC_D1_WRITE_DIS Write disable of core domain 1 0 1 read-write ENABLE Write to TOP_ADDR and BOT_ADDR of this region enabled 0 DISABLE Write to TOP_ADDR and BOT_ADDR of this region disabled 0x1 RDC_D1_LOCK Lock bit for bit 0 1 1 read-writeOnce UNLOCK Bit 0 is unlocked 0 LOCK Bit 0 is locked 0x1 IEE__IEE_RT1170 IEE IEE 0x4006C000 0 0x10000000 registers GCFG IEE Global Configuration 0 32 read-write 0 0xFFFFFFFF RL0 Region lock 0 bit 0 1 read-write RL0_0 Unlocked. 0 RL0_1 Key, Offset and Attribute registers are locked. 0x1 RL1 Region lock 1 bit 1 1 read-write RL1_0 Unlocked. 0 RL1_1 Key, Offset and Attribute registers are locked. 0x1 RL2 Region lock 2 bit 2 1 read-write RL2_0 Unlocked. 0 RL2_1 Key, Offset and Attribute registers are locked. 0x1 RL3 Region lock 3 bit 3 1 read-write RL3_0 Unlocked. 0 RL3_1 Key, Offset and Attribute registers are locked. 0x1 RL4 Region lock 4 bit 4 1 read-write RL4_0 Unlocked. 0 RL4_1 Key, Offset and Attribute registers are locked. 0x1 RL5 Region lock 5 bit 5 1 read-write RL5_0 Unlocked. 0 RL5_1 Key, Offset and Attribute registers are locked. 0x1 RL6 Region lock 6 bit 6 1 read-write RL6_0 Unlocked. 0 RL6_1 Key, Offset and Attribute registers are locked. 0x1 RL7 Region lock 7 bit 7 1 read-write RL7_0 Unlocked. 0 RL7_1 Key, Offset and Attribute registers are locked. 0x1 TME Test mode enable bit 16 1 read-write TME_0 Disabled. 0 TME_1 Enabled. 0x1 TMD Test mode disable bit 17 1 read-write TMD_0 Test mode is usable. 0 TMD_1 Test mode is disabled. 0x1 KEY_RD_DIS Key read disable bit 25 1 read-write KEY_RD_DIS_0 Key read enabled. Reading the key registers is allowed. 0 KEY_RD_DIS_1 Key read disabled. Reading the key registers is disabled. 0x1 MON_EN Monitor enable bit 28 1 read-write MON_EN_0 Performance monitoring disabled. Writing of the performance counter registers is enabled. 0 MON_EN_1 Performance monitoring enabled. Writing of the performance counter registers is disabled. 0x1 CLR_MON Clear monitor bit 29 1 write-only CLR_MON_0 Do not reset. 0 CLR_MON_1 Reset performance counters. 0x1 RST Reset bit 31 1 write-only RST_0 Do Not Reset. 0 RST_1 Reset IEE. 0x1 STA IEE Status 0x4 32 read-only 0x1 0xFFFFFFFF DSR DPA seed request bit 0 1 read-only DSR_0 No seed request present 0 DSR_1 Seed request present 0x1 AFD AES fault detected bit 4 1 read-only AFD_0 No fault detected 0 AFD_1 Fault detected 0x1 TSTMD IEE Test Mode Register 0x8 32 read-write 0 0xFFFFFFFF TMRDY Test mode ready bit. All AXI transactions have stopped and test can begin. 0 1 read-only TMRDY_0 Not Ready. 0 TMRDY_1 Ready. 0x1 TMR Test mode run bit 1 1 read-write TMR_0 Not running. May be written if IEE_GCFG[TME] = 1 0 TMR_1 Run AES Test until TMDONE is indicated. 0x1 TMENCR Test mode encrypt/decrypt bit. 2 1 read-write TMENCR_0 AES Test mode will do decryption. 0 TMENCR_1 AES Test mode will do encryption. 0x1 TMCONT Test mode continue bit. Set to indicate that operation will be followed by more data. 3 1 read-write TMCONT_0 Do not continue. This is the last block of data for AES. 0 TMCONT_1 Continue. Do not initialize AES after this block. 0x1 TMDONE Test mode done bit 4 1 read-only TMDONE_0 Not Done. 0 TMDONE_1 Test Done. 0x1 TMLEN Test mode length field 8 4 read-write DPAMS AES Mask Generation Seed 0xC 32 write-only 0 0xFFFFFFFF DPAMS DPA mask seed 0 32 write-only PC_S_LT Performance Counter, AES Slave Latency Threshold Value 0x20 32 read-write 0 0xFFFFFFFF SW_LT Slave write latency threshold in AXI clock cycles. 0 16 read-write SR_LT Slave read latency threshold in AXI clock cycles. 16 16 read-write PC_M_LT Performance Counter, AES Master Latency Threshold 0x24 32 read-write 0 0xFFFFFFFF MW_LT Master write latency threshold in AXI clock cycles. 0 12 read-write MR_LT Master read latency threshold in AXI clock cycles. 16 12 read-write PC_BLK_ENC Performance Counter, Number of AES Block Encryptions 0x40 32 read-write 0 0xFFFFFFFF BLK_ENC Number of AES block encryptions. Does not roll over if value maxes out. 0 32 read-write PC_BLK_DEC Performance Counter, Number of AES Block Decryptions 0x44 32 read-write 0 0xFFFFFFFF BLK_DEC Number of AES block decryptions. Does not roll over if value maxes out. 0 32 read-write PC_SR_TRANS Performance Counter, Number of AXI Slave Read Transactions 0x50 32 read-write 0 0xFFFFFFFF SR_TRANS Number of slave read transactions. 0 32 read-write PC_SW_TRANS Performance Counter, Number of AXI Slave Write Transactions 0x54 32 read-write 0 0xFFFFFFFF SW_TRANS Number of slave write transactions. 0 32 read-write PC_MR_TRANS Performance Counter, Number of AXI Master Read Transactions 0x58 32 read-write 0 0xFFFFFFFF MR_TRANS Number of master read transactions. 0 32 read-write PC_MW_TRANS Performance Counter, Number of AXI Master Write Transactions 0x5C 32 read-write 0 0xFFFFFFFF MW_TRANS Number of master write transactions. 0 32 read-write PC_M_MBR Performance Counter, Number of AXI Master Merge Buffer Read Transactions 0x64 32 read-write 0 0xFFFFFFFF M_MBR Number of master merge buffer read transactions. 0 32 read-write PC_SR_TBC_U Performance Counter, Upper Slave Read Transactions Byte Count 0x70 32 read-write 0 0xFFFFFFFF SR_TBC Number of bytes in slave read transactions. Upper 16 bits of SR_TBC[47:0]. 0 16 read-write PC_SR_TBC_L Performance Counter, Lower Slave Read Transactions Byte Count 0x74 32 read-write 0 0xFFFFFFFF SR_TBC Number of bytes in slave read transactions. Lower 32 bits of SR_TBC[47:0]. 0 32 read-write PC_SW_TBC_U Performance Counter, Upper Slave Write Transactions Byte Count 0x78 32 read-write 0 0xFFFFFFFF SW_TBC Number of bytes in slave write transactions. Upper 16 bits of SW_TBC[47:0]. 0 16 read-write PC_SW_TBC_L Performance Counter, Lower Slave Write Transactions Byte Count 0x7C 32 read-write 0 0xFFFFFFFF SW_TBC Number of bytes in slave write transactions. Lower 32 bits of SW_TBC[47:0]. 0 32 read-write PC_MR_TBC_U Performance Counter, Upper Master Read Transactions Byte Count 0x80 32 read-write 0 0xFFFFFFFF MR_TBC Number of bytes in master read transactions. 44 MSBs. Upper 16 bits of MR_TBC[43:0]. 0 16 read-write PC_MR_TBC_L Performance Counter, Lower Master Read Transactions Byte Count 0x84 32 read-write 0 0xFFFFFFFF MR_TBC_LSB Number of bytes in master read transactions. 4 LSBs, always 0. 0 4 read-only MR_TBC Number of bytes in master read transactions. 44 MSBs. Lower 28 bits of MR_TBC[43:0]. 4 28 read-write PC_MW_TBC_U Performance Counter, Upper Master Write Transactions Byte Count 0x88 32 read-write 0 0xFFFFFFFF MW_TBC Number of bytes in master write transactions. 44 MSBs. Upper 16 bits of MW_TBC[43:0]. 0 16 read-write PC_MW_TBC_L Performance Counter, Lower Master Write Transactions Byte Count 0x8C 32 read-write 0 0xFFFFFFFF MW_TBC_LSB Number of bytes in master write transactions. 4 LSBs, always 0. 0 4 read-only MW_TBC Number of bytes in master write transactions. 44 MSBs. Lower 28 bits of MR_TBC[43:0]. 4 28 read-write PC_SR_TLGTT Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold 0x90 32 read-write 0 0xFFFFFFFF SR_TLGTT Number of slave read transactions with latency greater than the threshold. 0 32 read-write PC_SW_TLGTT Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold 0x94 32 read-write 0 0xFFFFFFFF SW_TLGTT Number of slave write transactions with latency greater than the threshold. 0 32 read-write PC_MR_TLGTT Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold 0x98 32 read-write 0 0xFFFFFFFF MR_TLGTT Number of master read transactions with latency greater than the threshold. 0 32 read-write PC_MW_TLGTT Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold 0x9C 32 read-write 0 0xFFFFFFFF MW_TGTT Number of master write transactions with latency greater than the threshold. 0 32 read-write PC_SR_TLAT_U Performance Counter, Upper Slave Read Latency Count 0xA0 32 read-write 0 0xFFFFFFFF SR_TLAT Total slave read latency in AXI clock cycles. Upper 16 bits of SR_TLAT[47:0]. 0 16 read-write PC_SR_TLAT_L Performance Counter, Lower Slave Read Latency Count 0xA4 32 read-write 0 0xFFFFFFFF SR_TLAT Total slave read latency in AXI clock cycles. Lower 32 bits of SR_TLAT[47:0]. 0 32 read-write PC_SW_TLAT_U Performance Counter, Upper Slave Write Latency Count 0xA8 32 read-write 0 0xFFFFFFFF SW_TLAT Total slave write latency in AXI clock cycles. Upper 16 bits of SW_TLAT[47:0]. 0 16 read-write PC_SW_TLAT_L Performance Counter, Lower Slave Write Latency Count 0xAC 32 read-write 0 0xFFFFFFFF SW_TLAT Total slave write latency in AXI clock cycles. Lower 32 bits of SW_TLAT[47:0]. 0 32 read-write PC_MR_TLAT_U Performance Counter, Upper Master Read Latency Count 0xB0 32 read-write 0 0xFFFFFFFF MR_TLAT Total master read latency in AXI clock cycles. Upper 16 bits of MR_TLAT[47:0]. 0 16 read-write PC_MR_TLAT_L Performance Counter, Lower Master Read Latency Count 0xB4 32 read-write 0 0xFFFFFFFF MR_TLAT Total master read latency in AXI clock cycles. Lower 32 bits of MR_TLAT[47:0]. 0 32 read-write PC_MW_TLAT_U Performance Counter, Upper Master Write Latency Count 0xB8 32 read-write 0 0xFFFFFFFF MW_TLAT Total master write latency in AXI clock cycles. Upper 16 bits of MW_TLAT[47:0]. 0 16 read-write PC_MW_TLAT_L Performance Counter, Lower Master Write Latency Count 0xBC 32 read-write 0 0xFFFFFFFF MW_TLAT Total master write latency in AXI clock cycles. Lower 32 bits of MW_TLAT[47:0]. 0 32 read-write PC_SR_TNRT_U Performance Counter, Upper Slave Read Total Non-Responding Time 0xC0 32 read-write 0 0xFFFFFFFF SR_TNRT Total slave read non-responding time in AXI clock cycles. Upper 16 bits of SR_TNRT[47:0]. 0 16 read-write PC_SR_TNRT_L Performance Counter, Lower Slave Read Total Non-Responding Time 0xC4 32 read-write 0 0xFFFFFFFF SR_TNRT Total slave read non-responding time in AXI clock cycles. Lower 32 bits of SR_TNRT[47:0]. 0 32 read-write PC_SW_TNRT_U Performance Counter, Upper Slave Write Total Non-Responding Time 0xC8 32 read-write 0 0xFFFFFFFF SW_TNRT Total slave write non-responding time in AXI clock cycles. Upper 16 bits of SW_TNRT[47:0]. 0 16 read-write PC_SW_TNRT_L Performance Counter, Lower Slave Write Total Non-Responding Time 0xCC 32 read-write 0 0xFFFFFFFF SW_TNRT Total slave write non-responding time in AXI clock cycles. Lower 32 bits of SW_TNRT[47:0]. 0 32 read-write VIDR1 IEE Version ID Register 1 0xF0 32 read-only 0x340102 0xFFFFFFFF MIN_REV Minor revision number for IEE. 0 8 read-only MAJ_REV Major revision number for IEE. 8 8 read-only IP_ID ID for IEE. 16 16 read-only AESVID IEE AES Version ID Register 0xF8 32 read-only 0x20 0xFFFFFFFF AESRN AES revision number. 0 4 read-only AESVID AES version ID. 4 4 read-only 8 0x100 REGx[%s] Region Registers 0x100 REGATTR IEE Region REGION Attribute Register. 0 32 read-write 0 0xFFFFFFFF KS AES key size. 0 1 read-write KS_0 128 bits (CTR), 256 bits (XTS). 0 KS_1 256 bits (CTR), 512 bits (XTS). 0x1 MD AES Mode. 4 3 read-write MD_0 None (AXI error if accessed) 0 MD_1 XTS 0x1 MD_2 CTR w/ address binding 0x2 MD_3 CTR w/o address binding 0x3 MD_4 CTR keystream only 0x4 MD_5 Undefined, AXI error if used 0x5 MD_6 Undefined, AXI error if used 0x6 MD_7 Undefined, AXI error if used 0x7 BYP AES Bypass. 7 1 read-write BYP_0 use MD field 0 BYP_1 Bypass AES, no encrypt/decrypt 0x1 REGPO IEE Region REGION Page Offset Register 0x8 32 read-write 0 0xFFFFFFFF PGOFF This field represents a 4Kb page offset 0 24 read-write 8 0x4 0,1,2,3,4,5,6,7 REGKEY1_%s IEE Region REGION Key 1 Register 0x40 32 write-only 0 0xFFFFFFFF KEY1 Key 1. 0 32 write-only 8 0x4 0,1,2,3,4,5,6,7 REGKEY2_%s IEE Region REGION Key 2 Register 0x80 32 write-only 0 0xFFFFFFFF KEY2 Key 2. 0 32 write-only 32 0x4 AES_TST_DB[%s] IEE AES Test Mode Data Buffer 0xF00 32 read-write 0 0xFFFFFFFF AES_TST_DB0 AES test mode data buffer. 0 32 read-write DMA0 DMA DMA 0x40070000 0 0x1400 registers DMA0_DMA16 0 DMA1_DMA17 1 DMA2_DMA18 2 DMA3_DMA19 3 DMA4_DMA20 4 DMA5_DMA21 5 DMA6_DMA22 6 DMA7_DMA23 7 DMA8_DMA24 8 DMA9_DMA25 9 DMA10_DMA26 10 DMA11_DMA27 11 DMA12_DMA28 12 DMA13_DMA29 13 DMA14_DMA30 14 DMA15_DMA31 15 DMA_ERROR 16 CR Control 0 32 read-write 0x400 0x80FFFFFF EDBG Enable Debug 1 1 read-write DISABLED When the chip is in Debug mode, the eDMA continues to operate. 0 ENABLED When the chip is in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. 0x1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write DISABLED Fixed priority arbitration within each group 0 ENABLED Round robin arbitration within each group 0x1 ERGA Enable Round Robin Group Arbitration 3 1 read-write DISABLED Fixed priority arbitration 0 ENABLED Round robin arbitration 0x1 HOE Halt On Error 4 1 read-write NORMAL_OPS Normal operation 0 HALT_ON_ERROR Error causes HALT field to be automatically set to 1 0x1 HALT Halt eDMA Operations 5 1 read-write NORMAL_OPS Normal operation 0 HALT_DMA eDMA operations halted 0x1 CLM Continuous Link Mode 6 1 read-write CLM_OFF Continuous link mode is off 0 CLM_ON Continuous link mode is on 0x1 EMLM Enable Minor Loop Mapping 7 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 GRP0PRI Channel Group 0 Priority 8 1 read-write GRP1PRI Channel Group 1 Priority 10 1 read-write ECX Error Cancel Transfer 16 1 read-write NORMAL_OPS Normal operation 0 CANCEL Cancel the remaining data transfer 0x1 CX Cancel Transfer 17 1 read-write NORMAL_OPS Normal operation 0 CANCEL Cancel the remaining data transfer 0x1 VERSION eDMA version number 24 7 read-only ACTIVE eDMA Active Status 31 1 read-only IDLE eDMA is idle 0 ACTIVE eDMA is executing a channel 0x1 ES Error Status 0x4 32 read-only 0 0xFFFFFFFF DBE Destination Bus Error 0 1 read-only NO_ERROR No destination bus error. 0 ERROR The most-recently recorded error was a bus error on a destination write. 0x1 SBE Source Bus Error 1 1 read-only NO_ERROR No source bus error. 0 ERROR The most-recently recorded error was a bus error on a source read. 0x1 SGE Scatter/Gather Configuration Error 2 1 read-only NO_ERROR No scatter/gather configuration error. 0 ERROR The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field. 0x1 NCE NBYTES/CITER Configuration Error 3 1 read-only NO_ERROR No NBYTES/CITER configuration error. 0 ERROR The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]. 0x1 DOE Destination Offset Error 4 1 read-only NO_ERROR No destination offset configuration error. 0 ERROR The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. 0x1 DAE Destination Address Error 5 1 read-only NO_ERROR No destination address configuration error. 0 ERROR The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. 0x1 SOE Source Offset Error 6 1 read-only NO_ERROR No source offset configuration error. 0 ERROR The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. 0x1 SAE Source Address Error 7 1 read-only NO_ERROR No source address configuration error. 0 ERROR The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. 0x1 ERRCHN Error Channel Number or Canceled Channel Number 8 5 read-only CPE Channel Priority Error 14 1 read-only NO_ERROR No channel priority error. 0 ERROR The most-recently recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. 0x1 GPE Group Priority Error 15 1 read-only NO_ERROR No group priority error. 0 ERROR The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique. 0x1 ECX Transfer Canceled 16 1 read-only NO_CANCELS No canceled transfers 0 CANCELED The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field 0x1 VLD Logical OR of all ERR status fields 31 1 read-only NO_ERROR No ERR fields are 1 0 ERROR At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared 0x1 ERQ Enable Request 0xC 32 read-write 0 0xFFFFFFFF ERQ0 Enable DMA Request 0 0 1 read-write DISABLE The DMA request signal for channel 0 is disabled 0 ENABLE The DMA request signal for channel 0 is enabled 0x1 ERQ1 Enable DMA Request 1 1 1 read-write DISABLE The DMA request signal for channel 1 is disabled 0 ENABLE The DMA request signal for channel 1 is enabled 0x1 ERQ2 Enable DMA Request 2 2 1 read-write DISABLE The DMA request signal for channel 2 is disabled 0 ENABLE The DMA request signal for channel 2 is enabled 0x1 ERQ3 Enable DMA Request 3 3 1 read-write DISABLE The DMA request signal for channel 3 is disabled 0 ENABLE The DMA request signal for channel 3 is enabled 0x1 ERQ4 Enable DMA Request 4 4 1 read-write DISABLE The DMA request signal for channel 4 is disabled 0 ENABLE The DMA request signal for channel 4 is enabled 0x1 ERQ5 Enable DMA Request 5 5 1 read-write DISABLE The DMA request signal for channel 5 is disabled 0 ENABLE The DMA request signal for channel 5 is enabled 0x1 ERQ6 Enable DMA Request 6 6 1 read-write DISABLE The DMA request signal for channel 6 is disabled 0 ENABLE The DMA request signal for channel 6 is enabled 0x1 ERQ7 Enable DMA Request 7 7 1 read-write DISABLE The DMA request signal for channel 7 is disabled 0 ENABLE The DMA request signal for channel 7 is enabled 0x1 ERQ8 Enable DMA Request 8 8 1 read-write DISABLE The DMA request signal for channel 8 is disabled 0 ENABLE The DMA request signal for channel 8 is enabled 0x1 ERQ9 Enable DMA Request 9 9 1 read-write DISABLE The DMA request signal for channel 9 is disabled 0 ENABLE The DMA request signal for channel 9 is enabled 0x1 ERQ10 Enable DMA Request 10 10 1 read-write DISABLE The DMA request signal for channel 10 is disabled 0 ENABLE The DMA request signal for channel 10 is enabled 0x1 ERQ11 Enable DMA Request 11 11 1 read-write DISABLE The DMA request signal for channel 11 is disabled 0 ENABLE The DMA request signal for channel 11 is enabled 0x1 ERQ12 Enable DMA Request 12 12 1 read-write DISABLE The DMA request signal for channel 12 is disabled 0 ENABLE The DMA request signal for channel 12 is enabled 0x1 ERQ13 Enable DMA Request 13 13 1 read-write DISABLE The DMA request signal for channel 13 is disabled 0 ENABLE The DMA request signal for channel 13 is enabled 0x1 ERQ14 Enable DMA Request 14 14 1 read-write DISABLE The DMA request signal for channel 14 is disabled 0 ENABLE The DMA request signal for channel 14 is enabled 0x1 ERQ15 Enable DMA Request 15 15 1 read-write DISABLE The DMA request signal for channel 15 is disabled 0 ENABLE The DMA request signal for channel 15 is enabled 0x1 ERQ16 Enable DMA Request 16 16 1 read-write DISABLE The DMA request signal for channel 16 is disabled 0 ENABLE The DMA request signal for channel 16 is enabled 0x1 ERQ17 Enable DMA Request 17 17 1 read-write DISABLE The DMA request signal for channel 17 is disabled 0 ENABLE The DMA request signal for channel 17 is enabled 0x1 ERQ18 Enable DMA Request 18 18 1 read-write DISABLE The DMA request signal for channel 18 is disabled 0 ENABLE The DMA request signal for channel 18 is enabled 0x1 ERQ19 Enable DMA Request 19 19 1 read-write DISABLE The DMA request signal for channel 19 is disabled 0 ENABLE The DMA request signal for channel 19 is enabled 0x1 ERQ20 Enable DMA Request 20 20 1 read-write DISABLE The DMA request signal for channel 20 is disabled 0 ENABLE The DMA request signal for channel 20 is enabled 0x1 ERQ21 Enable DMA Request 21 21 1 read-write DISABLE The DMA request signal for channel 21 is disabled 0 ENABLE The DMA request signal for channel 21 is enabled 0x1 ERQ22 Enable DMA Request 22 22 1 read-write DISABLE The DMA request signal for channel 22 is disabled 0 ENABLE The DMA request signal for channel 22 is enabled 0x1 ERQ23 Enable DMA Request 23 23 1 read-write DISABLE The DMA request signal for channel 23 is disabled 0 ENABLE The DMA request signal for channel 23 is enabled 0x1 ERQ24 Enable DMA Request 24 24 1 read-write DISABLE The DMA request signal for channel 24 is disabled 0 ENABLE The DMA request signal for channel 24 is enabled 0x1 ERQ25 Enable DMA Request 25 25 1 read-write DISABLE The DMA request signal for channel 25 is disabled 0 ENABLE The DMA request signal for channel 25 is enabled 0x1 ERQ26 Enable DMA Request 26 26 1 read-write DISABLE The DMA request signal for channel 26 is disabled 0 ENABLE The DMA request signal for channel 26 is enabled 0x1 ERQ27 Enable DMA Request 27 27 1 read-write DISABLE The DMA request signal for channel 27 is disabled 0 ENABLE The DMA request signal for channel 27 is enabled 0x1 ERQ28 Enable DMA Request 28 28 1 read-write DISABLE The DMA request signal for channel 28 is disabled 0 ENABLE The DMA request signal for channel 28 is enabled 0x1 ERQ29 Enable DMA Request 29 29 1 read-write DISABLE The DMA request signal for channel 29 is disabled 0 ENABLE The DMA request signal for channel 29 is enabled 0x1 ERQ30 Enable DMA Request 30 30 1 read-write DISABLE The DMA request signal for channel 30 is disabled 0 ENABLE The DMA request signal for channel 30 is enabled 0x1 ERQ31 Enable DMA Request 31 31 1 read-write DISABLE The DMA request signal for channel 31 is disabled 0 ENABLE The DMA request signal for channel 31 is enabled 0x1 EEI Enable Error Interrupt 0x14 32 read-write 0 0xFFFFFFFF EEI0 Enable Error Interrupt 0 0 1 read-write NO_INTERRUPT An error on channel 0 does not generate an error interrupt 0 INTERRUPT An error on channel 0 generates an error interrupt request 0x1 EEI1 Enable Error Interrupt 1 1 1 read-write NO_INTERRUPT An error on channel 1 does not generate an error interrupt 0 INTERRUPT An error on channel 1 generates an error interrupt request 0x1 EEI2 Enable Error Interrupt 2 2 1 read-write NO_INTERRUPT An error on channel 2 does not generate an error interrupt 0 INTERRUPT An error on channel 2 generates an error interrupt request 0x1 EEI3 Enable Error Interrupt 3 3 1 read-write NO_INTERRUPT An error on channel 3 does not generate an error interrupt 0 INTERRUPT An error on channel 3 generates an error interrupt request 0x1 EEI4 Enable Error Interrupt 4 4 1 read-write NO_INTERRUPT An error on channel 4 does not generate an error interrupt 0 INTERRUPT An error on channel 4 generates an error interrupt request 0x1 EEI5 Enable Error Interrupt 5 5 1 read-write NO_INTERRUPT An error on channel 5 does not generate an error interrupt 0 INTERRUPT An error on channel 5 generates an error interrupt request 0x1 EEI6 Enable Error Interrupt 6 6 1 read-write NO_INTERRUPT An error on channel 6 does not generate an error interrupt 0 INTERRUPT An error on channel 6 generates an error interrupt request 0x1 EEI7 Enable Error Interrupt 7 7 1 read-write NO_INTERRUPT An error on channel 7 does not generate an error interrupt 0 INTERRUPT An error on channel 7 generates an error interrupt request 0x1 EEI8 Enable Error Interrupt 8 8 1 read-write NO_INTERRUPT An error on channel 8 does not generate an error interrupt 0 INTERRUPT An error on channel 8 generates an error interrupt request 0x1 EEI9 Enable Error Interrupt 9 9 1 read-write NO_INTERRUPT An error on channel 9 does not generate an error interrupt 0 INTERRUPT An error on channel 9 generates an error interrupt request 0x1 EEI10 Enable Error Interrupt 10 10 1 read-write NO_INTERRUPT An error on channel 10 does not generate an error interrupt 0 INTERRUPT An error on channel 10 generates an error interrupt request 0x1 EEI11 Enable Error Interrupt 11 11 1 read-write NO_INTERRUPT An error on channel 11 does not generate an error interrupt 0 INTERRUPT An error on channel 11 generates an error interrupt request 0x1 EEI12 Enable Error Interrupt 12 12 1 read-write NO_INTERRUPT An error on channel 12 does not generate an error interrupt 0 INTERRUPT An error on channel 12 generates an error interrupt request 0x1 EEI13 Enable Error Interrupt 13 13 1 read-write NO_INTERRUPT An error on channel 13 does not generate an error interrupt 0 INTERRUPT An error on channel 13 generates an error interrupt request 0x1 EEI14 Enable Error Interrupt 14 14 1 read-write NO_INTERRUPT An error on channel 14 does not generate an error interrupt 0 INTERRUPT An error on channel 14 generates an error interrupt request 0x1 EEI15 Enable Error Interrupt 15 15 1 read-write NO_INTERRUPT An error on channel 15 does not generate an error interrupt 0 INTERRUPT An error on channel 15 generates an error interrupt request 0x1 EEI16 Enable Error Interrupt 16 16 1 read-write NO_INTERRUPT An error on channel 16 does not generate an error interrupt 0 INTERRUPT An error on channel 16 generates an error interrupt request 0x1 EEI17 Enable Error Interrupt 17 17 1 read-write NO_INTERRUPT An error on channel 17 does not generate an error interrupt 0 INTERRUPT An error on channel 17 generates an error interrupt request 0x1 EEI18 Enable Error Interrupt 18 18 1 read-write NO_INTERRUPT An error on channel 18 does not generate an error interrupt 0 INTERRUPT An error on channel 18 generates an error interrupt request 0x1 EEI19 Enable Error Interrupt 19 19 1 read-write NO_INTERRUPT An error on channel 19 does not generate an error interrupt 0 INTERRUPT An error on channel 19 generates an error interrupt request 0x1 EEI20 Enable Error Interrupt 20 20 1 read-write NO_INTERRUPT An error on channel 20 does not generate an error interrupt 0 INTERRUPT An error on channel 20 generates an error interrupt request 0x1 EEI21 Enable Error Interrupt 21 21 1 read-write NO_INTERRUPT An error on channel 21 does not generate an error interrupt 0 INTERRUPT An error on channel 21 generates an error interrupt request 0x1 EEI22 Enable Error Interrupt 22 22 1 read-write NO_INTERRUPT An error on channel 22 does not generate an error interrupt 0 INTERRUPT An error on channel 22 generates an error interrupt request 0x1 EEI23 Enable Error Interrupt 23 23 1 read-write NO_INTERRUPT An error on channel 23 does not generate an error interrupt 0 INTERRUPT An error on channel 23 generates an error interrupt request 0x1 EEI24 Enable Error Interrupt 24 24 1 read-write NO_INTERRUPT An error on channel 24 does not generate an error interrupt 0 INTERRUPT An error on channel 24 generates an error interrupt request 0x1 EEI25 Enable Error Interrupt 25 25 1 read-write NO_INTERRUPT An error on channel 25 does not generate an error interrupt 0 INTERRUPT An error on channel 25 generates an error interrupt request 0x1 EEI26 Enable Error Interrupt 26 26 1 read-write NO_INTERRUPT An error on channel 26 does not generate an error interrupt 0 INTERRUPT An error on channel 26 generates an error interrupt request 0x1 EEI27 Enable Error Interrupt 27 27 1 read-write NO_INTERRUPT An error on channel 27 does not generate an error interrupt 0 INTERRUPT An error on channel 27 generates an error interrupt request 0x1 EEI28 Enable Error Interrupt 28 28 1 read-write NO_INTERRUPT An error on channel 28 does not generate an error interrupt 0 INTERRUPT An error on channel 28 generates an error interrupt request 0x1 EEI29 Enable Error Interrupt 29 29 1 read-write NO_INTERRUPT An error on channel 29 does not generate an error interrupt 0 INTERRUPT An error on channel 29 generates an error interrupt request 0x1 EEI30 Enable Error Interrupt 30 30 1 read-write NO_INTERRUPT An error on channel 30 does not generate an error interrupt 0 INTERRUPT An error on channel 30 generates an error interrupt request 0x1 EEI31 Enable Error Interrupt 31 31 1 read-write NO_INTERRUPT An error on channel 31 does not generate an error interrupt 0 INTERRUPT An error on channel 31 generates an error interrupt request 0x1 CEEI Clear Enable Error Interrupt 0x18 8 read-write 0 0xFF CEEI Clear Enable Error Interrupt 0 5 read-write CAEE Clear All Enable Error Interrupts 6 1 read-write CLEAR_EEI Write 0 only to the EEI field specified in the CEEI field 0 CLEAR_ALL Write 0 to all fields in EEI 0x1 NOP No Op Enable 7 1 read-write NORMAL_OPS Normal operation 0 NO_OPS No operation, ignore the other fields in this register 0x1 SEEI Set Enable Error Interrupt 0x19 8 read-write 0 0xFF SEEI Set Enable Error Interrupt 0 5 read-write SAEE Set All Enable Error Interrupts 6 1 read-write SET_EEI Write 1 only to the EEI field specified in the SEEI field 0 SET_ALL Writes 1 to all fields in EEI 0x1 NOP No Op Enable 7 1 read-write NORMAL_OPS Normal operation 0 NO_OPS No operation, ignore the other fields in this register 0x1 CERQ Clear Enable Request 0x1A 8 read-write 0 0xFF CERQ Clear Enable Request 0 5 read-write CAER Clear All Enable Requests 6 1 read-write CLEAR_ERQ Write 0 to only the ERQ field specified in the CERQ field 0 CLEAR_ALL Write 0 to all fields in ERQ 0x1 NOP No Op Enable 7 1 read-write NORMAL_OPS Normal operation 0 NO_OPS No operation, ignore the other fields in this register 0x1 SERQ Set Enable Request 0x1B 8 read-write 0 0xFF SERQ Set Enable Request 0 5 read-write SAER Set All Enable Requests 6 1 read-write SET_ERQ Write 1 to only the ERQ field specified in the SERQ field 0 SET_ALL Write 1 to all fields in ERQ 0x1 NOP No Op Enable 7 1 read-write NORMAL_OPS Normal operation 0 NO_OPS No operation, ignore the other fields in this register 0x1 CDNE Clear DONE Status Bit 0x1C 8 read-write 0 0xFF CDNE Clear DONE field 0 5 read-write CADN Clears All DONE fields 6 1 read-write CLEAR_DONE Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field 0 CLEAR_ALL Writes 0 to all bits in TCDn_CSR[DONE] 0x1 NOP No Op Enable 7 1 read-write NORMAL_OPS Normal operation 0 NO_OPS No operation; all other fields in this register are ignored. 0x1 SSRT Set START Bit 0x1D 8 read-write 0 0xFF SSRT Set START field 0 5 read-write SAST Set All START fields (activates all channels) 6 1 read-write SET_START Write 1 to only the TCDn_CSR[START] field specified in the SSRT field 0 SET_ALL Write 1 to all bits in TCDn_CSR[START] 0x1 NOP No Op Enable 7 1 read-write NORMAL_OPS Normal operation 0 NO_OPS No operation; all other fields in this register are ignored. 0x1 CERR Clear Error 0x1E 8 read-write 0 0xFF CERR Clear Error Indicator 0 5 read-write CAEI Clear All Error Indicators 6 1 read-write CLEAR_ERR Write 0 to only the ERR field specified in the CERR field 0 CLEAR_ALL Write 0 to all fields in ERR 0x1 NOP No Op Enable 7 1 read-write NORMAL_OPS Normal operation 0 NO_OPS No operation; all other fields in this register are ignored. 0x1 CINT Clear Interrupt Request 0x1F 8 read-write 0 0xFF CINT Clear Interrupt Request 0 5 read-write CAIR Clear All Interrupt Requests 6 1 read-write CLEAR_INT Clear only the INT field specified in the CINT field 0 CLEAR_ALL Clear all bits in INT 0x1 NOP No Op Enable 7 1 read-write NORMAL_OPS Normal operation 0 NO_OPS No operation; all other fields in this register are ignored. 0x1 INT Interrupt Request 0x24 32 read-write 0 0xFFFFFFFF oneToClear INT0 Interrupt Request 0 0 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 0 is cleared 0 ACTIVE The interrupt request for channel 0 is active 0x1 INT1 Interrupt Request 1 1 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 1 is cleared 0 ACTIVE The interrupt request for channel 1 is active 0x1 INT2 Interrupt Request 2 2 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 2 is cleared 0 ACTIVE The interrupt request for channel 2 is active 0x1 INT3 Interrupt Request 3 3 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 3 is cleared 0 ACTIVE The interrupt request for channel 3 is active 0x1 INT4 Interrupt Request 4 4 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 4 is cleared 0 ACTIVE The interrupt request for channel 4 is active 0x1 INT5 Interrupt Request 5 5 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 5 is cleared 0 ACTIVE The interrupt request for channel 5 is active 0x1 INT6 Interrupt Request 6 6 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 6 is cleared 0 CTIVE The interrupt request for channel 6 is active 0x1 INT7 Interrupt Request 7 7 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 7 is cleared 0 ACTIVE The interrupt request for channel 7 is active 0x1 INT8 Interrupt Request 8 8 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 8 is cleared 0 ACTIVE The interrupt request for channel 8 is active 0x1 INT9 Interrupt Request 9 9 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 9 is cleared 0 ACTIVE The interrupt request for channel 9 is active 0x1 INT10 Interrupt Request 10 10 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 10 is cleared 0 ACTIVE The interrupt request for channel 10 is active 0x1 INT11 Interrupt Request 11 11 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 11 is cleared 0 ACTIVE The interrupt request for channel 11 is active 0x1 INT12 Interrupt Request 12 12 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 12 is cleared 0 ACTIVE The interrupt request for channel 12 is active 0x1 INT13 Interrupt Request 13 13 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 13 is cleared 0 ACTIVE The interrupt request for channel 13 is active 0x1 INT14 Interrupt Request 14 14 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 14 is cleared 0 ACTIVE The interrupt request for channel 14 is active 0x1 INT15 Interrupt Request 15 15 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 15 is cleared 0 ACTIVE The interrupt request for channel 15 is active 0x1 INT16 Interrupt Request 16 16 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 16 is cleared 0 ACTIVE The interrupt request for channel 16 is active 0x1 INT17 Interrupt Request 17 17 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 17 is cleared 0 ACTIVE The interrupt request for channel 17 is active 0x1 INT18 Interrupt Request 18 18 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 18 is cleared 0 ACTIVE The interrupt request for channel 18 is active 0x1 INT19 Interrupt Request 19 19 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 19 is cleared 0 ACTIVE The interrupt request for channel 19 is active 0x1 INT20 Interrupt Request 20 20 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 20 is cleared 0 ACTIVE The interrupt request for channel 20 is active 0x1 INT21 Interrupt Request 21 21 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 21 is cleared 0 ACTIVE The interrupt request for channel 21 is active 0x1 INT22 Interrupt Request 22 22 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 22 is cleared 0 ACTIVE The interrupt request for channel 22 is active 0x1 INT23 Interrupt Request 23 23 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 23 is cleared 0 ACTIVE The interrupt request for channel 23 is active 0x1 INT24 Interrupt Request 24 24 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 24 is cleared 0 ACTIVE The interrupt request for channel 24 is active 0x1 INT25 Interrupt Request 25 25 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 25 is cleared 0 ACTIVE The interrupt request for channel 25 is active 0x1 INT26 Interrupt Request 26 26 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 26 is cleared 0 ACTIVE The interrupt request for channel 26 is active 0x1 INT27 Interrupt Request 27 27 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 27 is cleared 0 ACTIVE The interrupt request for channel 27 is active 0x1 INT28 Interrupt Request 28 28 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 28 is cleared 0 ACTIVE The interrupt request for channel 28 is active 0x1 INT29 Interrupt Request 29 29 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 29 is cleared 0 ACTIVE The interrupt request for channel 29 is active 0x1 INT30 Interrupt Request 30 30 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 30 is cleared 0 ACTIVE The interrupt request for channel 30 is active 0x1 INT31 Interrupt Request 31 31 1 read-write oneToClear NOT_ACTIVE The interrupt request for channel 31 is cleared 0 ACTIVE The interrupt request for channel 31 is active 0x1 ERR Error 0x2C 32 read-write 0 0xFFFFFFFF oneToClear ERR0 Error In Channel 0 0 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR1 Error In Channel 1 1 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR2 Error In Channel 2 2 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR3 Error In Channel 3 3 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR4 Error In Channel 4 4 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR5 Error In Channel 5 5 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR6 Error In Channel 6 6 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR7 Error In Channel 7 7 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR8 Error In Channel 8 8 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR9 Error In Channel 9 9 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR10 Error In Channel 10 10 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR11 Error In Channel 11 11 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR12 Error In Channel 12 12 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR13 Error In Channel 13 13 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR14 Error In Channel 14 14 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR15 Error In Channel 15 15 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR16 Error In Channel 16 16 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR17 Error In Channel 17 17 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR18 Error In Channel 18 18 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR19 Error In Channel 19 19 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR20 Error In Channel 20 20 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR21 Error In Channel 21 21 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR22 Error In Channel 22 22 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR23 Error In Channel 23 23 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR24 Error In Channel 24 24 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR25 Error In Channel 25 25 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR26 Error In Channel 26 26 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR27 Error In Channel 27 27 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR28 Error In Channel 28 28 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR29 Error In Channel 29 29 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR30 Error In Channel 30 30 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 ERR31 Error In Channel 31 31 1 read-write oneToClear NO_ERR No error in this channel has occurred 0 ERR An error in this channel has occurred 0x1 HRS Hardware Request Status 0x34 32 read-only 0 0xFFFFFFFF HRS0 Hardware Request Status Channel 0 0 1 read-only NO_HWRQST A hardware service request for channel 0 is not present 0 HWRQST A hardware service request for channel 0 is present 0x1 HRS1 Hardware Request Status Channel 1 1 1 read-only NO_HWRQST A hardware service request for channel 1 is not present 0 HWRQST A hardware service request for channel 1 is present 0x1 HRS2 Hardware Request Status Channel 2 2 1 read-only NO_HWRQST A hardware service request for channel 2 is not present 0 HWRQST A hardware service request for channel 2 is present 0x1 HRS3 Hardware Request Status Channel 3 3 1 read-only NO_HWRQST A hardware service request for channel 3 is not present 0 HWRQST A hardware service request for channel 3 is present 0x1 HRS4 Hardware Request Status Channel 4 4 1 read-only NO_HWRQST A hardware service request for channel 4 is not present 0 HWRQST A hardware service request for channel 4 is present 0x1 HRS5 Hardware Request Status Channel 5 5 1 read-only NO_HWRQST A hardware service request for channel 5 is not present 0 HWRQST A hardware service request for channel 5 is present 0x1 HRS6 Hardware Request Status Channel 6 6 1 read-only NO_HWRQST A hardware service request for channel 6 is not present 0 HWRQST A hardware service request for channel 6 is present 0x1 HRS7 Hardware Request Status Channel 7 7 1 read-only NO_HWRQST A hardware service request for channel 7 is not present 0 HWRQST A hardware service request for channel 7 is present 0x1 HRS8 Hardware Request Status Channel 8 8 1 read-only NO_HWRQST A hardware service request for channel 8 is not present 0 HWRQST A hardware service request for channel 8 is present 0x1 HRS9 Hardware Request Status Channel 9 9 1 read-only NO_HWRQST A hardware service request for channel 9 is not present 0 HWRQST A hardware service request for channel 9 is present 0x1 HRS10 Hardware Request Status Channel 10 10 1 read-only NO_HWRQST A hardware service request for channel 10 is not present 0 HWRQST A hardware service request for channel 10 is present 0x1 HRS11 Hardware Request Status Channel 11 11 1 read-only NO_HWRQST A hardware service request for channel 11 is not present 0 HWRQST A hardware service request for channel 11 is present 0x1 HRS12 Hardware Request Status Channel 12 12 1 read-only NO_HWRQST A hardware service request for channel 12 is not present 0 HWRQST A hardware service request for channel 12 is present 0x1 HRS13 Hardware Request Status Channel 13 13 1 read-only NO_HWRQST A hardware service request for channel 13 is not present 0 HWRQST A hardware service request for channel 13 is present 0x1 HRS14 Hardware Request Status Channel 14 14 1 read-only NO_HWRQST A hardware service request for channel 14 is not present 0 HWRQST A hardware service request for channel 14 is present 0x1 HRS15 Hardware Request Status Channel 15 15 1 read-only NO_HWRQST A hardware service request for channel 15 is not present 0 HWRQST A hardware service request for channel 15 is present 0x1 HRS16 Hardware Request Status Channel 16 16 1 read-only NO_HWRQST A hardware service request for channel 16 is not present 0 HWRQST A hardware service request for channel 16 is present 0x1 HRS17 Hardware Request Status Channel 17 17 1 read-only NO_HWRQST A hardware service request for channel 17 is not present 0 HWRQST A hardware service request for channel 17 is present 0x1 HRS18 Hardware Request Status Channel 18 18 1 read-only NO_HWRQST A hardware service request for channel 18 is not present 0 HWRQST A hardware service request for channel 18 is present 0x1 HRS19 Hardware Request Status Channel 19 19 1 read-only NO_HWRQST A hardware service request for channel 19 is not present 0 HWRQST A hardware service request for channel 19 is present 0x1 HRS20 Hardware Request Status Channel 20 20 1 read-only NO_HWRQST A hardware service request for channel 20 is not present 0 HWRQST A hardware service request for channel 20 is present 0x1 HRS21 Hardware Request Status Channel 21 21 1 read-only NO_HWRQST A hardware service request for channel 21 is not present 0 HWRQST A hardware service request for channel 21 is present 0x1 HRS22 Hardware Request Status Channel 22 22 1 read-only NO_HWRQST A hardware service request for channel 22 is not present 0 HWRQST A hardware service request for channel 22 is present 0x1 HRS23 Hardware Request Status Channel 23 23 1 read-only NO_HWRQST A hardware service request for channel 23 is not present 0 HWRQST A hardware service request for channel 23 is present 0x1 HRS24 Hardware Request Status Channel 24 24 1 read-only NO_HWRQST A hardware service request for channel 24 is not present 0 HWRQST A hardware service request for channel 24 is present 0x1 HRS25 Hardware Request Status Channel 25 25 1 read-only NO_HWRQST A hardware service request for channel 25 is not present 0 HWRQST A hardware service request for channel 25 is present 0x1 HRS26 Hardware Request Status Channel 26 26 1 read-only NO_HWRQST A hardware service request for channel 26 is not present 0 HWRQST A hardware service request for channel 26 is present 0x1 HRS27 Hardware Request Status Channel 27 27 1 read-only NO_HWRQST A hardware service request for channel 27 is not present 0 HWRQST A hardware service request for channel 27 is present 0x1 HRS28 Hardware Request Status Channel 28 28 1 read-only NO_HWRQST A hardware service request for channel 28 is not present 0 HWRQST A hardware service request for channel 28 is present 0x1 HRS29 Hardware Request Status Channel 29 29 1 read-only NO_HWRQST A hardware service request for channel 29 is not preset 0 HWRQST A hardware service request for channel 29 is present 0x1 HRS30 Hardware Request Status Channel 30 30 1 read-only NO_HWRQST A hardware service request for channel 30 is not present 0 HWRQST A hardware service request for channel 30 is present 0x1 HRS31 Hardware Request Status Channel 31 31 1 read-only NO_HWRQST A hardware service request for channel 31 is not present 0 HWRQST A hardware service request for channel 31 is present 0x1 EARS Enable Asynchronous Request in Stop 0x44 32 read-write 0 0xFFFFFFFF EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write DISABLE Disable asynchronous DMA request for channel 0 0 ENABLE Enable asynchronous DMA request for channel 0 0x1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write DISABLE Disable asynchronous DMA request for channel 1 0 ENABLE Enable asynchronous DMA request for channel 1 0x1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write DISABLE Disable asynchronous DMA request for channel 2 0 ENABLE Enable asynchronous DMA request for channel 2 0x1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write DISABLE Disable asynchronous DMA request for channel 3 0 ENABLE Enable asynchronous DMA request for channel 3 0x1 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4. 4 1 read-write DISABLE Disable asynchronous DMA request for channel 4 0 ENABLE Enable asynchronous DMA request for channel 4 0x1 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5. 5 1 read-write DISABLE Disable asynchronous DMA request for channel 5 0 ENABLE Enable asynchronous DMA request for channel 5 0x1 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6. 6 1 read-write DISABLE Disable asynchronous DMA request for channel 6 0 ENABLE Enable asynchronous DMA request for channel 6 0x1 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7. 7 1 read-write DISABLE Disable asynchronous DMA request for channel 7 0 ENABLE Enable asynchronous DMA request for channel 7 0x1 EDREQ_8 Enable asynchronous DMA request in stop mode for channel 8. 8 1 read-write DISABLE Disable asynchronous DMA request for channel 8 0 ENABLE Enable asynchronous DMA request for channel 8 0x1 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9. 9 1 read-write DISABLE Disable asynchronous DMA request for channel 9 0 ENABLE Enable asynchronous DMA request for channel 9 0x1 EDREQ_10 Enable asynchronous DMA request in stop mode for channel 10. 10 1 read-write DISABLE Disable asynchronous DMA request for channel 10 0 ENABLE Enable asynchronous DMA request for channel 10 0x1 EDREQ_11 Enable asynchronous DMA request in stop mode for channel 11. 11 1 read-write DISABLE Disable asynchronous DMA request for channel 11 0 ENABLE Enable asynchronous DMA request for channel 11 0x1 EDREQ_12 Enable asynchronous DMA request in stop mode for channel 12. 12 1 read-write DISABLE Disable asynchronous DMA request for channel 12 0 ENABLE Enable asynchronous DMA request for channel 12 0x1 EDREQ_13 Enable asynchronous DMA request in stop mode for channel 13. 13 1 read-write DISABLE Disable asynchronous DMA request for channel 13 0 ENABLE Enable asynchronous DMA request for channel 13 0x1 EDREQ_14 Enable asynchronous DMA request in stop mode for channel 14. 14 1 read-write DISABLE Disable asynchronous DMA request for channel 14 0 ENABLE Enable asynchronous DMA request for channel 14 0x1 EDREQ_15 Enable asynchronous DMA request in stop mode for channel 15. 15 1 read-write DISABLE Disable asynchronous DMA request for channel 15 0 ENABLE Enable asynchronous DMA request for channel 15 0x1 EDREQ_16 Enable asynchronous DMA request in stop mode for channel 16. 16 1 read-write DISABLE Disable asynchronous DMA request for channel 16 0 ENABLE Enable asynchronous DMA request for channel 16 0x1 EDREQ_17 Enable asynchronous DMA request in stop mode for channel 17. 17 1 read-write DISABLE Disable asynchronous DMA request for channel 17 0 ENABLE Enable asynchronous DMA request for channel 17 0x1 EDREQ_18 Enable asynchronous DMA request in stop mode for channel 18. 18 1 read-write DISABLE Disable asynchronous DMA request for channel 18 0 ENABLE Enable asynchronous DMA request for channel 18 0x1 EDREQ_19 Enable asynchronous DMA request in stop mode for channel 19. 19 1 read-write DISABLE Disable asynchronous DMA request for channel 19 0 ENABLE Enable asynchronous DMA request for channel 19 0x1 EDREQ_20 Enable asynchronous DMA request in stop mode for channel 20. 20 1 read-write DISABLE Disable asynchronous DMA request for channel 20 0 ENABLE Enable asynchronous DMA request for channel 20 0x1 EDREQ_21 Enable asynchronous DMA request in stop mode for channel 21. 21 1 read-write DISABLE Disable asynchronous DMA request for channel 21 0 ENABLE Enable asynchronous DMA request for channel 21 0x1 EDREQ_22 Enable asynchronous DMA request in stop mode for channel 22. 22 1 read-write DISABLE Disable asynchronous DMA request for channel 22 0 ENABLE Enable asynchronous DMA request for channel 22 0x1 EDREQ_23 Enable asynchronous DMA request in stop mode for channel 23. 23 1 read-write DISABLE Disable asynchronous DMA request for channel 23 0 ENABLE Enable asynchronous DMA request for channel 23 0x1 EDREQ_24 Enable asynchronous DMA request in stop mode for channel 24. 24 1 read-write DISABLE Disable asynchronous DMA request for channel 24 0 ENABLE Enable asynchronous DMA request for channel 24 0x1 EDREQ_25 Enable asynchronous DMA request in stop mode for channel 25. 25 1 read-write DISABLE Disable asynchronous DMA request for channel 25 0 ENABLE Enable asynchronous DMA request for channel 25 0x1 EDREQ_26 Enable asynchronous DMA request in stop mode for channel 26. 26 1 read-write DISABLE Disable asynchronous DMA request for channel 26 0 ENABLE Enable asynchronous DMA request for channel 26 0x1 EDREQ_27 Enable asynchronous DMA request in stop mode for channel 27. 27 1 read-write DISABLE Disable asynchronous DMA request for channel 27 0 ENABLE Enable asynchronous DMA request for channel 27 0x1 EDREQ_28 Enable asynchronous DMA request in stop mode for channel 28. 28 1 read-write DISABLE Disable asynchronous DMA request for channel 28 0 ENABLE Enable asynchronous DMA request for channel 28 0x1 EDREQ_29 Enable asynchronous DMA request in stop mode for channel 29. 29 1 read-write DISABLE Disable asynchronous DMA request for channel 29 0 ENABLE Enable asynchronous DMA request for channel 29 0x1 EDREQ_30 Enable asynchronous DMA request in stop mode for channel 30. 30 1 read-write DISABLE Disable asynchronous DMA request for channel 30 0 ENABLE Enable asynchronous DMA request for channel 30 0x1 EDREQ_31 Enable asynchronous DMA request in stop mode for channel 31. 31 1 read-write DISABLE Disable asynchronous DMA request for channel 31 0 ENABLE Enable asynchronous DMA request for channel 31 0x1 DCHPRI3 Channel Priority 0x100 8 read-write 0x3 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI2 Channel Priority 0x101 8 read-write 0x2 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI1 Channel Priority 0x102 8 read-write 0x1 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI0 Channel Priority 0x103 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI7 Channel Priority 0x104 8 read-write 0x7 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI6 Channel Priority 0x105 8 read-write 0x6 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI5 Channel Priority 0x106 8 read-write 0x5 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI4 Channel Priority 0x107 8 read-write 0x4 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI11 Channel Priority 0x108 8 read-write 0xB 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI10 Channel Priority 0x109 8 read-write 0xA 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI9 Channel Priority 0x10A 8 read-write 0x9 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI8 Channel Priority 0x10B 8 read-write 0x8 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI15 Channel Priority 0x10C 8 read-write 0xF 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI14 Channel Priority 0x10D 8 read-write 0xE 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI13 Channel Priority 0x10E 8 read-write 0xD 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI12 Channel Priority 0x10F 8 read-write 0xC 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI19 Channel Priority 0x110 8 read-write 0x13 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI18 Channel Priority 0x111 8 read-write 0x12 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI17 Channel Priority 0x112 8 read-write 0x11 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI16 Channel Priority 0x113 8 read-write 0x10 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI23 Channel Priority 0x114 8 read-write 0x17 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI22 Channel Priority 0x115 8 read-write 0x16 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI21 Channel Priority 0x116 8 read-write 0x15 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI20 Channel Priority 0x117 8 read-write 0x14 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI27 Channel Priority 0x118 8 read-write 0x1B 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI26 Channel Priority 0x119 8 read-write 0x1A 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI25 Channel Priority 0x11A 8 read-write 0x19 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI24 Channel Priority 0x11B 8 read-write 0x18 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI31 Channel Priority 0x11C 8 read-write 0x1F 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI30 Channel Priority 0x11D 8 read-write 0x1E 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI29 Channel Priority 0x11E 8 read-write 0x1D 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 DCHPRI28 Channel Priority 0x11F 8 read-write 0x1C 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write ENABLED Channel n can suspend a lower priority channel 0 DISABLED Channel n cannot suspend any channel, regardless of channel priority 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write DISABLED Channel n cannot be suspended by a higher priority channel's service request 0 ENABLED Channel n can be temporarily suspended by the service request of a higher priority channel 0x1 TCD0_SADDR TCD Source Address 0x1000 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD0_SOFF TCD Signed Source Address Offset 0x1004 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD0_ATTR TCD Transfer Attributes 0x1006 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD0_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD0_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD0_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD0_SLAST TCD Last Source Address Adjustment 0x100C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD0_DADDR TCD Destination Address 0x1010 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD0_DOFF TCD Signed Destination Address Offset 0x1014 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD0_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD0_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD0_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1018 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD0_CSR TCD Control and Status 0x101C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD0_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x101E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD0_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x101E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD1_SADDR TCD Source Address 0x1020 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD1_SOFF TCD Signed Source Address Offset 0x1024 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD1_ATTR TCD Transfer Attributes 0x1026 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD1_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD1_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD1_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD1_SLAST TCD Last Source Address Adjustment 0x102C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD1_DADDR TCD Destination Address 0x1030 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD1_DOFF TCD Signed Destination Address Offset 0x1034 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD1_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1036 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD1_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1036 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD1_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1038 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD1_CSR TCD Control and Status 0x103C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD1_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x103E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD1_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x103E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD2_SADDR TCD Source Address 0x1040 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD2_SOFF TCD Signed Source Address Offset 0x1044 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD2_ATTR TCD Transfer Attributes 0x1046 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD2_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD2_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD2_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD2_SLAST TCD Last Source Address Adjustment 0x104C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD2_DADDR TCD Destination Address 0x1050 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD2_DOFF TCD Signed Destination Address Offset 0x1054 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD2_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1056 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD2_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1056 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD2_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1058 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD2_CSR TCD Control and Status 0x105C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD2_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x105E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD2_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x105E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD3_SADDR TCD Source Address 0x1060 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD3_SOFF TCD Signed Source Address Offset 0x1064 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD3_ATTR TCD Transfer Attributes 0x1066 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD3_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD3_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD3_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD3_SLAST TCD Last Source Address Adjustment 0x106C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD3_DADDR TCD Destination Address 0x1070 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD3_DOFF TCD Signed Destination Address Offset 0x1074 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD3_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1076 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD3_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1076 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD3_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1078 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD3_CSR TCD Control and Status 0x107C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD3_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x107E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD3_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x107E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD4_SADDR TCD Source Address 0x1080 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD4_SOFF TCD Signed Source Address Offset 0x1084 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD4_ATTR TCD Transfer Attributes 0x1086 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD4_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1088 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD4_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1088 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD4_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1088 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD4_SLAST TCD Last Source Address Adjustment 0x108C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD4_DADDR TCD Destination Address 0x1090 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD4_DOFF TCD Signed Destination Address Offset 0x1094 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD4_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1096 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD4_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1096 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD4_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1098 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD4_CSR TCD Control and Status 0x109C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD4_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x109E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD4_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x109E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD5_SADDR TCD Source Address 0x10A0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD5_SOFF TCD Signed Source Address Offset 0x10A4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD5_ATTR TCD Transfer Attributes 0x10A6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD5_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x10A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD5_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x10A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD5_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x10A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD5_SLAST TCD Last Source Address Adjustment 0x10AC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD5_DADDR TCD Destination Address 0x10B0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD5_DOFF TCD Signed Destination Address Offset 0x10B4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD5_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x10B6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD5_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x10B6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD5_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10B8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD5_CSR TCD Control and Status 0x10BC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD5_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x10BE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD5_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x10BE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD6_SADDR TCD Source Address 0x10C0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD6_SOFF TCD Signed Source Address Offset 0x10C4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD6_ATTR TCD Transfer Attributes 0x10C6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD6_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x10C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD6_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x10C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD6_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x10C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD6_SLAST TCD Last Source Address Adjustment 0x10CC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD6_DADDR TCD Destination Address 0x10D0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD6_DOFF TCD Signed Destination Address Offset 0x10D4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD6_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x10D6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD6_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x10D6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD6_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10D8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD6_CSR TCD Control and Status 0x10DC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD6_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x10DE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD6_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x10DE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD7_SADDR TCD Source Address 0x10E0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD7_SOFF TCD Signed Source Address Offset 0x10E4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD7_ATTR TCD Transfer Attributes 0x10E6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD7_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x10E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD7_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x10E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD7_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x10E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD7_SLAST TCD Last Source Address Adjustment 0x10EC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD7_DADDR TCD Destination Address 0x10F0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD7_DOFF TCD Signed Destination Address Offset 0x10F4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD7_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x10F6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD7_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x10F6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD7_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10F8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD7_CSR TCD Control and Status 0x10FC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD7_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x10FE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD7_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x10FE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD8_SADDR TCD Source Address 0x1100 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD8_SOFF TCD Signed Source Address Offset 0x1104 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD8_ATTR TCD Transfer Attributes 0x1106 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD8_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1108 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD8_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1108 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD8_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1108 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD8_SLAST TCD Last Source Address Adjustment 0x110C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD8_DADDR TCD Destination Address 0x1110 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD8_DOFF TCD Signed Destination Address Offset 0x1114 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD8_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1116 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD8_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1116 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD8_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1118 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD8_CSR TCD Control and Status 0x111C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD8_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x111E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD8_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x111E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD9_SADDR TCD Source Address 0x1120 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD9_SOFF TCD Signed Source Address Offset 0x1124 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD9_ATTR TCD Transfer Attributes 0x1126 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD9_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1128 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD9_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1128 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD9_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1128 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD9_SLAST TCD Last Source Address Adjustment 0x112C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD9_DADDR TCD Destination Address 0x1130 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD9_DOFF TCD Signed Destination Address Offset 0x1134 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD9_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1136 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD9_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1136 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD9_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1138 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD9_CSR TCD Control and Status 0x113C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD9_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x113E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD9_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x113E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD10_SADDR TCD Source Address 0x1140 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD10_SOFF TCD Signed Source Address Offset 0x1144 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD10_ATTR TCD Transfer Attributes 0x1146 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD10_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1148 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD10_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1148 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD10_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1148 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD10_SLAST TCD Last Source Address Adjustment 0x114C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD10_DADDR TCD Destination Address 0x1150 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD10_DOFF TCD Signed Destination Address Offset 0x1154 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD10_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1156 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD10_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1156 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD10_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1158 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD10_CSR TCD Control and Status 0x115C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD10_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x115E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD10_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x115E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD11_SADDR TCD Source Address 0x1160 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD11_SOFF TCD Signed Source Address Offset 0x1164 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD11_ATTR TCD Transfer Attributes 0x1166 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD11_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1168 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD11_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1168 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD11_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1168 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD11_SLAST TCD Last Source Address Adjustment 0x116C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD11_DADDR TCD Destination Address 0x1170 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD11_DOFF TCD Signed Destination Address Offset 0x1174 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD11_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1176 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD11_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1176 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD11_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1178 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD11_CSR TCD Control and Status 0x117C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD11_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x117E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD11_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x117E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD12_SADDR TCD Source Address 0x1180 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD12_SOFF TCD Signed Source Address Offset 0x1184 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD12_ATTR TCD Transfer Attributes 0x1186 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD12_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1188 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD12_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1188 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD12_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1188 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD12_SLAST TCD Last Source Address Adjustment 0x118C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD12_DADDR TCD Destination Address 0x1190 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD12_DOFF TCD Signed Destination Address Offset 0x1194 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD12_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1196 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD12_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1196 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD12_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1198 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD12_CSR TCD Control and Status 0x119C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD12_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x119E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD12_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x119E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD13_SADDR TCD Source Address 0x11A0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD13_SOFF TCD Signed Source Address Offset 0x11A4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD13_ATTR TCD Transfer Attributes 0x11A6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD13_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x11A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD13_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x11A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD13_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x11A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD13_SLAST TCD Last Source Address Adjustment 0x11AC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD13_DADDR TCD Destination Address 0x11B0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD13_DOFF TCD Signed Destination Address Offset 0x11B4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD13_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x11B6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD13_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x11B6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD13_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11B8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD13_CSR TCD Control and Status 0x11BC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD13_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x11BE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD13_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x11BE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD14_SADDR TCD Source Address 0x11C0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD14_SOFF TCD Signed Source Address Offset 0x11C4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD14_ATTR TCD Transfer Attributes 0x11C6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD14_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x11C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD14_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x11C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD14_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x11C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD14_SLAST TCD Last Source Address Adjustment 0x11CC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD14_DADDR TCD Destination Address 0x11D0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD14_DOFF TCD Signed Destination Address Offset 0x11D4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD14_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x11D6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD14_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x11D6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD14_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11D8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD14_CSR TCD Control and Status 0x11DC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD14_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x11DE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD14_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x11DE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD15_SADDR TCD Source Address 0x11E0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD15_SOFF TCD Signed Source Address Offset 0x11E4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD15_ATTR TCD Transfer Attributes 0x11E6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD15_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x11E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD15_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x11E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD15_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x11E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD15_SLAST TCD Last Source Address Adjustment 0x11EC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD15_DADDR TCD Destination Address 0x11F0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD15_DOFF TCD Signed Destination Address Offset 0x11F4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD15_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x11F6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD15_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x11F6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD15_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11F8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD15_CSR TCD Control and Status 0x11FC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD15_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x11FE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD15_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x11FE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD16_SADDR TCD Source Address 0x1200 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD16_SOFF TCD Signed Source Address Offset 0x1204 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD16_ATTR TCD Transfer Attributes 0x1206 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD16_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1208 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD16_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1208 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD16_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1208 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD16_SLAST TCD Last Source Address Adjustment 0x120C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD16_DADDR TCD Destination Address 0x1210 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD16_DOFF TCD Signed Destination Address Offset 0x1214 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD16_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1216 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD16_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1216 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD16_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1218 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD16_CSR TCD Control and Status 0x121C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD16_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x121E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD16_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x121E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD17_SADDR TCD Source Address 0x1220 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD17_SOFF TCD Signed Source Address Offset 0x1224 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD17_ATTR TCD Transfer Attributes 0x1226 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD17_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1228 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD17_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1228 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD17_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1228 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD17_SLAST TCD Last Source Address Adjustment 0x122C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD17_DADDR TCD Destination Address 0x1230 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD17_DOFF TCD Signed Destination Address Offset 0x1234 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD17_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1236 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD17_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1236 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD17_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1238 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD17_CSR TCD Control and Status 0x123C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD17_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x123E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD17_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x123E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD18_SADDR TCD Source Address 0x1240 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD18_SOFF TCD Signed Source Address Offset 0x1244 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD18_ATTR TCD Transfer Attributes 0x1246 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD18_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1248 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD18_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1248 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD18_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1248 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD18_SLAST TCD Last Source Address Adjustment 0x124C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD18_DADDR TCD Destination Address 0x1250 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD18_DOFF TCD Signed Destination Address Offset 0x1254 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD18_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1256 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD18_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1256 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD18_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1258 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD18_CSR TCD Control and Status 0x125C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD18_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x125E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD18_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x125E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD19_SADDR TCD Source Address 0x1260 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD19_SOFF TCD Signed Source Address Offset 0x1264 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD19_ATTR TCD Transfer Attributes 0x1266 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD19_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1268 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD19_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1268 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD19_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1268 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD19_SLAST TCD Last Source Address Adjustment 0x126C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD19_DADDR TCD Destination Address 0x1270 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD19_DOFF TCD Signed Destination Address Offset 0x1274 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD19_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1276 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD19_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1276 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD19_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1278 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD19_CSR TCD Control and Status 0x127C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD19_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x127E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD19_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x127E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD20_SADDR TCD Source Address 0x1280 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD20_SOFF TCD Signed Source Address Offset 0x1284 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD20_ATTR TCD Transfer Attributes 0x1286 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD20_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1288 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD20_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1288 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD20_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1288 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD20_SLAST TCD Last Source Address Adjustment 0x128C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD20_DADDR TCD Destination Address 0x1290 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD20_DOFF TCD Signed Destination Address Offset 0x1294 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD20_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1296 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD20_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1296 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD20_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1298 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD20_CSR TCD Control and Status 0x129C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD20_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x129E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD20_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x129E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD21_SADDR TCD Source Address 0x12A0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD21_SOFF TCD Signed Source Address Offset 0x12A4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD21_ATTR TCD Transfer Attributes 0x12A6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD21_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x12A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD21_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x12A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD21_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x12A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD21_SLAST TCD Last Source Address Adjustment 0x12AC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD21_DADDR TCD Destination Address 0x12B0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD21_DOFF TCD Signed Destination Address Offset 0x12B4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD21_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x12B6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD21_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x12B6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD21_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x12B8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD21_CSR TCD Control and Status 0x12BC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD21_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x12BE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD21_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x12BE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD22_SADDR TCD Source Address 0x12C0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD22_SOFF TCD Signed Source Address Offset 0x12C4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD22_ATTR TCD Transfer Attributes 0x12C6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD22_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x12C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD22_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x12C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD22_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x12C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD22_SLAST TCD Last Source Address Adjustment 0x12CC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD22_DADDR TCD Destination Address 0x12D0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD22_DOFF TCD Signed Destination Address Offset 0x12D4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD22_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x12D6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD22_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x12D6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD22_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x12D8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD22_CSR TCD Control and Status 0x12DC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD22_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x12DE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD22_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x12DE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD23_SADDR TCD Source Address 0x12E0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD23_SOFF TCD Signed Source Address Offset 0x12E4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD23_ATTR TCD Transfer Attributes 0x12E6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD23_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x12E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD23_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x12E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD23_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x12E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD23_SLAST TCD Last Source Address Adjustment 0x12EC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD23_DADDR TCD Destination Address 0x12F0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD23_DOFF TCD Signed Destination Address Offset 0x12F4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD23_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x12F6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD23_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x12F6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD23_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x12F8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD23_CSR TCD Control and Status 0x12FC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD23_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x12FE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD23_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x12FE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD24_SADDR TCD Source Address 0x1300 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD24_SOFF TCD Signed Source Address Offset 0x1304 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD24_ATTR TCD Transfer Attributes 0x1306 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD24_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1308 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD24_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1308 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD24_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1308 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD24_SLAST TCD Last Source Address Adjustment 0x130C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD24_DADDR TCD Destination Address 0x1310 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD24_DOFF TCD Signed Destination Address Offset 0x1314 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD24_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1316 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD24_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1316 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD24_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1318 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD24_CSR TCD Control and Status 0x131C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD24_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x131E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD24_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x131E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD25_SADDR TCD Source Address 0x1320 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD25_SOFF TCD Signed Source Address Offset 0x1324 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD25_ATTR TCD Transfer Attributes 0x1326 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD25_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1328 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD25_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1328 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD25_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1328 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD25_SLAST TCD Last Source Address Adjustment 0x132C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD25_DADDR TCD Destination Address 0x1330 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD25_DOFF TCD Signed Destination Address Offset 0x1334 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD25_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1336 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD25_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1336 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD25_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1338 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD25_CSR TCD Control and Status 0x133C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD25_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x133E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD25_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x133E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD26_SADDR TCD Source Address 0x1340 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD26_SOFF TCD Signed Source Address Offset 0x1344 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD26_ATTR TCD Transfer Attributes 0x1346 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD26_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1348 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD26_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1348 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD26_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1348 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD26_SLAST TCD Last Source Address Adjustment 0x134C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD26_DADDR TCD Destination Address 0x1350 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD26_DOFF TCD Signed Destination Address Offset 0x1354 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD26_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1356 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD26_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1356 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD26_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1358 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD26_CSR TCD Control and Status 0x135C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD26_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x135E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD26_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x135E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD27_SADDR TCD Source Address 0x1360 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD27_SOFF TCD Signed Source Address Offset 0x1364 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD27_ATTR TCD Transfer Attributes 0x1366 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD27_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1368 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD27_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1368 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD27_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1368 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD27_SLAST TCD Last Source Address Adjustment 0x136C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD27_DADDR TCD Destination Address 0x1370 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD27_DOFF TCD Signed Destination Address Offset 0x1374 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD27_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1376 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD27_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1376 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD27_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1378 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD27_CSR TCD Control and Status 0x137C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD27_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x137E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD27_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x137E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD28_SADDR TCD Source Address 0x1380 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD28_SOFF TCD Signed Source Address Offset 0x1384 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD28_ATTR TCD Transfer Attributes 0x1386 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD28_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1388 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD28_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1388 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD28_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1388 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD28_SLAST TCD Last Source Address Adjustment 0x138C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD28_DADDR TCD Destination Address 0x1390 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD28_DOFF TCD Signed Destination Address Offset 0x1394 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD28_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1396 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD28_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1396 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD28_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1398 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD28_CSR TCD Control and Status 0x139C 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD28_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x139E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD28_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x139E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD29_SADDR TCD Source Address 0x13A0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD29_SOFF TCD Signed Source Address Offset 0x13A4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD29_ATTR TCD Transfer Attributes 0x13A6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD29_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x13A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD29_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x13A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD29_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x13A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD29_SLAST TCD Last Source Address Adjustment 0x13AC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD29_DADDR TCD Destination Address 0x13B0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD29_DOFF TCD Signed Destination Address Offset 0x13B4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD29_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x13B6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD29_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x13B6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD29_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x13B8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD29_CSR TCD Control and Status 0x13BC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD29_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x13BE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD29_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x13BE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD30_SADDR TCD Source Address 0x13C0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD30_SOFF TCD Signed Source Address Offset 0x13C4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD30_ATTR TCD Transfer Attributes 0x13C6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD30_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x13C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD30_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x13C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD30_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x13C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD30_SLAST TCD Last Source Address Adjustment 0x13CC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD30_DADDR TCD Destination Address 0x13D0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD30_DOFF TCD Signed Destination Address Offset 0x13D4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD30_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x13D6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD30_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x13D6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD30_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x13D8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD30_CSR TCD Control and Status 0x13DC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD30_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x13DE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD30_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x13DE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD31_SADDR TCD Source Address 0x13E0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD31_SOFF TCD Signed Source Address Offset 0x13E4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD31_ATTR TCD Transfer Attributes 0x13E6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write EIGHT 8-bit 0 SIXTEEN_BIT 16-bit 0x1 THIRTYTWO_BIT 32-bit 0x2 SIXTYFOUR 64-bit 0x3 THIRTYTWO_BYTE 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write DISABLED Source address modulo feature is disabled 0 ENABLED Value defines address range used to set up circular data queue 0x1 ENABLED Value defines address range used to set up circular data queue 0x2 ENABLED Value defines address range used to set up circular data queue 0x3 ENABLED Value defines address range used to set up circular data queue 0x4 ENABLED Value defines address range used to set up circular data queue 0x5 ENABLED Value defines address range used to set up circular data queue 0x6 ENABLED Value defines address range used to set up circular data queue 0x7 ENABLED Value defines address range used to set up circular data queue 0x8 ENABLED Value defines address range used to set up circular data queue 0x9 TCD31_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x13E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD31_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x13E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD31_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x13E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset Enable 30 1 read-write DISABLED The minor loop offset is not applied to the DADDR 0 ENABLED The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write DISABLED The minor loop offset is not applied to the SADDR 0 ENABLED The minor loop offset is applied to the SADDR 0x1 TCD31_SLAST TCD Last Source Address Adjustment 0x13EC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD31_DADDR TCD Destination Address 0x13F0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD31_DOFF TCD Signed Destination Address Offset 0x13F4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD31_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x13F6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD31_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x13F6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD31_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x13F8 32 read-write 0 0 DLASTSGA Destination last address adjustment, or next memory address TCD for channel (scatter/gather) 0 32 read-write TCD31_CSR TCD Control and Status 0x13FC 16 read-write 0 0 START Channel Start 0 1 read-write NO_START Channel is not explicitly started 0 START Channel is explicitly started via a software initiated service request 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write DISABLED End of major loop interrupt is disabled 0 ENABLED End of major loop interrupt is enabled 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write DISABLED Half-point interrupt is disabled 0 ENABLED Half-point interrupt is enabled 0x1 DREQ Disable Request 3 1 read-write NO_CLEAR The channel's ERQ field is not affected 0 CLEAR The channel's ERQ field value changes to 0 when the major loop is complete 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write NORMAL The current channel's TCD is normal format 0 SCATTER The current channel's TCD specifies a scatter gather format 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write DISABLED No eDMA engine stalls 0 STALL4 eDMA engine stalls for 4 cycles after each R/W 0x2 STALL8 eDMA engine stalls for 8 cycles after each R/W 0x3 TCD31_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x13FE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 TCD31_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x13FE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write DISABLED Channel-to-channel linking is disabled 0 ENABLED Channel-to-channel linking is enabled 0x1 DMAMUX0 DMAMUX DMAMUX 0x40074000 0 0x80 registers 32 0x4 CHCFG[%s] Channel index Configuration Register 0 32 read-write 0 0xFFFFFFFF SOURCE DMA Channel Source (Slot Number) 0 8 read-write A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 LPUART1 LPUART LPUART LPUART 0x4007C000 0 0x30 registers LPUART1 20 VERID Version ID Register 0 32 read-only 0x4010003 0xFFFFFFFF FEATURE Feature Identification Number 0 16 read-only STANDARD Standard feature set. 0x1 MODEM Standard feature set with MODEM/IrDA support. 0x3 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x202 0xFFFFFFFF TXFIFO Transmit FIFO Size 0 8 read-only RXFIFO Receive FIFO Size 8 8 read-only GLOBAL LPUART Global Register 0x8 32 read-write 0 0xFFFFFFFF RST Software Reset 1 1 read-write NO_EFFECT Module is not reset. 0 RESET Module is reset. 0x1 PINCFG LPUART Pin Configuration Register 0xC 32 read-write 0 0xFFFFFFFF TRGSEL Trigger Select 0 2 read-write DISABLED Input trigger is disabled. 0 TRG_RXD Input trigger is used instead of RXD pin input. 0x1 TRG_CTS Input trigger is used instead of CTS_B pin input. 0x2 TRG_TXD Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is internally ANDed with the input trigger. 0x3 BAUD LPUART Baud Rate Register 0x10 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write ONE One stop bit. 0 TWO Two stop bits. 0x1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write DISABLE Hardware interrupts from STAT[RXEDGIF] are disabled. 0 ENABLE Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. 0x1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write DISABLE Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). 0 ENABLE Hardware interrupt is requested when STAT[LBKDIF] flag is 1. 0x1 RESYNCDIS Resynchronization Disable 16 1 read-write RESYNC Resynchronization during received data word is supported. 0 NO_RESYNC Resynchronization during received data word is disabled. 0x1 BOTHEDGE Both Edge Sampling 17 1 read-write DISABLED Receiver samples input data using the rising edge of the baud rate clock. 0 ENABLED Receiver samples input data using the rising and falling edge of the baud rate clock. 0x1 MATCFG Match Configuration 18 2 read-write ADDR_MATCH Address Match Wakeup 0 IDLE_MATCH Idle Match Wakeup 0x1 ONOFF_MATCH Match On and Match Off 0x2 RWU_MATCH Enables RWU on Data Match and Match On/Off for transmitter CTS input 0x3 RDMAE Receiver Full DMA Enable 21 1 read-write DISABLED DMA request disabled. 0 ENABLED DMA request enabled. 0x1 TDMAE Transmitter DMA Enable 23 1 read-write DISABLED DMA request disabled. 0 ENABLED DMA request enabled. 0x1 OSR Oversampling Ratio 24 5 read-write DEFAULT Writing 0 to this field results in an oversampling ratio of 16 0 OSR_4 Oversampling ratio of 4, requires BOTHEDGE to be set. 0x3 OSR_5 Oversampling ratio of 5, requires BOTHEDGE to be set. 0x4 OSR_6 Oversampling ratio of 6, requires BOTHEDGE to be set. 0x5 OSR_7 Oversampling ratio of 7, requires BOTHEDGE to be set. 0x6 OSR_8 Oversampling ratio of 8. 0x7 OSR_9 Oversampling ratio of 9. 0x8 OSR_10 Oversampling ratio of 10. 0x9 OSR_11 Oversampling ratio of 11. 0xA OSR_12 Oversampling ratio of 12. 0xB OSR_13 Oversampling ratio of 13. 0xC OSR_14 Oversampling ratio of 14. 0xD OSR_15 Oversampling ratio of 15. 0xE OSR_16 Oversampling ratio of 16. 0xF OSR_17 Oversampling ratio of 17. 0x10 OSR_18 Oversampling ratio of 18. 0x11 OSR_19 Oversampling ratio of 19. 0x12 OSR_20 Oversampling ratio of 20. 0x13 OSR_21 Oversampling ratio of 21. 0x14 OSR_22 Oversampling ratio of 22. 0x15 OSR_23 Oversampling ratio of 23. 0x16 OSR_24 Oversampling ratio of 24. 0x17 OSR_25 Oversampling ratio of 25. 0x18 OSR_26 Oversampling ratio of 26. 0x19 OSR_27 Oversampling ratio of 27. 0x1A OSR_28 Oversampling ratio of 28. 0x1B OSR_29 Oversampling ratio of 29. 0x1C OSR_30 Oversampling ratio of 30. 0x1D OSR_31 Oversampling ratio of 31. 0x1E OSR_32 Oversampling ratio of 32. 0x1F M10 10-bit Mode select 29 1 read-write DISABLED Receiver and transmitter use 7-bit to 9-bit data characters. 0 ENABLED Receiver and transmitter use 10-bit data characters. 0x1 MAEN2 Match Address Mode Enable 2 30 1 read-write DISABLED Normal operation. 0 ENABLED Enables automatic address matching or data matching mode for MATCH[MA2]. 0x1 MAEN1 Match Address Mode Enable 1 31 1 read-write DISABLED Normal operation. 0 ENABLED Enables automatic address matching or data matching mode for MATCH[MA1]. 0x1 STAT LPUART Status Register 0x14 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write oneToClear NOMATCH Received data is not equal to MA2 0 MATCH Received data is equal to MA2 0x1 MA1F Match 1 Flag 15 1 read-write oneToClear NOMATCH Received data is not equal to MA1 0 MATCH Received data is equal to MA1 0x1 PF Parity Error Flag 16 1 read-write oneToClear NOPARITY No parity error. 0 PARITY Parity error. 0x1 FE Framing Error Flag 17 1 read-write oneToClear NOERROR No framing error detected. This does not guarantee the framing is correct. 0 ERROR Framing error. 0x1 NF Noise Flag 18 1 read-write oneToClear NONOISE No noise detected. 0 NOISE Noise detected in the received character in the DATA register. 0x1 OR Receiver Overrun Flag 19 1 read-write oneToClear NO_OVERRUN No overrun. 0 OVERRUN Receive overrun (new LPUART data lost). 0x1 IDLE Idle Line Flag 20 1 read-write oneToClear NOIDLE No idle line detected. 0 IDLE Idle line is detected. 0x1 RDRF Receive Data Register Full Flag 21 1 read-only NO_RXDATA Receive FIFO level is less than watermark. 0 RXDATA Receive FIFO level is equal or greater than watermark. 0x1 TC Transmission Complete Flag 22 1 read-only ACTIVE Transmitter active (sending data, a preamble, or a break). 0 COMPLETE Transmitter idle (transmission activity complete). 0x1 TDRE Transmit Data Register Empty Flag 23 1 read-only TXDATA Transmit FIFO level is greater than watermark. 0 NO_TXDATA Transmit FIFO level is equal or less than watermark. 0x1 RAF Receiver Active Flag 24 1 read-only IDLE LPUART receiver idle waiting for a start bit. 0 ACTIVE LPUART receiver active (RXD input not idle). 0x1 LBKDE LIN Break Detection Enable 25 1 read-write DISABLED LIN break detect is disabled, normal break character can be detected. 0 ENABLED LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). 0x1 BRK13 Break Character Generation Length 26 1 read-write SHORT Break character is transmitted with length of 9 to 13 bit times. 0 LONG Break character is transmitted with length of 12 to 15 bit times. 0x1 RWUID Receive Wake Up Idle Detect 27 1 read-write IDLE_NOTSET During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. 0 IDLE_SET During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. 0x1 RXINV Receive Data Inversion 28 1 read-write NOT_INVERTED Receive data not inverted. 0 INVERTED Receive data inverted. 0x1 MSBF MSB First 29 1 read-write LSB_FIRST LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. 0 MSB_FIRST MSB (identified as bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. . 0x1 RXEDGIF RXD Pin Active Edge Interrupt Flag 30 1 read-write oneToClear NO_EDGE No active edge on the receive pin has occurred. 0 EDGE An active edge on the receive pin has occurred. 0x1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write oneToClear NOT_DETECTED No LIN break character has been detected. 0 DETECTED LIN break character has been detected. 0x1 CTRL LPUART Control Register 0x18 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write EVEN Even parity. 0 ODD Odd parity. 0x1 PE Parity Enable 1 1 read-write DISABLED No hardware parity generation or checking. 0 ENABLED Parity enabled. 0x1 ILT Idle Line Type Select 2 1 read-write FROM_START Idle character bit count starts after start bit. 0 FROM_STOP Idle character bit count starts after stop bit. 0x1 WAKE Receiver Wakeup Method Select 3 1 read-write IDLE Configures RWU for idle-line wakeup. 0 MARK Configures RWU with address-mark wakeup. 0x1 M 9-Bit or 8-Bit Mode Select 4 1 read-write DATA8 Receiver and transmitter use 8-bit data characters. 0 DATA9 Receiver and transmitter use 9-bit data characters. 0x1 RSRC Receiver Source Select 5 1 read-write NO_EFFECT Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. 0 ONEWIRE Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. 0x1 DOZEEN Doze Enable 6 1 read-write ENABLED LPUART is enabled in Doze mode. 0 DISABLED LPUART is disabled in Doze mode . 0x1 LOOPS Loop Mode Select 7 1 read-write NOFFECT Normal operation - RXD and TXD use separate pins. 0 LOOPBACK Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). 0x1 IDLECFG Idle Configuration 8 3 read-write IDLE_1 1 idle character 0 IDLE_2 2 idle characters 0x1 IDLE_4 4 idle characters 0x2 IDLE_8 8 idle characters 0x3 IDLE_16 16 idle characters 0x4 IDLE_32 32 idle characters 0x5 IDLE_64 64 idle characters 0x6 IDLE_128 128 idle characters 0x7 M7 7-Bit Mode Select 11 1 read-write NO_EFFECT Receiver and transmitter use 8-bit to 10-bit data characters. 0 DATA7 Receiver and transmitter use 7-bit data characters. 0x1 MA2IE Match 2 Interrupt Enable 14 1 read-write DISABLED MA2F interrupt disabled 0 ENABLED MA2F interrupt enabled 0x1 MA1IE Match 1 Interrupt Enable 15 1 read-write DISABLED MA1F interrupt disabled 0 ENABLED MA1F interrupt enabled 0x1 SBK Send Break 16 1 read-write NO_EFFECT Normal transmitter operation. 0 TX_BREAK Queue break character(s) to be sent. 0x1 RWU Receiver Wakeup Control 17 1 read-write NO_EFFECT Normal receiver operation. 0 RX_WAKEUP LPUART receiver in standby waiting for wakeup condition. 0x1 RE Receiver Enable 18 1 read-write DISABLED Receiver disabled. 0 ENABLED Receiver enabled. 0x1 TE Transmitter Enable 19 1 read-write DISABLED Transmitter disabled. 0 ENABLED Transmitter enabled. 0x1 ILIE Idle Line Interrupt Enable 20 1 read-write DISABLED Hardware interrupts from IDLE disabled; use polling. 0 ENABLED Hardware interrupt is requested when IDLE flag is 1. 0x1 RIE Receiver Interrupt Enable 21 1 read-write DISABLED Hardware interrupts from RDRF disabled. 0 ENABLED Hardware interrupt is requested when RDRF flag is 1. 0x1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write DISABLED Hardware interrupts from TC disabled. 0 ENABLED Hardware interrupt is requested when TC flag is 1. 0x1 TIE Transmit Interrupt Enable 23 1 read-write DISABLED Hardware interrupts from TDRE disabled. 0 ENABLED Hardware interrupt is requested when TDRE flag is 1. 0x1 PEIE Parity Error Interrupt Enable 24 1 read-write DISABLED PF interrupts disabled; use polling). 0 ENABLED Hardware interrupt is requested when PF is set. 0x1 FEIE Framing Error Interrupt Enable 25 1 read-write DISABLED FE interrupts disabled; use polling. 0 ENABLED Hardware interrupt is requested when FE is set. 0x1 NEIE Noise Error Interrupt Enable 26 1 read-write DISABLED NF interrupts disabled; use polling. 0 ENABLED Hardware interrupt is requested when NF is set. 0x1 ORIE Overrun Interrupt Enable 27 1 read-write DISABLED OR interrupts disabled; use polling. 0 ENABLED Hardware interrupt is requested when OR is set. 0x1 TXINV Transmit Data Inversion 28 1 read-write NOT_INVERTED Transmit data not inverted. 0 INVERTED Transmit data inverted. 0x1 TXDIR TXD Pin Direction in Single-Wire Mode 29 1 read-write TX_INPUT TXD pin is an input in single-wire mode. 0 TX_OUTPUT TXD pin is an output in single-wire mode. 0x1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0x1C 32 read-write 0x1000 0xFFFFFFFF R0T0 R0T0 0 1 read-write R1T1 R1T1 1 1 read-write R2T2 R2T2 2 1 read-write R3T3 R3T3 3 1 read-write R4T4 R4T4 4 1 read-write R5T5 R5T5 5 1 read-write R6T6 R6T6 6 1 read-write R7T7 R7T7 7 1 read-write R8T8 R8T8 8 1 read-write R9T9 R9T9 9 1 read-write IDLINE Idle Line 11 1 read-only NO_IDLE Receiver was not idle before receiving this character. 0 IDLE Receiver was idle before receiving this character. 0x1 RXEMPT Receive Buffer Empty 12 1 read-only NOT_EMPTY Receive buffer contains valid data. 0 EMPTY Receive buffer is empty, data returned on read is not valid. 0x1 FRETSC Frame Error / Transmit Special Character 13 1 read-write NO_ERROR The dataword is received without a frame error on read, or transmit a normal character on write. 0 ERROR The dataword is received with a frame error, or transmit an idle or break character on transmit. 0x1 PARITYE Parity Error 14 1 read-only NO_PARITY The dataword is received without a parity error. 0 PARITY The dataword is received with a parity error. 0x1 NOISY Noisy Data Received 15 1 read-only NO_NOISE The dataword is received without noise. 0 NOISE The data is received with noise. 0x1 MATCH LPUART Match Address Register 0x20 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write DISABLED CTS has no effect on the transmitter. 0 ENABLED Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. 0x1 TXRTSE Transmitter request-to-send enable 1 1 read-write DISABLED The transmitter has no effect on RTS. 0 ENABLED When a character is placed into an empty transmit shift register, RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter FIFO and shift register are completely sent, including the last stop bit. 0x1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write LOW Transmitter RTS is active low. 0 HIGH Transmitter RTS is active high. 0x1 RXRTSE Receiver request-to-send enable 3 1 read-write DISABLED The receiver has no effect on RTS. 0 ENABLED RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. 0x1 TXCTSC Transmit CTS Configuration 4 1 read-write START CTS input is sampled at the start of each character. 0 IDLE CTS input is sampled when the transmitter is idle. 0x1 TXCTSSRC Transmit CTS Source 5 1 read-write CTS CTS input is the CTS_B pin. 0 MATCH CTS input is an internal connection to the receiver address match result. 0x1 RTSWATER Receive RTS Configuration 8 2 read-write TNP Transmitter narrow pulse 16 2 read-write ONE_SAMPLE 1/OSR. 0 TWO_SAMPLE 2/OSR. 0x1 THREE_SAMPLE 3/OSR. 0x2 FOUR_SAMPLE 4/OSR. 0x3 IREN Infrared enable 18 1 read-write DISABLED IR disabled. 0 ENABLED IR enabled. 0x1 FIFO LPUART FIFO Register 0x28 32 read-write 0xC00011 0xFFFFFFFF RXFIFOSIZE Receive FIFO Buffer Depth 0 3 read-only FIFO_1 Receive FIFO/Buffer depth = 1 dataword. 0 FIFO_4 Receive FIFO/Buffer depth = 4 datawords. 0x1 FIFO_8 Receive FIFO/Buffer depth = 8 datawords. 0x2 FIFO_16 Receive FIFO/Buffer depth = 16 datawords. 0x3 FIFO_32 Receive FIFO/Buffer depth = 32 datawords. 0x4 FIFO_64 Receive FIFO/Buffer depth = 64 datawords. 0x5 FIFO_128 Receive FIFO/Buffer depth = 128 datawords. 0x6 FIFO_256 Receive FIFO/Buffer depth = 256 datawords. 0x7 RXFE Receive FIFO Enable 3 1 read-write DISABLED Receive FIFO is not enabled. Buffer depth is 1. 0 ENABLED Receive FIFO is enabled. Buffer depth is indicted by RXFIFOSIZE. 0x1 TXFIFOSIZE Transmit FIFO Buffer Depth 4 3 read-only FIFO_1 Transmit FIFO/Buffer depth = 1 dataword. 0 FIFO_4 Transmit FIFO/Buffer depth = 4 datawords. 0x1 FIFO_8 Transmit FIFO/Buffer depth = 8 datawords. 0x2 FIFO_16 Transmit FIFO/Buffer depth = 16 datawords. 0x3 FIFO_32 Transmit FIFO/Buffer depth = 32 datawords. 0x4 FIFO_64 Transmit FIFO/Buffer depth = 64 datawords. 0x5 FIFO_128 Transmit FIFO/Buffer depth = 128 datawords. 0x6 FIFO_256 Transmit FIFO/Buffer depth = 256 datawords 0x7 TXFE Transmit FIFO Enable 7 1 read-write DISABLED Transmit FIFO is not enabled. Buffer depth is 1. 0 ENABLED Transmit FIFO is enabled. Buffer depth is indicated by TXFIFOSIZE. 0x1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write DISABLED RXUF flag does not generate an interrupt to the host. 0 ENABLED RXUF flag generates an interrupt to the host. 0x1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write DISABLED TXOF flag does not generate an interrupt to the host. 0 ENABLED TXOF flag generates an interrupt to the host. 0x1 RXIDEN Receiver Idle Empty Enable 10 3 read-write DISABLED Disable RDRF assertion due to partially filled FIFO when receiver is idle. 0 IDLE_1 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 0x1 IDLE_2 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 0x2 IDLE_4 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 0x3 IDLE_8 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 0x4 IDLE_16 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 0x5 IDLE_32 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 0x6 IDLE_64 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. 0x7 RXFLUSH Receive FIFO Flush 14 1 read-write NO_EFFECT No flush operation occurs. 0 RXFIFO_RST All data in the receive FIFO/buffer is cleared out. 0x1 TXFLUSH Transmit FIFO Flush 15 1 read-write NO_EFFECT No flush operation occurs. 0 TXFIFO_RST All data in the transmit FIFO is cleared out. 0x1 RXUF Receiver FIFO Underflow Flag 16 1 read-write oneToClear NO_UNDERFLOW No receive FIFO underflow has occurred since the last time the flag was cleared. 0 UNDERFLOW At least one receive FIFO underflow has occurred since the last time the flag was cleared. 0x1 TXOF Transmitter FIFO Overflow Flag 17 1 read-write oneToClear NO_OVERFLOW No transmit FIFO overflow has occurred since the last time the flag was cleared. 0 OVERFLOW At least one transmit FIFO overflow has occurred since the last time the flag was cleared. 0x1 RXEMPT Receive FIFO/Buffer Empty 22 1 read-only NOT_EMPTY Receive buffer is not empty. 0 EMPTY Receive buffer is empty. 0x1 TXEMPT Transmit FIFO/Buffer Empty 23 1 read-only NOT_EMPTY Transmit buffer is not empty. 0 EMPTY Transmit buffer is empty. 0x1 WATER LPUART Watermark Register 0x2C 32 read-write 0 0xFFFFFFFF TXWATER Transmit Watermark 0 2 read-write TXCOUNT Transmit Counter 8 3 read-only RXWATER Receive Watermark 16 2 read-write RXCOUNT Receive Counter 24 3 read-only LPUART2 LPUART LPUART 0x40080000 0 0x30 registers LPUART2 21 LPUART3 LPUART LPUART 0x40084000 0 0x30 registers LPUART3 22 LPUART4 LPUART LPUART 0x40088000 0 0x30 registers LPUART4 23 LPUART5 LPUART LPUART 0x4008C000 0 0x30 registers LPUART5 24 LPUART6 LPUART LPUART 0x40090000 0 0x30 registers LPUART6 25 LPUART7 LPUART LPUART 0x40094000 0 0x30 registers LPUART7 26 LPUART8 LPUART LPUART 0x40098000 0 0x30 registers LPUART8 27 LPUART9 LPUART LPUART 0x4009C000 0 0x30 registers LPUART9 28 LPUART10 LPUART LPUART 0x400A0000 0 0x30 registers LPUART10 29 LPUART11 LPUART LPUART 0x40C24000 0 0x30 registers LPUART11 30 LPUART12 LPUART LPUART 0x40C28000 0 0x30 registers LPUART12 31 FLEXIO1 FLEXIO FLEXIO FLEXIO 0x400AC000 0 0x8A0 registers FLEXIO1 110 VERID Version ID Register 0 32 read-only 0x2000001 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only standard Standard features implemented. 0 state_logic_parallel Supports state, logic and parallel modes. 0x1 pinctrl Supports pin control registers. 0x2 state_logic_parallel_pinctrl Supports state, logic and parallel modes; plus pin control registers. 0x3 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x2200808 0xFFFFFFFF SHIFTER Shifter Number 0 8 read-only TIMER Timer Number 8 8 read-only PIN Pin Number 16 8 read-only TRIGGER Trigger Number 24 8 read-only CTRL FlexIO Control Register 0x8 32 read-write 0 0xFFFFFFFF FLEXEN FlexIO Enable 0 1 read-write disable FlexIO module is disabled. 0 enable FlexIO module is enabled. 0x1 SWRST Software Reset 1 1 read-write disable Software reset is disabled 0 enable Software reset is enabled, all FlexIO registers except the Control Register are reset. 0x1 FASTACC Fast Access 2 1 read-write normal Configures for normal register accesses to FlexIO 0 fast Configures for fast register accesses to FlexIO 0x1 DBGE Debug Enable 30 1 read-write disable FlexIO is disabled in debug modes. 0 emable FlexIO is enabled in debug modes 0x1 DOZEN Doze Enable 31 1 read-write enable FlexIO enabled in Doze modes. 0 disable FlexIO disabled in Doze modes. 0x1 PIN Pin State Register 0xC 32 read-only 0 0xFFFFFFFF PDI Pin Data Input 0 32 read-only SHIFTSTAT Shifter Status Register 0x10 32 read-write 0 0xFFFFFFFF oneToClear SSF Shifter Status Flag 0 8 read-write oneToClear SHIFTERR Shifter Error Register 0x14 32 read-write 0 0xFFFFFFFF oneToClear SEF Shifter Error Flags 0 8 read-write oneToClear TIMSTAT Timer Status Register 0x18 32 read-write 0 0xFFFFFFFF oneToClear TSF Timer Status Flags 0 8 read-write oneToClear SHIFTSIEN Shifter Status Interrupt Enable 0x20 32 read-write 0 0xFFFFFFFF SSIE Shifter Status Interrupt Enable 0 8 read-write SHIFTEIEN Shifter Error Interrupt Enable 0x24 32 read-write 0 0xFFFFFFFF SEIE Shifter Error Interrupt Enable 0 8 read-write TIMIEN Timer Interrupt Enable Register 0x28 32 read-write 0 0xFFFFFFFF TEIE Timer Status Interrupt Enable 0 8 read-write SHIFTSDEN Shifter Status DMA Enable 0x30 32 read-write 0 0xFFFFFFFF SSDE Shifter Status DMA Enable 0 8 read-write TIMERSDEN Timer Status DMA Enable 0x38 32 read-write 0 0xFFFFFFFF TSDE Timer Status DMA Enable 0 8 read-write SHIFTSTATE Shifter State Register 0x40 32 read-write 0 0xFFFFFFFF STATE Current State Pointer 0 3 read-write 8 0x4 SHIFTCTL[%s] Shifter Control N Register 0x80 32 read-write 0 0xFFFFFFFF SMOD Shifter Mode 0 3 read-write disable Disabled. 0 receive Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 transmit Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 matchstore Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 matchcont Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 state State mode. SHIFTBUF contents are used for storing programmable state attributes. 0x6 logic Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. 0x7 PINPOL Shifter Pin Polarity 7 1 read-write active_high Pin is active high 0 active_low Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write PINCFG Shifter Pin Configuration 16 2 read-write disable Shifter pin output disabled 0 opend_bidirouten Shifter pin open drain or bidirectional output enable 0x1 bidir_outdata Shifter pin bidirectional output data 0x2 output Shifter pin output 0x3 TIMPOL Timer Polarity 23 1 read-write posedge Shift on posedge of Shift clock 0 negedge Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write 8 0x4 SHIFTCFG[%s] Shifter Configuration N Register 0x100 32 read-write 0 0xFFFFFFFF SSTART Shifter Start bit 0 2 read-write value00 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 value01 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 value10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 value11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write value00 Stop bit disabled for transmitter/receiver/match store 0 value10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 value11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 INSRC Input Source 8 1 read-write pin Pin 0 shifter_nplus1 Shifter N+1 Output 0x1 LATST Late Store 9 1 read-write preshift Shift register stores the pre-shift register state. 0 postshift Shift register stores the post-shift register state. 0x1 PWIDTH Parallel Width 16 5 read-write 8 0x4 SHIFTBUF[%s] Shifter Buffer N Register 0x200 32 read-write 0 0xFFFFFFFF SHIFTBUF Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFBIS[%s] Shifter Buffer N Bit Swapped Register 0x280 32 read-write 0 0xFFFFFFFF SHIFTBUFBIS Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFBYS[%s] Shifter Buffer N Byte Swapped Register 0x300 32 read-write 0 0xFFFFFFFF SHIFTBUFBYS Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFBBS[%s] Shifter Buffer N Bit Byte Swapped Register 0x380 32 read-write 0 0xFFFFFFFF SHIFTBUFBBS Shift Buffer 0 32 read-write 8 0x4 TIMCTL[%s] Timer Control N Register 0x400 32 read-write 0 0xFFFFFFFF TIMOD Timer Mode 0 3 read-write disable Timer Disabled. 0 dual8bit_baud Dual 8-bit counters baud mode. 0x1 dual8bit_pwm_h Dual 8-bit counters PWM high mode. 0x2 single16bit Single 16-bit counter mode. 0x3 single16bit_disable Single 16-bit counter disable mode. 0x4 dual8bit_word Dual 8-bit counters word mode. 0x5 dual8bit_pwm_l Dual 8-bit counters PWM low mode. 0x6 single16bit_in_capture Single 16-bit input capture mode. 0x7 ONETIM Timer One Time Operation 5 1 read-write not_blocked The timer enable event is generated as normal. 0 blocked The timer enable event is blocked unless timer status flag is clear. 0x1 PININS Timer Pin Input Select 6 1 read-write pinsel Timer pin input and output are selected by PINSEL. 0 pinselplus1 Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL. 0x1 PINPOL Timer Pin Polarity 7 1 read-write active_high Pin is active high 0 active_low Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write PINCFG Timer Pin Configuration 16 2 read-write outdisable Timer pin output disabled 0 opend_bidirouten Timer pin open drain or bidirectional output enable 0x1 bidir_outdata Timer pin bidirectional output data 0x2 output Timer pin output 0x3 TRGSRC Trigger Source 22 1 read-write ext_trig External trigger selected 0 internal_trig Internal trigger selected 0x1 TRGPOL Trigger Polarity 23 1 read-write active_high Trigger active high 0 active_low Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write 8 0x4 TIMCFG[%s] Timer Configuration N Register 0x480 32 read-write 0 0xFFFFFFFF TSTART Timer Start Bit 1 1 read-write disable Start bit disabled 0 enable Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write stop_disable Stop bit disabled 0 enable_tmrcmp Stop bit is enabled on timer compare 0x1 enable_tmrdisable Stop bit is enabled on timer disable 0x2 enable_tmr_cmp_dis Stop bit is enabled on timer compare and timer disable 0x3 TIMENA Timer Enable 8 3 read-write enable Timer always enabled 0 tmr_nminus1_en Timer enabled on Timer N-1 enable 0x1 tmr_trighi_en Timer enabled on Trigger high 0x2 tmr_trig_pin_hi_en Timer enabled on Trigger high and Pin high 0x3 tmr_pinrise_en Timer enabled on Pin rising edge 0x4 tmr_pinrise_trighi_en Timer enabled on Pin rising edge and Trigger high 0x5 tmr_trigrise_en Timer enabled on Trigger rising edge 0x6 tmr_trigedge_en Timer enabled on Trigger rising or falling edge 0x7 TIMDIS Timer Disable 12 3 read-write never Timer never disabled 0 tmr_nminus1 Timer disabled on Timer N-1 disable 0x1 tmr_cmp Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 tmr_cmp_triglow Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 pin_edge Timer disabled on Pin rising or falling edge 0x4 pin_edge_trighi Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 trig_falledge Timer disabled on Trigger falling edge 0x6 TIMRST Timer Reset 16 3 read-write never Timer never reset 0 tmr_out_hi Timer reset on Timer Output high. 0x1 pin_eq_tmr_out Timer reset on Timer Pin equal to Timer Output 0x2 trig_eq_tmr_out Timer reset on Timer Trigger equal to Timer Output 0x3 pin_rise_edge Timer reset on Timer Pin rising edge 0x4 trig_rise_edge Timer reset on Trigger rising edge 0x6 trig_edge Timer reset on Trigger rising or falling edge 0x7 TIMDEC Timer Decrement 20 3 read-write flexio_clk_shiftclk_tmr_out Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 trig_edge_shiftclk_tmr_out Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 pin_edge_shiftclk_tmr_out Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 trig_edge_shiftclk_trig_in Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 flexio_clk_div16_shiftclk_tmr_out Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output. 0x4 flexio_clk_div256_shiftclk_tmr_out Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output. 0x5 pin_rise_shiftclk_pin_in Decrement counter on Pin input (rising edge), Shift clock equals Pin input. 0x6 trig_rise_shiftclk_trig_in Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input. 0x7 TIMOUT Timer Output 24 2 read-write one Timer output is logic one when enabled and is not affected by timer reset 0 zero Timer output is logic zero when enabled and is not affected by timer reset 0x1 one_tmrreset Timer output is logic one when enabled and on timer reset 0x2 zero_tmrreset Timer output is logic zero when enabled and on timer reset 0x3 8 0x4 TIMCMP[%s] Timer Compare N Register 0x500 32 read-write 0 0xFFFFFFFF CMP Timer Compare Value 0 16 read-write 8 0x4 SHIFTBUFNBS[%s] Shifter Buffer N Nibble Byte Swapped Register 0x680 32 read-write 0 0xFFFFFFFF SHIFTBUFNBS Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFHWS[%s] Shifter Buffer N Half Word Swapped Register 0x700 32 read-write 0 0xFFFFFFFF SHIFTBUFHWS Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFNIS[%s] Shifter Buffer N Nibble Swapped Register 0x780 32 read-write 0 0xFFFFFFFF SHIFTBUFNIS Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFOES[%s] Shifter Buffer N Odd Even Swapped Register 0x800 32 read-write 0 0xFFFFFFFF SHIFTBUFOES Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFEOS[%s] Shifter Buffer N Even Odd Swapped Register 0x880 32 read-write 0 0xFFFFFFFF SHIFTBUFEOS Shift Buffer 0 32 read-write FLEXIO2 FLEXIO FLEXIO 0x400B0000 0 0x8A0 registers FLEXIO2 111 AOI1 AOI AOI AOI 0x400B8000 0 0x10 registers BFCRT010 Boolean Function Term 0 and 1 Configuration Register for EVENTn 0 16 read-write 0 0xFFFF PT1_DC Product term 1, D input configuration 0 2 read-write PT1_DC_0 Force the D input in this product term to a logical zero 0 PT1_DC_1 Pass the D input in this product term 0x1 PT1_DC_2 Complement the D input in this product term 0x2 PT1_DC_3 Force the D input in this product term to a logical one 0x3 PT1_CC Product term 1, C input configuration 2 2 read-write PT1_CC_0 Force the C input in this product term to a logical zero 0 PT1_CC_1 Pass the C input in this product term 0x1 PT1_CC_2 Complement the C input in this product term 0x2 PT1_CC_3 Force the C input in this product term to a logical one 0x3 PT1_BC Product term 1, B input configuration 4 2 read-write PT1_BC_0 Force the B input in this product term to a logical zero 0 PT1_BC_1 Pass the B input in this product term 0x1 PT1_BC_2 Complement the B input in this product term 0x2 PT1_BC_3 Force the B input in this product term to a logical one 0x3 PT1_AC Product term 1, A input configuration 6 2 read-write PT1_AC_0 Force the A input in this product term to a logical zero 0 PT1_AC_1 Pass the A input in this product term 0x1 PT1_AC_2 Complement the A input in this product term 0x2 PT1_AC_3 Force the A input in this product term to a logical one 0x3 PT0_DC Product term 0, D input configuration 8 2 read-write PT0_DC_0 Force the D input in this product term to a logical zero 0 PT0_DC_1 Pass the D input in this product term 0x1 PT0_DC_2 Complement the D input in this product term 0x2 PT0_DC_3 Force the D input in this product term to a logical one 0x3 PT0_CC Product term 0, C input configuration 10 2 read-write PT0_CC_0 Force the C input in this product term to a logical zero 0 PT0_CC_1 Pass the C input in this product term 0x1 PT0_CC_2 Complement the C input in this product term 0x2 PT0_CC_3 Force the C input in this product term to a logical one 0x3 PT0_BC Product term 0, B input configuration 12 2 read-write PT0_BC_0 Force the B input in this product term to a logical zero 0 PT0_BC_1 Pass the B input in this product term 0x1 PT0_BC_2 Complement the B input in this product term 0x2 PT0_BC_3 Force the B input in this product term to a logical one 0x3 PT0_AC Product term 0, A input configuration 14 2 read-write PT0_AC_0 Force the A input in this product term to a logical zero 0 PT0_AC_1 Pass the A input in this product term 0x1 PT0_AC_2 Complement the A input in this product term 0x2 PT0_AC_3 Force the A input in this product term to a logical one 0x3 BFCRT230 Boolean Function Term 2 and 3 Configuration Register for EVENTn 0x2 16 read-write 0 0xFFFF PT3_DC Product term 3, D input configuration 0 2 read-write PT3_DC_0 Force the D input in this product term to a logical zero 0 PT3_DC_1 Pass the D input in this product term 0x1 PT3_DC_2 Complement the D input in this product term 0x2 PT3_DC_3 Force the D input in this product term to a logical one 0x3 PT3_CC Product term 3, C input configuration 2 2 read-write PT3_CC_0 Force the C input in this product term to a logical zero 0 PT3_CC_1 Pass the C input in this product term 0x1 PT3_CC_2 Complement the C input in this product term 0x2 PT3_CC_3 Force the C input in this product term to a logical one 0x3 PT3_BC Product term 3, B input configuration 4 2 read-write PT3_BC_0 Force the B input in this product term to a logical zero 0 PT3_BC_1 Pass the B input in this product term 0x1 PT3_BC_2 Complement the B input in this product term 0x2 PT3_BC_3 Force the B input in this product term to a logical one 0x3 PT3_AC Product term 3, A input configuration 6 2 read-write PT3_AC_0 Force the A input in this product term to a logical zero 0 PT3_AC_1 Pass the A input in this product term 0x1 PT3_AC_2 Complement the A input in this product term 0x2 PT3_AC_3 Force the A input in this product term to a logical one 0x3 PT2_DC Product term 2, D input configuration 8 2 read-write PT2_DC_0 Force the D input in this product term to a logical zero 0 PT2_DC_1 Pass the D input in this product term 0x1 PT2_DC_2 Complement the D input in this product term 0x2 PT2_DC_3 Force the D input in this product term to a logical one 0x3 PT2_CC Product term 2, C input configuration 10 2 read-write PT2_CC_0 Force the C input in this product term to a logical zero 0 PT2_CC_1 Pass the C input in this product term 0x1 PT2_CC_2 Complement the C input in this product term 0x2 PT2_CC_3 Force the C input in this product term to a logical one 0x3 PT2_BC Product term 2, B input configuration 12 2 read-write PT2_BC_0 Force the B input in this product term to a logical zero 0 PT2_BC_1 Pass the B input in this product term 0x1 PT2_BC_2 Complement the B input in this product term 0x2 PT2_BC_3 Force the B input in this product term to a logical one 0x3 PT2_AC Product term 2, A input configuration 14 2 read-write PT2_AC_0 Force the A input in this product term to a logical zero 0 PT2_AC_1 Pass the A input in this product term 0x1 PT2_AC_2 Complement the A input in this product term 0x2 PT2_AC_3 Force the A input in this product term to a logical one 0x3 BFCRT011 Boolean Function Term 0 and 1 Configuration Register for EVENTn 0x4 16 read-write 0 0xFFFF PT1_DC Product term 1, D input configuration 0 2 read-write PT1_DC_0 Force the D input in this product term to a logical zero 0 PT1_DC_1 Pass the D input in this product term 0x1 PT1_DC_2 Complement the D input in this product term 0x2 PT1_DC_3 Force the D input in this product term to a logical one 0x3 PT1_CC Product term 1, C input configuration 2 2 read-write PT1_CC_0 Force the C input in this product term to a logical zero 0 PT1_CC_1 Pass the C input in this product term 0x1 PT1_CC_2 Complement the C input in this product term 0x2 PT1_CC_3 Force the C input in this product term to a logical one 0x3 PT1_BC Product term 1, B input configuration 4 2 read-write PT1_BC_0 Force the B input in this product term to a logical zero 0 PT1_BC_1 Pass the B input in this product term 0x1 PT1_BC_2 Complement the B input in this product term 0x2 PT1_BC_3 Force the B input in this product term to a logical one 0x3 PT1_AC Product term 1, A input configuration 6 2 read-write PT1_AC_0 Force the A input in this product term to a logical zero 0 PT1_AC_1 Pass the A input in this product term 0x1 PT1_AC_2 Complement the A input in this product term 0x2 PT1_AC_3 Force the A input in this product term to a logical one 0x3 PT0_DC Product term 0, D input configuration 8 2 read-write PT0_DC_0 Force the D input in this product term to a logical zero 0 PT0_DC_1 Pass the D input in this product term 0x1 PT0_DC_2 Complement the D input in this product term 0x2 PT0_DC_3 Force the D input in this product term to a logical one 0x3 PT0_CC Product term 0, C input configuration 10 2 read-write PT0_CC_0 Force the C input in this product term to a logical zero 0 PT0_CC_1 Pass the C input in this product term 0x1 PT0_CC_2 Complement the C input in this product term 0x2 PT0_CC_3 Force the C input in this product term to a logical one 0x3 PT0_BC Product term 0, B input configuration 12 2 read-write PT0_BC_0 Force the B input in this product term to a logical zero 0 PT0_BC_1 Pass the B input in this product term 0x1 PT0_BC_2 Complement the B input in this product term 0x2 PT0_BC_3 Force the B input in this product term to a logical one 0x3 PT0_AC Product term 0, A input configuration 14 2 read-write PT0_AC_0 Force the A input in this product term to a logical zero 0 PT0_AC_1 Pass the A input in this product term 0x1 PT0_AC_2 Complement the A input in this product term 0x2 PT0_AC_3 Force the A input in this product term to a logical one 0x3 BFCRT231 Boolean Function Term 2 and 3 Configuration Register for EVENTn 0x6 16 read-write 0 0xFFFF PT3_DC Product term 3, D input configuration 0 2 read-write PT3_DC_0 Force the D input in this product term to a logical zero 0 PT3_DC_1 Pass the D input in this product term 0x1 PT3_DC_2 Complement the D input in this product term 0x2 PT3_DC_3 Force the D input in this product term to a logical one 0x3 PT3_CC Product term 3, C input configuration 2 2 read-write PT3_CC_0 Force the C input in this product term to a logical zero 0 PT3_CC_1 Pass the C input in this product term 0x1 PT3_CC_2 Complement the C input in this product term 0x2 PT3_CC_3 Force the C input in this product term to a logical one 0x3 PT3_BC Product term 3, B input configuration 4 2 read-write PT3_BC_0 Force the B input in this product term to a logical zero 0 PT3_BC_1 Pass the B input in this product term 0x1 PT3_BC_2 Complement the B input in this product term 0x2 PT3_BC_3 Force the B input in this product term to a logical one 0x3 PT3_AC Product term 3, A input configuration 6 2 read-write PT3_AC_0 Force the A input in this product term to a logical zero 0 PT3_AC_1 Pass the A input in this product term 0x1 PT3_AC_2 Complement the A input in this product term 0x2 PT3_AC_3 Force the A input in this product term to a logical one 0x3 PT2_DC Product term 2, D input configuration 8 2 read-write PT2_DC_0 Force the D input in this product term to a logical zero 0 PT2_DC_1 Pass the D input in this product term 0x1 PT2_DC_2 Complement the D input in this product term 0x2 PT2_DC_3 Force the D input in this product term to a logical one 0x3 PT2_CC Product term 2, C input configuration 10 2 read-write PT2_CC_0 Force the C input in this product term to a logical zero 0 PT2_CC_1 Pass the C input in this product term 0x1 PT2_CC_2 Complement the C input in this product term 0x2 PT2_CC_3 Force the C input in this product term to a logical one 0x3 PT2_BC Product term 2, B input configuration 12 2 read-write PT2_BC_0 Force the B input in this product term to a logical zero 0 PT2_BC_1 Pass the B input in this product term 0x1 PT2_BC_2 Complement the B input in this product term 0x2 PT2_BC_3 Force the B input in this product term to a logical one 0x3 PT2_AC Product term 2, A input configuration 14 2 read-write PT2_AC_0 Force the A input in this product term to a logical zero 0 PT2_AC_1 Pass the A input in this product term 0x1 PT2_AC_2 Complement the A input in this product term 0x2 PT2_AC_3 Force the A input in this product term to a logical one 0x3 BFCRT012 Boolean Function Term 0 and 1 Configuration Register for EVENTn 0x8 16 read-write 0 0xFFFF PT1_DC Product term 1, D input configuration 0 2 read-write PT1_DC_0 Force the D input in this product term to a logical zero 0 PT1_DC_1 Pass the D input in this product term 0x1 PT1_DC_2 Complement the D input in this product term 0x2 PT1_DC_3 Force the D input in this product term to a logical one 0x3 PT1_CC Product term 1, C input configuration 2 2 read-write PT1_CC_0 Force the C input in this product term to a logical zero 0 PT1_CC_1 Pass the C input in this product term 0x1 PT1_CC_2 Complement the C input in this product term 0x2 PT1_CC_3 Force the C input in this product term to a logical one 0x3 PT1_BC Product term 1, B input configuration 4 2 read-write PT1_BC_0 Force the B input in this product term to a logical zero 0 PT1_BC_1 Pass the B input in this product term 0x1 PT1_BC_2 Complement the B input in this product term 0x2 PT1_BC_3 Force the B input in this product term to a logical one 0x3 PT1_AC Product term 1, A input configuration 6 2 read-write PT1_AC_0 Force the A input in this product term to a logical zero 0 PT1_AC_1 Pass the A input in this product term 0x1 PT1_AC_2 Complement the A input in this product term 0x2 PT1_AC_3 Force the A input in this product term to a logical one 0x3 PT0_DC Product term 0, D input configuration 8 2 read-write PT0_DC_0 Force the D input in this product term to a logical zero 0 PT0_DC_1 Pass the D input in this product term 0x1 PT0_DC_2 Complement the D input in this product term 0x2 PT0_DC_3 Force the D input in this product term to a logical one 0x3 PT0_CC Product term 0, C input configuration 10 2 read-write PT0_CC_0 Force the C input in this product term to a logical zero 0 PT0_CC_1 Pass the C input in this product term 0x1 PT0_CC_2 Complement the C input in this product term 0x2 PT0_CC_3 Force the C input in this product term to a logical one 0x3 PT0_BC Product term 0, B input configuration 12 2 read-write PT0_BC_0 Force the B input in this product term to a logical zero 0 PT0_BC_1 Pass the B input in this product term 0x1 PT0_BC_2 Complement the B input in this product term 0x2 PT0_BC_3 Force the B input in this product term to a logical one 0x3 PT0_AC Product term 0, A input configuration 14 2 read-write PT0_AC_0 Force the A input in this product term to a logical zero 0 PT0_AC_1 Pass the A input in this product term 0x1 PT0_AC_2 Complement the A input in this product term 0x2 PT0_AC_3 Force the A input in this product term to a logical one 0x3 BFCRT232 Boolean Function Term 2 and 3 Configuration Register for EVENTn 0xA 16 read-write 0 0xFFFF PT3_DC Product term 3, D input configuration 0 2 read-write PT3_DC_0 Force the D input in this product term to a logical zero 0 PT3_DC_1 Pass the D input in this product term 0x1 PT3_DC_2 Complement the D input in this product term 0x2 PT3_DC_3 Force the D input in this product term to a logical one 0x3 PT3_CC Product term 3, C input configuration 2 2 read-write PT3_CC_0 Force the C input in this product term to a logical zero 0 PT3_CC_1 Pass the C input in this product term 0x1 PT3_CC_2 Complement the C input in this product term 0x2 PT3_CC_3 Force the C input in this product term to a logical one 0x3 PT3_BC Product term 3, B input configuration 4 2 read-write PT3_BC_0 Force the B input in this product term to a logical zero 0 PT3_BC_1 Pass the B input in this product term 0x1 PT3_BC_2 Complement the B input in this product term 0x2 PT3_BC_3 Force the B input in this product term to a logical one 0x3 PT3_AC Product term 3, A input configuration 6 2 read-write PT3_AC_0 Force the A input in this product term to a logical zero 0 PT3_AC_1 Pass the A input in this product term 0x1 PT3_AC_2 Complement the A input in this product term 0x2 PT3_AC_3 Force the A input in this product term to a logical one 0x3 PT2_DC Product term 2, D input configuration 8 2 read-write PT2_DC_0 Force the D input in this product term to a logical zero 0 PT2_DC_1 Pass the D input in this product term 0x1 PT2_DC_2 Complement the D input in this product term 0x2 PT2_DC_3 Force the D input in this product term to a logical one 0x3 PT2_CC Product term 2, C input configuration 10 2 read-write PT2_CC_0 Force the C input in this product term to a logical zero 0 PT2_CC_1 Pass the C input in this product term 0x1 PT2_CC_2 Complement the C input in this product term 0x2 PT2_CC_3 Force the C input in this product term to a logical one 0x3 PT2_BC Product term 2, B input configuration 12 2 read-write PT2_BC_0 Force the B input in this product term to a logical zero 0 PT2_BC_1 Pass the B input in this product term 0x1 PT2_BC_2 Complement the B input in this product term 0x2 PT2_BC_3 Force the B input in this product term to a logical one 0x3 PT2_AC Product term 2, A input configuration 14 2 read-write PT2_AC_0 Force the A input in this product term to a logical zero 0 PT2_AC_1 Pass the A input in this product term 0x1 PT2_AC_2 Complement the A input in this product term 0x2 PT2_AC_3 Force the A input in this product term to a logical one 0x3 BFCRT013 Boolean Function Term 0 and 1 Configuration Register for EVENTn 0xC 16 read-write 0 0xFFFF PT1_DC Product term 1, D input configuration 0 2 read-write PT1_DC_0 Force the D input in this product term to a logical zero 0 PT1_DC_1 Pass the D input in this product term 0x1 PT1_DC_2 Complement the D input in this product term 0x2 PT1_DC_3 Force the D input in this product term to a logical one 0x3 PT1_CC Product term 1, C input configuration 2 2 read-write PT1_CC_0 Force the C input in this product term to a logical zero 0 PT1_CC_1 Pass the C input in this product term 0x1 PT1_CC_2 Complement the C input in this product term 0x2 PT1_CC_3 Force the C input in this product term to a logical one 0x3 PT1_BC Product term 1, B input configuration 4 2 read-write PT1_BC_0 Force the B input in this product term to a logical zero 0 PT1_BC_1 Pass the B input in this product term 0x1 PT1_BC_2 Complement the B input in this product term 0x2 PT1_BC_3 Force the B input in this product term to a logical one 0x3 PT1_AC Product term 1, A input configuration 6 2 read-write PT1_AC_0 Force the A input in this product term to a logical zero 0 PT1_AC_1 Pass the A input in this product term 0x1 PT1_AC_2 Complement the A input in this product term 0x2 PT1_AC_3 Force the A input in this product term to a logical one 0x3 PT0_DC Product term 0, D input configuration 8 2 read-write PT0_DC_0 Force the D input in this product term to a logical zero 0 PT0_DC_1 Pass the D input in this product term 0x1 PT0_DC_2 Complement the D input in this product term 0x2 PT0_DC_3 Force the D input in this product term to a logical one 0x3 PT0_CC Product term 0, C input configuration 10 2 read-write PT0_CC_0 Force the C input in this product term to a logical zero 0 PT0_CC_1 Pass the C input in this product term 0x1 PT0_CC_2 Complement the C input in this product term 0x2 PT0_CC_3 Force the C input in this product term to a logical one 0x3 PT0_BC Product term 0, B input configuration 12 2 read-write PT0_BC_0 Force the B input in this product term to a logical zero 0 PT0_BC_1 Pass the B input in this product term 0x1 PT0_BC_2 Complement the B input in this product term 0x2 PT0_BC_3 Force the B input in this product term to a logical one 0x3 PT0_AC Product term 0, A input configuration 14 2 read-write PT0_AC_0 Force the A input in this product term to a logical zero 0 PT0_AC_1 Pass the A input in this product term 0x1 PT0_AC_2 Complement the A input in this product term 0x2 PT0_AC_3 Force the A input in this product term to a logical one 0x3 BFCRT233 Boolean Function Term 2 and 3 Configuration Register for EVENTn 0xE 16 read-write 0 0xFFFF PT3_DC Product term 3, D input configuration 0 2 read-write PT3_DC_0 Force the D input in this product term to a logical zero 0 PT3_DC_1 Pass the D input in this product term 0x1 PT3_DC_2 Complement the D input in this product term 0x2 PT3_DC_3 Force the D input in this product term to a logical one 0x3 PT3_CC Product term 3, C input configuration 2 2 read-write PT3_CC_0 Force the C input in this product term to a logical zero 0 PT3_CC_1 Pass the C input in this product term 0x1 PT3_CC_2 Complement the C input in this product term 0x2 PT3_CC_3 Force the C input in this product term to a logical one 0x3 PT3_BC Product term 3, B input configuration 4 2 read-write PT3_BC_0 Force the B input in this product term to a logical zero 0 PT3_BC_1 Pass the B input in this product term 0x1 PT3_BC_2 Complement the B input in this product term 0x2 PT3_BC_3 Force the B input in this product term to a logical one 0x3 PT3_AC Product term 3, A input configuration 6 2 read-write PT3_AC_0 Force the A input in this product term to a logical zero 0 PT3_AC_1 Pass the A input in this product term 0x1 PT3_AC_2 Complement the A input in this product term 0x2 PT3_AC_3 Force the A input in this product term to a logical one 0x3 PT2_DC Product term 2, D input configuration 8 2 read-write PT2_DC_0 Force the D input in this product term to a logical zero 0 PT2_DC_1 Pass the D input in this product term 0x1 PT2_DC_2 Complement the D input in this product term 0x2 PT2_DC_3 Force the D input in this product term to a logical one 0x3 PT2_CC Product term 2, C input configuration 10 2 read-write PT2_CC_0 Force the C input in this product term to a logical zero 0 PT2_CC_1 Pass the C input in this product term 0x1 PT2_CC_2 Complement the C input in this product term 0x2 PT2_CC_3 Force the C input in this product term to a logical one 0x3 PT2_BC Product term 2, B input configuration 12 2 read-write PT2_BC_0 Force the B input in this product term to a logical zero 0 PT2_BC_1 Pass the B input in this product term 0x1 PT2_BC_2 Complement the B input in this product term 0x2 PT2_BC_3 Force the B input in this product term to a logical one 0x3 PT2_AC Product term 2, A input configuration 14 2 read-write PT2_AC_0 Force the A input in this product term to a logical zero 0 PT2_AC_1 Pass the A input in this product term 0x1 PT2_AC_2 Complement the A input in this product term 0x2 PT2_AC_3 Force the A input in this product term to a logical one 0x3 AOI2 AOI AOI 0x400BC000 0 0x10 registers CAN1 CAN CAN CAN 0x400C4000 0 0xC0C registers CAN1 44 CAN1_ERROR 45 MCR Module Configuration register 0 32 read-write 0x5980000F 0xFFFFFFFF MAXMB Number Of The Last Message Buffer 0 7 read-write IDAM ID Acceptance Mode 8 2 read-write one_full_ID Format A: One full ID (standard and extended) per ID filter table element. 0 two_full_ID Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. 0x1 four_partial_ID Format C: Four partial 8-bit standard IDs per ID filter table element. 0x2 all_frames_rejected Format D: All frames rejected. 0x3 FDEN CAN FD operation enable 11 1 read-write CAN_FD_disabled CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. 0 CAN_FD_enabled CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. 0x1 AEN Abort Enable 12 1 read-write abort_disabled Abort disabled. 0 abort_enabled Abort enabled. 0x1 LPRIOEN Local Priority Enable 13 1 read-write local_priority_disabled Local Priority disabled. 0 local_priority_enabled Local Priority enabled. 0x1 DMA DMA Enable 15 1 read-write id2 DMA feature for RX FIFO disabled. 0 id4 DMA feature for RX FIFO enabled. 0x1 IRMQ Individual Rx Masking And Queue Enable 16 1 read-write individual_rx_masking_disabled Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. 0 individual_rx_masking_enabled Individual Rx masking and queue feature are enabled. 0x1 SRXDIS Self Reception Disable 17 1 read-write self_reception_enabled Self-reception enabled. 0 self_reception_disabled Self-reception disabled. 0x1 DOZE Doze Mode Enable 18 1 read-write low_power_doze_disabled FlexCAN is not enabled to enter low-power mode when Doze mode is requested. 0 low_power_doze_enabled FlexCAN is enabled to enter low-power mode when Doze mode is requested. 0x1 WAKSRC Wake Up Source 19 1 read-write unfiltered_rx_input FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. 0 filtered_rx_input FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. 0x1 LPMACK Low-Power Mode Acknowledge 20 1 read-only low_power_no FlexCAN is not in a low-power mode. 0 low_power_yes FlexCAN is in a low-power mode. 0x1 WRNEN Warning Interrupt Enable 21 1 read-write TWRNINT_RWRNINT_inactive TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. 0 TWRNINT_RWRNINT_active TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. 0x1 SLFWAK Self Wake Up 22 1 read-write self_wakeup_disabled FlexCAN Self Wake Up feature is disabled. 0 self_wakeup_enabled FlexCAN Self Wake Up feature is enabled. 0x1 SUPV Supervisor Mode 23 1 read-write id2 FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. 0 id4 FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. 0x1 FRZACK Freeze Mode Acknowledge 24 1 read-only freeze_mode_no FlexCAN not in Freeze mode, prescaler running. 0 freeze_mode_yes FlexCAN in Freeze mode, prescaler stopped. 0x1 SOFTRST Soft Reset 25 1 read-write SOFTRST_no_reset_request No reset request. 0 SOFTRST_reset_registers Resets the registers affected by soft reset. 0x1 WAKMSK Wake Up Interrupt Mask 26 1 read-write wakeup_interrupt_disabled Wake Up interrupt is disabled. 0 wakeup_interrupt_enabled Wake Up interrupt is enabled. 0x1 NOTRDY FlexCAN Not Ready 27 1 read-only id1 FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode. 0 id2 FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode. 0x1 HALT Halt FlexCAN 28 1 read-write HALT_disable No Freeze mode request. 0 HALT_enable Enters Freeze mode if the FRZ bit is asserted. 0x1 RFEN Rx FIFO Enable 29 1 read-write id2 Rx FIFO not enabled. 0 id4 Rx FIFO enabled. 0x1 FRZ Freeze Enable 30 1 read-write freeze_mode_disabled Not enabled to enter Freeze mode. 0 freeze_mode_enabled Enabled to enter Freeze mode. 0x1 MDIS Module Disable 31 1 read-write flexcan_enabled Enable the FlexCAN module. 0 flexcan_disabled Disable the FlexCAN module. 0x1 CTRL1 Control 1 register 0x4 32 read-write 0 0xFFFFFFFF PROPSEG Propagation Segment 0 3 read-write LOM Listen-Only Mode 3 1 read-write listen_only_mode_disabled Listen-Only mode is deactivated. 0 listen_only_mode_enabled FlexCAN module operates in Listen-Only mode. 0x1 LBUF Lowest Buffer Transmitted First 4 1 read-write highest_buffer_first Buffer with highest priority is transmitted first. 0 lowest_buffer_first Lowest number buffer is transmitted first. 0x1 TSYN Timer Sync 5 1 read-write timer_sync_disabled Timer sync feature disabled 0 timer_sync_enabled Timer sync feature enabled 0x1 BOFFREC Bus Off Recovery 6 1 read-write auto_recover_enabled Automatic recovering from Bus Off state enabled. 0 auto_recover_disabled Automatic recovering from Bus Off state disabled. 0x1 SMP CAN Bit Sampling 7 1 read-write one_sample Just one sample is used to determine the bit value. 0 three_sample Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples; a majority rule is used. 0x1 RWRNMSK Rx Warning Interrupt Mask 10 1 read-write rx_warning_int_disabled Rx Warning interrupt disabled. 0 rx_warning_int_enabled Rx Warning interrupt enabled. 0x1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write tx_warning_int_disabled Tx Warning interrupt disabled. 0 tx_warning_int_enabled Tx Warning interrupt enabled. 0x1 LPB Loop Back Mode 12 1 read-write loopback_disabled Loop Back disabled. 0 loopback_enabled Loop Back enabled. 0x1 CLKSRC CAN Engine Clock Source 13 1 read-write oscillator_clock The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. 0 peripheral_clock The CAN engine clock source is the peripheral clock. 0x1 ERRMSK Error Interrupt Mask 14 1 read-write error_int_disabled Error interrupt disabled. 0 error_int_enabled Error interrupt enabled. 0x1 BOFFMSK Bus Off Interrupt Mask 15 1 read-write bus_off_int_disabled Bus Off interrupt disabled. 0 bus_off_int_enabled Bus Off interrupt enabled. 0x1 PSEG2 Phase Segment 2 16 3 read-write PSEG1 Phase Segment 1 19 3 read-write RJW Resync Jump Width 22 2 read-write PRESDIV Prescaler Division Factor 24 8 read-write TIMER Free Running Timer 0x8 32 read-write 0 0xFFFFFFFF TIMER Timer Value 0 16 read-write RXMGMASK Rx Mailboxes Global Mask register 0x10 32 read-write 0 0 MG Rx Mailboxes Global Mask Bits 0 32 read-write RX14MASK Rx 14 Mask register 0x14 32 read-write 0 0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write RX15MASK Rx 15 Mask register 0x18 32 read-write 0 0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write ECR Error Counter 0x1C 32 read-write 0 0xFFFFFFFF TXERRCNT Transmit Error Counter 0 8 read-write RXERRCNT Receive Error Counter 8 8 read-write TXERRCNT_FAST Transmit Error Counter for fast bits 16 8 read-write RXERRCNT_FAST Receive Error Counter for fast bits 24 8 read-write ESR1 Error and Status 1 register 0x20 32 read-write 0 0xFFFFFFFF WAKINT Wake-Up Interrupt 0 1 read-write oneToClear DISABLE No such occurrence. 0 ENABLE Indicates a recessive to dominant transition was received on the CAN bus. 0x1 ERRINT Error Interrupt 1 1 read-write oneToClear DISABLE No such occurrence. 0 ENABLE Indicates setting of any error bit in the Error and Status register. 0x1 BOFFINT Bus Off Interrupt 2 1 read-write oneToClear DISABLE No such occurrence. 0 ENABLE FlexCAN module entered Bus Off state. 0x1 RX FlexCAN In Reception 3 1 read-only DISABLE FlexCAN is not receiving a message. 0 ENABLE FlexCAN is receiving a message. 0x1 FLTCONF Fault Confinement State 4 2 read-only error_active Error Active 0 error_passive Error Passive 0x1 bus_off Bus Off #1x TX FlexCAN In Transmission 6 1 read-only transmit_message_no FlexCAN is not transmitting a message. 0 transmit_message_yes FlexCAN is transmitting a message. 0x1 IDLE IDLE 7 1 read-only can_bus_not_idle No such occurrence. 0 can_bus_idle CAN bus is now IDLE. 0x1 RXWRN Rx Error Warning 8 1 read-only RXERRCNT_LT_96 No such occurrence. 0 RXERRCNT_GTE_96 RXERRCNT is greater than or equal to 96. 0x1 TXWRN TX Error Warning 9 1 read-only TXERRCNT_LT_96 No such occurrence. 0 TXERRCNT_GTE_96 TXERRCNT is greater than or equal to 96. 0x1 STFERR Stuffing Error 10 1 read-only stuffing_error_no No such occurrence. 0 stuffing_error_yes A stuffing error occurred since last read of this register. 0x1 FRMERR Form Error 11 1 read-only form_error_no No such occurrence. 0 form_error_yes A Form Error occurred since last read of this register. 0x1 CRCERR Cyclic Redundancy Check Error 12 1 read-only CRC_error_no No such occurrence. 0 CRC_error_yes A CRC error occurred since last read of this register. 0x1 ACKERR Acknowledge Error 13 1 read-only ACK_error_no No such occurrence. 0 ACK_error_yes An ACK error occurred since last read of this register. 0x1 BIT0ERR Bit0 Error 14 1 read-only bit0_error_no No such occurrence. 0 bit0_error_yes At least one bit sent as dominant is received as recessive. 0x1 BIT1ERR Bit1 Error 15 1 read-only bit1_error_no No such occurrence. 0 bit1_error_yes At least one bit sent as recessive is received as dominant. 0x1 RWRNINT Rx Warning Interrupt Flag 16 1 read-write oneToClear Rx_warning_int_no No such occurrence. 0 Rx_warning_int_yes The Rx error counter transitioned from less than 96 to greater than or equal to 96. 0x1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write oneToClear Tx_warning_int_no No such occurrence. 0 Tx_warning_int_yes The Tx error counter transitioned from less than 96 to greater than or equal to 96. 0x1 SYNCH CAN Synchronization Status 18 1 read-only CAN_bus_sync_no FlexCAN is not synchronized to the CAN bus. 0 CAN_bus_sync_yes FlexCAN is synchronized to the CAN bus. 0x1 BOFFDONEINT Bus Off Done Interrupt 19 1 read-write oneToClear bus_off_not_done No such occurrence. 0 bus_off_done FlexCAN module has completed Bus Off process. 0x1 ERRINT_FAST Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set 20 1 read-write oneToClear errors_data_phase_no No such occurrence. 0 errors_data_phase_yes Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set. 0x1 ERROVR Error Overrun 21 1 read-write oneToClear overrun_not_occurred Overrun has not occurred. 0 overrun_occurred Overrun has occurred. 0x1 STFERR_FAST Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set 26 1 read-only stuffing_error_no No such occurrence. 0 stuffing_error_yes A stuffing error occurred since last read of this register. 0x1 FRMERR_FAST Form Error in the Data Phase of CAN FD frames with the BRS bit set 27 1 read-only form_error_no No such occurrence. 0 form_error_yes A form error occurred since last read of this register. 0x1 CRCERR_FAST Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set 28 1 read-only CRC_error_no No such occurrence. 0 CRC_error_yes A CRC error occurred since last read of this register. 0x1 BIT0ERR_FAST Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set 30 1 read-only bit0_error_no No such occurrence. 0 bit0_error_yes At least one bit sent as dominant is received as recessive. 0x1 BIT1ERR_FAST Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set 31 1 read-only bit1_error_no No such occurrence. 0 bit1_error_yes At least one bit sent as recessive is received as dominant. 0x1 IMASK2 Interrupt Masks 2 register 0x24 32 read-write 0 0xFFFFFFFF BUF63TO32M Buffer MBi Mask 0 32 read-write IMASK1 Interrupt Masks 1 register 0x28 32 read-write 0 0xFFFFFFFF BUF31TO0M Buffer MBi Mask 0 32 read-write IFLAG2 Interrupt Flags 2 register 0x2C 32 read-write 0 0xFFFFFFFF oneToClear BUF63TO32I Buffer MBi Interrupt 0 32 read-write oneToClear IFLAG1 Interrupt Flags 1 register 0x30 32 read-write 0 0xFFFFFFFF oneToClear BUF0I Buffer MB0 Interrupt Or Clear FIFO bit 0 1 read-write oneToClear buffer_Tx_Rx_not_complete The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0 buffer_Tx_Rx_complete The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. 0x1 BUF4TO1I Buffer MBi Interrupt Or Reserved 1 4 read-write oneToClear BUF5I Buffer MB5 Interrupt Or Frames available in Rx FIFO 5 1 read-write oneToClear id2 No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0 id4 MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. 0x1 BUF6I Buffer MB6 Interrupt Or Rx FIFO Warning 6 1 read-write oneToClear id2 No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 0 id4 MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 0x1 BUF7I Buffer MB7 Interrupt Or Rx FIFO Overflow 7 1 read-write oneToClear id2 No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 0 id4 MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 0x1 BUF31TO8I Buffer MBi Interrupt 8 24 read-write oneToClear CTRL2 Control 2 register 0x34 32 read-write 0x800000 0xFFFFFFFF EDFLTDIS Edge Filter Disable 11 1 read-write ENABLE Edge filter is enabled 0 DISABLE Edge filter is disabled 0x1 ISOCANFDEN ISO CAN FD Enable 12 1 read-write non_ISO FlexCAN operates using the non-ISO CAN FD protocol. 0 ISO FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). 0x1 PREXCEN Protocol Exception Enable 14 1 read-write DISABLE Protocol exception is disabled. 0 ENABLE Protocol exception is enabled. 0x1 TIMER_SRC Timer Source 15 1 read-write CAN_bit_clock The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. 0 external_clock The free running timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device-specific section for details about the external time tick. 0x1 EACEN Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 16 1 read-write RTR_compare_no Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. 0 RTR_compare_yes Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. 0x1 RRS Remote Request Storing 17 1 read-write remote_response_frame_not_generated Remote response frame is generated. 0 remote_response_frame_generated Remote request frame is stored. 0x1 MRP Mailboxes Reception Priority 18 1 read-write id2 Matching starts from Rx FIFO and continues on mailboxes. 0 id4 Matching starts from mailboxes and continues on Rx FIFO. 0x1 TASD Tx Arbitration Start Delay 19 5 read-write RFFN Number Of Rx FIFO Filters 24 4 read-write WRMFRZ Write-Access To Memory In Freeze Mode 28 1 read-write DISABLE Maintain the write access restrictions. 0 ENABLE Enable unrestricted write access to FlexCAN memory. 0x1 ECRWRE Error-correction Configuration Register Write Enable 29 1 read-write DISABLE Disable update. 0 ENABLE Enable update. 0x1 BOFFDONEMSK Bus Off Done Interrupt Mask 30 1 read-write DISABLE Bus off done interrupt disabled. 0 ENABLE Bus off done interrupt enabled. 0x1 ERRMSK_FAST Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames 31 1 read-write DISABLE ERRINT_FAST error interrupt disabled. 0 ENABLE ERRINT_FAST error interrupt enabled. 0x1 ESR2 Error and Status 2 register 0x38 32 read-only 0 0xFFFFFFFF IMB Inactive Mailbox 13 1 read-only inactive_mailbox_no If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox. 0 inactive_mailbox_yes If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one. 0x1 VPS Valid Priority Status 14 1 read-only invalid Contents of IMB and LPTM are invalid. 0 valid Contents of IMB and LPTM are valid. 0x1 LPTM Lowest Priority Tx Mailbox 16 7 read-only CRCR CRC register 0x44 32 read-only 0 0xFFFFFFFF TXCRC Transmitted CRC value 0 15 read-only MBCRC CRC Mailbox 16 7 read-only RXFGMASK Rx FIFO Global Mask register 0x48 32 read-write 0 0 FGM Rx FIFO Global Mask Bits 0 32 read-write RXFIR Rx FIFO Information register 0x4C 32 read-only 0 0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only CBT CAN Bit Timing register 0x50 32 read-write 0 0xFFFFFFFF EPSEG2 Extended Phase Segment 2 0 5 read-write EPSEG1 Extended Phase Segment 1 5 5 read-write EPROPSEG Extended Propagation Segment 10 6 read-write ERJW Extended Resync Jump Width 16 5 read-write EPRESDIV Extended Prescaler Division Factor 21 10 read-write BTF Bit Timing Format Enable 31 1 read-write DISABLE Extended bit time definitions disabled. 0 ENABLE Extended bit time definitions enabled. 0x1 CS0 Message Buffer 0 CS Register MB_SIZE 0x80 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_16B_CS_L Message Buffer 0 CS Register MB_SIZE 0x80 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_32B_CS_L Message Buffer 0 CS Register MB_SIZE 0x80 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_64B_CS_L Message Buffer 0 CS Register MB_SIZE 0x80 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_8B_CS Message Buffer 0 CS Register MB_SIZE 0x80 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID0 Message Buffer 0 ID Register MB_SIZE 0x84 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_16B_ID_L Message Buffer 0 ID Register MB_SIZE 0x84 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_32B_ID_L Message Buffer 0 ID Register MB_SIZE 0x84 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_64B_ID_L Message Buffer 0 ID Register MB_SIZE 0x84 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_8B_ID Message Buffer 0 ID Register MB_SIZE 0x84 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_16B_WORD0_L Message Buffer 0 WORD_16B Register MB_SIZE 0x88 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_32B_WORD0_L Message Buffer 0 WORD_32B Register MB_SIZE 0x88 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD0_L Message Buffer 0 WORD_64B Register MB_SIZE 0x88 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_8B_WORD0 Message Buffer 0 WORD_8B Register MB_SIZE 0x88 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD00 Message Buffer 0 WORD0 Register MB_SIZE 0x88 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_16B_WORD1_L Message Buffer 0 WORD_16B Register MB_SIZE 0x8C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_32B_WORD1_L Message Buffer 0 WORD_32B Register MB_SIZE 0x8C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD1_L Message Buffer 0 WORD_64B Register MB_SIZE 0x8C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_8B_WORD1 Message Buffer 0 WORD_8B Register MB_SIZE 0x8C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD10 Message Buffer 0 WORD1 Register MB_SIZE 0x8C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS1 Message Buffer 1 CS Register MB_SIZE 0x90 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_16B_WORD2_L Message Buffer 0 WORD_16B Register MB_SIZE 0x90 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_32B_WORD2_L Message Buffer 0 WORD_32B Register MB_SIZE 0x90 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD2_L Message Buffer 0 WORD_64B Register MB_SIZE 0x90 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_8B_CS Message Buffer 1 CS Register MB_SIZE 0x90 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID1 Message Buffer 1 ID Register MB_SIZE 0x94 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_16B_WORD3_L Message Buffer 0 WORD_16B Register MB_SIZE 0x94 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_32B_WORD3_L Message Buffer 0 WORD_32B Register MB_SIZE 0x94 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD3_L Message Buffer 0 WORD_64B Register MB_SIZE 0x94 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_8B_ID Message Buffer 1 ID Register MB_SIZE 0x94 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_32B_WORD4_L Message Buffer 0 WORD_32B Register MB_SIZE 0x98 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD4_L Message Buffer 0 WORD_64B Register MB_SIZE 0x98 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_CS_L Message Buffer 1 CS Register MB_SIZE 0x98 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB1_8B_WORD0 Message Buffer 1 WORD_8B Register MB_SIZE 0x98 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD01 Message Buffer 1 WORD0 Register MB_SIZE 0x98 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_32B_WORD5_L Message Buffer 0 WORD_32B Register MB_SIZE 0x9C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD5_L Message Buffer 0 WORD_64B Register MB_SIZE 0x9C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_ID_L Message Buffer 1 ID Register MB_SIZE 0x9C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_8B_WORD1 Message Buffer 1 WORD_8B Register MB_SIZE 0x9C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD11 Message Buffer 1 WORD1 Register MB_SIZE 0x9C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS2 Message Buffer 2 CS Register MB_SIZE 0xA0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_32B_WORD6_L Message Buffer 0 WORD_32B Register MB_SIZE 0xA0 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD6_L Message Buffer 0 WORD_64B Register MB_SIZE 0xA0 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_WORD0_L Message Buffer 1 WORD_16B Register MB_SIZE 0xA0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_8B_CS Message Buffer 2 CS Register MB_SIZE 0xA0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID2 Message Buffer 2 ID Register MB_SIZE 0xA4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_32B_WORD7_L Message Buffer 0 WORD_32B Register MB_SIZE 0xA4 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD7_L Message Buffer 0 WORD_64B Register MB_SIZE 0xA4 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_WORD1_L Message Buffer 1 WORD_16B Register MB_SIZE 0xA4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_8B_ID Message Buffer 2 ID Register MB_SIZE 0xA4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_64B_WORD8_L Message Buffer 0 WORD_64B Register MB_SIZE 0xA8 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_WORD2_L Message Buffer 1 WORD_16B Register MB_SIZE 0xA8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_CS_L Message Buffer 1 CS Register MB_SIZE 0xA8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB2_8B_WORD0 Message Buffer 2 WORD_8B Register MB_SIZE 0xA8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD02 Message Buffer 2 WORD0 Register MB_SIZE 0xA8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD9_L Message Buffer 0 WORD_64B Register MB_SIZE 0xAC 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_WORD3_L Message Buffer 1 WORD_16B Register MB_SIZE 0xAC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_ID_L Message Buffer 1 ID Register MB_SIZE 0xAC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_8B_WORD1 Message Buffer 2 WORD_8B Register MB_SIZE 0xAC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD12 Message Buffer 2 WORD1 Register MB_SIZE 0xAC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS3 Message Buffer 3 CS Register MB_SIZE 0xB0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_64B_WORD10_L Message Buffer 0 WORD_64B Register MB_SIZE 0xB0 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD0_L Message Buffer 1 WORD_32B Register MB_SIZE 0xB0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_CS_L Message Buffer 2 CS Register MB_SIZE 0xB0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_8B_CS Message Buffer 3 CS Register MB_SIZE 0xB0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID3 Message Buffer 3 ID Register MB_SIZE 0xB4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_64B_WORD11_L Message Buffer 0 WORD_64B Register MB_SIZE 0xB4 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD1_L Message Buffer 1 WORD_32B Register MB_SIZE 0xB4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_ID_L Message Buffer 2 ID Register MB_SIZE 0xB4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_8B_ID Message Buffer 3 ID Register MB_SIZE 0xB4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_64B_WORD12_L Message Buffer 0 WORD_64B Register MB_SIZE 0xB8 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD2_L Message Buffer 1 WORD_32B Register MB_SIZE 0xB8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_WORD0_L Message Buffer 2 WORD_16B Register MB_SIZE 0xB8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_8B_WORD0 Message Buffer 3 WORD_8B Register MB_SIZE 0xB8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD03 Message Buffer 3 WORD0 Register MB_SIZE 0xB8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD13_L Message Buffer 0 WORD_64B Register MB_SIZE 0xBC 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD3_L Message Buffer 1 WORD_32B Register MB_SIZE 0xBC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_WORD1_L Message Buffer 2 WORD_16B Register MB_SIZE 0xBC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_8B_WORD1 Message Buffer 3 WORD_8B Register MB_SIZE 0xBC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD13 Message Buffer 3 WORD1 Register MB_SIZE 0xBC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS4 Message Buffer 4 CS Register MB_SIZE 0xC0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_64B_WORD14_L Message Buffer 0 WORD_64B Register MB_SIZE 0xC0 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD4_L Message Buffer 1 WORD_32B Register MB_SIZE 0xC0 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_WORD2_L Message Buffer 2 WORD_16B Register MB_SIZE 0xC0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_8B_CS Message Buffer 4 CS Register MB_SIZE 0xC0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID4 Message Buffer 4 ID Register MB_SIZE 0xC4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_64B_WORD15_L Message Buffer 0 WORD_64B Register MB_SIZE 0xC4 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD5_L Message Buffer 1 WORD_32B Register MB_SIZE 0xC4 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_WORD3_L Message Buffer 2 WORD_16B Register MB_SIZE 0xC4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_8B_ID Message Buffer 4 ID Register MB_SIZE 0xC4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_32B_WORD6_L Message Buffer 1 WORD_32B Register MB_SIZE 0xC8 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_CS_L Message Buffer 1 CS Register MB_SIZE 0xC8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_16B_CS_L Message Buffer 3 CS Register MB_SIZE 0xC8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_8B_WORD0 Message Buffer 4 WORD_8B Register MB_SIZE 0xC8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD04 Message Buffer 4 WORD0 Register MB_SIZE 0xC8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD7_L Message Buffer 1 WORD_32B Register MB_SIZE 0xCC 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_ID_L Message Buffer 1 ID Register MB_SIZE 0xCC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_16B_ID_L Message Buffer 3 ID Register MB_SIZE 0xCC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_8B_WORD1 Message Buffer 4 WORD_8B Register MB_SIZE 0xCC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD14 Message Buffer 4 WORD1 Register MB_SIZE 0xCC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS5 Message Buffer 5 CS Register MB_SIZE 0xD0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB1_64B_WORD0_L Message Buffer 1 WORD_64B Register MB_SIZE 0xD0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_CS_L Message Buffer 2 CS Register MB_SIZE 0xD0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_16B_WORD0_L Message Buffer 3 WORD_16B Register MB_SIZE 0xD0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_8B_CS Message Buffer 5 CS Register MB_SIZE 0xD0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID5 Message Buffer 5 ID Register MB_SIZE 0xD4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD1_L Message Buffer 1 WORD_64B Register MB_SIZE 0xD4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_ID_L Message Buffer 2 ID Register MB_SIZE 0xD4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_16B_WORD1_L Message Buffer 3 WORD_16B Register MB_SIZE 0xD4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_8B_ID Message Buffer 5 ID Register MB_SIZE 0xD4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD2_L Message Buffer 1 WORD_64B Register MB_SIZE 0xD8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD0_L Message Buffer 2 WORD_32B Register MB_SIZE 0xD8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_16B_WORD2_L Message Buffer 3 WORD_16B Register MB_SIZE 0xD8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_8B_WORD0 Message Buffer 5 WORD_8B Register MB_SIZE 0xD8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD05 Message Buffer 5 WORD0 Register MB_SIZE 0xD8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_WORD3_L Message Buffer 1 WORD_64B Register MB_SIZE 0xDC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD1_L Message Buffer 2 WORD_32B Register MB_SIZE 0xDC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_16B_WORD3_L Message Buffer 3 WORD_16B Register MB_SIZE 0xDC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_8B_WORD1 Message Buffer 5 WORD_8B Register MB_SIZE 0xDC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD15 Message Buffer 5 WORD1 Register MB_SIZE 0xDC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS6 Message Buffer 6 CS Register MB_SIZE 0xE0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB1_64B_WORD4_L Message Buffer 1 WORD_64B Register MB_SIZE 0xE0 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD2_L Message Buffer 2 WORD_32B Register MB_SIZE 0xE0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_16B_CS_L Message Buffer 4 CS Register MB_SIZE 0xE0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_8B_CS Message Buffer 6 CS Register MB_SIZE 0xE0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID6 Message Buffer 6 ID Register MB_SIZE 0xE4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD5_L Message Buffer 1 WORD_64B Register MB_SIZE 0xE4 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD3_L Message Buffer 2 WORD_32B Register MB_SIZE 0xE4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_16B_ID_L Message Buffer 4 ID Register MB_SIZE 0xE4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_8B_ID Message Buffer 6 ID Register MB_SIZE 0xE4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD6_L Message Buffer 1 WORD_64B Register MB_SIZE 0xE8 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD4_L Message Buffer 2 WORD_32B Register MB_SIZE 0xE8 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_16B_WORD0_L Message Buffer 4 WORD_16B Register MB_SIZE 0xE8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_8B_WORD0 Message Buffer 6 WORD_8B Register MB_SIZE 0xE8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD06 Message Buffer 6 WORD0 Register MB_SIZE 0xE8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_WORD7_L Message Buffer 1 WORD_64B Register MB_SIZE 0xEC 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD5_L Message Buffer 2 WORD_32B Register MB_SIZE 0xEC 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_16B_WORD1_L Message Buffer 4 WORD_16B Register MB_SIZE 0xEC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_8B_WORD1 Message Buffer 6 WORD_8B Register MB_SIZE 0xEC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD16 Message Buffer 6 WORD1 Register MB_SIZE 0xEC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS7 Message Buffer 7 CS Register MB_SIZE 0xF0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB1_64B_WORD8_L Message Buffer 1 WORD_64B Register MB_SIZE 0xF0 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD6_L Message Buffer 2 WORD_32B Register MB_SIZE 0xF0 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_16B_WORD2_L Message Buffer 4 WORD_16B Register MB_SIZE 0xF0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_8B_CS Message Buffer 7 CS Register MB_SIZE 0xF0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID7 Message Buffer 7 ID Register MB_SIZE 0xF4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD9_L Message Buffer 1 WORD_64B Register MB_SIZE 0xF4 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD7_L Message Buffer 2 WORD_32B Register MB_SIZE 0xF4 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_16B_WORD3_L Message Buffer 4 WORD_16B Register MB_SIZE 0xF4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_8B_ID Message Buffer 7 ID Register MB_SIZE 0xF4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD10_L Message Buffer 1 WORD_64B Register MB_SIZE 0xF8 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_CS_L Message Buffer 3 CS Register MB_SIZE 0xF8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_16B_CS_L Message Buffer 5 CS Register MB_SIZE 0xF8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB7_8B_WORD0 Message Buffer 7 WORD_8B Register MB_SIZE 0xF8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD07 Message Buffer 7 WORD0 Register MB_SIZE 0xF8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_WORD11_L Message Buffer 1 WORD_64B Register MB_SIZE 0xFC 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_ID_L Message Buffer 3 ID Register MB_SIZE 0xFC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_16B_ID_L Message Buffer 5 ID Register MB_SIZE 0xFC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB7_8B_WORD1 Message Buffer 7 WORD_8B Register MB_SIZE 0xFC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD17 Message Buffer 7 WORD1 Register MB_SIZE 0xFC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS8 Message Buffer 8 CS Register MB_SIZE 0x100 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB1_64B_WORD12_L Message Buffer 1 WORD_64B Register MB_SIZE 0x100 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD0_L Message Buffer 3 WORD_32B Register MB_SIZE 0x100 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_16B_WORD0_L Message Buffer 5 WORD_16B Register MB_SIZE 0x100 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_8B_CS Message Buffer 8 CS Register MB_SIZE 0x100 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID8 Message Buffer 8 ID Register MB_SIZE 0x104 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD13_L Message Buffer 1 WORD_64B Register MB_SIZE 0x104 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD1_L Message Buffer 3 WORD_32B Register MB_SIZE 0x104 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_16B_WORD1_L Message Buffer 5 WORD_16B Register MB_SIZE 0x104 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_8B_ID Message Buffer 8 ID Register MB_SIZE 0x104 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD14_L Message Buffer 1 WORD_64B Register MB_SIZE 0x108 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD2_L Message Buffer 3 WORD_32B Register MB_SIZE 0x108 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_16B_WORD2_L Message Buffer 5 WORD_16B Register MB_SIZE 0x108 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_8B_WORD0 Message Buffer 8 WORD_8B Register MB_SIZE 0x108 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD08 Message Buffer 8 WORD0 Register MB_SIZE 0x108 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_WORD15_L Message Buffer 1 WORD_64B Register MB_SIZE 0x10C 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD3_L Message Buffer 3 WORD_32B Register MB_SIZE 0x10C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_16B_WORD3_L Message Buffer 5 WORD_16B Register MB_SIZE 0x10C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_8B_WORD1 Message Buffer 8 WORD_8B Register MB_SIZE 0x10C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD18 Message Buffer 8 WORD1 Register MB_SIZE 0x10C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS9 Message Buffer 9 CS Register MB_SIZE 0x110 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB2_64B_CS_L Message Buffer 2 CS Register MB_SIZE 0x110 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_32B_WORD4_L Message Buffer 3 WORD_32B Register MB_SIZE 0x110 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_16B_CS_L Message Buffer 6 CS Register MB_SIZE 0x110 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB9_8B_CS Message Buffer 9 CS Register MB_SIZE 0x110 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID9 Message Buffer 9 ID Register MB_SIZE 0x114 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_ID_L Message Buffer 2 ID Register MB_SIZE 0x114 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_32B_WORD5_L Message Buffer 3 WORD_32B Register MB_SIZE 0x114 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_16B_ID_L Message Buffer 6 ID Register MB_SIZE 0x114 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB9_8B_ID Message Buffer 9 ID Register MB_SIZE 0x114 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_WORD0_L Message Buffer 2 WORD_64B Register MB_SIZE 0x118 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD6_L Message Buffer 3 WORD_32B Register MB_SIZE 0x118 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_16B_WORD0_L Message Buffer 6 WORD_16B Register MB_SIZE 0x118 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_8B_WORD0 Message Buffer 9 WORD_8B Register MB_SIZE 0x118 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD09 Message Buffer 9 WORD0 Register MB_SIZE 0x118 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD1_L Message Buffer 2 WORD_64B Register MB_SIZE 0x11C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD7_L Message Buffer 3 WORD_32B Register MB_SIZE 0x11C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_16B_WORD1_L Message Buffer 6 WORD_16B Register MB_SIZE 0x11C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_8B_WORD1 Message Buffer 9 WORD_8B Register MB_SIZE 0x11C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD19 Message Buffer 9 WORD1 Register MB_SIZE 0x11C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS10 Message Buffer 10 CS Register MB_SIZE 0x120 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB10_8B_CS Message Buffer 10 CS Register MB_SIZE 0x120 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB2_64B_WORD2_L Message Buffer 2 WORD_64B Register MB_SIZE 0x120 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_CS_L Message Buffer 4 CS Register MB_SIZE 0x120 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_16B_WORD2_L Message Buffer 6 WORD_16B Register MB_SIZE 0x120 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write ID10 Message Buffer 10 ID Register MB_SIZE 0x124 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_8B_ID Message Buffer 10 ID Register MB_SIZE 0x124 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_WORD3_L Message Buffer 2 WORD_64B Register MB_SIZE 0x124 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_ID_L Message Buffer 4 ID Register MB_SIZE 0x124 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_16B_WORD3_L Message Buffer 6 WORD_16B Register MB_SIZE 0x124 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_8B_WORD0 Message Buffer 10 WORD_8B Register MB_SIZE 0x128 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD4_L Message Buffer 2 WORD_64B Register MB_SIZE 0x128 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD0_L Message Buffer 4 WORD_32B Register MB_SIZE 0x128 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_CS_L Message Buffer 7 CS Register MB_SIZE 0x128 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write WORD010 Message Buffer 10 WORD0 Register MB_SIZE 0x128 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_8B_WORD1 Message Buffer 10 WORD_8B Register MB_SIZE 0x12C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD5_L Message Buffer 2 WORD_64B Register MB_SIZE 0x12C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD1_L Message Buffer 4 WORD_32B Register MB_SIZE 0x12C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_ID_L Message Buffer 7 ID Register MB_SIZE 0x12C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD110 Message Buffer 10 WORD1 Register MB_SIZE 0x12C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS11 Message Buffer 11 CS Register MB_SIZE 0x130 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB11_8B_CS Message Buffer 11 CS Register MB_SIZE 0x130 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB2_64B_WORD6_L Message Buffer 2 WORD_64B Register MB_SIZE 0x130 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD2_L Message Buffer 4 WORD_32B Register MB_SIZE 0x130 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_WORD0_L Message Buffer 7 WORD_16B Register MB_SIZE 0x130 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write ID11 Message Buffer 11 ID Register MB_SIZE 0x134 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB11_8B_ID Message Buffer 11 ID Register MB_SIZE 0x134 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_WORD7_L Message Buffer 2 WORD_64B Register MB_SIZE 0x134 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD3_L Message Buffer 4 WORD_32B Register MB_SIZE 0x134 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_WORD1_L Message Buffer 7 WORD_16B Register MB_SIZE 0x134 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_8B_WORD0 Message Buffer 11 WORD_8B Register MB_SIZE 0x138 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD8_L Message Buffer 2 WORD_64B Register MB_SIZE 0x138 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD4_L Message Buffer 4 WORD_32B Register MB_SIZE 0x138 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_WORD2_L Message Buffer 7 WORD_16B Register MB_SIZE 0x138 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD011 Message Buffer 11 WORD0 Register MB_SIZE 0x138 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_8B_WORD1 Message Buffer 11 WORD_8B Register MB_SIZE 0x13C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD9_L Message Buffer 2 WORD_64B Register MB_SIZE 0x13C 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD5_L Message Buffer 4 WORD_32B Register MB_SIZE 0x13C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_WORD3_L Message Buffer 7 WORD_16B Register MB_SIZE 0x13C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD111 Message Buffer 11 WORD1 Register MB_SIZE 0x13C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS12 Message Buffer 12 CS Register MB_SIZE 0x140 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB12_8B_CS Message Buffer 12 CS Register MB_SIZE 0x140 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB2_64B_WORD10_L Message Buffer 2 WORD_64B Register MB_SIZE 0x140 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD6_L Message Buffer 4 WORD_32B Register MB_SIZE 0x140 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_16B_CS_L Message Buffer 8 CS Register MB_SIZE 0x140 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID12 Message Buffer 12 ID Register MB_SIZE 0x144 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB12_8B_ID Message Buffer 12 ID Register MB_SIZE 0x144 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_WORD11_L Message Buffer 2 WORD_64B Register MB_SIZE 0x144 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD7_L Message Buffer 4 WORD_32B Register MB_SIZE 0x144 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_16B_ID_L Message Buffer 8 ID Register MB_SIZE 0x144 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB12_8B_WORD0 Message Buffer 12 WORD_8B Register MB_SIZE 0x148 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD12_L Message Buffer 2 WORD_64B Register MB_SIZE 0x148 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_CS_L Message Buffer 5 CS Register MB_SIZE 0x148 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB8_16B_WORD0_L Message Buffer 8 WORD_16B Register MB_SIZE 0x148 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD012 Message Buffer 12 WORD0 Register MB_SIZE 0x148 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB12_8B_WORD1 Message Buffer 12 WORD_8B Register MB_SIZE 0x14C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD13_L Message Buffer 2 WORD_64B Register MB_SIZE 0x14C 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_ID_L Message Buffer 5 ID Register MB_SIZE 0x14C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB8_16B_WORD1_L Message Buffer 8 WORD_16B Register MB_SIZE 0x14C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD112 Message Buffer 12 WORD1 Register MB_SIZE 0x14C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS13 Message Buffer 13 CS Register MB_SIZE 0x150 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB13_8B_CS Message Buffer 13 CS Register MB_SIZE 0x150 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB2_64B_WORD14_L Message Buffer 2 WORD_64B Register MB_SIZE 0x150 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_WORD0_L Message Buffer 5 WORD_32B Register MB_SIZE 0x150 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_16B_WORD2_L Message Buffer 8 WORD_16B Register MB_SIZE 0x150 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write ID13 Message Buffer 13 ID Register MB_SIZE 0x154 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB13_8B_ID Message Buffer 13 ID Register MB_SIZE 0x154 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_WORD15_L Message Buffer 2 WORD_64B Register MB_SIZE 0x154 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_WORD1_L Message Buffer 5 WORD_32B Register MB_SIZE 0x154 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_16B_WORD3_L Message Buffer 8 WORD_16B Register MB_SIZE 0x154 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB13_8B_WORD0 Message Buffer 13 WORD_8B Register MB_SIZE 0x158 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_CS_L Message Buffer 3 CS Register MB_SIZE 0x158 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_32B_WORD2_L Message Buffer 5 WORD_32B Register MB_SIZE 0x158 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_CS_L Message Buffer 9 CS Register MB_SIZE 0x158 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write WORD013 Message Buffer 13 WORD0 Register MB_SIZE 0x158 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB13_8B_WORD1 Message Buffer 13 WORD_8B Register MB_SIZE 0x15C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_ID_L Message Buffer 3 ID Register MB_SIZE 0x15C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_32B_WORD3_L Message Buffer 5 WORD_32B Register MB_SIZE 0x15C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_ID_L Message Buffer 9 ID Register MB_SIZE 0x15C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD113 Message Buffer 13 WORD1 Register MB_SIZE 0x15C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS14 Message Buffer 14 CS Register MB_SIZE 0x160 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB14_8B_CS Message Buffer 14 CS Register MB_SIZE 0x160 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_64B_WORD0_L Message Buffer 3 WORD_64B Register MB_SIZE 0x160 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_WORD4_L Message Buffer 5 WORD_32B Register MB_SIZE 0x160 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_WORD0_L Message Buffer 9 WORD_16B Register MB_SIZE 0x160 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write ID14 Message Buffer 14 ID Register MB_SIZE 0x164 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB14_8B_ID Message Buffer 14 ID Register MB_SIZE 0x164 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_64B_WORD1_L Message Buffer 3 WORD_64B Register MB_SIZE 0x164 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_WORD5_L Message Buffer 5 WORD_32B Register MB_SIZE 0x164 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_WORD1_L Message Buffer 9 WORD_16B Register MB_SIZE 0x164 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB14_8B_WORD0 Message Buffer 14 WORD_8B Register MB_SIZE 0x168 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD2_L Message Buffer 3 WORD_64B Register MB_SIZE 0x168 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_WORD6_L Message Buffer 5 WORD_32B Register MB_SIZE 0x168 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_WORD2_L Message Buffer 9 WORD_16B Register MB_SIZE 0x168 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD014 Message Buffer 14 WORD0 Register MB_SIZE 0x168 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB14_8B_WORD1 Message Buffer 14 WORD_8B Register MB_SIZE 0x16C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD3_L Message Buffer 3 WORD_64B Register MB_SIZE 0x16C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_WORD7_L Message Buffer 5 WORD_32B Register MB_SIZE 0x16C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_WORD3_L Message Buffer 9 WORD_16B Register MB_SIZE 0x16C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD114 Message Buffer 14 WORD1 Register MB_SIZE 0x16C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS15 Message Buffer 15 CS Register MB_SIZE 0x170 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB10_16B_CS_L Message Buffer 10 CS Register MB_SIZE 0x170 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB15_8B_CS Message Buffer 15 CS Register MB_SIZE 0x170 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_64B_WORD4_L Message Buffer 3 WORD_64B Register MB_SIZE 0x170 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_CS_L Message Buffer 6 CS Register MB_SIZE 0x170 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID15 Message Buffer 15 ID Register MB_SIZE 0x174 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_16B_ID_L Message Buffer 10 ID Register MB_SIZE 0x174 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB15_8B_ID Message Buffer 15 ID Register MB_SIZE 0x174 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_64B_WORD5_L Message Buffer 3 WORD_64B Register MB_SIZE 0x174 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_ID_L Message Buffer 6 ID Register MB_SIZE 0x174 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_16B_WORD0_L Message Buffer 10 WORD_16B Register MB_SIZE 0x178 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB15_8B_WORD0 Message Buffer 15 WORD_8B Register MB_SIZE 0x178 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD6_L Message Buffer 3 WORD_64B Register MB_SIZE 0x178 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD0_L Message Buffer 6 WORD_32B Register MB_SIZE 0x178 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD015 Message Buffer 15 WORD0 Register MB_SIZE 0x178 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_16B_WORD1_L Message Buffer 10 WORD_16B Register MB_SIZE 0x17C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB15_8B_WORD1 Message Buffer 15 WORD_8B Register MB_SIZE 0x17C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD7_L Message Buffer 3 WORD_64B Register MB_SIZE 0x17C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD1_L Message Buffer 6 WORD_32B Register MB_SIZE 0x17C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD115 Message Buffer 15 WORD1 Register MB_SIZE 0x17C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS16 Message Buffer 16 CS Register MB_SIZE 0x180 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB10_16B_WORD2_L Message Buffer 10 WORD_16B Register MB_SIZE 0x180 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB16_8B_CS Message Buffer 16 CS Register MB_SIZE 0x180 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_64B_WORD8_L Message Buffer 3 WORD_64B Register MB_SIZE 0x180 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD2_L Message Buffer 6 WORD_32B Register MB_SIZE 0x180 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write ID16 Message Buffer 16 ID Register MB_SIZE 0x184 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_16B_WORD3_L Message Buffer 10 WORD_16B Register MB_SIZE 0x184 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB16_8B_ID Message Buffer 16 ID Register MB_SIZE 0x184 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_64B_WORD9_L Message Buffer 3 WORD_64B Register MB_SIZE 0x184 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD3_L Message Buffer 6 WORD_32B Register MB_SIZE 0x184 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_16B_CS_L Message Buffer 11 CS Register MB_SIZE 0x188 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB16_8B_WORD0 Message Buffer 16 WORD_8B Register MB_SIZE 0x188 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD10_L Message Buffer 3 WORD_64B Register MB_SIZE 0x188 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD4_L Message Buffer 6 WORD_32B Register MB_SIZE 0x188 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD016 Message Buffer 16 WORD0 Register MB_SIZE 0x188 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_16B_ID_L Message Buffer 11 ID Register MB_SIZE 0x18C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB16_8B_WORD1 Message Buffer 16 WORD_8B Register MB_SIZE 0x18C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD11_L Message Buffer 3 WORD_64B Register MB_SIZE 0x18C 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD5_L Message Buffer 6 WORD_32B Register MB_SIZE 0x18C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD116 Message Buffer 16 WORD1 Register MB_SIZE 0x18C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS17 Message Buffer 17 CS Register MB_SIZE 0x190 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB11_16B_WORD0_L Message Buffer 11 WORD_16B Register MB_SIZE 0x190 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_8B_CS Message Buffer 17 CS Register MB_SIZE 0x190 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_64B_WORD12_L Message Buffer 3 WORD_64B Register MB_SIZE 0x190 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD6_L Message Buffer 6 WORD_32B Register MB_SIZE 0x190 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write ID17 Message Buffer 17 ID Register MB_SIZE 0x194 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB11_16B_WORD1_L Message Buffer 11 WORD_16B Register MB_SIZE 0x194 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_8B_ID Message Buffer 17 ID Register MB_SIZE 0x194 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_64B_WORD13_L Message Buffer 3 WORD_64B Register MB_SIZE 0x194 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD7_L Message Buffer 6 WORD_32B Register MB_SIZE 0x194 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_16B_WORD2_L Message Buffer 11 WORD_16B Register MB_SIZE 0x198 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_8B_WORD0 Message Buffer 17 WORD_8B Register MB_SIZE 0x198 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD14_L Message Buffer 3 WORD_64B Register MB_SIZE 0x198 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_CS_L Message Buffer 7 CS Register MB_SIZE 0x198 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write WORD017 Message Buffer 17 WORD0 Register MB_SIZE 0x198 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_16B_WORD3_L Message Buffer 11 WORD_16B Register MB_SIZE 0x19C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_8B_WORD1 Message Buffer 17 WORD_8B Register MB_SIZE 0x19C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD15_L Message Buffer 3 WORD_64B Register MB_SIZE 0x19C 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_ID_L Message Buffer 7 ID Register MB_SIZE 0x19C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD117 Message Buffer 17 WORD1 Register MB_SIZE 0x19C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS18 Message Buffer 18 CS Register MB_SIZE 0x1A0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB12_16B_CS_L Message Buffer 12 CS Register MB_SIZE 0x1A0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB18_8B_CS Message Buffer 18 CS Register MB_SIZE 0x1A0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_64B_CS_L Message Buffer 4 CS Register MB_SIZE 0x1A0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB7_32B_WORD0_L Message Buffer 7 WORD_32B Register MB_SIZE 0x1A0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write ID18 Message Buffer 18 ID Register MB_SIZE 0x1A4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB12_16B_ID_L Message Buffer 12 ID Register MB_SIZE 0x1A4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB18_8B_ID Message Buffer 18 ID Register MB_SIZE 0x1A4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_64B_ID_L Message Buffer 4 ID Register MB_SIZE 0x1A4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB7_32B_WORD1_L Message Buffer 7 WORD_32B Register MB_SIZE 0x1A4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB12_16B_WORD0_L Message Buffer 12 WORD_16B Register MB_SIZE 0x1A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB18_8B_WORD0 Message Buffer 18 WORD_8B Register MB_SIZE 0x1A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD0_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_WORD2_L Message Buffer 7 WORD_32B Register MB_SIZE 0x1A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD018 Message Buffer 18 WORD0 Register MB_SIZE 0x1A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB12_16B_WORD1_L Message Buffer 12 WORD_16B Register MB_SIZE 0x1AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB18_8B_WORD1 Message Buffer 18 WORD_8B Register MB_SIZE 0x1AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD1_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_WORD3_L Message Buffer 7 WORD_32B Register MB_SIZE 0x1AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD118 Message Buffer 18 WORD1 Register MB_SIZE 0x1AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS19 Message Buffer 19 CS Register MB_SIZE 0x1B0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB12_16B_WORD2_L Message Buffer 12 WORD_16B Register MB_SIZE 0x1B0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_8B_CS Message Buffer 19 CS Register MB_SIZE 0x1B0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_64B_WORD2_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1B0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_WORD4_L Message Buffer 7 WORD_32B Register MB_SIZE 0x1B0 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write ID19 Message Buffer 19 ID Register MB_SIZE 0x1B4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB12_16B_WORD3_L Message Buffer 12 WORD_16B Register MB_SIZE 0x1B4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_8B_ID Message Buffer 19 ID Register MB_SIZE 0x1B4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_64B_WORD3_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1B4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_WORD5_L Message Buffer 7 WORD_32B Register MB_SIZE 0x1B4 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB13_16B_CS_L Message Buffer 13 CS Register MB_SIZE 0x1B8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB19_8B_WORD0 Message Buffer 19 WORD_8B Register MB_SIZE 0x1B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD4_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_WORD6_L Message Buffer 7 WORD_32B Register MB_SIZE 0x1B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD019 Message Buffer 19 WORD0 Register MB_SIZE 0x1B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB13_16B_ID_L Message Buffer 13 ID Register MB_SIZE 0x1BC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB19_8B_WORD1 Message Buffer 19 WORD_8B Register MB_SIZE 0x1BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD5_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_WORD7_L Message Buffer 7 WORD_32B Register MB_SIZE 0x1BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD119 Message Buffer 19 WORD1 Register MB_SIZE 0x1BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS20 Message Buffer 20 CS Register MB_SIZE 0x1C0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB13_16B_WORD0_L Message Buffer 13 WORD_16B Register MB_SIZE 0x1C0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB20_8B_CS Message Buffer 20 CS Register MB_SIZE 0x1C0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_64B_WORD6_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1C0 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_CS_L Message Buffer 8 CS Register MB_SIZE 0x1C0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID20 Message Buffer 20 ID Register MB_SIZE 0x1C4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB13_16B_WORD1_L Message Buffer 13 WORD_16B Register MB_SIZE 0x1C4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB20_8B_ID Message Buffer 20 ID Register MB_SIZE 0x1C4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_64B_WORD7_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1C4 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_ID_L Message Buffer 8 ID Register MB_SIZE 0x1C4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB13_16B_WORD2_L Message Buffer 13 WORD_16B Register MB_SIZE 0x1C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB20_8B_WORD0 Message Buffer 20 WORD_8B Register MB_SIZE 0x1C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD8_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD0_L Message Buffer 8 WORD_32B Register MB_SIZE 0x1C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD020 Message Buffer 20 WORD0 Register MB_SIZE 0x1C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB13_16B_WORD3_L Message Buffer 13 WORD_16B Register MB_SIZE 0x1CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB20_8B_WORD1 Message Buffer 20 WORD_8B Register MB_SIZE 0x1CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD9_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD1_L Message Buffer 8 WORD_32B Register MB_SIZE 0x1CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD120 Message Buffer 20 WORD1 Register MB_SIZE 0x1CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS21 Message Buffer 21 CS Register MB_SIZE 0x1D0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB14_16B_CS_L Message Buffer 14 CS Register MB_SIZE 0x1D0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB21_8B_CS Message Buffer 21 CS Register MB_SIZE 0x1D0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_64B_WORD10_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1D0 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD2_L Message Buffer 8 WORD_32B Register MB_SIZE 0x1D0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write ID21 Message Buffer 21 ID Register MB_SIZE 0x1D4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB14_16B_ID_L Message Buffer 14 ID Register MB_SIZE 0x1D4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB21_8B_ID Message Buffer 21 ID Register MB_SIZE 0x1D4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_64B_WORD11_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1D4 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD3_L Message Buffer 8 WORD_32B Register MB_SIZE 0x1D4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB14_16B_WORD0_L Message Buffer 14 WORD_16B Register MB_SIZE 0x1D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB21_8B_WORD0 Message Buffer 21 WORD_8B Register MB_SIZE 0x1D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD12_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD4_L Message Buffer 8 WORD_32B Register MB_SIZE 0x1D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD021 Message Buffer 21 WORD0 Register MB_SIZE 0x1D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB14_16B_WORD1_L Message Buffer 14 WORD_16B Register MB_SIZE 0x1DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB21_8B_WORD1 Message Buffer 21 WORD_8B Register MB_SIZE 0x1DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD13_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD5_L Message Buffer 8 WORD_32B Register MB_SIZE 0x1DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD121 Message Buffer 21 WORD1 Register MB_SIZE 0x1DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS22 Message Buffer 22 CS Register MB_SIZE 0x1E0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB14_16B_WORD2_L Message Buffer 14 WORD_16B Register MB_SIZE 0x1E0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB22_8B_CS Message Buffer 22 CS Register MB_SIZE 0x1E0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_64B_WORD14_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1E0 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD6_L Message Buffer 8 WORD_32B Register MB_SIZE 0x1E0 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write ID22 Message Buffer 22 ID Register MB_SIZE 0x1E4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB14_16B_WORD3_L Message Buffer 14 WORD_16B Register MB_SIZE 0x1E4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB22_8B_ID Message Buffer 22 ID Register MB_SIZE 0x1E4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_64B_WORD15_L Message Buffer 4 WORD_64B Register MB_SIZE 0x1E4 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD7_L Message Buffer 8 WORD_32B Register MB_SIZE 0x1E4 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB15_16B_CS_L Message Buffer 15 CS Register MB_SIZE 0x1E8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB22_8B_WORD0 Message Buffer 22 WORD_8B Register MB_SIZE 0x1E8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_CS_L Message Buffer 5 CS Register MB_SIZE 0x1E8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB9_32B_CS_L Message Buffer 9 CS Register MB_SIZE 0x1E8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write WORD022 Message Buffer 22 WORD0 Register MB_SIZE 0x1E8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB15_16B_ID_L Message Buffer 15 ID Register MB_SIZE 0x1EC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB22_8B_WORD1 Message Buffer 22 WORD_8B Register MB_SIZE 0x1EC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_ID_L Message Buffer 5 ID Register MB_SIZE 0x1EC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB9_32B_ID_L Message Buffer 9 ID Register MB_SIZE 0x1EC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD122 Message Buffer 22 WORD1 Register MB_SIZE 0x1EC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS23 Message Buffer 23 CS Register MB_SIZE 0x1F0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB15_16B_WORD0_L Message Buffer 15 WORD_16B Register MB_SIZE 0x1F0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB23_8B_CS Message Buffer 23 CS Register MB_SIZE 0x1F0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_64B_WORD0_L Message Buffer 5 WORD_64B Register MB_SIZE 0x1F0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD0_L Message Buffer 9 WORD_32B Register MB_SIZE 0x1F0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write ID23 Message Buffer 23 ID Register MB_SIZE 0x1F4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB15_16B_WORD1_L Message Buffer 15 WORD_16B Register MB_SIZE 0x1F4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB23_8B_ID Message Buffer 23 ID Register MB_SIZE 0x1F4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_64B_WORD1_L Message Buffer 5 WORD_64B Register MB_SIZE 0x1F4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD1_L Message Buffer 9 WORD_32B Register MB_SIZE 0x1F4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB15_16B_WORD2_L Message Buffer 15 WORD_16B Register MB_SIZE 0x1F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB23_8B_WORD0 Message Buffer 23 WORD_8B Register MB_SIZE 0x1F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD2_L Message Buffer 5 WORD_64B Register MB_SIZE 0x1F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD2_L Message Buffer 9 WORD_32B Register MB_SIZE 0x1F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD023 Message Buffer 23 WORD0 Register MB_SIZE 0x1F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB15_16B_WORD3_L Message Buffer 15 WORD_16B Register MB_SIZE 0x1FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB23_8B_WORD1 Message Buffer 23 WORD_8B Register MB_SIZE 0x1FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD3_L Message Buffer 5 WORD_64B Register MB_SIZE 0x1FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD3_L Message Buffer 9 WORD_32B Register MB_SIZE 0x1FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD123 Message Buffer 23 WORD1 Register MB_SIZE 0x1FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS24 Message Buffer 24 CS Register MB_SIZE 0x200 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB16_16B_CS_L Message Buffer 16 CS Register MB_SIZE 0x200 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB24_8B_CS Message Buffer 24 CS Register MB_SIZE 0x200 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_64B_WORD4_L Message Buffer 5 WORD_64B Register MB_SIZE 0x200 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD4_L Message Buffer 9 WORD_32B Register MB_SIZE 0x200 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write ID24 Message Buffer 24 ID Register MB_SIZE 0x204 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB16_16B_ID_L Message Buffer 16 ID Register MB_SIZE 0x204 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB24_8B_ID Message Buffer 24 ID Register MB_SIZE 0x204 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_64B_WORD5_L Message Buffer 5 WORD_64B Register MB_SIZE 0x204 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD5_L Message Buffer 9 WORD_32B Register MB_SIZE 0x204 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB16_16B_WORD0_L Message Buffer 16 WORD_16B Register MB_SIZE 0x208 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB24_8B_WORD0 Message Buffer 24 WORD_8B Register MB_SIZE 0x208 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD6_L Message Buffer 5 WORD_64B Register MB_SIZE 0x208 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD6_L Message Buffer 9 WORD_32B Register MB_SIZE 0x208 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD024 Message Buffer 24 WORD0 Register MB_SIZE 0x208 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB16_16B_WORD1_L Message Buffer 16 WORD_16B Register MB_SIZE 0x20C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB24_8B_WORD1 Message Buffer 24 WORD_8B Register MB_SIZE 0x20C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD7_L Message Buffer 5 WORD_64B Register MB_SIZE 0x20C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD7_L Message Buffer 9 WORD_32B Register MB_SIZE 0x20C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD124 Message Buffer 24 WORD1 Register MB_SIZE 0x20C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS25 Message Buffer 25 CS Register MB_SIZE 0x210 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB10_32B_CS_L Message Buffer 10 CS Register MB_SIZE 0x210 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB16_16B_WORD2_L Message Buffer 16 WORD_16B Register MB_SIZE 0x210 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB25_8B_CS Message Buffer 25 CS Register MB_SIZE 0x210 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_64B_WORD8_L Message Buffer 5 WORD_64B Register MB_SIZE 0x210 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write ID25 Message Buffer 25 ID Register MB_SIZE 0x214 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_32B_ID_L Message Buffer 10 ID Register MB_SIZE 0x214 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB16_16B_WORD3_L Message Buffer 16 WORD_16B Register MB_SIZE 0x214 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB25_8B_ID Message Buffer 25 ID Register MB_SIZE 0x214 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_64B_WORD9_L Message Buffer 5 WORD_64B Register MB_SIZE 0x214 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_32B_WORD0_L Message Buffer 10 WORD_32B Register MB_SIZE 0x218 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_CS_L Message Buffer 17 CS Register MB_SIZE 0x218 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB25_8B_WORD0 Message Buffer 25 WORD_8B Register MB_SIZE 0x218 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD10_L Message Buffer 5 WORD_64B Register MB_SIZE 0x218 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD025 Message Buffer 25 WORD0 Register MB_SIZE 0x218 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_32B_WORD1_L Message Buffer 10 WORD_32B Register MB_SIZE 0x21C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_ID_L Message Buffer 17 ID Register MB_SIZE 0x21C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB25_8B_WORD1 Message Buffer 25 WORD_8B Register MB_SIZE 0x21C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD11_L Message Buffer 5 WORD_64B Register MB_SIZE 0x21C 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD125 Message Buffer 25 WORD1 Register MB_SIZE 0x21C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS26 Message Buffer 26 CS Register MB_SIZE 0x220 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB10_32B_WORD2_L Message Buffer 10 WORD_32B Register MB_SIZE 0x220 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_WORD0_L Message Buffer 17 WORD_16B Register MB_SIZE 0x220 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB26_8B_CS Message Buffer 26 CS Register MB_SIZE 0x220 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_64B_WORD12_L Message Buffer 5 WORD_64B Register MB_SIZE 0x220 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write ID26 Message Buffer 26 ID Register MB_SIZE 0x224 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_32B_WORD3_L Message Buffer 10 WORD_32B Register MB_SIZE 0x224 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_WORD1_L Message Buffer 17 WORD_16B Register MB_SIZE 0x224 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB26_8B_ID Message Buffer 26 ID Register MB_SIZE 0x224 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_64B_WORD13_L Message Buffer 5 WORD_64B Register MB_SIZE 0x224 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_32B_WORD4_L Message Buffer 10 WORD_32B Register MB_SIZE 0x228 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_WORD2_L Message Buffer 17 WORD_16B Register MB_SIZE 0x228 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB26_8B_WORD0 Message Buffer 26 WORD_8B Register MB_SIZE 0x228 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD14_L Message Buffer 5 WORD_64B Register MB_SIZE 0x228 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD026 Message Buffer 26 WORD0 Register MB_SIZE 0x228 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_32B_WORD5_L Message Buffer 10 WORD_32B Register MB_SIZE 0x22C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_WORD3_L Message Buffer 17 WORD_16B Register MB_SIZE 0x22C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB26_8B_WORD1 Message Buffer 26 WORD_8B Register MB_SIZE 0x22C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD15_L Message Buffer 5 WORD_64B Register MB_SIZE 0x22C 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD126 Message Buffer 26 WORD1 Register MB_SIZE 0x22C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS27 Message Buffer 27 CS Register MB_SIZE 0x230 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB10_32B_WORD6_L Message Buffer 10 WORD_32B Register MB_SIZE 0x230 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB18_16B_CS_L Message Buffer 18 CS Register MB_SIZE 0x230 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB27_8B_CS Message Buffer 27 CS Register MB_SIZE 0x230 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_64B_CS_L Message Buffer 6 CS Register MB_SIZE 0x230 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID27 Message Buffer 27 ID Register MB_SIZE 0x234 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_32B_WORD7_L Message Buffer 10 WORD_32B Register MB_SIZE 0x234 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB18_16B_ID_L Message Buffer 18 ID Register MB_SIZE 0x234 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB27_8B_ID Message Buffer 27 ID Register MB_SIZE 0x234 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_64B_ID_L Message Buffer 6 ID Register MB_SIZE 0x234 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB11_32B_CS_L Message Buffer 11 CS Register MB_SIZE 0x238 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB18_16B_WORD0_L Message Buffer 18 WORD_16B Register MB_SIZE 0x238 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB27_8B_WORD0 Message Buffer 27 WORD_8B Register MB_SIZE 0x238 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD0_L Message Buffer 6 WORD_64B Register MB_SIZE 0x238 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD027 Message Buffer 27 WORD0 Register MB_SIZE 0x238 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_32B_ID_L Message Buffer 11 ID Register MB_SIZE 0x23C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB18_16B_WORD1_L Message Buffer 18 WORD_16B Register MB_SIZE 0x23C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB27_8B_WORD1 Message Buffer 27 WORD_8B Register MB_SIZE 0x23C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD1_L Message Buffer 6 WORD_64B Register MB_SIZE 0x23C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD127 Message Buffer 27 WORD1 Register MB_SIZE 0x23C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS28 Message Buffer 28 CS Register MB_SIZE 0x240 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB11_32B_WORD0_L Message Buffer 11 WORD_32B Register MB_SIZE 0x240 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB18_16B_WORD2_L Message Buffer 18 WORD_16B Register MB_SIZE 0x240 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB28_8B_CS Message Buffer 28 CS Register MB_SIZE 0x240 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_64B_WORD2_L Message Buffer 6 WORD_64B Register MB_SIZE 0x240 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write ID28 Message Buffer 28 ID Register MB_SIZE 0x244 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB11_32B_WORD1_L Message Buffer 11 WORD_32B Register MB_SIZE 0x244 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB18_16B_WORD3_L Message Buffer 18 WORD_16B Register MB_SIZE 0x244 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB28_8B_ID Message Buffer 28 ID Register MB_SIZE 0x244 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_64B_WORD3_L Message Buffer 6 WORD_64B Register MB_SIZE 0x244 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_32B_WORD2_L Message Buffer 11 WORD_32B Register MB_SIZE 0x248 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_CS_L Message Buffer 19 CS Register MB_SIZE 0x248 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB28_8B_WORD0 Message Buffer 28 WORD_8B Register MB_SIZE 0x248 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD4_L Message Buffer 6 WORD_64B Register MB_SIZE 0x248 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD028 Message Buffer 28 WORD0 Register MB_SIZE 0x248 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_32B_WORD3_L Message Buffer 11 WORD_32B Register MB_SIZE 0x24C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_ID_L Message Buffer 19 ID Register MB_SIZE 0x24C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB28_8B_WORD1 Message Buffer 28 WORD_8B Register MB_SIZE 0x24C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD5_L Message Buffer 6 WORD_64B Register MB_SIZE 0x24C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD128 Message Buffer 28 WORD1 Register MB_SIZE 0x24C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS29 Message Buffer 29 CS Register MB_SIZE 0x250 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB11_32B_WORD4_L Message Buffer 11 WORD_32B Register MB_SIZE 0x250 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_WORD0_L Message Buffer 19 WORD_16B Register MB_SIZE 0x250 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB29_8B_CS Message Buffer 29 CS Register MB_SIZE 0x250 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_64B_WORD6_L Message Buffer 6 WORD_64B Register MB_SIZE 0x250 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write ID29 Message Buffer 29 ID Register MB_SIZE 0x254 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB11_32B_WORD5_L Message Buffer 11 WORD_32B Register MB_SIZE 0x254 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_WORD1_L Message Buffer 19 WORD_16B Register MB_SIZE 0x254 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB29_8B_ID Message Buffer 29 ID Register MB_SIZE 0x254 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_64B_WORD7_L Message Buffer 6 WORD_64B Register MB_SIZE 0x254 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_32B_WORD6_L Message Buffer 11 WORD_32B Register MB_SIZE 0x258 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_WORD2_L Message Buffer 19 WORD_16B Register MB_SIZE 0x258 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB29_8B_WORD0 Message Buffer 29 WORD_8B Register MB_SIZE 0x258 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD8_L Message Buffer 6 WORD_64B Register MB_SIZE 0x258 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD029 Message Buffer 29 WORD0 Register MB_SIZE 0x258 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_32B_WORD7_L Message Buffer 11 WORD_32B Register MB_SIZE 0x25C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_WORD3_L Message Buffer 19 WORD_16B Register MB_SIZE 0x25C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB29_8B_WORD1 Message Buffer 29 WORD_8B Register MB_SIZE 0x25C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD9_L Message Buffer 6 WORD_64B Register MB_SIZE 0x25C 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD129 Message Buffer 29 WORD1 Register MB_SIZE 0x25C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS30 Message Buffer 30 CS Register MB_SIZE 0x260 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB20_16B_CS_L Message Buffer 20 CS Register MB_SIZE 0x260 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB30_8B_CS Message Buffer 30 CS Register MB_SIZE 0x260 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_64B_WORD10_L Message Buffer 6 WORD_64B Register MB_SIZE 0x260 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write ID30 Message Buffer 30 ID Register MB_SIZE 0x264 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB20_16B_ID_L Message Buffer 20 ID Register MB_SIZE 0x264 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB30_8B_ID Message Buffer 30 ID Register MB_SIZE 0x264 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_64B_WORD11_L Message Buffer 6 WORD_64B Register MB_SIZE 0x264 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB20_16B_WORD0_L Message Buffer 20 WORD_16B Register MB_SIZE 0x268 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB30_8B_WORD0 Message Buffer 30 WORD_8B Register MB_SIZE 0x268 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD12_L Message Buffer 6 WORD_64B Register MB_SIZE 0x268 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD030 Message Buffer 30 WORD0 Register MB_SIZE 0x268 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB20_16B_WORD1_L Message Buffer 20 WORD_16B Register MB_SIZE 0x26C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB30_8B_WORD1 Message Buffer 30 WORD_8B Register MB_SIZE 0x26C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD13_L Message Buffer 6 WORD_64B Register MB_SIZE 0x26C 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD130 Message Buffer 30 WORD1 Register MB_SIZE 0x26C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS31 Message Buffer 31 CS Register MB_SIZE 0x270 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB20_16B_WORD2_L Message Buffer 20 WORD_16B Register MB_SIZE 0x270 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB31_8B_CS Message Buffer 31 CS Register MB_SIZE 0x270 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_64B_WORD14_L Message Buffer 6 WORD_64B Register MB_SIZE 0x270 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write ID31 Message Buffer 31 ID Register MB_SIZE 0x274 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB20_16B_WORD3_L Message Buffer 20 WORD_16B Register MB_SIZE 0x274 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB31_8B_ID Message Buffer 31 ID Register MB_SIZE 0x274 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_64B_WORD15_L Message Buffer 6 WORD_64B Register MB_SIZE 0x274 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB31_8B_WORD0 Message Buffer 31 WORD_8B Register MB_SIZE 0x278 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD031 Message Buffer 31 WORD0 Register MB_SIZE 0x278 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB31_8B_WORD1 Message Buffer 31 WORD_8B Register MB_SIZE 0x27C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD131 Message Buffer 31 WORD1 Register MB_SIZE 0x27C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS32 Message Buffer 32 CS Register MB_SIZE 0x280 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_16B_CS_H Message Buffer 0 CS Register MB_SIZE 0x280 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_32B_CS_H Message Buffer 0 CS Register MB_SIZE 0x280 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_64B_CS_H Message Buffer 0 CS Register MB_SIZE 0x280 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB32_8B_CS Message Buffer 32 CS Register MB_SIZE 0x280 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID32 Message Buffer 32 ID Register MB_SIZE 0x284 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_16B_ID_H Message Buffer 0 ID Register MB_SIZE 0x284 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_32B_ID_H Message Buffer 0 ID Register MB_SIZE 0x284 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_64B_ID_H Message Buffer 0 ID Register MB_SIZE 0x284 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB32_8B_ID Message Buffer 32 ID Register MB_SIZE 0x284 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_16B_WORD0_H Message Buffer 0 WORD_16B Register MB_SIZE 0x288 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_32B_WORD0_H Message Buffer 0 WORD_32B Register MB_SIZE 0x288 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD0_H Message Buffer 0 WORD_64B Register MB_SIZE 0x288 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB32_8B_WORD0 Message Buffer 32 WORD_8B Register MB_SIZE 0x288 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD032 Message Buffer 32 WORD0 Register MB_SIZE 0x288 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_16B_WORD1_H Message Buffer 0 WORD_16B Register MB_SIZE 0x28C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_32B_WORD1_H Message Buffer 0 WORD_32B Register MB_SIZE 0x28C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD1_H Message Buffer 0 WORD_64B Register MB_SIZE 0x28C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB32_8B_WORD1 Message Buffer 32 WORD_8B Register MB_SIZE 0x28C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD132 Message Buffer 32 WORD1 Register MB_SIZE 0x28C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS33 Message Buffer 33 CS Register MB_SIZE 0x290 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_16B_WORD2_H Message Buffer 0 WORD_16B Register MB_SIZE 0x290 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_32B_WORD2_H Message Buffer 0 WORD_32B Register MB_SIZE 0x290 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD2_H Message Buffer 0 WORD_64B Register MB_SIZE 0x290 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB33_8B_CS Message Buffer 33 CS Register MB_SIZE 0x290 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID33 Message Buffer 33 ID Register MB_SIZE 0x294 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_16B_WORD3_H Message Buffer 0 WORD_16B Register MB_SIZE 0x294 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_32B_WORD3_H Message Buffer 0 WORD_32B Register MB_SIZE 0x294 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD3_H Message Buffer 0 WORD_64B Register MB_SIZE 0x294 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB33_8B_ID Message Buffer 33 ID Register MB_SIZE 0x294 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_32B_WORD4_H Message Buffer 0 WORD_32B Register MB_SIZE 0x298 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD4_H Message Buffer 0 WORD_64B Register MB_SIZE 0x298 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_CS_H Message Buffer 1 CS Register MB_SIZE 0x298 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB33_8B_WORD0 Message Buffer 33 WORD_8B Register MB_SIZE 0x298 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD033 Message Buffer 33 WORD0 Register MB_SIZE 0x298 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_32B_WORD5_H Message Buffer 0 WORD_32B Register MB_SIZE 0x29C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD5_H Message Buffer 0 WORD_64B Register MB_SIZE 0x29C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_ID_H Message Buffer 1 ID Register MB_SIZE 0x29C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB33_8B_WORD1 Message Buffer 33 WORD_8B Register MB_SIZE 0x29C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD133 Message Buffer 33 WORD1 Register MB_SIZE 0x29C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS34 Message Buffer 34 CS Register MB_SIZE 0x2A0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_32B_WORD6_H Message Buffer 0 WORD_32B Register MB_SIZE 0x2A0 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD6_H Message Buffer 0 WORD_64B Register MB_SIZE 0x2A0 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_WORD0_H Message Buffer 1 WORD_16B Register MB_SIZE 0x2A0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB34_8B_CS Message Buffer 34 CS Register MB_SIZE 0x2A0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID34 Message Buffer 34 ID Register MB_SIZE 0x2A4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_32B_WORD7_H Message Buffer 0 WORD_32B Register MB_SIZE 0x2A4 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD7_H Message Buffer 0 WORD_64B Register MB_SIZE 0x2A4 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_WORD1_H Message Buffer 1 WORD_16B Register MB_SIZE 0x2A4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB34_8B_ID Message Buffer 34 ID Register MB_SIZE 0x2A4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_64B_WORD8_H Message Buffer 0 WORD_64B Register MB_SIZE 0x2A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_WORD2_H Message Buffer 1 WORD_16B Register MB_SIZE 0x2A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_CS_H Message Buffer 1 CS Register MB_SIZE 0x2A8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB34_8B_WORD0 Message Buffer 34 WORD_8B Register MB_SIZE 0x2A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD034 Message Buffer 34 WORD0 Register MB_SIZE 0x2A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD9_H Message Buffer 0 WORD_64B Register MB_SIZE 0x2AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_16B_WORD3_H Message Buffer 1 WORD_16B Register MB_SIZE 0x2AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_ID_H Message Buffer 1 ID Register MB_SIZE 0x2AC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB34_8B_WORD1 Message Buffer 34 WORD_8B Register MB_SIZE 0x2AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD134 Message Buffer 34 WORD1 Register MB_SIZE 0x2AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS35 Message Buffer 35 CS Register MB_SIZE 0x2B0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_64B_WORD10_H Message Buffer 0 WORD_64B Register MB_SIZE 0x2B0 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD0_H Message Buffer 1 WORD_32B Register MB_SIZE 0x2B0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_CS_H Message Buffer 2 CS Register MB_SIZE 0x2B0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB35_8B_CS Message Buffer 35 CS Register MB_SIZE 0x2B0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID35 Message Buffer 35 ID Register MB_SIZE 0x2B4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_64B_WORD11_H Message Buffer 0 WORD_64B Register MB_SIZE 0x2B4 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD1_H Message Buffer 1 WORD_32B Register MB_SIZE 0x2B4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_ID_H Message Buffer 2 ID Register MB_SIZE 0x2B4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB35_8B_ID Message Buffer 35 ID Register MB_SIZE 0x2B4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_64B_WORD12_H Message Buffer 0 WORD_64B Register MB_SIZE 0x2B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD2_H Message Buffer 1 WORD_32B Register MB_SIZE 0x2B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_WORD0_H Message Buffer 2 WORD_16B Register MB_SIZE 0x2B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB35_8B_WORD0 Message Buffer 35 WORD_8B Register MB_SIZE 0x2B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD035 Message Buffer 35 WORD0 Register MB_SIZE 0x2B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB0_64B_WORD13_H Message Buffer 0 WORD_64B Register MB_SIZE 0x2BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD3_H Message Buffer 1 WORD_32B Register MB_SIZE 0x2BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_WORD1_H Message Buffer 2 WORD_16B Register MB_SIZE 0x2BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB35_8B_WORD1 Message Buffer 35 WORD_8B Register MB_SIZE 0x2BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD135 Message Buffer 35 WORD1 Register MB_SIZE 0x2BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS36 Message Buffer 36 CS Register MB_SIZE 0x2C0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB0_64B_WORD14_H Message Buffer 0 WORD_64B Register MB_SIZE 0x2C0 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD4_H Message Buffer 1 WORD_32B Register MB_SIZE 0x2C0 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_WORD2_H Message Buffer 2 WORD_16B Register MB_SIZE 0x2C0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB36_8B_CS Message Buffer 36 CS Register MB_SIZE 0x2C0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID36 Message Buffer 36 ID Register MB_SIZE 0x2C4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB0_64B_WORD15_H Message Buffer 0 WORD_64B Register MB_SIZE 0x2C4 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD5_H Message Buffer 1 WORD_32B Register MB_SIZE 0x2C4 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_16B_WORD3_H Message Buffer 2 WORD_16B Register MB_SIZE 0x2C4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB36_8B_ID Message Buffer 36 ID Register MB_SIZE 0x2C4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_32B_WORD6_H Message Buffer 1 WORD_32B Register MB_SIZE 0x2C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_CS_H Message Buffer 1 CS Register MB_SIZE 0x2C8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB36_8B_WORD0 Message Buffer 36 WORD_8B Register MB_SIZE 0x2C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_16B_CS_H Message Buffer 3 CS Register MB_SIZE 0x2C8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write WORD036 Message Buffer 36 WORD0 Register MB_SIZE 0x2C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_32B_WORD7_H Message Buffer 1 WORD_32B Register MB_SIZE 0x2CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_ID_H Message Buffer 1 ID Register MB_SIZE 0x2CC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB36_8B_WORD1 Message Buffer 36 WORD_8B Register MB_SIZE 0x2CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_16B_ID_H Message Buffer 3 ID Register MB_SIZE 0x2CC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD136 Message Buffer 36 WORD1 Register MB_SIZE 0x2CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS37 Message Buffer 37 CS Register MB_SIZE 0x2D0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB1_64B_WORD0_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2D0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_CS_H Message Buffer 2 CS Register MB_SIZE 0x2D0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB37_8B_CS Message Buffer 37 CS Register MB_SIZE 0x2D0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_16B_WORD0_H Message Buffer 3 WORD_16B Register MB_SIZE 0x2D0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write ID37 Message Buffer 37 ID Register MB_SIZE 0x2D4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD1_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2D4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_ID_H Message Buffer 2 ID Register MB_SIZE 0x2D4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB37_8B_ID Message Buffer 37 ID Register MB_SIZE 0x2D4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_16B_WORD1_H Message Buffer 3 WORD_16B Register MB_SIZE 0x2D4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_WORD2_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD0_H Message Buffer 2 WORD_32B Register MB_SIZE 0x2D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB37_8B_WORD0 Message Buffer 37 WORD_8B Register MB_SIZE 0x2D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_16B_WORD2_H Message Buffer 3 WORD_16B Register MB_SIZE 0x2D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD037 Message Buffer 37 WORD0 Register MB_SIZE 0x2D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_WORD3_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD1_H Message Buffer 2 WORD_32B Register MB_SIZE 0x2DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB37_8B_WORD1 Message Buffer 37 WORD_8B Register MB_SIZE 0x2DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_16B_WORD3_H Message Buffer 3 WORD_16B Register MB_SIZE 0x2DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD137 Message Buffer 37 WORD1 Register MB_SIZE 0x2DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS38 Message Buffer 38 CS Register MB_SIZE 0x2E0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB1_64B_WORD4_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2E0 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD2_H Message Buffer 2 WORD_32B Register MB_SIZE 0x2E0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB38_8B_CS Message Buffer 38 CS Register MB_SIZE 0x2E0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_16B_CS_H Message Buffer 4 CS Register MB_SIZE 0x2E0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID38 Message Buffer 38 ID Register MB_SIZE 0x2E4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD5_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2E4 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD3_H Message Buffer 2 WORD_32B Register MB_SIZE 0x2E4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB38_8B_ID Message Buffer 38 ID Register MB_SIZE 0x2E4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_16B_ID_H Message Buffer 4 ID Register MB_SIZE 0x2E4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD6_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2E8 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD4_H Message Buffer 2 WORD_32B Register MB_SIZE 0x2E8 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB38_8B_WORD0 Message Buffer 38 WORD_8B Register MB_SIZE 0x2E8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_16B_WORD0_H Message Buffer 4 WORD_16B Register MB_SIZE 0x2E8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD038 Message Buffer 38 WORD0 Register MB_SIZE 0x2E8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_WORD7_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2EC 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD5_H Message Buffer 2 WORD_32B Register MB_SIZE 0x2EC 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB38_8B_WORD1 Message Buffer 38 WORD_8B Register MB_SIZE 0x2EC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_16B_WORD1_H Message Buffer 4 WORD_16B Register MB_SIZE 0x2EC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD138 Message Buffer 38 WORD1 Register MB_SIZE 0x2EC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS39 Message Buffer 39 CS Register MB_SIZE 0x2F0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB1_64B_WORD8_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2F0 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD6_H Message Buffer 2 WORD_32B Register MB_SIZE 0x2F0 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB39_8B_CS Message Buffer 39 CS Register MB_SIZE 0x2F0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_16B_WORD2_H Message Buffer 4 WORD_16B Register MB_SIZE 0x2F0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write ID39 Message Buffer 39 ID Register MB_SIZE 0x2F4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD9_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2F4 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_32B_WORD7_H Message Buffer 2 WORD_32B Register MB_SIZE 0x2F4 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB39_8B_ID Message Buffer 39 ID Register MB_SIZE 0x2F4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_16B_WORD3_H Message Buffer 4 WORD_16B Register MB_SIZE 0x2F4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_WORD10_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write MB39_8B_WORD0 Message Buffer 39 WORD_8B Register MB_SIZE 0x2F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_CS_H Message Buffer 3 CS Register MB_SIZE 0x2F8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_16B_CS_H Message Buffer 5 CS Register MB_SIZE 0x2F8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write WORD039 Message Buffer 39 WORD0 Register MB_SIZE 0x2F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_WORD11_H Message Buffer 1 WORD_64B Register MB_SIZE 0x2FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB39_8B_WORD1 Message Buffer 39 WORD_8B Register MB_SIZE 0x2FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_ID_H Message Buffer 3 ID Register MB_SIZE 0x2FC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_16B_ID_H Message Buffer 5 ID Register MB_SIZE 0x2FC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD139 Message Buffer 39 WORD1 Register MB_SIZE 0x2FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS40 Message Buffer 40 CS Register MB_SIZE 0x300 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB1_64B_WORD12_H Message Buffer 1 WORD_64B Register MB_SIZE 0x300 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD0_H Message Buffer 3 WORD_32B Register MB_SIZE 0x300 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB40_8B_CS Message Buffer 40 CS Register MB_SIZE 0x300 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_16B_WORD0_H Message Buffer 5 WORD_16B Register MB_SIZE 0x300 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write ID40 Message Buffer 40 ID Register MB_SIZE 0x304 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB1_64B_WORD13_H Message Buffer 1 WORD_64B Register MB_SIZE 0x304 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD1_H Message Buffer 3 WORD_32B Register MB_SIZE 0x304 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB40_8B_ID Message Buffer 40 ID Register MB_SIZE 0x304 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_16B_WORD1_H Message Buffer 5 WORD_16B Register MB_SIZE 0x304 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_WORD14_H Message Buffer 1 WORD_64B Register MB_SIZE 0x308 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD2_H Message Buffer 3 WORD_32B Register MB_SIZE 0x308 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB40_8B_WORD0 Message Buffer 40 WORD_8B Register MB_SIZE 0x308 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_16B_WORD2_H Message Buffer 5 WORD_16B Register MB_SIZE 0x308 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD040 Message Buffer 40 WORD0 Register MB_SIZE 0x308 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB1_64B_WORD15_H Message Buffer 1 WORD_64B Register MB_SIZE 0x30C 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD3_H Message Buffer 3 WORD_32B Register MB_SIZE 0x30C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB40_8B_WORD1 Message Buffer 40 WORD_8B Register MB_SIZE 0x30C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_16B_WORD3_H Message Buffer 5 WORD_16B Register MB_SIZE 0x30C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD140 Message Buffer 40 WORD1 Register MB_SIZE 0x30C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS41 Message Buffer 41 CS Register MB_SIZE 0x310 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB2_64B_CS_H Message Buffer 2 CS Register MB_SIZE 0x310 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_32B_WORD4_H Message Buffer 3 WORD_32B Register MB_SIZE 0x310 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB41_8B_CS Message Buffer 41 CS Register MB_SIZE 0x310 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_16B_CS_H Message Buffer 6 CS Register MB_SIZE 0x310 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID41 Message Buffer 41 ID Register MB_SIZE 0x314 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_ID_H Message Buffer 2 ID Register MB_SIZE 0x314 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_32B_WORD5_H Message Buffer 3 WORD_32B Register MB_SIZE 0x314 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB41_8B_ID Message Buffer 41 ID Register MB_SIZE 0x314 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_16B_ID_H Message Buffer 6 ID Register MB_SIZE 0x314 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_WORD0_H Message Buffer 2 WORD_64B Register MB_SIZE 0x318 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD6_H Message Buffer 3 WORD_32B Register MB_SIZE 0x318 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB41_8B_WORD0 Message Buffer 41 WORD_8B Register MB_SIZE 0x318 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_16B_WORD0_H Message Buffer 6 WORD_16B Register MB_SIZE 0x318 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD041 Message Buffer 41 WORD0 Register MB_SIZE 0x318 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD1_H Message Buffer 2 WORD_64B Register MB_SIZE 0x31C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_32B_WORD7_H Message Buffer 3 WORD_32B Register MB_SIZE 0x31C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB41_8B_WORD1 Message Buffer 41 WORD_8B Register MB_SIZE 0x31C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_16B_WORD1_H Message Buffer 6 WORD_16B Register MB_SIZE 0x31C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD141 Message Buffer 41 WORD1 Register MB_SIZE 0x31C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS42 Message Buffer 42 CS Register MB_SIZE 0x320 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB2_64B_WORD2_H Message Buffer 2 WORD_64B Register MB_SIZE 0x320 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB42_8B_CS Message Buffer 42 CS Register MB_SIZE 0x320 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_32B_CS_H Message Buffer 4 CS Register MB_SIZE 0x320 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_16B_WORD2_H Message Buffer 6 WORD_16B Register MB_SIZE 0x320 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write ID42 Message Buffer 42 ID Register MB_SIZE 0x324 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_WORD3_H Message Buffer 2 WORD_64B Register MB_SIZE 0x324 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB42_8B_ID Message Buffer 42 ID Register MB_SIZE 0x324 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_32B_ID_H Message Buffer 4 ID Register MB_SIZE 0x324 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_16B_WORD3_H Message Buffer 6 WORD_16B Register MB_SIZE 0x324 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD4_H Message Buffer 2 WORD_64B Register MB_SIZE 0x328 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB42_8B_WORD0 Message Buffer 42 WORD_8B Register MB_SIZE 0x328 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD0_H Message Buffer 4 WORD_32B Register MB_SIZE 0x328 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_CS_H Message Buffer 7 CS Register MB_SIZE 0x328 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write WORD042 Message Buffer 42 WORD0 Register MB_SIZE 0x328 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD5_H Message Buffer 2 WORD_64B Register MB_SIZE 0x32C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB42_8B_WORD1 Message Buffer 42 WORD_8B Register MB_SIZE 0x32C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD1_H Message Buffer 4 WORD_32B Register MB_SIZE 0x32C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_ID_H Message Buffer 7 ID Register MB_SIZE 0x32C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD142 Message Buffer 42 WORD1 Register MB_SIZE 0x32C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS43 Message Buffer 43 CS Register MB_SIZE 0x330 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB2_64B_WORD6_H Message Buffer 2 WORD_64B Register MB_SIZE 0x330 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB43_8B_CS Message Buffer 43 CS Register MB_SIZE 0x330 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_32B_WORD2_H Message Buffer 4 WORD_32B Register MB_SIZE 0x330 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_WORD0_H Message Buffer 7 WORD_16B Register MB_SIZE 0x330 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write ID43 Message Buffer 43 ID Register MB_SIZE 0x334 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_WORD7_H Message Buffer 2 WORD_64B Register MB_SIZE 0x334 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB43_8B_ID Message Buffer 43 ID Register MB_SIZE 0x334 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_32B_WORD3_H Message Buffer 4 WORD_32B Register MB_SIZE 0x334 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_WORD1_H Message Buffer 7 WORD_16B Register MB_SIZE 0x334 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD8_H Message Buffer 2 WORD_64B Register MB_SIZE 0x338 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write MB43_8B_WORD0 Message Buffer 43 WORD_8B Register MB_SIZE 0x338 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD4_H Message Buffer 4 WORD_32B Register MB_SIZE 0x338 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_WORD2_H Message Buffer 7 WORD_16B Register MB_SIZE 0x338 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD043 Message Buffer 43 WORD0 Register MB_SIZE 0x338 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD9_H Message Buffer 2 WORD_64B Register MB_SIZE 0x33C 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB43_8B_WORD1 Message Buffer 43 WORD_8B Register MB_SIZE 0x33C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_32B_WORD5_H Message Buffer 4 WORD_32B Register MB_SIZE 0x33C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_16B_WORD3_H Message Buffer 7 WORD_16B Register MB_SIZE 0x33C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD143 Message Buffer 43 WORD1 Register MB_SIZE 0x33C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS44 Message Buffer 44 CS Register MB_SIZE 0x340 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB2_64B_WORD10_H Message Buffer 2 WORD_64B Register MB_SIZE 0x340 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write MB44_8B_CS Message Buffer 44 CS Register MB_SIZE 0x340 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_32B_WORD6_H Message Buffer 4 WORD_32B Register MB_SIZE 0x340 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_16B_CS_H Message Buffer 8 CS Register MB_SIZE 0x340 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID44 Message Buffer 44 ID Register MB_SIZE 0x344 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_WORD11_H Message Buffer 2 WORD_64B Register MB_SIZE 0x344 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB44_8B_ID Message Buffer 44 ID Register MB_SIZE 0x344 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_32B_WORD7_H Message Buffer 4 WORD_32B Register MB_SIZE 0x344 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_16B_ID_H Message Buffer 8 ID Register MB_SIZE 0x344 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_WORD12_H Message Buffer 2 WORD_64B Register MB_SIZE 0x348 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write MB44_8B_WORD0 Message Buffer 44 WORD_8B Register MB_SIZE 0x348 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_CS_H Message Buffer 5 CS Register MB_SIZE 0x348 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB8_16B_WORD0_H Message Buffer 8 WORD_16B Register MB_SIZE 0x348 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD044 Message Buffer 44 WORD0 Register MB_SIZE 0x348 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB2_64B_WORD13_H Message Buffer 2 WORD_64B Register MB_SIZE 0x34C 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB44_8B_WORD1 Message Buffer 44 WORD_8B Register MB_SIZE 0x34C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_ID_H Message Buffer 5 ID Register MB_SIZE 0x34C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB8_16B_WORD1_H Message Buffer 8 WORD_16B Register MB_SIZE 0x34C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD144 Message Buffer 44 WORD1 Register MB_SIZE 0x34C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS45 Message Buffer 45 CS Register MB_SIZE 0x350 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB2_64B_WORD14_H Message Buffer 2 WORD_64B Register MB_SIZE 0x350 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write MB45_8B_CS Message Buffer 45 CS Register MB_SIZE 0x350 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_32B_WORD0_H Message Buffer 5 WORD_32B Register MB_SIZE 0x350 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_16B_WORD2_H Message Buffer 8 WORD_16B Register MB_SIZE 0x350 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write ID45 Message Buffer 45 ID Register MB_SIZE 0x354 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB2_64B_WORD15_H Message Buffer 2 WORD_64B Register MB_SIZE 0x354 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB45_8B_ID Message Buffer 45 ID Register MB_SIZE 0x354 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_32B_WORD1_H Message Buffer 5 WORD_32B Register MB_SIZE 0x354 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_16B_WORD3_H Message Buffer 8 WORD_16B Register MB_SIZE 0x354 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_CS_H Message Buffer 3 CS Register MB_SIZE 0x358 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB45_8B_WORD0 Message Buffer 45 WORD_8B Register MB_SIZE 0x358 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_WORD2_H Message Buffer 5 WORD_32B Register MB_SIZE 0x358 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_CS_H Message Buffer 9 CS Register MB_SIZE 0x358 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write WORD045 Message Buffer 45 WORD0 Register MB_SIZE 0x358 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_ID_H Message Buffer 3 ID Register MB_SIZE 0x35C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB45_8B_WORD1 Message Buffer 45 WORD_8B Register MB_SIZE 0x35C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_WORD3_H Message Buffer 5 WORD_32B Register MB_SIZE 0x35C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_ID_H Message Buffer 9 ID Register MB_SIZE 0x35C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD145 Message Buffer 45 WORD1 Register MB_SIZE 0x35C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS46 Message Buffer 46 CS Register MB_SIZE 0x360 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_64B_WORD0_H Message Buffer 3 WORD_64B Register MB_SIZE 0x360 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB46_8B_CS Message Buffer 46 CS Register MB_SIZE 0x360 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_32B_WORD4_H Message Buffer 5 WORD_32B Register MB_SIZE 0x360 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_WORD0_H Message Buffer 9 WORD_16B Register MB_SIZE 0x360 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write ID46 Message Buffer 46 ID Register MB_SIZE 0x364 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_64B_WORD1_H Message Buffer 3 WORD_64B Register MB_SIZE 0x364 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB46_8B_ID Message Buffer 46 ID Register MB_SIZE 0x364 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_32B_WORD5_H Message Buffer 5 WORD_32B Register MB_SIZE 0x364 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_WORD1_H Message Buffer 9 WORD_16B Register MB_SIZE 0x364 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD2_H Message Buffer 3 WORD_64B Register MB_SIZE 0x368 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB46_8B_WORD0 Message Buffer 46 WORD_8B Register MB_SIZE 0x368 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_WORD6_H Message Buffer 5 WORD_32B Register MB_SIZE 0x368 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_WORD2_H Message Buffer 9 WORD_16B Register MB_SIZE 0x368 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD046 Message Buffer 46 WORD0 Register MB_SIZE 0x368 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD3_H Message Buffer 3 WORD_64B Register MB_SIZE 0x36C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB46_8B_WORD1 Message Buffer 46 WORD_8B Register MB_SIZE 0x36C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_32B_WORD7_H Message Buffer 5 WORD_32B Register MB_SIZE 0x36C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_16B_WORD3_H Message Buffer 9 WORD_16B Register MB_SIZE 0x36C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD146 Message Buffer 46 WORD1 Register MB_SIZE 0x36C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS47 Message Buffer 47 CS Register MB_SIZE 0x370 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB10_16B_CS_H Message Buffer 10 CS Register MB_SIZE 0x370 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_64B_WORD4_H Message Buffer 3 WORD_64B Register MB_SIZE 0x370 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB47_8B_CS Message Buffer 47 CS Register MB_SIZE 0x370 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_32B_CS_H Message Buffer 6 CS Register MB_SIZE 0x370 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID47 Message Buffer 47 ID Register MB_SIZE 0x374 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_16B_ID_H Message Buffer 10 ID Register MB_SIZE 0x374 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_64B_WORD5_H Message Buffer 3 WORD_64B Register MB_SIZE 0x374 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB47_8B_ID Message Buffer 47 ID Register MB_SIZE 0x374 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_32B_ID_H Message Buffer 6 ID Register MB_SIZE 0x374 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_16B_WORD0_H Message Buffer 10 WORD_16B Register MB_SIZE 0x378 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD6_H Message Buffer 3 WORD_64B Register MB_SIZE 0x378 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB47_8B_WORD0 Message Buffer 47 WORD_8B Register MB_SIZE 0x378 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD0_H Message Buffer 6 WORD_32B Register MB_SIZE 0x378 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD047 Message Buffer 47 WORD0 Register MB_SIZE 0x378 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_16B_WORD1_H Message Buffer 10 WORD_16B Register MB_SIZE 0x37C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD7_H Message Buffer 3 WORD_64B Register MB_SIZE 0x37C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB47_8B_WORD1 Message Buffer 47 WORD_8B Register MB_SIZE 0x37C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD1_H Message Buffer 6 WORD_32B Register MB_SIZE 0x37C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD147 Message Buffer 47 WORD1 Register MB_SIZE 0x37C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS48 Message Buffer 48 CS Register MB_SIZE 0x380 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB10_16B_WORD2_H Message Buffer 10 WORD_16B Register MB_SIZE 0x380 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD8_H Message Buffer 3 WORD_64B Register MB_SIZE 0x380 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write MB48_8B_CS Message Buffer 48 CS Register MB_SIZE 0x380 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_32B_WORD2_H Message Buffer 6 WORD_32B Register MB_SIZE 0x380 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write ID48 Message Buffer 48 ID Register MB_SIZE 0x384 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_16B_WORD3_H Message Buffer 10 WORD_16B Register MB_SIZE 0x384 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD9_H Message Buffer 3 WORD_64B Register MB_SIZE 0x384 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB48_8B_ID Message Buffer 48 ID Register MB_SIZE 0x384 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_32B_WORD3_H Message Buffer 6 WORD_32B Register MB_SIZE 0x384 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_16B_CS_H Message Buffer 11 CS Register MB_SIZE 0x388 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB3_64B_WORD10_H Message Buffer 3 WORD_64B Register MB_SIZE 0x388 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write MB48_8B_WORD0 Message Buffer 48 WORD_8B Register MB_SIZE 0x388 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD4_H Message Buffer 6 WORD_32B Register MB_SIZE 0x388 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD048 Message Buffer 48 WORD0 Register MB_SIZE 0x388 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_16B_ID_H Message Buffer 11 ID Register MB_SIZE 0x38C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB3_64B_WORD11_H Message Buffer 3 WORD_64B Register MB_SIZE 0x38C 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB48_8B_WORD1 Message Buffer 48 WORD_8B Register MB_SIZE 0x38C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_32B_WORD5_H Message Buffer 6 WORD_32B Register MB_SIZE 0x38C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD148 Message Buffer 48 WORD1 Register MB_SIZE 0x38C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS49 Message Buffer 49 CS Register MB_SIZE 0x390 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB11_16B_WORD0_H Message Buffer 11 WORD_16B Register MB_SIZE 0x390 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD12_H Message Buffer 3 WORD_64B Register MB_SIZE 0x390 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write MB49_8B_CS Message Buffer 49 CS Register MB_SIZE 0x390 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_32B_WORD6_H Message Buffer 6 WORD_32B Register MB_SIZE 0x390 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write ID49 Message Buffer 49 ID Register MB_SIZE 0x394 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB11_16B_WORD1_H Message Buffer 11 WORD_16B Register MB_SIZE 0x394 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD13_H Message Buffer 3 WORD_64B Register MB_SIZE 0x394 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB49_8B_ID Message Buffer 49 ID Register MB_SIZE 0x394 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_32B_WORD7_H Message Buffer 6 WORD_32B Register MB_SIZE 0x394 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_16B_WORD2_H Message Buffer 11 WORD_16B Register MB_SIZE 0x398 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD14_H Message Buffer 3 WORD_64B Register MB_SIZE 0x398 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write MB49_8B_WORD0 Message Buffer 49 WORD_8B Register MB_SIZE 0x398 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_CS_H Message Buffer 7 CS Register MB_SIZE 0x398 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write WORD049 Message Buffer 49 WORD0 Register MB_SIZE 0x398 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_16B_WORD3_H Message Buffer 11 WORD_16B Register MB_SIZE 0x39C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB3_64B_WORD15_H Message Buffer 3 WORD_64B Register MB_SIZE 0x39C 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB49_8B_WORD1 Message Buffer 49 WORD_8B Register MB_SIZE 0x39C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_ID_H Message Buffer 7 ID Register MB_SIZE 0x39C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD149 Message Buffer 49 WORD1 Register MB_SIZE 0x39C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS50 Message Buffer 50 CS Register MB_SIZE 0x3A0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB12_16B_CS_H Message Buffer 12 CS Register MB_SIZE 0x3A0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_64B_CS_H Message Buffer 4 CS Register MB_SIZE 0x3A0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB50_8B_CS Message Buffer 50 CS Register MB_SIZE 0x3A0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB7_32B_WORD0_H Message Buffer 7 WORD_32B Register MB_SIZE 0x3A0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write ID50 Message Buffer 50 ID Register MB_SIZE 0x3A4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB12_16B_ID_H Message Buffer 12 ID Register MB_SIZE 0x3A4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_64B_ID_H Message Buffer 4 ID Register MB_SIZE 0x3A4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB50_8B_ID Message Buffer 50 ID Register MB_SIZE 0x3A4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB7_32B_WORD1_H Message Buffer 7 WORD_32B Register MB_SIZE 0x3A4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB12_16B_WORD0_H Message Buffer 12 WORD_16B Register MB_SIZE 0x3A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD0_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB50_8B_WORD0 Message Buffer 50 WORD_8B Register MB_SIZE 0x3A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_WORD2_H Message Buffer 7 WORD_32B Register MB_SIZE 0x3A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD050 Message Buffer 50 WORD0 Register MB_SIZE 0x3A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB12_16B_WORD1_H Message Buffer 12 WORD_16B Register MB_SIZE 0x3AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD1_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB50_8B_WORD1 Message Buffer 50 WORD_8B Register MB_SIZE 0x3AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_WORD3_H Message Buffer 7 WORD_32B Register MB_SIZE 0x3AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD150 Message Buffer 50 WORD1 Register MB_SIZE 0x3AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS51 Message Buffer 51 CS Register MB_SIZE 0x3B0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB12_16B_WORD2_H Message Buffer 12 WORD_16B Register MB_SIZE 0x3B0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD2_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3B0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB51_8B_CS Message Buffer 51 CS Register MB_SIZE 0x3B0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB7_32B_WORD4_H Message Buffer 7 WORD_32B Register MB_SIZE 0x3B0 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write ID51 Message Buffer 51 ID Register MB_SIZE 0x3B4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB12_16B_WORD3_H Message Buffer 12 WORD_16B Register MB_SIZE 0x3B4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD3_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3B4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB51_8B_ID Message Buffer 51 ID Register MB_SIZE 0x3B4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB7_32B_WORD5_H Message Buffer 7 WORD_32B Register MB_SIZE 0x3B4 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB13_16B_CS_H Message Buffer 13 CS Register MB_SIZE 0x3B8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_64B_WORD4_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB51_8B_WORD0 Message Buffer 51 WORD_8B Register MB_SIZE 0x3B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_WORD6_H Message Buffer 7 WORD_32B Register MB_SIZE 0x3B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD051 Message Buffer 51 WORD0 Register MB_SIZE 0x3B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB13_16B_ID_H Message Buffer 13 ID Register MB_SIZE 0x3BC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_64B_WORD5_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB51_8B_WORD1 Message Buffer 51 WORD_8B Register MB_SIZE 0x3BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB7_32B_WORD7_H Message Buffer 7 WORD_32B Register MB_SIZE 0x3BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD151 Message Buffer 51 WORD1 Register MB_SIZE 0x3BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS52 Message Buffer 52 CS Register MB_SIZE 0x3C0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB13_16B_WORD0_H Message Buffer 13 WORD_16B Register MB_SIZE 0x3C0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD6_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3C0 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB52_8B_CS Message Buffer 52 CS Register MB_SIZE 0x3C0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB8_32B_CS_H Message Buffer 8 CS Register MB_SIZE 0x3C0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID52 Message Buffer 52 ID Register MB_SIZE 0x3C4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB13_16B_WORD1_H Message Buffer 13 WORD_16B Register MB_SIZE 0x3C4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD7_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3C4 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB52_8B_ID Message Buffer 52 ID Register MB_SIZE 0x3C4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB8_32B_ID_H Message Buffer 8 ID Register MB_SIZE 0x3C4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB13_16B_WORD2_H Message Buffer 13 WORD_16B Register MB_SIZE 0x3C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD8_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write MB52_8B_WORD0 Message Buffer 52 WORD_8B Register MB_SIZE 0x3C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD0_H Message Buffer 8 WORD_32B Register MB_SIZE 0x3C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD052 Message Buffer 52 WORD0 Register MB_SIZE 0x3C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB13_16B_WORD3_H Message Buffer 13 WORD_16B Register MB_SIZE 0x3CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD9_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB52_8B_WORD1 Message Buffer 52 WORD_8B Register MB_SIZE 0x3CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD1_H Message Buffer 8 WORD_32B Register MB_SIZE 0x3CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD152 Message Buffer 52 WORD1 Register MB_SIZE 0x3CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS53 Message Buffer 53 CS Register MB_SIZE 0x3D0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB14_16B_CS_H Message Buffer 14 CS Register MB_SIZE 0x3D0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB4_64B_WORD10_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3D0 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write MB53_8B_CS Message Buffer 53 CS Register MB_SIZE 0x3D0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB8_32B_WORD2_H Message Buffer 8 WORD_32B Register MB_SIZE 0x3D0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write ID53 Message Buffer 53 ID Register MB_SIZE 0x3D4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB14_16B_ID_H Message Buffer 14 ID Register MB_SIZE 0x3D4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB4_64B_WORD11_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3D4 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB53_8B_ID Message Buffer 53 ID Register MB_SIZE 0x3D4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB8_32B_WORD3_H Message Buffer 8 WORD_32B Register MB_SIZE 0x3D4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB14_16B_WORD0_H Message Buffer 14 WORD_16B Register MB_SIZE 0x3D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD12_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write MB53_8B_WORD0 Message Buffer 53 WORD_8B Register MB_SIZE 0x3D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD4_H Message Buffer 8 WORD_32B Register MB_SIZE 0x3D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD053 Message Buffer 53 WORD0 Register MB_SIZE 0x3D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB14_16B_WORD1_H Message Buffer 14 WORD_16B Register MB_SIZE 0x3DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD13_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB53_8B_WORD1 Message Buffer 53 WORD_8B Register MB_SIZE 0x3DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB8_32B_WORD5_H Message Buffer 8 WORD_32B Register MB_SIZE 0x3DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD153 Message Buffer 53 WORD1 Register MB_SIZE 0x3DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS54 Message Buffer 54 CS Register MB_SIZE 0x3E0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB14_16B_WORD2_H Message Buffer 14 WORD_16B Register MB_SIZE 0x3E0 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD14_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3E0 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write MB54_8B_CS Message Buffer 54 CS Register MB_SIZE 0x3E0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB8_32B_WORD6_H Message Buffer 8 WORD_32B Register MB_SIZE 0x3E0 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write ID54 Message Buffer 54 ID Register MB_SIZE 0x3E4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB14_16B_WORD3_H Message Buffer 14 WORD_16B Register MB_SIZE 0x3E4 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB4_64B_WORD15_H Message Buffer 4 WORD_64B Register MB_SIZE 0x3E4 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB54_8B_ID Message Buffer 54 ID Register MB_SIZE 0x3E4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB8_32B_WORD7_H Message Buffer 8 WORD_32B Register MB_SIZE 0x3E4 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB15_16B_CS_H Message Buffer 15 CS Register MB_SIZE 0x3E8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB54_8B_WORD0 Message Buffer 54 WORD_8B Register MB_SIZE 0x3E8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_CS_H Message Buffer 5 CS Register MB_SIZE 0x3E8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB9_32B_CS_H Message Buffer 9 CS Register MB_SIZE 0x3E8 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write WORD054 Message Buffer 54 WORD0 Register MB_SIZE 0x3E8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB15_16B_ID_H Message Buffer 15 ID Register MB_SIZE 0x3EC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB54_8B_WORD1 Message Buffer 54 WORD_8B Register MB_SIZE 0x3EC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_ID_H Message Buffer 5 ID Register MB_SIZE 0x3EC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB9_32B_ID_H Message Buffer 9 ID Register MB_SIZE 0x3EC 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD154 Message Buffer 54 WORD1 Register MB_SIZE 0x3EC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS55 Message Buffer 55 CS Register MB_SIZE 0x3F0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB15_16B_WORD0_H Message Buffer 15 WORD_16B Register MB_SIZE 0x3F0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB55_8B_CS Message Buffer 55 CS Register MB_SIZE 0x3F0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_64B_WORD0_H Message Buffer 5 WORD_64B Register MB_SIZE 0x3F0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD0_H Message Buffer 9 WORD_32B Register MB_SIZE 0x3F0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write ID55 Message Buffer 55 ID Register MB_SIZE 0x3F4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB15_16B_WORD1_H Message Buffer 15 WORD_16B Register MB_SIZE 0x3F4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB55_8B_ID Message Buffer 55 ID Register MB_SIZE 0x3F4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_64B_WORD1_H Message Buffer 5 WORD_64B Register MB_SIZE 0x3F4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD1_H Message Buffer 9 WORD_32B Register MB_SIZE 0x3F4 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB15_16B_WORD2_H Message Buffer 15 WORD_16B Register MB_SIZE 0x3F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB55_8B_WORD0 Message Buffer 55 WORD_8B Register MB_SIZE 0x3F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD2_H Message Buffer 5 WORD_64B Register MB_SIZE 0x3F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD2_H Message Buffer 9 WORD_32B Register MB_SIZE 0x3F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD055 Message Buffer 55 WORD0 Register MB_SIZE 0x3F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB15_16B_WORD3_H Message Buffer 15 WORD_16B Register MB_SIZE 0x3FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB55_8B_WORD1 Message Buffer 55 WORD_8B Register MB_SIZE 0x3FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD3_H Message Buffer 5 WORD_64B Register MB_SIZE 0x3FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD3_H Message Buffer 9 WORD_32B Register MB_SIZE 0x3FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD155 Message Buffer 55 WORD1 Register MB_SIZE 0x3FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS56 Message Buffer 56 CS Register MB_SIZE 0x400 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB16_16B_CS_H Message Buffer 16 CS Register MB_SIZE 0x400 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB56_8B_CS Message Buffer 56 CS Register MB_SIZE 0x400 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_64B_WORD4_H Message Buffer 5 WORD_64B Register MB_SIZE 0x400 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD4_H Message Buffer 9 WORD_32B Register MB_SIZE 0x400 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write ID56 Message Buffer 56 ID Register MB_SIZE 0x404 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB16_16B_ID_H Message Buffer 16 ID Register MB_SIZE 0x404 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB56_8B_ID Message Buffer 56 ID Register MB_SIZE 0x404 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_64B_WORD5_H Message Buffer 5 WORD_64B Register MB_SIZE 0x404 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD5_H Message Buffer 9 WORD_32B Register MB_SIZE 0x404 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB16_16B_WORD0_H Message Buffer 16 WORD_16B Register MB_SIZE 0x408 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB56_8B_WORD0 Message Buffer 56 WORD_8B Register MB_SIZE 0x408 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD6_H Message Buffer 5 WORD_64B Register MB_SIZE 0x408 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD6_H Message Buffer 9 WORD_32B Register MB_SIZE 0x408 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD056 Message Buffer 56 WORD0 Register MB_SIZE 0x408 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB16_16B_WORD1_H Message Buffer 16 WORD_16B Register MB_SIZE 0x40C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB56_8B_WORD1 Message Buffer 56 WORD_8B Register MB_SIZE 0x40C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD7_H Message Buffer 5 WORD_64B Register MB_SIZE 0x40C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB9_32B_WORD7_H Message Buffer 9 WORD_32B Register MB_SIZE 0x40C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD156 Message Buffer 56 WORD1 Register MB_SIZE 0x40C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS57 Message Buffer 57 CS Register MB_SIZE 0x410 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB10_32B_CS_H Message Buffer 10 CS Register MB_SIZE 0x410 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB16_16B_WORD2_H Message Buffer 16 WORD_16B Register MB_SIZE 0x410 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB57_8B_CS Message Buffer 57 CS Register MB_SIZE 0x410 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_64B_WORD8_H Message Buffer 5 WORD_64B Register MB_SIZE 0x410 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write ID57 Message Buffer 57 ID Register MB_SIZE 0x414 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_32B_ID_H Message Buffer 10 ID Register MB_SIZE 0x414 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB16_16B_WORD3_H Message Buffer 16 WORD_16B Register MB_SIZE 0x414 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB57_8B_ID Message Buffer 57 ID Register MB_SIZE 0x414 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_64B_WORD9_H Message Buffer 5 WORD_64B Register MB_SIZE 0x414 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_32B_WORD0_H Message Buffer 10 WORD_32B Register MB_SIZE 0x418 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_CS_H Message Buffer 17 CS Register MB_SIZE 0x418 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB57_8B_WORD0 Message Buffer 57 WORD_8B Register MB_SIZE 0x418 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD10_H Message Buffer 5 WORD_64B Register MB_SIZE 0x418 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD057 Message Buffer 57 WORD0 Register MB_SIZE 0x418 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_32B_WORD1_H Message Buffer 10 WORD_32B Register MB_SIZE 0x41C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_ID_H Message Buffer 17 ID Register MB_SIZE 0x41C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB57_8B_WORD1 Message Buffer 57 WORD_8B Register MB_SIZE 0x41C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD11_H Message Buffer 5 WORD_64B Register MB_SIZE 0x41C 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD157 Message Buffer 57 WORD1 Register MB_SIZE 0x41C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS58 Message Buffer 58 CS Register MB_SIZE 0x420 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB10_32B_WORD2_H Message Buffer 10 WORD_32B Register MB_SIZE 0x420 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_WORD0_H Message Buffer 17 WORD_16B Register MB_SIZE 0x420 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB58_8B_CS Message Buffer 58 CS Register MB_SIZE 0x420 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB5_64B_WORD12_H Message Buffer 5 WORD_64B Register MB_SIZE 0x420 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write ID58 Message Buffer 58 ID Register MB_SIZE 0x424 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_32B_WORD3_H Message Buffer 10 WORD_32B Register MB_SIZE 0x424 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_WORD1_H Message Buffer 17 WORD_16B Register MB_SIZE 0x424 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB58_8B_ID Message Buffer 58 ID Register MB_SIZE 0x424 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB5_64B_WORD13_H Message Buffer 5 WORD_64B Register MB_SIZE 0x424 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_32B_WORD4_H Message Buffer 10 WORD_32B Register MB_SIZE 0x428 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_WORD2_H Message Buffer 17 WORD_16B Register MB_SIZE 0x428 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB58_8B_WORD0 Message Buffer 58 WORD_8B Register MB_SIZE 0x428 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD14_H Message Buffer 5 WORD_64B Register MB_SIZE 0x428 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD058 Message Buffer 58 WORD0 Register MB_SIZE 0x428 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB10_32B_WORD5_H Message Buffer 10 WORD_32B Register MB_SIZE 0x42C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB17_16B_WORD3_H Message Buffer 17 WORD_16B Register MB_SIZE 0x42C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB58_8B_WORD1 Message Buffer 58 WORD_8B Register MB_SIZE 0x42C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB5_64B_WORD15_H Message Buffer 5 WORD_64B Register MB_SIZE 0x42C 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD158 Message Buffer 58 WORD1 Register MB_SIZE 0x42C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS59 Message Buffer 59 CS Register MB_SIZE 0x430 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB10_32B_WORD6_H Message Buffer 10 WORD_32B Register MB_SIZE 0x430 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB18_16B_CS_H Message Buffer 18 CS Register MB_SIZE 0x430 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB59_8B_CS Message Buffer 59 CS Register MB_SIZE 0x430 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_64B_CS_H Message Buffer 6 CS Register MB_SIZE 0x430 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ID59 Message Buffer 59 ID Register MB_SIZE 0x434 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB10_32B_WORD7_H Message Buffer 10 WORD_32B Register MB_SIZE 0x434 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB18_16B_ID_H Message Buffer 18 ID Register MB_SIZE 0x434 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB59_8B_ID Message Buffer 59 ID Register MB_SIZE 0x434 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_64B_ID_H Message Buffer 6 ID Register MB_SIZE 0x434 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB11_32B_CS_H Message Buffer 11 CS Register MB_SIZE 0x438 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB18_16B_WORD0_H Message Buffer 18 WORD_16B Register MB_SIZE 0x438 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB59_8B_WORD0 Message Buffer 59 WORD_8B Register MB_SIZE 0x438 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD0_H Message Buffer 6 WORD_64B Register MB_SIZE 0x438 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD059 Message Buffer 59 WORD0 Register MB_SIZE 0x438 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_32B_ID_H Message Buffer 11 ID Register MB_SIZE 0x43C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB18_16B_WORD1_H Message Buffer 18 WORD_16B Register MB_SIZE 0x43C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB59_8B_WORD1 Message Buffer 59 WORD_8B Register MB_SIZE 0x43C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD1_H Message Buffer 6 WORD_64B Register MB_SIZE 0x43C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD159 Message Buffer 59 WORD1 Register MB_SIZE 0x43C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS60 Message Buffer 60 CS Register MB_SIZE 0x440 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB11_32B_WORD0_H Message Buffer 11 WORD_32B Register MB_SIZE 0x440 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB18_16B_WORD2_H Message Buffer 18 WORD_16B Register MB_SIZE 0x440 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB60_8B_CS Message Buffer 60 CS Register MB_SIZE 0x440 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_64B_WORD2_H Message Buffer 6 WORD_64B Register MB_SIZE 0x440 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write ID60 Message Buffer 60 ID Register MB_SIZE 0x444 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB11_32B_WORD1_H Message Buffer 11 WORD_32B Register MB_SIZE 0x444 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB18_16B_WORD3_H Message Buffer 18 WORD_16B Register MB_SIZE 0x444 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB60_8B_ID Message Buffer 60 ID Register MB_SIZE 0x444 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_64B_WORD3_H Message Buffer 6 WORD_64B Register MB_SIZE 0x444 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_32B_WORD2_H Message Buffer 11 WORD_32B Register MB_SIZE 0x448 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_CS_H Message Buffer 19 CS Register MB_SIZE 0x448 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB60_8B_WORD0 Message Buffer 60 WORD_8B Register MB_SIZE 0x448 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD4_H Message Buffer 6 WORD_64B Register MB_SIZE 0x448 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD060 Message Buffer 60 WORD0 Register MB_SIZE 0x448 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_32B_WORD3_H Message Buffer 11 WORD_32B Register MB_SIZE 0x44C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_ID_H Message Buffer 19 ID Register MB_SIZE 0x44C 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB60_8B_WORD1 Message Buffer 60 WORD_8B Register MB_SIZE 0x44C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD5_H Message Buffer 6 WORD_64B Register MB_SIZE 0x44C 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD160 Message Buffer 60 WORD1 Register MB_SIZE 0x44C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS61 Message Buffer 61 CS Register MB_SIZE 0x450 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB11_32B_WORD4_H Message Buffer 11 WORD_32B Register MB_SIZE 0x450 32 read-write 0 0xFFFFFFFF DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_WORD0_H Message Buffer 19 WORD_16B Register MB_SIZE 0x450 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB61_8B_CS Message Buffer 61 CS Register MB_SIZE 0x450 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_64B_WORD6_H Message Buffer 6 WORD_64B Register MB_SIZE 0x450 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write ID61 Message Buffer 61 ID Register MB_SIZE 0x454 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB11_32B_WORD5_H Message Buffer 11 WORD_32B Register MB_SIZE 0x454 32 read-write 0 0xFFFFFFFF DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_WORD1_H Message Buffer 19 WORD_16B Register MB_SIZE 0x454 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB61_8B_ID Message Buffer 61 ID Register MB_SIZE 0x454 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_64B_WORD7_H Message Buffer 6 WORD_64B Register MB_SIZE 0x454 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_32B_WORD6_H Message Buffer 11 WORD_32B Register MB_SIZE 0x458 32 read-write 0 0xFFFFFFFF DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_WORD2_H Message Buffer 19 WORD_16B Register MB_SIZE 0x458 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB61_8B_WORD0 Message Buffer 61 WORD_8B Register MB_SIZE 0x458 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD8_H Message Buffer 6 WORD_64B Register MB_SIZE 0x458 32 read-write 0 0xFFFFFFFF DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD061 Message Buffer 61 WORD0 Register MB_SIZE 0x458 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB11_32B_WORD7_H Message Buffer 11 WORD_32B Register MB_SIZE 0x45C 32 read-write 0 0xFFFFFFFF DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write MB19_16B_WORD3_H Message Buffer 19 WORD_16B Register MB_SIZE 0x45C 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB61_8B_WORD1 Message Buffer 61 WORD_8B Register MB_SIZE 0x45C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD9_H Message Buffer 6 WORD_64B Register MB_SIZE 0x45C 32 read-write 0 0xFFFFFFFF DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD161 Message Buffer 61 WORD1 Register MB_SIZE 0x45C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS62 Message Buffer 62 CS Register MB_SIZE 0x460 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB20_16B_CS_H Message Buffer 20 CS Register MB_SIZE 0x460 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB62_8B_CS Message Buffer 62 CS Register MB_SIZE 0x460 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_64B_WORD10_H Message Buffer 6 WORD_64B Register MB_SIZE 0x460 32 read-write 0 0xFFFFFFFF DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write ID62 Message Buffer 62 ID Register MB_SIZE 0x464 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB20_16B_ID_H Message Buffer 20 ID Register MB_SIZE 0x464 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB62_8B_ID Message Buffer 62 ID Register MB_SIZE 0x464 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_64B_WORD11_H Message Buffer 6 WORD_64B Register MB_SIZE 0x464 32 read-write 0 0xFFFFFFFF DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write MB20_16B_WORD0_H Message Buffer 20 WORD_16B Register MB_SIZE 0x468 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB62_8B_WORD0 Message Buffer 62 WORD_8B Register MB_SIZE 0x468 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD12_H Message Buffer 6 WORD_64B Register MB_SIZE 0x468 32 read-write 0 0xFFFFFFFF DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD062 Message Buffer 62 WORD0 Register MB_SIZE 0x468 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB20_16B_WORD1_H Message Buffer 20 WORD_16B Register MB_SIZE 0x46C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB62_8B_WORD1 Message Buffer 62 WORD_8B Register MB_SIZE 0x46C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write MB6_64B_WORD13_H Message Buffer 6 WORD_64B Register MB_SIZE 0x46C 32 read-write 0 0xFFFFFFFF DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD162 Message Buffer 62 WORD1 Register MB_SIZE 0x46C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write CS63 Message Buffer 63 CS Register MB_SIZE 0x470 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB20_16B_WORD2_H Message Buffer 20 WORD_16B Register MB_SIZE 0x470 32 read-write 0 0xFFFFFFFF DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write MB63_8B_CS Message Buffer 63 CS Register MB_SIZE 0x470 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write MB6_64B_WORD14_H Message Buffer 6 WORD_64B Register MB_SIZE 0x470 32 read-write 0 0xFFFFFFFF DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write ID63 Message Buffer 63 ID Register MB_SIZE 0x474 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB20_16B_WORD3_H Message Buffer 20 WORD_16B Register MB_SIZE 0x474 32 read-write 0 0xFFFFFFFF DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write MB63_8B_ID Message Buffer 63 ID Register MB_SIZE 0x474 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write MB6_64B_WORD15_H Message Buffer 6 WORD_64B Register MB_SIZE 0x474 32 read-write 0 0xFFFFFFFF DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write MB63_8B_WORD0 Message Buffer 63 WORD_8B Register MB_SIZE 0x478 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD063 Message Buffer 63 WORD0 Register MB_SIZE 0x478 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write MB63_8B_WORD1 Message Buffer 63 WORD_8B Register MB_SIZE 0x47C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write WORD163 Message Buffer 63 WORD1 Register MB_SIZE 0x47C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write 64 0x4 RXIMR[%s] Rx Individual Mask registers 0x880 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write MECR Memory Error Control register 0xAE0 32 read-write 0x800C0080 0xFFFFFFFF NCEFAFRZ Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode 7 1 read-write normal Keep normal operation. 0 freeze Put FlexCAN in Freeze mode (see section "Freeze mode"). 0x1 ECCDIS Error Correction Disable 8 1 read-write ENABLE Enable memory error correction. 0 DISABLE Disable memory error correction. 0x1 RERRDIS Error Report Disable 9 1 read-write ENABLE Enable updates of the error report registers. 0 DISABLE Disable updates of the error report registers. 0x1 EXTERRIE Extended Error Injection Enable 13 1 read-write inject_32_bit Error injection is applied only to the 32-bit word. 0 inject_64_bit Error injection is applied to the 64-bit word. 0x1 FAERRIE FlexCAN Access Error Injection Enable 14 1 read-write DISABLE Injection is disabled. 0 ENABLE Injection is enabled. 0x1 HAERRIE Host Access Error Injection Enable 15 1 read-write DISABLE Injection is disabled. 0 ENABLE Injection is enabled. 0x1 CEI_MSK Correctable Errors Interrupt Mask 16 1 read-write DISABLE Interrupt is disabled. 0 ENABLE Interrupt is enabled. 0x1 FANCEI_MSK FlexCAN Access With Non-Correctable Errors Interrupt Mask 18 1 read-write DISABLE Interrupt is disabled. 0 ENABLE Interrupt is enabled. 0x1 HANCEI_MSK Host Access With Non-Correctable Errors Interrupt Mask 19 1 read-write DISABLE Interrupt is disabled. 0 ENABLE Interrupt is enabled. 0x1 ECRWRDIS Error Configuration Register Write Disable 31 1 read-write ENABLE Write is enabled. 0 DISABLE Write is disabled. 0x1 ERRIAR Error Injection Address register 0xAE4 32 read-write 0 0xFFFFFFFF INJADDR_L Error Injection Address Low 0 2 read-only INJADDR_H Error Injection Address High 2 12 read-write ERRIDPR Error Injection Data Pattern register 0xAE8 32 read-write 0 0xFFFFFFFF DFLIP Data flip pattern 0 32 read-write ERRIPPR Error Injection Parity Pattern register 0xAEC 32 read-write 0 0xFFFFFFFF PFLIP0 Parity Flip Pattern For Byte 0 (Least Significant) 0 5 read-write PFLIP1 Parity Flip Pattern For Byte 1 8 5 read-write PFLIP2 Parity Flip Pattern For Byte 2 16 5 read-write PFLIP3 Parity Flip Pattern For Byte 3 (most significant) 24 5 read-write RERRAR Error Report Address register 0xAF0 32 read-only 0 0xFFFFFFFF ERRADDR Address Where Error Detected 0 14 read-only SAID SAID 16 3 read-only NCE Non-Correctable Error 24 1 read-only correctable Reporting a correctable error 0 non_correctable Reporting a non-correctable error 0x1 RERRDR Error Report Data register 0xAF4 32 read-only 0 0xFFFFFFFF RDATA Raw data word read from memory with error 0 32 read-only RERRSYNR Error Report Syndrome register 0xAF8 32 read-only 0 0xFFFFFFFF SYND0 Error Syndrome For Byte 0 (least significant) 0 5 read-only BE0 Byte Enabled For Byte 0 (least significant) 7 1 read-only not_read The byte was not read. 0 read The byte was read. 0x1 SYND1 Error Syndrome for Byte 1 8 5 read-only BE1 Byte Enabled For Byte 1 15 1 read-only not_read The byte was not read. 0 read The byte was read. 0x1 SYND2 Error Syndrome For Byte 2 16 5 read-only BE2 Byte Enabled For Byte 2 23 1 read-only not_read The byte was not read. 0 read The byte was read. 0x1 SYND3 Error Syndrome For Byte 3 (most significant) 24 5 read-only BE3 Byte Enabled For Byte 3 (most significant) 31 1 read-only not_read The byte was not read. 0 read The byte was read. 0x1 ERRSR Error Status register 0xAFC 32 read-write 0 0xFFFFFFFF oneToClear CEIOF Correctable Error Interrupt Overrun Flag 0 1 read-write oneToClear no_overrun No overrun on correctable errors 0 overrun Overrun on correctable errors 0x1 FANCEIOF FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag 2 1 read-write oneToClear no_overrun No overrun on non-correctable errors in FlexCAN access 0 overrun Overrun on non-correctable errors in FlexCAN access 0x1 HANCEIOF Host Access With Non-Correctable Error Interrupt Overrun Flag 3 1 read-write oneToClear no_overrun No overrun on non-correctable errors in host access 0 overrun Overrun on non-correctable errors in host access 0x1 CEIF Correctable Error Interrupt Flag 16 1 read-write oneToClear no_errors No correctable errors were detected so far. 0 errors A correctable error was detected. 0x1 FANCEIF FlexCAN Access With Non-Correctable Error Interrupt Flag 18 1 read-write oneToClear not_found No non-correctable errors were detected in FlexCAN accesses so far. 0 found A non-correctable error was detected in a FlexCAN access. 0x1 HANCEIF Host Access With Non-Correctable Error Interrupt Flag 19 1 read-write oneToClear not_found No non-correctable errors were detected in host accesses so far. 0 found A non-correctable error was detected in a host access. 0x1 FDCTRL CAN FD Control register 0xC00 32 read-write 0x80000100 0xFFFFFFFF TDCVAL Transceiver Delay Compensation Value 0 6 read-only TDCOFF Transceiver Delay Compensation Offset 8 5 read-write TDCFAIL Transceiver Delay Compensation Fail 14 1 read-write oneToClear in_range Measured loop delay is in range. 0 out_of_range Measured loop delay is out of range. 0x1 TDCEN Transceiver Delay Compensation Enable 15 1 read-write DISABLE TDC is disabled 0 ENABLE TDC is enabled 0x1 MBDSR0 Message Buffer Data Size for Region 0 16 2 read-write R0_8_bytes Selects 8 bytes per message buffer. 0 R0_16_bytes Selects 16 bytes per message buffer. 0x1 R0_32_bytes Selects 32 bytes per message buffer. 0x2 R0_64_bytes Selects 64 bytes per message buffer. 0x3 MBDSR1 Message Buffer Data Size for Region 1 19 2 read-write R1_8_bytes Selects 8 bytes per message buffer. 0 R1_16_bytes Selects 16 bytes per message buffer. 0x1 R1_32_bytes Selects 32 bytes per message buffer. 0x2 R1_64_bytes Selects 64 bytes per message buffer. 0x3 FDRATE Bit Rate Switch Enable 31 1 read-write nominal Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. 0 bit_rate_switching Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. 0x1 FDCBT CAN FD Bit Timing register 0xC04 32 read-write 0 0xFFFFFFFF FPSEG2 Fast Phase Segment 2 0 3 read-write FPSEG1 Fast Phase Segment 1 5 3 read-write FPROPSEG Fast Propagation Segment 10 5 read-write FRJW Fast Resync Jump Width 16 3 read-write FPRESDIV Fast Prescaler Division Factor 20 10 read-write FDCRC CAN FD CRC register 0xC08 32 read-only 0 0xFFFFFFFF FD_TXCRC Extended Transmitted CRC value 0 21 read-only FD_MBCRC CRC Mailbox Number for FD_TXCRC 24 7 read-only CAN2 CAN CAN 0x400C8000 0 0xC0C registers CAN2 46 CAN2_ERROR 47 CAN3 CAN CAN 0x40C3C000 0 0xC0C registers CAN3 48 CAN3_ERROR 49 CAN1_WRAPPER FlexCAN wrapper CAN1 CAN_WRAPPER CAN_WRAPPER 0x400C4000 0 0x9E4 registers GFWR Glitch Filter Width Register 0x9E0 32 read-write 0x7F 0xFFFFFFFF GFWR Glitch Filter Width 0 8 read-write CAN2_WRAPPER FlexCAN wrapper CAN2 CAN_WRAPPER 0x400C8000 0 0x9E4 registers CAN3_WRAPPER FlexCAN wrapper CAN3 CAN_WRAPPER 0x40C3C000 0 0x9E4 registers FLEXSPI1 FlexSPI FLEXSPI FLEXSPI 0x400CC000 0 0x460 registers FLEXSPI1 130 MCR0 Module Control Register 0 0 32 read-write 0xFFFF80C2 0xFFFFFFFF SWRESET Software Reset 0 1 read-write MDIS Module Disable 1 1 read-write RXCLKSRC Sample Clock source selection for Flash Reading 4 2 read-write RXCLKSRC_0 Dummy Read strobe generated by FlexSPI Controller and loopback internally. 0 RXCLKSRC_1 Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. 0x1 RXCLKSRC_3 Flash provided Read strobe and input from DQS pad 0x3 ARDFEN Enable AHB bus Read Access to IP RX FIFO. 6 1 read-write ARDFEN_0 IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. 0 ARDFEN_1 IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. 0x1 ATDFEN Enable AHB bus Write Access to IP TX FIFO. 7 1 read-write ATDFEN_0 IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. 0 ATDFEN_1 IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. 0x1 SERCLKDIV The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking. 8 3 read-write SERCLKDIV_0 Divided by 1 0 SERCLKDIV_1 Divided by 2 0x1 SERCLKDIV_2 Divided by 3 0x2 SERCLKDIV_3 Divided by 4 0x3 SERCLKDIV_4 Divided by 5 0x4 SERCLKDIV_5 Divided by 6 0x5 SERCLKDIV_6 Divided by 7 0x6 SERCLKDIV_7 Divided by 8 0x7 HSEN Half Speed Serial Flash access Enable. 11 1 read-write HSEN_0 Disable divide by 2 of serial flash clock for half speed commands. 0 HSEN_1 Enable divide by 2 of serial flash clock for half speed commands. 0x1 DOZEEN Doze mode enable bit 12 1 read-write DOZEEN_0 Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. 0 DOZEEN_1 Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. 0x1 COMBINATIONEN This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]), when Port A and Port B are of 4 bit data width. 13 1 read-write COMBINATIONEN_0 Disable. 0 COMBINATIONEN_1 Enable. 0x1 SCKFREERUNEN This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). 14 1 read-write SCKFREERUNEN_0 Disable. 0 SCKFREERUNEN_1 Enable. 0x1 IPGRANTWAIT Time out wait cycle for IP command grant. 16 8 read-write AHBGRANTWAIT Timeout wait cycle for AHB command grant. 24 8 read-write MCR1 Module Control Register 1 0x4 32 read-write 0xFFFFFFFF 0xFFFFFFFF AHBBUSWAIT AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response 0 16 read-write SEQWAIT Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles 16 16 read-write MCR2 Module Control Register 2 0x8 32 read-write 0x200081F7 0xFFFFFFFF CLRAHBBUFOPT This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. 11 1 read-write CLRAHBBUFOPT_0 AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. 0 CLRAHBBUFOPT_1 AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. 0x1 SAMEDEVICEEN All external devices are same devices (both in types and size) for A1/A2/B1/B2. 15 1 read-write individual_parallel In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. 0 ENABLE FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. 0x1 SCKBDIFFOPT B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set. 19 1 read-write SCKBDIFFOPT_0 B_SCLK pad is used as port B SCLK clock output. Port B flash access is available. 0 SCKBDIFFOPT_1 B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. 0x1 RESUMEWAIT Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. 24 8 read-write AHBCR AHB Bus Control Register 0xC 32 read-write 0x18 0xFFFFFFFF APAREN Parallel mode enabled for AHB triggered Command (both read and write) . 0 1 read-write individual Flash will be accessed in Individual mode. 0 ENABLE Flash will be accessed in Parallel mode. 0x1 CLRAHBRXBUF Clear the status/pointers of AHB RX Buffer. Auto-cleared. 1 1 read-write CACHABLEEN Enable AHB bus cachable read access support. 3 1 read-write CACHABLEEN_0 Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. 0 CACHABLEEN_1 Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. 0x1 BUFFERABLEEN Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. 4 1 read-write BUFFERABLEEN_0 Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. 0 BUFFERABLEEN_1 Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. 0x1 PREFETCHEN AHB Read Prefetch Enable. 5 1 read-write READADDROPT AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. 6 1 read-write READADDROPT_0 There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable. 0 READADDROPT_1 There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement. 0x1 READSZALIGN AHB Read Size Alignment 10 1 read-write READSZALIGN_0 AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN... 0 READSZALIGN_1 AHB read size to up size to 8 bytes aligned, no prefetching 0x1 ECCEN AHB Read ECC Enable 11 1 read-write ECCEN_0 AHB read ECC check disabled 0 ECCEN_1 AHB read ECC check enabled 0x1 SPLITEN AHB transaction SPLIT 12 1 read-write SPLITEN_0 AHB Split disabled 0 SPLITEN_1 AHB Split enabled 0x1 SPLIT_LIMIT AHB SPLIT SIZE 13 2 read-write SPLIT_LIMIT_0 AHB Split Size=8bytes 0 SPLIT_LIMIT_1 AHB Split Size=16bytes 0x1 SPLIT_LIMIT_2 AHB Split Size=32bytes 0x2 SPLIT_LIMIT_3 AHB Split Size=64bytes 0x3 KEYECCEN OTFAD KEY BLOC ECC Enable 15 1 read-write KEYECCEN_0 AHB KEY ECC check disabled 0 KEYECCEN_1 AHB KEY ECC check enabled 0x1 ECCSINGLEERRCLR AHB ECC Single bit ERR CLR 16 1 read-write ECCMULTIERRCLR AHB ECC Multi bits ERR CLR 17 1 read-write HMSTRIDREMAP AHB Master ID Remapping enable 18 1 read-write ECCSWAPEN ECC Read data swap function 19 1 read-write DISABLE rdata send to ecc check without swap. 0 ENABLE rdata send to ecc ehck with swap. 0x1 ALIGNMENT Decides all AHB read/write boundary. All access cross the boundary will be divided into smaller sub accesses. 20 2 read-write bit0 No limit 0 bit1 1 KBytes 0x1 bit2 512 Bytes 0x2 bit3 256 Bytes 0x3 INTEN Interrupt Enable Register 0x10 32 read-write 0 0xFFFFFFFF IPCMDDONEEN IP triggered Command Sequences Execution finished interrupt enable. 0 1 read-write IPCMDGEEN IP triggered Command Sequences Grant Timeout interrupt enable. 1 1 read-write AHBCMDGEEN AHB triggered Command Sequences Grant Timeout interrupt enable. 2 1 read-write IPCMDERREN IP triggered Command Sequences Error Detected interrupt enable. 3 1 read-write AHBCMDERREN AHB triggered Command Sequences Error Detected interrupt enable. 4 1 read-write IPRXWAEN IP RX FIFO WaterMark available interrupt enable. 5 1 read-write IPTXWEEN IP TX FIFO WaterMark empty interrupt enable. 6 1 read-write SCKSTOPBYRDEN SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. 8 1 read-write SCKSTOPBYWREN SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. 9 1 read-write AHBBUSERROREN AHB Bus error interrupt enable.Refer Interrupts chapter for more details. 10 1 read-write SEQTIMEOUTEN Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. 11 1 read-write KEYDONEEN OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details. 12 1 read-write KEYERROREN OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details. 13 1 read-write ECCMULTIERREN ECC multi bits error interrupt enable.Refer Interrupts chapter for more details. 14 1 read-write ECCSINGLEERREN ECC single bit error interrupt enable.Refer Interrupts chapter for more details. 15 1 read-write IPCMDSECUREVIOEN IP command security violation interrupt enable. 16 1 read-write INTR Interrupt Register 0x14 32 read-write 0 0xFFFFFFFF IPCMDDONE IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated. 0 1 read-write oneToClear IPCMDGE IP triggered Command Sequences Grant Timeout interrupt. 1 1 read-write oneToClear AHBCMDGE AHB triggered Command Sequences Grant Timeout interrupt. 2 1 read-write oneToClear IPCMDERR IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all. 3 1 read-write oneToClear AHBCMDERR AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all. 4 1 read-write oneToClear IPRXWA IP RX FIFO watermark available interrupt. 5 1 read-write oneToClear IPTXWE IP TX FIFO watermark empty interrupt. 6 1 read-write oneToClear SCKSTOPBYRD SCLK is stopped during command sequence because Async RX FIFO full interrupt. 8 1 read-write oneToClear SCKSTOPBYWR SCLK is stopped during command sequence because Async TX FIFO empty interrupt. 9 1 read-write oneToClear AHBBUSERROR AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt. 10 1 read-write oneToClear SEQTIMEOUT Sequence execution timeout interrupt. 11 1 read-write oneToClear KEYDONE OTFAD key blob processing done interrupt. 12 1 read-write oneToClear KEYERROR OTFAD key blob processing error interrupt. 13 1 read-only ECCMULTIERR ECC multi bits error interrupt. 14 1 read-write oneToClear ECCSINGLEERR ECC single bit error interrupt. 15 1 read-write oneToClear IPCMDSECUREVIO IP command security violation interrupt. 16 1 read-write oneToClear LUTKEY LUT Key Register 0x18 32 read-write 0x5AF05AF0 0xFFFFFFFF KEY The Key to lock or unlock LUT. 0 32 read-write LUTCR LUT Control Register 0x1C 32 read-write 0x2 0xFFFFFFFF LOCK Lock LUT 0 1 read-write UNLOCK Unlock LUT 1 1 read-write PROTECT LUT protection 2 1 read-write AHBRXBUF0CR0 AHB RX Buffer 0 Control Register 0 0x20 32 read-write 0x80000040 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 10 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 3 read-write REGIONEN AHB RX Buffer address region funciton enable 30 1 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write AHBRXBUF1CR0 AHB RX Buffer 1 Control Register 0 0x24 32 read-write 0x80010040 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 10 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 3 read-write REGIONEN AHB RX Buffer address region funciton enable 30 1 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write AHBRXBUF2CR0 AHB RX Buffer 2 Control Register 0 0x28 32 read-write 0x80020040 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 10 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 3 read-write REGIONEN AHB RX Buffer address region funciton enable 30 1 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write AHBRXBUF3CR0 AHB RX Buffer 3 Control Register 0 0x2C 32 read-write 0x80030040 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 10 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 3 read-write REGIONEN AHB RX Buffer address region funciton enable 30 1 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write AHBRXBUF4CR0 AHB RX Buffer 4 Control Register 0 0x30 32 read-write 0x80040040 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 10 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 3 read-write REGIONEN AHB RX Buffer address region funciton enable 30 1 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write AHBRXBUF5CR0 AHB RX Buffer 5 Control Register 0 0x34 32 read-write 0x80050040 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 10 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 3 read-write REGIONEN AHB RX Buffer address region funciton enable 30 1 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write AHBRXBUF6CR0 AHB RX Buffer 6 Control Register 0 0x38 32 read-write 0x80060040 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 10 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 3 read-write REGIONEN AHB RX Buffer address region funciton enable 30 1 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write AHBRXBUF7CR0 AHB RX Buffer 7 Control Register 0 0x3C 32 read-write 0x80070040 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 10 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 3 read-write REGIONEN AHB RX Buffer address region funciton enable 30 1 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write FLSHA1CR0 Flash Control Register 0 0x60 32 read-write 0x10000 0xFFFFFFFF FLSHSZ Flash Size in KByte. 0 23 read-write SPLITWREN AHB write access split function control. 30 1 read-write SPLITRDEN AHB read access split function control. 31 1 read-write FLSHA2CR0 Flash Control Register 0 0x64 32 read-write 0x10000 0xFFFFFFFF FLSHSZ Flash Size in KByte. 0 23 read-write SPLITWREN AHB write access split function control. 30 1 read-write SPLITRDEN AHB read access split function control. 31 1 read-write FLSHB1CR0 Flash Control Register 0 0x68 32 read-write 0x10000 0xFFFFFFFF FLSHSZ Flash Size in KByte. 0 23 read-write SPLITWREN AHB write access split function control. 30 1 read-write SPLITRDEN AHB read access split function control. 31 1 read-write FLSHB2CR0 Flash Control Register 0 0x6C 32 read-write 0x10000 0xFFFFFFFF FLSHSZ Flash Size in KByte. 0 23 read-write SPLITWREN AHB write access split function control. 30 1 read-write SPLITRDEN AHB read access split function control. 31 1 read-write 4 0x4 A1,A2,B1,B2 FLSHCR1%s Flash Control Register 1 0x70 32 read-write 0x63 0xFFFFFFFF TCSS Serial Flash CS setup time. 0 5 read-write TCSH Serial Flash CS Hold time. 5 5 read-write WA Word Addressable. 10 1 read-write CAS Column Address Size. 11 4 read-write CSINTERVALUNIT CS interval unit 15 1 read-write CSINTERVALUNIT_0 The CS interval unit is 1 serial clock cycle 0 CSINTERVALUNIT_1 The CS interval unit is 256 serial clock cycle 0x1 CSINTERVAL This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0. 16 16 read-write 4 0x4 A1,A2,B1,B2 FLSHCR2%s Flash Control Register 2 0x80 32 read-write 0 0xFFFFFFFF ARDSEQID Sequence Index for AHB Read triggered Command in LUT. 0 4 read-write ARDSEQNUM Sequence Number for AHB Read triggered Command in LUT. 5 3 read-write AWRSEQID Sequence Index for AHB Write triggered Command. 8 4 read-write AWRSEQNUM Sequence Number for AHB Write triggered Command. 13 3 read-write AWRWAIT For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface 16 12 read-write AWRWAITUNIT AWRWAIT unit 28 3 read-write AWRWAITUNIT_0 The AWRWAIT unit is 2 ahb clock cycle 0 AWRWAITUNIT_1 The AWRWAIT unit is 8 ahb clock cycle 0x1 AWRWAITUNIT_2 The AWRWAIT unit is 32 ahb clock cycle 0x2 AWRWAITUNIT_3 The AWRWAIT unit is 128 ahb clock cycle 0x3 AWRWAITUNIT_4 The AWRWAIT unit is 512 ahb clock cycle 0x4 AWRWAITUNIT_5 The AWRWAIT unit is 2048 ahb clock cycle 0x5 AWRWAITUNIT_6 The AWRWAIT unit is 8192 ahb clock cycle 0x6 AWRWAITUNIT_7 The AWRWAIT unit is 32768 ahb clock cycle 0x7 CLRINSTRPTR Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details. 31 1 read-write FLSHCR4 Flash Control Register 4 0x94 32 read-write 0xC3 0xFFFFFFFF WMOPT1 Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. 0 1 read-write DISABLE DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. 0 ENABLE DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode. 0x1 WMOPT2 Write mask option bit 2. When using AP memory, This option bit could be used to remove AHB write burst minimal length limitation. When using this bit, WMOPT1 should also be set. 1 1 read-write WMOPT2_0 DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst length when flash is accessed in individual mode. 0 WMOPT2_1 DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst length when flash is accessed in individual mode, the minimal write burst length should be 4. 0x1 WMENA Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. 2 1 read-write WMENA_0 Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0 WMENA_1 Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. 0x1 WMENB Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. 3 1 read-write WMENB_0 Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0 WMENB_1 Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. 0x1 PAR_WM Enable APMEM 16 bit write mask function, bit 9 for A1-B1 pair, bit 10 for A2-B2 pair. 9 2 read-write PAR_ADDR_ADJ_DIS Disable the address shift logic for lower density of 16 bit PSRAM. 11 1 read-write IPCR0 IP Control Register 0 0xA0 32 read-write 0 0xFFFFFFFF SFAR Serial Flash Address for IP command. 0 32 read-write IPCR1 IP Control Register 1 0xA4 32 read-write 0 0xFFFFFFFF IDATSZ Flash Read/Program Data Size (in Bytes) for IP command. 0 16 read-write ISEQID Sequence Index in LUT for IP command. 16 4 read-write ISEQNUM Sequence Number for IP command: ISEQNUM+1. 24 3 read-write IPAREN Parallel mode Enabled for IP command. 31 1 read-write DISABLE Flash will be accessed in Individual mode. 0 ENABLE Flash will be accessed in Parallel mode. 0x1 IPCMD IP Command Register 0xB0 32 read-write 0 0xFFFFFFFF TRG Setting this bit will trigger an IP Command. 0 1 read-write IPRXFCR IP RX FIFO Control Register 0xB8 32 read-write 0 0xFFFFFFFF CLRIPRXF Clear all valid data entries in IP RX FIFO. 0 1 read-write RXDMAEN IP RX FIFO reading by DMA enabled. 1 1 read-write RXDMAEN_0 IP RX FIFO would be read by processor. 0 RXDMAEN_1 IP RX FIFO would be read by DMA. 0x1 RXWMRK Watermark level is (RXWMRK+1)*64 Bits. 2 5 read-write IPTXFCR IP TX FIFO Control Register 0xBC 32 read-write 0 0xFFFFFFFF CLRIPTXF Clear all valid data entries in IP TX FIFO. 0 1 read-write TXDMAEN IP TX FIFO filling by DMA enabled. 1 1 read-write TXDMAEN_0 IP TX FIFO would be filled by processor. 0 TXDMAEN_1 IP TX FIFO would be filled by DMA. 0x1 TXWMRK Watermark level is (TXWMRK+1)*64 Bits. 2 5 read-write 2 0x4 A,B DLLCR%s DLL Control Register 0 0xC0 32 read-write 0x100 0xFFFFFFFF DLLEN DLL calibration enable. 0 1 read-write DLLRESET Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation). 1 1 read-write SLVDLYTARGET The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1, OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended. 3 4 read-write OVRDEN Slave clock delay line delay cell number selection override enable. 8 1 read-write OVRDVAL Slave clock delay line delay cell number selection override value. 9 6 read-write MISCCR4 Misc Control Register 4 0xD0 32 read-only 0 0xFFFFFFFF AHBADDRESS AHB bus address that trigger the current ECC multi bits error interrupt. 0 32 read-only MISCCR5 Misc Control Register 5 0xD4 32 read-only 0 0xFFFFFFFF ECCSINGLEERRORCORR ECC single bit error correction indication. 0 32 read-only MISCCR6 Misc Control Register 6 0xD8 32 read-only 0 0xFFFFFFFF VALID ECC single error information Valid 0 1 read-only HIT ECC single error information Hit 1 1 read-only ADDRESS ECC single error address 2 30 read-only MISCCR7 Misc Control Register 7 0xDC 32 read-only 0 0xFFFFFFFF VALID ECC multi error information Valid 0 1 read-only HIT ECC multi error information Hit 1 1 read-only ADDRESS ECC multi error address 2 30 read-only STS0 Status Register 0 0xE0 32 read-only 0x2 0xFFFFFFFF SEQIDLE This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface. 0 1 read-only ARBIDLE This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. 1 1 read-only ARBCMDSRC This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). 2 2 read-only ARBCMDSRC_0 Triggered by AHB read command (triggered by AHB read). 0 ARBCMDSRC_1 Triggered by AHB write command (triggered by AHB Write). 0x1 ARBCMDSRC_2 Triggered by IP command (triggered by setting register bit IPCMD.TRG). 0x2 ARBCMDSRC_3 Triggered by suspended command (resumed). 0x3 STS1 Status Register 1 0xE4 32 read-only 0 0xFFFFFFFF AHBCMDERRID Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). 0 4 read-only AHBCMDERRCODE Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). 8 4 read-only AHBCMDERRCODE_0 No error. 0 AHBCMDERRCODE_2 AHB Write command with JMP_ON_CS instruction used in the sequence. 0x2 AHBCMDERRCODE_3 There is unknown instruction opcode in the sequence. 0x3 AHBCMDERRCODE_4 Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0x4 AHBCMDERRCODE_5 Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0x5 AHBCMDERRCODE_14 Sequence execution timeout. 0xE IPCMDERRID Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). 16 4 read-only IPCMDERRCODE Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). 24 4 read-only IPCMDERRCODE_0 No error. 0 IPCMDERRCODE_2 IP command with JMP_ON_CS instruction used in the sequence. 0x2 IPCMDERRCODE_3 There is unknown instruction opcode in the sequence. 0x3 IPCMDERRCODE_4 Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0x4 IPCMDERRCODE_5 Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0x5 IPCMDERRCODE_6 Flash access start address exceed the whole flash address range (A1/A2/B1/B2). 0x6 IPCMDERRCODE_14 Sequence execution timeout. 0xE IPCMDERRCODE_15 Flash boundary crossed. 0xF STS2 Status Register 2 0xE8 32 read-only 0x1000100 0xFFFFFFFF ASLVLOCK Flash A sample clock slave delay line locked. 0 1 read-only AREFLOCK Flash A sample clock reference delay line locked. 1 1 read-only ASLVSEL Flash A sample clock slave delay line delay cell number selection . 2 6 read-only AREFSEL Flash A sample clock reference delay line delay cell number selection. 8 6 read-only BSLVLOCK Flash B sample clock slave delay line locked. 16 1 read-only BREFLOCK Flash B sample clock reference delay line locked. 17 1 read-only BSLVSEL Flash B sample clock slave delay line delay cell number selection. 18 6 read-only BREFSEL Flash B sample clock reference delay line delay cell number selection. 24 6 read-only AHBSPNDSTS AHB Suspend Status Register 0xEC 32 read-only 0 0xFFFFFFFF ACTIVE Indicates if an AHB read prefetch command sequence has been suspended. 0 1 read-only BUFID AHB RX BUF ID for suspended command sequence. 1 3 read-only DATLFT Left Data size for suspended command sequence (in byte). 16 16 read-only IPRXFSTS IP RX FIFO Status Register 0xF0 32 read-only 0 0xFFFFFFFF FILL Fill level of IP RX FIFO. 0 8 read-only RDCNTR Total Read Data Counter: RDCNTR * 64 Bits. 16 16 read-only IPTXFSTS IP TX FIFO Status Register 0xF4 32 read-only 0 0xFFFFFFFF FILL Fill level of IP TX FIFO. 0 8 read-only WRCNTR Total Write Data Counter: WRCNTR * 64 Bits. 16 16 read-only 32 0x4 RFDR[%s] IP RX FIFO Data Register x 0x100 32 read-only 0 0xFFFFFFFF RXDATA RX Data 0 32 read-only 32 0x4 TFDR[%s] IP TX FIFO Data Register x 0x180 32 write-only 0 0xFFFFFFFF TXDATA TX Data 0 32 write-only 64 0x4 LUT[%s] LUT x 0x200 32 read-write 0 0 OPERAND0 OPERAND0 0 8 read-write NUM_PADS0 NUM_PADS0 8 2 read-write OPCODE0 OPCODE 10 6 read-write OPERAND1 OPERAND1 16 8 read-write NUM_PADS1 NUM_PADS1 24 2 read-write OPCODE1 OPCODE1 26 6 read-write HMSTR0CR AHB Master ID 0 Control Register 0x400 32 read-write 0x40FFCF 0xFFFFFFFF MASK Mask bits for AHB master ID. 0 16 read-write DISABLE Mask 0 ENABLE Unmask 0x1 MSTRID This is expected Master ID. 16 16 read-write HMSTR1CR AHB Master ID 1 Control Register 0x404 32 read-write 0xFFCF 0xFFFFFFFF MASK Mask bits for AHB master ID. 0 16 read-write DISABLE Mask 0 ENABLE Unmask 0x1 MSTRID This is expected Master ID. 16 16 read-write HMSTR2CR AHB Master ID 2 Control Register 0x408 32 read-write 0x4F00F 0xFFFFFFFF MASK Mask bits for AHB master ID. 0 16 read-write DISABLE Mask 0 ENABLE Unmask 0x1 MSTRID This is expected Master ID. 16 16 read-write HMSTR3CR AHB Master ID 3 Control Register 0x40C 32 read-write 0x22807F 0xFFFFFFFF MASK Mask bits for AHB master ID. 0 16 read-write DISABLE Mask 0 ENABLE Unmask 0x1 MSTRID This is expected Master ID. 16 16 read-write HMSTR4CR AHB Master ID 4 Control Register 0x410 32 read-write 0x32F87F 0xFFFFFFFF MASK Mask bits for AHB master ID. 0 16 read-write DISABLE Mask 0 ENABLE Unmask 0x1 MSTRID This is expected Master ID. 16 16 read-write HMSTR5CR AHB Master ID 5 Control Register 0x414 32 read-write 0x11F87F 0xFFFFFFFF MASK Mask bits for AHB master ID. 0 16 read-write DISABLE Mask 0 ENABLE Unmask 0x1 MSTRID This is expected Master ID. 16 16 read-write HMSTR6CR AHB Master ID 6 Control Register 0x418 32 read-write 0 0xFFFFFFFF MASK Mask bits for AHB master ID. 0 16 read-write DISABLE Mask 0 ENABLE Unmask 0x1 MSTRID This is expected Master ID. 16 16 read-write HMSTR7CR AHB Master ID 7 Control Register 0x41C 32 read-write 0 0xFFFFFFFF MASK Mask bits for AHB master ID. 0 16 read-write DISABLE Mask 0 ENABLE Unmask 0x1 MSTRID This is expected Master ID. 16 16 read-write HADDRSTART HADDR REMAP START ADDR 0x420 32 read-write 0 0xFFFFFFFF REMAPEN AHB Bus address remap function enable 0 1 read-write REMAPEN_0 HADDR REMAP Disabled 0 REMAPEN_1 HADDR REMAP Enabled 0x1 KBINECC OTFAD Keyblob is in ECC region and need to be remapped 1 1 read-write KBINECC_0 If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset 0 KBINECC_1 If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset*2 0x1 ADDRSTART HADDR remap range's start addr, 4K aligned When ADDRSTART setting is same as ASFM_BASE, and OTFAD keyblob function is enabled, keyblob will also be remapped 12 20 read-write HADDREND HADDR REMAP END ADDR 0x424 32 read-write 0 0xFFFFFFFF ENDSTART HADDR remap range's end addr, 4K aligned 12 20 read-write HADDROFFSET HADDR REMAP OFFSET 0x428 32 read-write 0 0xFFFFFFFF ADDROFFSET HADDR offset field, remapped address will be ADDR[31:12]=ADDR_original[31:12]+ADDROFFSET 12 20 read-write IPSNSZSTART0 IPS nonsecure region Start address of region 0 0x430 32 read-write 0 0xFFFFFFFF start_address Start address of region 0. Minimal 4K Bytes aligned. It is flash address. 12 20 read-write IPSNSZEND0 IPS nonsecure region End address of region 0 0x434 32 read-write 0 0xFFFFFFFF end_address End address of region 0. Minimal 4K Bytes aligned. It is flash address. 12 20 read-write IPSNSZSTART1 IPS nonsecure region Start address of region 1 0x438 32 read-write 0 0xFFFFFFFF start_address Start address of region 1. Minimal 4K Bytes aligned. It is flash address. 12 20 read-write IPSNSZEND1 IPS nonsecure region End address of region 1 0x43C 32 read-write 0 0xFFFFFFFF end_address End address of region 1. Minimal 4K Bytes aligned. It is flash address. 12 20 read-write AHBBUFREGIONSTART0 RX BUF Start address of region 0 0x440 32 read-write 0 0xFFFFFFFF start_address Start address of region 0. Minimal 4K Bytes aligned. It is system address. 12 20 read-write AHBBUFREGIONEND0 RX BUF region End address of region 0 0x444 32 read-write 0 0xFFFFFFFF end_address End address of region 0. Minimal 4K Bytes aligned. It is system address. 12 20 read-write AHBBUFREGIONSTART1 RX BUF Start address of region 1 0x448 32 read-write 0 0xFFFFFFFF start_address Start address of region 1. Minimal 4K Bytes aligned. It is system address. 12 20 read-write AHBBUFREGIONEND1 RX BUF region End address of region 1 0x44C 32 read-write 0 0xFFFFFFFF end_address End address of region 1. Minimal 4K Bytes aligned. It is system address. 12 20 read-write AHBBUFREGIONSTART2 RX BUF Start address of region 2 0x450 32 read-write 0 0xFFFFFFFF start_address Start address of region 2. Minimal 4K Bytes aligned. It is system address. 12 20 read-write AHBBUFREGIONEND2 RX BUF region End address of region 2 0x454 32 read-write 0 0xFFFFFFFF end_address End address of region 2. Minimal 4K Bytes aligned. It is system address. 12 20 read-write AHBBUFREGIONSTART3 RX BUF Start address of region 3 0x458 32 read-write 0 0xFFFFFFFF start_address Start address of region 3. Minimal 4K Bytes aligned. It is system address. 12 20 read-write AHBBUFREGIONEND3 RX BUF region End address of region 3 0x45C 32 read-write 0 0xFFFFFFFF end_address End address of region 3. Minimal 4K Bytes aligned. It is system address. 12 20 read-write FLEXSPI2 FlexSPI FLEXSPI 0x400D0000 0 0x460 registers FLEXSPI2 131 OTFAD1 OTFAD FLEXSPI1 OTFAD OTFAD 0x400CC000 0 0xDE0 registers CR Control Register 0xC00 32 read-write 0 0xFFFFFFFF FERR Force Error 1 1 read-write FERR_0 No effect on the SR[KBERE] indicator. 0 FERR_1 SR[KBERR] is immediately set after a write with this data bit set. 0x1 FLDM Force Logically Disabled Mode 3 1 read-write FLDM_0 No effect on the operating mode. 0 FLDM_1 Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode. 0x1 KBSE Key Blob Scramble Enable 4 1 read-write KBSE_0 Key blob KEK scrambling is disabled. 0 KBSE_1 Key blob KEK scrambling is enabled. 0x1 KBPE Key Blob Processing Enable 5 1 read-write KBPE_0 Key blob processing is disabled. 0 KBPE_1 Key blob processing is enabled. 0x1 RRAE Restricted Register Access Enable 7 1 read-write RRAE_0 Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". 0 RRAE_1 Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI. 0x1 SKBP Start key blob processing 30 1 read-write SKBP_0 Key blob processing is not initiated. 0 SKBP_1 Properly-enabled key blob processing is initiated. 0x1 GE Global OTFAD Enable 31 1 read-write GE_0 OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing. 0 GE_1 OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration. 0x1 SR Status Register 0xC04 32 read-write 0x40 0xFFFFFFFF KBERR Key Blob Error 0 1 read-write oneToClear KBERR_0 No key blob error detected. 0 KBERR_1 One or more key blob errors has been detected. 0x1 MDPCP MDPC Present 1 1 read-only MODE Operating Mode 2 2 read-only MODE_0 Operating in Normal mode (NRM) 0 MODE_1 Unused (reserved) 0x1 MODE_2 Unused (reserved) 0x2 MODE_3 Operating in Logically Disabled Mode (LDM) 0x3 NCTX Number of Contexts 4 4 read-only CTXER0 Context Error 8 1 read-only NOERROR No key blob error was detected for context "n". 0 ERROR A key blob integrity error might have been detected in context "n". 0x1 CTXER1 Context Error 9 1 read-only NOERROR No key blob error was detected for context "n". 0 ERROR A key blob integrity error might have been detected in context "n". 0x1 CTXER2 Context Error 10 1 read-only NOERROR No key blob error was detected for context "n". 0 ERROR A key blob integrity error might have been detected in context "n". 0x1 CTXER3 Context Error 11 1 read-only NOERROR No key blob error was detected for context "n". 0 ERROR A key blob integrity error might have been detected in context "n". 0x1 CTXIE0 Context Integrity Error 16 1 read-only NOINTEGRITYERR No key blob integrity error was detected for context "n". 0 INTEGRITYERR A key blob integrity error was detected in context "n". 0x1 CTXIE1 Context Integrity Error 17 1 read-only NOINTEGRITYERR No key blob integrity error was detected for context "n". 0 INTEGRITYERR A key blob integrity error was detected in context "n". 0x1 CTXIE2 Context Integrity Error 18 1 read-only NOINTEGRITYERR No key blob integrity error was detected for context "n". 0 INTEGRITYERR A key blob integrity error was detected in context "n". 0x1 CTXIE3 Context Integrity Error 19 1 read-only NOINTEGRITYERR No key blob integrity error was detected for context "n". 0 INTEGRITYERR A key blob integrity error was detected in context "n". 0x1 HRL Hardware Revision Level 24 4 read-only RRAM Restricted Register Access Mode 28 1 read-only RRAM_0 Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". 0 RRAM_1 Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI. 0x1 GEM Global Enable Mode 29 1 read-only GEM_0 OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing. 0 GEM_1 OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration. 0x1 KBPE Key Blob Processing Enable 30 1 read-only KBPE_0 Key blob processing is not enabled. 0 KBPE_1 Key blob processing is enabled. 0x1 KBD Key Blob Processing Done 31 1 read-only KBD_0 Key blob processing was not enabled, or is not complete. 0 KBD_1 Key blob processing was enabled and is complete. 0x1 4 0x40 CTX[%s] no description available 0xD00 4 0x4 0,1,2,3 CTX_KEY%s AES Key Word 0 32 read-write 0 0xFFFFFFFF KEY AES Key 0 32 read-write 2 0x4 0,1 CTX_CTR%s AES Counter Word 0x10 32 read-write 0 0xFFFFFFFF CTR AES Counter 0 32 read-write CTX_RGD_W0 AES Region Descriptor Word0 0x18 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 10 22 read-write CTX_RGD_W1 AES Region Descriptor Word1 0x1C 32 read-write 0x3F8 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 Context is invalid. 0 VLD_1 Context is valid. 0x1 ADE AES Decryption Enable. 1 1 read-write ADE_0 Bypass the fetched data. 0 ADE_1 Perform the CTR-AES128 mode decryption on the fetched data. 0x1 RO Read-Only 2 1 read-write RO_0 The context registers can be accessed normally (as defined by SR[RRAM]). 0 RO_1 The context registers are read-only and accesses may be further restricted based on SR[RRAM]. 0x1 ENDADDR End Address 10 22 read-write OTFAD2 OTFAD FLEXSPI2 OTFAD 0x400D0000 0 0xDE0 registers SEMC SEMC SEMC 0x400D4000 0 0x154 registers SEMC 132 MCR Module Control Register 0 32 read-write 0x10000002 0xFFFFFFFF SWRST Software Reset 0 1 read-write SWRST_0 No reset 0 SWRST_1 Reset 0x1 MDIS Module Disable 1 1 read-write MDIS_0 Module enabled 0 MDIS_1 Module disabled 0x1 DQSMD DQS (read strobe) mode 2 1 read-write DQSMD_0 Dummy read strobe loopbacked internally 0 DQSMD_1 Dummy read strobe loopbacked from DQS pad 0x1 WPOL0 WAIT/RDY polarity for SRAM/NOR 6 1 read-write WPOL0_0 WAIT/RDY polarity is not changed. 0 WPOL0_1 WAIT/RDY polarity is inverted. 0x1 WPOL1 R/B# polarity for NAND device 7 1 read-write WPOL1_0 R/B# polarity is not changed. 0 WPOL1_1 R/B# polarity is inverted. 0x1 CTO Command Execution timeout cycles 16 8 read-write BTO Bus timeout cycles 24 5 read-write BTO_0 255*1 0 BTO_1 255*2 0x1 BTO_31 255*231 0x1F IOCR IO MUX Control Register 0x4 32 read-write 0 0xFFFFFFFF MUX_A8 SEMC_ADDR08 output selection 0 4 read-write MUX_A8_0 SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode 0 MUX_A8_1 SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode 0x1 MUX_A8_2 SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode 0x2 MUX_A8_3 SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode 0x3 MUX_A8_4 NAND CE# 0x4 MUX_A8_5 NOR CE# 0x5 MUX_A8_6 SRAM CE# 0 0x6 MUX_A8_7 DBI CSX 0x7 MUX_A8_8 SRAM CE# 1 0x8 MUX_A8_9 SRAM CE# 2 0x9 MUX_A8_10 SRAM CE# 3 0xA MUX_A8_11 SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode 0xB MUX_A8_12 SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode 0xC MUX_A8_13 SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode 0xD MUX_A8_14 SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode 0xE MUX_A8_15 SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode 0xF MUX_CSX0 SEMC_CSX0 output selection 4 4 read-write MUX_CSX0_0 NOR/SRAM Address bit 24 (A24) in Non-ADMUX mode 0 MUX_CSX0_1 SDRAM CS1 0x1 MUX_CSX0_2 SDRAM CS2 0x2 MUX_CSX0_3 SDRAM CS3 0x3 MUX_CSX0_4 NAND CE# 0x4 MUX_CSX0_5 NOR CE# 0x5 MUX_CSX0_6 SRAM CE# 0 0x6 MUX_CSX0_7 DBI CSX 0x7 MUX_CSX0_8 SRAM CE# 1 0x8 MUX_CSX0_9 SRAM CE# 2 0x9 MUX_CSX0_10 SRAM CE# 3 0xA MUX_CSX0_11 NOR/SRAM Address bit 24 (A24) 0xB MUX_CSX0_12 NOR/SRAM Address bit 24 (A24) 0xC MUX_CSX0_13 NOR/SRAM Address bit 24 (A24) 0xD MUX_CSX0_14 NOR/SRAM Address bit 24 (A24) 0xE MUX_CSX0_15 NOR/SRAM Address bit 24 (A24) 0xF MUX_CSX1 SEMC_CSX1 output selection 8 4 read-write MUX_CSX1_0 NOR/SRAM Address bit 25 (A25) in Non-ADMUX mode 0 MUX_CSX1_1 SDRAM CS1 0x1 MUX_CSX1_2 SDRAM CS2 0x2 MUX_CSX1_3 SDRAM CS3 0x3 MUX_CSX1_4 NAND CE# 0x4 MUX_CSX1_5 NOR CE# 0x5 MUX_CSX1_6 SRAM CE# 0 0x6 MUX_CSX1_7 DBI CSX 0x7 MUX_CSX1_8 SRAM CE# 1 0x8 MUX_CSX1_9 SRAM CE# 2 0x9 MUX_CSX1_10 SRAM CE# 3 0xA MUX_CSX1_11 NOR/SRAM Address bit 25 (A25) 0xB MUX_CSX1_12 NOR/SRAM Address bit 25 (A25) 0xC MUX_CSX1_13 NOR/SRAM Address bit 25 (A25) 0xD MUX_CSX1_14 NOR/SRAM Address bit 25 (A25) 0xE MUX_CSX1_15 NOR/SRAM Address bit 25 (A25) 0xF MUX_CSX2 SEMC_CSX2 output selection 12 4 read-write MUX_CSX2_0 NOR/SRAM Address bit 26 (A26) in Non-ADMUX mode 0 MUX_CSX2_1 SDRAM CS1 0x1 MUX_CSX2_2 SDRAM CS2 0x2 MUX_CSX2_3 SDRAM CS3 0x3 MUX_CSX2_4 NAND CE# 0x4 MUX_CSX2_5 NOR CE# 0x5 MUX_CSX2_6 SRAM CE# 0 0x6 MUX_CSX2_7 DBI CSX 0x7 MUX_CSX2_8 SRAM CE# 1 0x8 MUX_CSX2_9 SRAM CE# 2 0x9 MUX_CSX2_10 SRAM CE# 3 0xA MUX_CSX2_11 NOR/SRAM Address bit 26 (A26) 0xB MUX_CSX2_12 NOR/SRAM Address bit 26 (A26) 0xC MUX_CSX2_13 NOR/SRAM Address bit 26 (A26) 0xD MUX_CSX2_14 NOR/SRAM Address bit 26 (A26) 0xE MUX_CSX2_15 NOR/SRAM Address bit 26 (A26) 0xF MUX_CSX3 SEMC_CSX3 output selection 16 4 read-write MUX_CSX3_0 NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode 0 MUX_CSX3_1 SDRAM CS1 0x1 MUX_CSX3_2 SDRAM CS2 0x2 MUX_CSX3_3 SDRAM CS3 0x3 MUX_CSX3_4 NAND CE# 0x4 MUX_CSX3_5 NOR CE# 0x5 MUX_CSX3_6 SRAM CE# 0 0x6 MUX_CSX3_7 DBI CSX 0x7 MUX_CSX3_8 SRAM CE# 1 0x8 MUX_CSX3_9 SRAM CE# 2 0x9 MUX_CSX3_10 SRAM CE# 3 0xA MUX_CSX3_11 NOR/SRAM Address bit 27 (A27) 0xB MUX_CSX3_12 NOR/SRAM Address bit 27 (A27) 0xC MUX_CSX3_13 NOR/SRAM Address bit 27 (A27) 0xD MUX_CSX3_14 NOR/SRAM Address bit 27 (A27) 0xE MUX_CSX3_15 NOR/SRAM Address bit 27 (A27) 0xF MUX_RDY SEMC_RDY function selection 20 4 read-write MUX_RDY_0 NAND R/B# input 0 MUX_RDY_1 SDRAM CS1 0x1 MUX_RDY_2 SDRAM CS2 0x2 MUX_RDY_3 SDRAM CS3 0x3 MUX_RDY_4 NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode 0x4 MUX_RDY_5 NOR CE# 0x5 MUX_RDY_6 SRAM CE# 0 0x6 MUX_RDY_7 DBI CSX 0x7 MUX_RDY_8 SRAM CE# 1 0x8 MUX_RDY_9 SRAM CE# 2 0x9 MUX_RDY_10 SRAM CE# 3 0xA MUX_RDY_11 NOR/SRAM Address bit 27 0xB MUX_RDY_12 NOR/SRAM Address bit 27 0xC MUX_RDY_13 NOR/SRAM Address bit 27 0xD MUX_RDY_14 NOR/SRAM Address bit 27 0xE MUX_RDY_15 NOR/SRAM Address bit 27 0xF MUX_CLKX0 SEMC_CLKX0 function selection 24 2 read-write MUX_CLKX0_0 Keep low 0 MUX_CLKX0_1 NOR clock 0x1 MUX_CLKX0_2 SRAM clock 0x2 MUX_CLKX0_3 NOR and SRAM clock, suitable for Multi-Chip Product package 0x3 MUX_CLKX1 SEMC_CLKX1 function selection 26 2 read-write MUX_CLKX1_0 Keep low 0 MUX_CLKX1_1 NOR clock 0x1 MUX_CLKX1_2 SRAM clock 0x2 MUX_CLKX1_3 NOR and SRAM clock, suitable for Multi-Chip Product package 0x3 CLKX0_AO SEMC_CLKX0 Always On 28 1 read-write CLKX0_AO_0 SEMC_CLKX0 is controlled by MUX_CLKX0 0 CLKX0_AO_1 SEMC_CLKX0 is always on 0x1 CLKX1_AO SEMC_CLKX1 Always On 29 1 read-write CLKX1_AO_0 SEMC_CLKX1 is controlled by MUX_CLKX1 0 CLKX1_AO_1 SEMC_CLKX1 is always on 0x1 BMCR0 Bus (AXI) Master Control Register 0 0x8 32 read-write 0 0xFFFFFFFF WQOS Weight of QOS 0 4 read-write WAGE Weight of AGE 4 4 read-write WSH Weight of Slave Hit without read/write switch 8 8 read-write WRWS Weight of slave hit with Read/Write Switch 16 8 read-write BMCR1 Bus (AXI) Master Control Register 1 0xC 32 read-write 0 0xFFFFFFFF WQOS Weight of QOS 0 4 read-write WAGE Weight of AGE 4 4 read-write WPH Weight of Page Hit 8 8 read-write WRWS Weight of slave hit without Read/Write Switch 16 8 read-write WBR Weight of Bank Rotation 24 8 read-write 9 0x4 BR[%s] Base Register n 0x10 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 The memory is invalid, can not be accessed. 0 VLD_1 The memory is valid, can be accessed. 0x1 MS Memory size 1 5 read-write MS_0 4KB 0 MS_1 8KB 0x1 MS_2 16KB 0x2 MS_3 32KB 0x3 MS_4 64KB 0x4 MS_5 128KB 0x5 MS_6 256KB 0x6 MS_7 512KB 0x7 MS_8 1MB 0x8 MS_9 2MB 0x9 MS_10 4MB 0xA MS_11 8MB 0xB MS_12 16MB 0xC MS_13 32MB 0xD MS_14 64MB 0xE MS_15 128MB 0xF MS_16 256MB 0x10 MS_17 512MB 0x11 MS_18 1GB 0x12 MS_19 2GB 0x13 MS_20 4GB 0x14 MS_21 4GB 0x15 MS_22 4GB 0x16 MS_23 4GB 0x17 MS_24 4GB 0x18 MS_25 4GB 0x19 MS_26 4GB 0x1A MS_27 4GB 0x1B MS_28 4GB 0x1C MS_29 4GB 0x1D MS_30 4GB 0x1E MS_31 4GB 0x1F BA Base Address 12 20 read-write DLLCR DLL Control Register 0x34 32 read-write 0x100 0xFFFFFFFF DLLEN DLL calibration enable 0 1 read-write DLLEN_0 DLL calibration is disabled. 0 DLLEN_1 DLL calibration is enabled. 0x1 DLLRESET DLL Reset 1 1 read-write DLLRESET_0 DLL is not reset. 0 DLLRESET_1 DLL is reset. 0x1 SLVDLYTARGET Delay Target for Slave 3 4 read-write OVRDEN Override Enable 8 1 read-write OVRDEN_0 The delay cell number is not overridden. 0 OVRDEN_1 The delay cell number is overridden. 0x1 OVRDVAL Override Value 9 6 read-write INTEN Interrupt Enable Register 0x38 32 read-write 0 0xFFFFFFFF IPCMDDONEEN IP command done interrupt enable 0 1 read-write IPCMDDONEEN_0 Interrupt is disabled 0 IPCMDDONEEN_1 Interrupt is enabled 0x1 IPCMDERREN IP command error interrupt enable 1 1 read-write IPCMDERREN_0 Interrupt is disabled 0 IPCMDERREN_1 Interrupt is enabled 0x1 AXICMDERREN AXI command error interrupt enable 2 1 read-write AXICMDERREN_0 Interrupt is disabled 0 AXICMDERREN_1 Interrupt is enabled 0x1 AXIBUSERREN AXI bus error interrupt enable 3 1 read-write AXIBUSERREN_0 Interrupt is disabled 0 AXIBUSERREN_1 Interrupt is enabled 0x1 NDPAGEENDEN NAND page end interrupt enable 4 1 read-write NDPAGEENDEN_0 Interrupt is disabled 0 NDPAGEENDEN_1 Interrupt is enabled 0x1 NDNOPENDEN NAND no pending AXI access interrupt enable 5 1 read-write NDNOPENDEN_0 Interrupt is disabled 0 NDNOPENDEN_1 Interrupt is enabled 0x1 INTR Interrupt Register 0x3C 32 read-write 0 0xFFFFFFFF oneToClear IPCMDDONE IP command normal done interrupt 0 1 read-write oneToClear IPCMDDONE_0 IP command is not done. 0 IPCMDDONE_1 IP command is done. 0x1 IPCMDERR IP command error done interrupt 1 1 read-write oneToClear IPCMDERR_0 No IP command error. 0 IPCMDERR_1 IP command error occurs. 0x1 AXICMDERR AXI command error interrupt 2 1 read-write oneToClear AXICMDERR_0 No AXI command error. 0 AXICMDERR_1 AXI command error occurs. 0x1 AXIBUSERR AXI bus error interrupt 3 1 read-write oneToClear AXIBUSERR_0 No AXI bus error. 0 AXIBUSERR_1 AXI bus error occurs. 0x1 NDPAGEEND NAND page end interrupt 4 1 read-write oneToClear NDPAGEEND_0 The last address of main space in the NAND is not written by AXI command. 0 NDPAGEEND_1 The last address of main space in the NAND is written by AXI command. 0x1 NDNOPEND NAND no pending AXI write transaction interrupt 5 1 read-write oneToClear NDNOPEND_0 At least one NAND AXI write transaction is pending or no NAND write transaction is sent to the queue. 0 NDNOPEND_1 All NAND AXI write pending transactions are finished. 0x1 SDRAMCR0 SDRAM Control Register 0 0x40 32 read-write 0xC26 0xFFFFFFFF PS Port Size 0 2 read-write PS_0 8bit 0 PS_1 16bit 0x1 PS_2 32bit 0x2 BL Burst Length 4 3 read-write BL_0 1 0 BL_1 2 0x1 BL_2 4 0x2 BL_3 8 0x3 BL_4 8 0x4 BL_5 8 0x5 BL_6 8 0x6 BL_7 8 0x7 COL8 Column 8 selection 7 1 read-write COL8_0 Column address bit number is decided by COL field. 0 COL8_1 Column address bit number is 8. COL field is ignored. 0x1 COL Column address bit number 8 2 read-write COL_0 12 0 COL_1 11 0x1 COL_2 10 0x2 COL_3 9 0x3 CL CAS Latency 10 2 read-write CL_0 1 0 CL_1 1 0x1 CL_2 2 0x2 CL_3 3 0x3 BANK2 2 Bank selection bit 14 1 read-write BANK2_0 SDRAM device has 4 banks. 0 BANK2_1 SDRAM device has 2 banks. 0x1 SDRAMCR1 SDRAM Control Register 1 0x44 32 read-write 0x994934 0xFFFFFFFF PRE2ACT PRECHARGE to ACTIVE/REFRESH command wait time 0 4 read-write ACT2RW ACTIVE to READ/WRITE delay 4 4 read-write RFRC REFRESH recovery time 8 5 read-write WRC WRITE recovery time 13 3 read-write CKEOFF CKE off minimum time 16 4 read-write ACT2PRE ACTIVE to PRECHARGE minimum time 20 4 read-write SDRAMCR2 SDRAM Control Register 2 0x48 32 read-write 0x80000EEE 0xFFFFFFFF SRRC SELF REFRESH recovery time 0 8 read-write REF2REF REFRESH to REFRESH delay 8 8 read-write ACT2ACT ACTIVE to ACTIVE delay 16 8 read-write ITO SDRAM idle timeout 24 8 read-write ITO_0 IDLE timeout period is 256*Prescale period. 0 ITO_1 IDLE timeout period is ITO*Prescale period. 0x1 ITO_2 IDLE timeout period is ITO*Prescale period. 0x2 ITO_3 IDLE timeout period is ITO*Prescale period. 0x3 ITO_4 IDLE timeout period is ITO*Prescale period. 0x4 ITO_5 IDLE timeout period is ITO*Prescale period. 0x5 ITO_6 IDLE timeout period is ITO*Prescale period. 0x6 ITO_7 IDLE timeout period is ITO*Prescale period. 0x7 ITO_8 IDLE timeout period is ITO*Prescale period. 0x8 ITO_9 IDLE timeout period is ITO*Prescale period. 0x9 SDRAMCR3 SDRAM Control Register 3 0x4C 32 read-write 0x40808000 0xFFFFFFFF REN Refresh enable 0 1 read-write REN_0 The SEMC does not send AUTO REFRESH command automatically 0 REN_1 The SEMC sends AUTO REFRESH command automatically 0x1 REBL Refresh burst length 1 3 read-write REBL_0 1 0 REBL_1 2 0x1 REBL_2 3 0x2 REBL_3 4 0x3 REBL_4 5 0x4 REBL_5 6 0x5 REBL_6 7 0x6 REBL_7 8 0x7 PRESCALE Prescaler period 8 8 read-write PRESCALE_0 (256*16+1) clock cycles 0 PRESCALE_1 (PRESCALE*16+1) clock cycles 0x1 PRESCALE_2 (PRESCALE*16+1) clock cycles 0x2 PRESCALE_3 (PRESCALE*16+1) clock cycles 0x3 PRESCALE_4 (PRESCALE*16+1) clock cycles 0x4 PRESCALE_5 (PRESCALE*16+1) clock cycles 0x5 PRESCALE_6 (PRESCALE*16+1) clock cycles 0x6 PRESCALE_7 (PRESCALE*16+1) clock cycles 0x7 PRESCALE_8 (PRESCALE*16+1) clock cycles 0x8 PRESCALE_9 (PRESCALE*16+1) clock cycles 0x9 RT Refresh timer period 16 8 read-write RT_0 (256+1)*(Prescaler period) 0 RT_1 (RT+1)*(Prescaler period) 0x1 RT_2 (RT+1)*(Prescaler period) 0x2 RT_3 (RT+1)*(Prescaler period) 0x3 RT_4 (RT+1)*(Prescaler period) 0x4 RT_5 (RT+1)*(Prescaler period) 0x5 RT_6 (RT+1)*(Prescaler period) 0x6 RT_7 (RT+1)*(Prescaler period) 0x7 RT_8 (RT+1)*(Prescaler period) 0x8 RT_9 (RT+1)*(Prescaler period) 0x9 UT Urgent refresh threshold 24 8 read-write UT_0 256*(Prescaler period) 0 UT_1 UT*(Prescaler period) 0x1 UT_2 UT*(Prescaler period) 0x2 UT_3 UT*(Prescaler period) 0x3 UT_4 UT*(Prescaler period) 0x4 UT_5 UT*(Prescaler period) 0x5 UT_6 UT*(Prescaler period) 0x6 UT_7 UT*(Prescaler period) 0x7 UT_8 UT*(Prescaler period) 0x8 UT_9 UT*(Prescaler period) 0x9 NANDCR0 NAND Control Register 0 0x50 32 read-write 0 0xFFFFFFFF PS Port Size 0 1 read-write PS_0 8bit 0 PS_1 16bit 0x1 SYNCEN Synchronous Mode Enable 1 1 read-write SYNCEN_0 Asynchronous mode is enabled. 0 SYNCEN_1 Synchronous mode is enabled. 0x1 BL Burst Length 4 3 read-write BL_0 1 0 BL_1 2 0x1 BL_2 4 0x2 BL_3 8 0x3 BL_4 16 0x4 BL_5 32 0x5 BL_6 64 0x6 BL_7 64 0x7 EDO EDO mode enabled 7 1 read-write EDO_0 EDO mode disabled 0 EDO_1 EDO mode enabled 0x1 COL Column address bit number 8 3 read-write COL_0 16 0 COL_1 15 0x1 COL_2 14 0x2 COL_3 13 0x3 COL_4 12 0x4 COL_5 11 0x5 COL_6 10 0x6 COL_7 9 0x7 NANDCR1 NAND Control Register 1 0x54 32 read-write 0 0xFFFFFFFF CES CE# setup time 0 4 read-write CEH CE# hold time 4 4 read-write WEL WE# low time 8 4 read-write WEH WE# high time 12 4 read-write REL RE# low time 16 4 read-write REH RE# high time 20 4 read-write TA Turnaround time 24 4 read-write CEITV CE# interval time 28 4 read-write NANDCR2 NAND Control Register 2 0x58 32 read-write 0x10410 0xFFFFFFFF TWHR WE# high to RE# low time 0 6 read-write TRHW RE# high to WE# low time 6 6 read-write TADL Address cycle to data loading time 12 6 read-write TRR Ready to RE# low time 18 6 read-write TWB WE# high to busy time 24 6 read-write NANDCR3 NAND Control Register 3 0x5C 32 read-write 0 0xFFFFFFFF NDOPT1 NAND option bit 1 0 1 read-write NDOPT2 NAND option bit 2 1 1 read-write NDOPT3 NAND option bit 3 2 1 read-write CLE NAND CLE Option 3 1 read-write RDS Read Data Setup time 16 4 read-write RDH Read Data Hold time 20 4 read-write WDS Write Data Setup time 24 4 read-write WDH Write Data Hold time 28 4 read-write NORCR0 NOR Control Register 0 0x60 32 read-write 0 0xFFFFFFFF PS Port Size 0 1 read-write PS_0 8bit 0 PS_1 16bit 0x1 SYNCEN Synchronous Mode Enable 1 1 read-write SYNCEN_0 Asynchronous mode is enabled. 0 SYNCEN_1 Synchronous mode is enabled. Only fixed latency mode is supported. 0x1 BL Burst Length 4 3 read-write BL_0 1 0 BL_1 2 0x1 BL_2 4 0x2 BL_3 8 0x3 BL_4 16 0x4 BL_5 32 0x5 BL_6 64 0x6 BL_7 64 0x7 AM Address Mode 8 2 read-write AM_0 Address/Data MUX mode (ADMUX) 0 AM_1 Advanced Address/Data MUX mode (AADM) 0x1 AM_2 Address/Data non-MUX mode (Non-ADMUX) 0x2 AM_3 Address/Data non-MUX mode (Non-ADMUX) 0x3 ADVP ADV# Polarity 10 1 read-write ADVP_0 ADV# is active low. 0 ADVP_1 ADV# is active high. 0x1 ADVH ADV# level control during address hold state 11 1 read-write ADVH_0 ADV# is high during address hold state. 0 ADVH_1 ADV# is low during address hold state. 0x1 COL Column Address bit width 12 4 read-write COL_0 12 Bits 0 COL_1 11 Bits 0x1 COL_2 10 Bits 0x2 COL_3 9 Bits 0x3 COL_4 8 Bits 0x4 COL_5 7 Bits 0x5 COL_6 6 Bits 0x6 COL_7 5 Bits 0x7 COL_8 4 Bits 0x8 COL_9 3 Bits 0x9 COL_10 2 Bits 0xA COL_11 12 Bits 0xB COL_12 12 Bits 0xC COL_13 12 Bits 0xD COL_14 12 Bits 0xE COL_15 12 Bits 0xF NORCR1 NOR Control Register 1 0x64 32 read-write 0 0xFFFFFFFF CES CE setup time 0 4 read-write CEH CE hold time 4 4 read-write AS Address setup time 8 4 read-write AH Address hold time 12 4 read-write WEL WE low time 16 4 read-write WEH WE high time 20 4 read-write REL RE low time 24 4 read-write REH RE high time 28 4 read-write NORCR2 NOR Control Register 2 0x68 32 read-write 0 0xFFFFFFFF TA Turnaround time 8 4 read-write AWDH Address to write data hold time 12 4 read-write LC Latency count 16 4 read-write RD Read time 20 4 read-write CEITV CE# interval time 24 4 read-write RDH Read hold time 28 4 read-write NORCR3 NOR Control Register 3 0x6C 32 read-write 0 0xFFFFFFFF ASSR Address setup time for SYNC read 0 4 read-write AHSR Address hold time for SYNC read 4 4 read-write SRAMCR0 SRAM Control Register 0 0x70 32 read-write 0 0xFFFFFFFF PS Port Size 0 1 read-write PS_0 8bit 0 PS_1 16bit 0x1 SYNCEN Synchronous Mode Enable 1 1 read-write SYNCEN_0 Asynchronous mode is enabled. 0 SYNCEN_1 Synchronous mode is enabled. Only fixed latency mode is supported. 0x1 WAITEN Wait Enable 2 1 read-write WAITEN_0 The SEMC does not monitor wait pin. 0 WAITEN_1 The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted. 0x1 WAITSP Wait Sample 3 1 read-write WAITSP_0 Wait pin is directly used by the SEMC. 0 WAITSP_1 Wait pin is sampled by internal clock before it is used. 0x1 BL Burst Length 4 3 read-write BL_0 1 0 BL_1 2 0x1 BL_2 4 0x2 BL_3 8 0x3 BL_4 16 0x4 BL_5 32 0x5 BL_6 64 0x6 BL_7 64 0x7 AM Address Mode 8 2 read-write AM_0 Address/Data MUX mode (ADMUX) 0 AM_1 Advanced Address/Data MUX mode (AADM) 0x1 AM_2 Address/Data non-MUX mode (Non-ADMUX) 0x2 AM_3 Address/Data non-MUX mode (Non-ADMUX) 0x3 ADVP ADV# polarity 10 1 read-write ADVP_0 ADV# is active low. 0 ADVP_1 ADV# is active high. 0x1 ADVH ADV# level control during address hold state 11 1 read-write ADVH_0 ADV# is high during address hold state. 0 ADVH_1 ADV# is low during address hold state. 0x1 COL Column Address bit width 12 4 read-write COL_0 12 Bits 0 COL_1 11 Bits 0x1 COL_2 10 Bits 0x2 COL_3 9 Bits 0x3 COL_4 8 Bits 0x4 COL_5 7 Bits 0x5 COL_6 6 Bits 0x6 COL_7 5 Bits 0x7 COL_8 4 Bits 0x8 COL_9 3 Bits 0x9 COL_10 2 Bits 0xA COL_11 12 Bits 0xB COL_12 12 Bits 0xC COL_13 12 Bits 0xD COL_14 12 Bits 0xE COL_15 12 Bits 0xF SRAMCR1 SRAM Control Register 1 0x74 32 read-write 0 0xFFFFFFFF CES CE setup time 0 4 read-write CEH CE hold time 4 4 read-write AS Address setup time 8 4 read-write AH Address hold time 12 4 read-write WEL WE low time 16 4 read-write WEH WE high time 20 4 read-write REL RE low time 24 4 read-write REH RE high time 28 4 read-write SRAMCR2 SRAM Control Register 2 0x78 32 read-write 0 0xFFFFFFFF WDS Write Data setup time 0 4 read-write WDH Write Data hold time 4 4 read-write TA Turnaround time 8 4 read-write AWDH Address to write data hold time 12 4 read-write LC Latency count 16 4 read-write RD Read time 20 4 read-write CEITV CE# interval time 24 4 read-write RDH Read hold time 28 4 read-write SRAMCR3 SRAM Control Register 3 0x7C 32 read-write 0 0xFFFFFFFF DBICR0 DBI-B Control Register 0 0x80 32 read-write 0 0xFFFFFFFF PS Port Size 0 1 read-write PS_0 8bit 0 PS_1 16bit 0x1 BL Burst Length 4 3 read-write BL_0 1 0 BL_1 2 0x1 BL_2 4 0x2 BL_3 8 0x3 BL_4 16 0x4 BL_5 32 0x5 BL_6 64 0x6 BL_7 64 0x7 COL Column Address bit width 12 4 read-write COL_0 12 Bits 0 COL_1 11 Bits 0x1 COL_2 10 Bits 0x2 COL_3 9 Bits 0x3 COL_4 8 Bits 0x4 COL_5 7 Bits 0x5 COL_6 6 Bits 0x6 COL_7 5 Bits 0x7 COL_8 4 Bits 0x8 COL_9 3 Bits 0x9 COL_10 2 Bits 0xA COL_11 12 Bits 0xB COL_12 12 Bits 0xC COL_13 12 Bits 0xD COL_14 12 Bits 0xE COL_15 12 Bits 0xF DBICR1 DBI-B Control Register 1 0x84 32 read-write 0 0xFFFFFFFF CES CSX Setup Time 0 4 read-write CEH CSX Hold Time 4 4 read-write WEL WRX Low Time 8 4 read-write WEH WRX High Time 12 4 read-write REL RDX Low Time 16 7 read-write REH RDX High Time 24 7 read-write DBICR2 DBI-B Control Register 2 0x88 32 read-write 0 0xFFFFFFFF CEITV CSX interval time 0 4 read-write IPCR0 IP Command Control Register 0 0x90 32 read-write 0 0xFFFFFFFF SA Slave address 0 32 read-write IPCR1 IP Command Control Register 1 0x94 32 read-write 0 0xFFFFFFFF DATSZ Data Size in Byte 0 3 read-write DATSZ_0 4 0 DATSZ_1 1 0x1 DATSZ_2 2 0x2 DATSZ_3 3 0x3 DATSZ_4 4 0x4 DATSZ_5 4 0x5 DATSZ_6 4 0x6 DATSZ_7 4 0x7 NAND_EXT_ADDR NAND Extended Address 8 8 read-write IPCR2 IP Command Control Register 2 0x98 32 read-write 0 0xFFFFFFFF BM0 Byte Mask for Byte 0 (IPTXDAT bit 7:0) 0 1 read-write BM0_0 Byte is unmasked 0 BM0_1 Byte is masked 0x1 BM1 Byte Mask for Byte 1 (IPTXDAT bit 15:8) 1 1 read-write BM1_0 Byte is unmasked 0 BM1_1 Byte is masked 0x1 BM2 Byte Mask for Byte 2 (IPTXDAT bit 23:16) 2 1 read-write BM2_0 Byte is unmasked 0 BM2_1 Byte is masked 0x1 BM3 Byte Mask for Byte 3 (IPTXDAT bit 31:24) 3 1 read-write BM3_0 Byte is unmasked 0 BM3_1 Byte is masked 0x1 IPCMD IP Command Register 0x9C 32 read-write 0 0xFFFFFFFF CMD SDRAM Commands: 0x8: Read 0x9: Write 0xA: Mode Register Set 0xB: Active 0xC: Auto Refresh 0xD: Self Refresh 0xE: Precharge 0xF: Precharge All Others: Reserved Self Refresh is sent to all SDRAM devices because they share the same SEMC_CLK pin 0 16 read-write KEY This field should be written with 0xA55A when trigging an IP command for all device types 16 16 write-only IPTXDAT TX DATA Register 0xA0 32 read-write 0 0xFFFFFFFF DAT Data value to use for an IP write command 0 32 read-write IPRXDAT RX DATA Register 0xB0 32 read-only 0 0xFFFFFFFF DAT Data returned by device for an IP read command. 0 32 read-only STS0 Status Register 0 0xC0 32 read-only 0x1 0xFFFFFFFF IDLE Indicating whether the SEMC is in idle state. 0 1 read-only NARDY Indicating NAND device Ready/WAIT# pin level. 1 1 read-only NARDY_0 NAND device is not ready 0 NARDY_1 NAND device is ready 0x1 STS1 Status Register 1 0xC4 32 read-only 0 0xFFFFFFFF STS2 Status Register 2 0xC8 32 read-only 0 0xFFFFFFFF NDWRPEND This field indicating whether there is pending AXI command (write) to NAND device. 3 1 read-only NDWRPEND_0 No pending 0 NDWRPEND_1 Pending 0x1 STS3 Status Register 3 0xCC 32 read-only 0 0xFFFFFFFF STS4 Status Register 4 0xD0 32 read-only 0 0xFFFFFFFF STS5 Status Register 5 0xD4 32 read-only 0 0xFFFFFFFF STS6 Status Register 6 0xD8 32 read-only 0 0xFFFFFFFF STS7 Status Register 7 0xDC 32 read-only 0 0xFFFFFFFF STS8 Status Register 8 0xE0 32 read-only 0 0xFFFFFFFF STS9 Status Register 9 0xE4 32 read-only 0 0xFFFFFFFF STS10 Status Register 10 0xE8 32 read-only 0 0xFFFFFFFF STS11 Status Register 11 0xEC 32 read-only 0 0xFFFFFFFF STS12 Status Register 12 0xF0 32 read-only 0 0xFFFFFFFF NDADDR This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4). 0 32 read-only STS13 Status Register 13 0xF4 32 read-only 0x100 0xFFFFFFFF SLVLOCK Sample clock slave delay line locked. 0 1 read-only SLVLOCK_0 Slave delay line is not locked. 0 SLVLOCK_1 Slave delay line is locked. 0x1 REFLOCK Sample clock reference delay line locked. 1 1 read-only REFLOCK_0 Reference delay line is not locked. 0 REFLOCK_1 Reference delay line is locked. 0x1 SLVSEL Sample clock slave delay line delay cell number selection. 2 6 read-only REFSEL Sample clock reference delay line delay cell number selection. 8 6 read-only STS14 Status Register 14 0xF8 32 read-only 0 0xFFFFFFFF STS15 Status Register 15 0xFC 32 read-only 0 0xFFFFFFFF BR9 Base Register 9 0x100 32 read-write 0xA0000018 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 The memory is invalid, can not be accessed. 0 VLD_1 The memory is valid, can be accessed. 0x1 MS Memory size 1 5 read-write MS_0 4KB 0 MS_1 8KB 0x1 MS_2 16KB 0x2 MS_3 32KB 0x3 MS_4 64KB 0x4 MS_5 128KB 0x5 MS_6 256KB 0x6 MS_7 512KB 0x7 MS_8 1MB 0x8 MS_9 2MB 0x9 MS_10 4MB 0xA MS_11 8MB 0xB MS_12 16MB 0xC MS_13 32MB 0xD MS_14 64MB 0xE MS_15 128MB 0xF MS_16 256MB 0x10 MS_17 512MB 0x11 MS_18 1GB 0x12 MS_19 2GB 0x13 MS_20 4GB 0x14 MS_21 4GB 0x15 MS_22 4GB 0x16 MS_23 4GB 0x17 MS_24 4GB 0x18 MS_25 4GB 0x19 MS_26 4GB 0x1A MS_27 4GB 0x1B MS_28 4GB 0x1C MS_29 4GB 0x1D MS_30 4GB 0x1E MS_31 4GB 0x1F BA Base Address 12 20 read-write BR10 Base Register 10 0x104 32 read-write 0xA4000018 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 The memory is invalid, can not be accessed. 0 VLD_1 The memory is valid, can be accessed. 0x1 MS Memory size 1 5 read-write MS_0 4KB 0 MS_1 8KB 0x1 MS_2 16KB 0x2 MS_3 32KB 0x3 MS_4 64KB 0x4 MS_5 128KB 0x5 MS_6 256KB 0x6 MS_7 512KB 0x7 MS_8 1MB 0x8 MS_9 2MB 0x9 MS_10 4MB 0xA MS_11 8MB 0xB MS_12 16MB 0xC MS_13 32MB 0xD MS_14 64MB 0xE MS_15 128MB 0xF MS_16 256MB 0x10 MS_17 512MB 0x11 MS_18 1GB 0x12 MS_19 2GB 0x13 MS_20 4GB 0x14 MS_21 4GB 0x15 MS_22 4GB 0x16 MS_23 4GB 0x17 MS_24 4GB 0x18 MS_25 4GB 0x19 MS_26 4GB 0x1A MS_27 4GB 0x1B MS_28 4GB 0x1C MS_29 4GB 0x1D MS_30 4GB 0x1E MS_31 4GB 0x1F BA Base Address 12 20 read-write BR11 Base Register 11 0x108 32 read-write 0xA8000018 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 The memory is invalid, can not be accessed. 0 VLD_1 The memory is valid, can be accessed. 0x1 MS Memory size 1 5 read-write MS_0 4KB 0 MS_1 8KB 0x1 MS_2 16KB 0x2 MS_3 32KB 0x3 MS_4 64KB 0x4 MS_5 128KB 0x5 MS_6 256KB 0x6 MS_7 512KB 0x7 MS_8 1MB 0x8 MS_9 2MB 0x9 MS_10 4MB 0xA MS_11 8MB 0xB MS_12 16MB 0xC MS_13 32MB 0xD MS_14 64MB 0xE MS_15 128MB 0xF MS_16 256MB 0x10 MS_17 512MB 0x11 MS_18 1GB 0x12 MS_19 2GB 0x13 MS_20 4GB 0x14 MS_21 4GB 0x15 MS_22 4GB 0x16 MS_23 4GB 0x17 MS_24 4GB 0x18 MS_25 4GB 0x19 MS_26 4GB 0x1A MS_27 4GB 0x1B MS_28 4GB 0x1C MS_29 4GB 0x1D MS_30 4GB 0x1E MS_31 4GB 0x1F BA Base Address 12 20 read-write SRAMCR4 SRAM Control Register 4 0x120 32 read-write 0 0xFFFFFFFF PS Port Size 0 1 read-write PS_0 8bit 0 PS_1 16bit 0x1 SYNCEN Synchronous Mode Enable 1 1 read-write SYNCEN_0 Asynchronous mode is enabled. 0 SYNCEN_1 Synchronous mode is enabled. Only fixed latency mode is supported. 0x1 WAITEN Wait Enable 2 1 read-write WAITEN_0 The SEMC does not monitor wait pin. 0 WAITEN_1 The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted. 0x1 WAITSP Wait Sample 3 1 read-write WAITSP_0 Wait pin is directly used by the SEMC. 0 WAITSP_1 Wait pin is sampled by internal clock before it is used. 0x1 BL Burst Length 4 3 read-write BL_0 1 0 BL_1 2 0x1 BL_2 4 0x2 BL_3 8 0x3 BL_4 16 0x4 BL_5 32 0x5 BL_6 64 0x6 BL_7 64 0x7 AM Address Mode 8 2 read-write AM_0 Address/Data MUX mode (ADMUX) 0 AM_1 Advanced Address/Data MUX mode (AADM) 0x1 AM_2 Address/Data non-MUX mode (Non-ADMUX) 0x2 AM_3 Address/Data non-MUX mode (Non-ADMUX) 0x3 ADVP ADV# polarity 10 1 read-write ADVP_0 ADV# is active low. 0 ADVP_1 ADV# is active high. 0x1 ADVH ADV# level control during address hold state 11 1 read-write ADVH_0 ADV# is high during address hold state. 0 ADVH_1 ADV# is low during address hold state. 0x1 COL Column Address bit width 12 4 read-write COL_0 12 Bits 0 COL_1 11 Bits 0x1 COL_2 10 Bits 0x2 COL_3 9 Bits 0x3 COL_4 8 Bits 0x4 COL_5 7 Bits 0x5 COL_6 6 Bits 0x6 COL_7 5 Bits 0x7 COL_8 4 Bits 0x8 COL_9 3 Bits 0x9 COL_10 2 Bits 0xA COL_11 12 Bits 0xB COL_12 12 Bits 0xC COL_13 12 Bits 0xD COL_14 12 Bits 0xE COL_15 12 Bits 0xF SRAMCR5 SRAM Control Register 5 0x124 32 read-write 0 0xFFFFFFFF CES CE setup time 0 4 read-write CEH CE hold time 4 4 read-write AS Address setup time 8 4 read-write AH Address hold time 12 4 read-write WEL WE low time 16 4 read-write WEH WE high time 20 4 read-write REL RE low time 24 4 read-write REH RE high time 28 4 read-write SRAMCR6 SRAM Control Register 6 0x128 32 read-write 0 0xFFFFFFFF WDS Write Data setup time 0 4 read-write WDH Write Data hold time 4 4 read-write TA Turnaround time 8 4 read-write AWDH Address to write data hold time 12 4 read-write LC Latency count 16 4 read-write RD Read time 20 4 read-write CEITV CE# interval time 24 4 read-write RDH Read hold time 28 4 read-write DCCR Delay Chain Control Register 0x150 32 read-write 0 0xFFFFFFFF SDRAMEN Delay chain insertion enable for SRAM device. 0 1 read-write SDRAMEN_0 Delay chain is not inserted. 0 SDRAMEN_1 Delay chain is inserted. 0x1 SDRAMVAL Clock delay line delay cell number selection value for SDRAM device. 1 5 read-write NOREN Delay chain insertion enable for NOR device. 8 1 read-write NOREN_0 Delay chain is not inserted. 0 NOREN_1 Delay chain is inserted. 0x1 NORVAL Clock delay line delay cell number selection value for NOR device. 9 5 read-write SRAM0EN Delay chain insertion enable for SRAM device 0. 16 1 read-write SRAM0EN_0 Delay chain is not inserted. 0 SRAM0EN_1 Delay chain is inserted. 0x1 SRAM0VAL Clock delay line delay cell number selection value for SRAM device 0. 17 5 read-write SRAMXEN Delay chain insertion enable for SRAM device 1-3. 24 1 read-write SRAMXEN_0 Delay chain is not inserted. 0 SRAMXEN_1 Delay chain is inserted. 0x1 SRAMXVAL Clock delay line delay cell number selection value for SRAM device 1-3. 25 5 read-write PIT1 PIT PIT PIT 0x400D8000 0 0x140 registers PIT1 155 MCR PIT Module Control Register 0 32 read-write 0x2 0xFFFFFFFF FRZ Freeze 0 1 read-write t000001 Timers continue to run in Debug mode. 0 t0000011 Timers are stopped in Debug mode. 0x1 MDIS Module Disable for PIT 1 1 read-write t0301 Clock for standard PIT timers is enabled. 0 t00000111 Clock for standard PIT timers is disabled. 0x1 LTMR64H PIT Upper Lifetime Timer Register 0xE0 32 read-only 0 0xFFFFFFFF LTH Life Timer value 0 32 read-only LTMR64L PIT Lower Lifetime Timer Register 0xE4 32 read-only 0 0xFFFFFFFF LTL Life Timer value 0 32 read-only 4 0x10 TIMER[%s] no description available 0x100 LDVAL Timer Load Value Register 0 32 read-write 0 0xFFFFFFFF TSV Timer Start Value 0 32 read-write CVAL Current Timer Value Register 0x4 32 read-only 0 0xFFFFFFFF TVL Current Timer Value 0 32 read-only TCTRL Timer Control Register 0x8 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write t02981 Timer n is disabled. 0 t008981 Timer n is enabled. 0x1 TIE Timer Interrupt Enable 1 1 read-write t0331 Interrupt requests from Timer n are disabled. 0 t077711 Interrupt is requested whenever TIF is set. 0x1 CHN Chain Mode 2 1 read-write timer0001 Timer is not chained. 0 timer0081 Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1. 0x1 TFLG Timer Flag Register 0xC 32 read-write 0 0xFFFFFFFF oneToClear TIF Timer Interrupt Flag 0 1 read-write oneToClear t0022331 Timeout has not yet occurred. 0 t0022332221 Timeout has occurred. 0x1 PIT2 PIT PIT 0x40CB0000 0 0x140 registers PIT2 156 KPP KPP KPP 0x400E0000 0 0x8 registers KPP 51 KPCR Keypad Control Register 0 16 read-write 0 0xFFFF KRE KRE 0 8 read-write KRE_0 Row is not included in the keypad key press detect. 0 KRE_1 Row is included in the keypad key press detect. 0x1 KCO KCO 8 8 read-write TOTEM_POLE Column strobe output is totem pole drive. 0 OPEN_DRAIN Column strobe output is open drain. 0x1 KPSR Keypad Status Register 0x2 16 read-write 0x400 0xFFFF KPKD KPKD 0 1 read-write oneToClear KPKD_0 No key presses detected 0 KPKD_1 A key has been depressed 0x1 KPKR KPKR 1 1 read-write oneToClear KPKR_0 No key release detected 0 KPKR_1 All keys have been released 0x1 KDSC KDSC 2 1 read-write KDSC_0 No effect 0 KDSC_1 Set bits that clear the keypad depress synchronizer chain 0x1 KRSS KRSS 3 1 read-write KRSS_0 No effect 0 KRSS_1 Set bits which sets keypad release synchronizer chain 0x1 KDIE KDIE 8 1 read-write KDIE_0 No interrupt request is generated when KPKD is set. 0 KDIE_1 An interrupt request is generated when KPKD is set. 0x1 KRIE KRIE 9 1 read-write KRIE_0 No interrupt request is generated when KPKR is set. 0 KRIE_1 An interrupt request is generated when KPKR is set. 0x1 KDDR Keypad Data Direction Register 0x4 16 read-write 0 0xFFFF KRDD KRDD 0 8 read-write INPUT ROWn pin configured as an input. 0 OUTPUT ROWn pin configured as an output. 0x1 KCDD KCDD 8 8 read-write INPUT COLn pin is configured as an input. 0 OUTPUT COLn pin is configured as an output. 0x1 KPDR Keypad Data Register 0x6 16 read-write 0 0xFFFF KRD KRD 0 8 read-write KCD KCD 8 8 read-write IOMUXC_GPR IOMUXC GPR IOMUXC_GPR 0x400E4000 0 0x134 registers GPR_IRQ 53 GPR0 GPR0 General Purpose Register 0 32 read-write 0x18 0xFFFFFFFF SAI1_MCLK1_SEL SAI1 MCLK1 source select 0 3 read-write SAI1_MCLK2_SEL SAI1 MCLK2 source select 3 3 read-write SAI1_MCLK3_SEL SAI1 MCLK3 source select 6 2 read-write SAI1_MCLK_DIR SAI1_MCLK signal direction control 8 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR1 GPR1 General Purpose Register 0x4 32 read-write 0 0xFFFFFFFF SAI2_MCLK3_SEL SAI2 MCLK3 source select 0 2 read-write SAI2_MCLK_DIR SAI2_MCLK signal direction control 8 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR2 GPR2 General Purpose Register 0x8 32 read-write 0 0xFFFFFFFF SAI3_MCLK3_SEL SAI3 MCLK3 source select 0 2 read-write SAI3_MCLK_DIR SAI3_MCLK signal direction control 8 1 read-write SAI4_MCLK_DIR SAI4_MCLK signal direction control 9 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR3 GPR3 General Purpose Register 0xC 32 read-write 0 0xFFFFFFFF MQS_CLK_DIV Divider ratio control for mclk from hmclk. 0 8 read-write MQS_SW_RST MQS software reset 8 1 read-write MQS_EN MQS enable 9 1 read-write MQS_OVERSAMPLE Medium Quality Sound (MQS) Oversample 10 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR4 GPR4 General Purpose Register 0x10 32 read-write 0 0xFFFFFFFF ENET_TX_CLK_SEL ENET TX_CLK select 0 1 read-write ENET_REF_CLK_DIR ENET_REF_CLK direction control 1 1 read-write ENET_TIME_SEL ENET master timer source select 2 1 read-write ENET_EVENT0IN_SEL ENET ENET_1588_EVENT0_IN source select 3 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR5 GPR5 General Purpose Register 0x14 32 read-write 0 0xFFFFFFFF ENET1G_TX_CLK_SEL ENET1G TX_CLK select 0 1 read-write ENET1G_REF_CLK_DIR ENET1G_REF_CLK direction control 1 1 read-write ENET1G_RGMII_EN ENET1G RGMII TX clock output enable 2 1 read-write ENET1G_TIME_SEL ENET1G master timer source select 3 1 read-write ENET1G_EVENT0IN_SEL ENET1G ENET_1588_EVENT0_IN source select 4 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR6 GPR6 General Purpose Register 0x18 32 read-write 0 0xFFFFFFFF ENET_QOS_REF_CLK_DIR ENET_QOS_REF_CLK direction control 0 1 read-write ENET_QOS_RGMII_EN ENET_QOS RGMII TX clock output enable 1 1 read-write ENET_QOS_TIME_SEL ENET_QOS master timer source select 2 1 read-write ENET_QOS_INTF_SEL ENET_QOS PHY Interface Select 3 3 read-write ENET_QOS_CLKGEN_EN ENET_QOS clock generator enable 6 1 read-write ENET_QOS_EVENT0IN_SEL ENET_QOS ENET_1588_EVENT0_IN source select 7 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR7 GPR7 General Purpose Register 0x1C 32 read-write 0 0xFFFFFFFF GINT Global interrupt 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR8 GPR8 General Purpose Register 0x20 32 read-write 0 0xFFFFFFFF WDOG1_MASK WDOG1 timeout mask for WDOG_ANY 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR9 GPR9 General Purpose Register 0x24 32 read-write 0 0xFFFFFFFF WDOG2_MASK WDOG2 timeout mask for WDOG_ANY 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR10 GPR10 General Purpose Register 0x28 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR11 GPR11 General Purpose Register 0x2C 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR12 GPR12 General Purpose Register 0x30 32 read-write 0 0xFFFFFFFF QTIMER1_TMR_CNTS_FREEZE QTIMER1 timer counter freeze 0 1 read-write QTIMER1_TRM0_INPUT_SEL QTIMER1 TMR0 input select 8 1 read-write QTIMER1_TRM1_INPUT_SEL QTIMER1 TMR1 input select 9 1 read-write QTIMER1_TRM2_INPUT_SEL QTIMER1 TMR2 input select 10 1 read-write QTIMER1_TRM3_INPUT_SEL QTIMER1 TMR3 input select 11 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR13 GPR13 General Purpose Register 0x34 32 read-write 0 0xFFFFFFFF QTIMER2_TMR_CNTS_FREEZE QTIMER2 timer counter freeze 0 1 read-write QTIMER2_TRM0_INPUT_SEL QTIMER2 TMR0 input select 8 1 read-write QTIMER2_TRM1_INPUT_SEL QTIMER2 TMR1 input select 9 1 read-write QTIMER2_TRM2_INPUT_SEL QTIMER2 TMR2 input select 10 1 read-write QTIMER2_TRM3_INPUT_SEL QTIMER2 TMR3 input select 11 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR14 GPR14 General Purpose Register 0x38 32 read-write 0 0xFFFFFFFF QTIMER3_TMR_CNTS_FREEZE QTIMER3 timer counter freeze 0 1 read-write QTIMER3_TRM0_INPUT_SEL QTIMER3 TMR0 input select 8 1 read-write QTIMER3_TRM1_INPUT_SEL QTIMER3 TMR1 input select 9 1 read-write QTIMER3_TRM2_INPUT_SEL QTIMER3 TMR2 input select 10 1 read-write QTIMER3_TRM3_INPUT_SEL QTIMER3 TMR3 input select 11 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR15 GPR15 General Purpose Register 0x3C 32 read-write 0 0xFFFFFFFF QTIMER4_TMR_CNTS_FREEZE QTIMER4 timer counter freeze 0 1 read-write QTIMER4_TRM0_INPUT_SEL QTIMER4 TMR0 input select 8 1 read-write QTIMER4_TRM1_INPUT_SEL QTIMER4 TMR1 input select 9 1 read-write QTIMER4_TRM2_INPUT_SEL QTIMER4 TMR2 input select 10 1 read-write QTIMER4_TRM3_INPUT_SEL QTIMER4 TMR3 input select 11 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR16 GPR16 General Purpose Register 0x40 32 read-write 0xAA03 0xFFFFFFFF FLEXRAM_BANK_CFG_SEL FlexRAM bank config source select 2 1 read-write CM7_FORCE_HCLK_EN CM7 platform AHB clock enable 3 1 read-write M7_GPC_SLEEP_SEL CM7 sleep request selection 5 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR17 GPR17 General Purpose Register 0x44 32 read-write 0 0xFFFFFFFF FLEXRAM_BANK_CFG_LOW FlexRAM bank config value 0 16 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR18 GPR18 General Purpose Register 0x48 32 read-write 0 0xFFFFFFFF FLEXRAM_BANK_CFG_HIGH FlexRAM bank config value 0 16 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR20 GPR20 General Purpose Register 0x50 32 read-write 0 0xFFFFFFFF IOMUXC_XBAR_DIR_SEL_4 IOMUXC XBAR_INOUT4 function direction select 0 1 read-write IOMUXC_XBAR_DIR_SEL_5 IOMUXC XBAR_INOUT5 function direction select 1 1 read-write IOMUXC_XBAR_DIR_SEL_6 IOMUXC XBAR_INOUT6 function direction select 2 1 read-write IOMUXC_XBAR_DIR_SEL_7 IOMUXC XBAR_INOUT7 function direction select 3 1 read-write IOMUXC_XBAR_DIR_SEL_8 IOMUXC XBAR_INOUT8 function direction select 4 1 read-write IOMUXC_XBAR_DIR_SEL_9 IOMUXC XBAR_INOUT9 function direction select 5 1 read-write IOMUXC_XBAR_DIR_SEL_10 IOMUXC XBAR_INOUT10 function direction select 6 1 read-write IOMUXC_XBAR_DIR_SEL_11 IOMUXC XBAR_INOUT11 function direction select 7 1 read-write IOMUXC_XBAR_DIR_SEL_12 IOMUXC XBAR_INOUT12 function direction select 8 1 read-write IOMUXC_XBAR_DIR_SEL_13 IOMUXC XBAR_INOUT13 function direction select 9 1 read-write IOMUXC_XBAR_DIR_SEL_14 IOMUXC XBAR_INOUT14 function direction select 10 1 read-write IOMUXC_XBAR_DIR_SEL_15 IOMUXC XBAR_INOUT15 function direction select 11 1 read-write IOMUXC_XBAR_DIR_SEL_16 IOMUXC XBAR_INOUT16 function direction select 12 1 read-write IOMUXC_XBAR_DIR_SEL_17 IOMUXC XBAR_INOUT17 function direction select 13 1 read-write IOMUXC_XBAR_DIR_SEL_18 IOMUXC XBAR_INOUT18 function direction select 14 1 read-write IOMUXC_XBAR_DIR_SEL_19 IOMUXC XBAR_INOUT19 function direction select 15 1 read-write IOMUXC_XBAR_DIR_SEL_20 IOMUXC XBAR_INOUT20 function direction select 16 1 read-write IOMUXC_XBAR_DIR_SEL_21 IOMUXC XBAR_INOUT21 function direction select 17 1 read-write IOMUXC_XBAR_DIR_SEL_22 IOMUXC XBAR_INOUT22 function direction select 18 1 read-write IOMUXC_XBAR_DIR_SEL_23 IOMUXC XBAR_INOUT23 function direction select 19 1 read-write IOMUXC_XBAR_DIR_SEL_24 IOMUXC XBAR_INOUT24 function direction select 20 1 read-write IOMUXC_XBAR_DIR_SEL_25 IOMUXC XBAR_INOUT25 function direction select 21 1 read-write IOMUXC_XBAR_DIR_SEL_26 IOMUXC XBAR_INOUT26 function direction select 22 1 read-write IOMUXC_XBAR_DIR_SEL_27 IOMUXC XBAR_INOUT27 function direction select 23 1 read-write IOMUXC_XBAR_DIR_SEL_28 IOMUXC XBAR_INOUT28 function direction select 24 1 read-write IOMUXC_XBAR_DIR_SEL_29 IOMUXC XBAR_INOUT29 function direction select 25 1 read-write IOMUXC_XBAR_DIR_SEL_30 IOMUXC XBAR_INOUT30 function direction select 26 1 read-write IOMUXC_XBAR_DIR_SEL_31 IOMUXC XBAR_INOUT31 function direction select 27 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR21 GPR21 General Purpose Register 0x54 32 read-write 0 0xFFFFFFFF IOMUXC_XBAR_DIR_SEL_32 IOMUXC XBAR_INOUT32 function direction select 0 1 read-write IOMUXC_XBAR_DIR_SEL_33 IOMUXC XBAR_INOUT33 function direction select 1 1 read-write IOMUXC_XBAR_DIR_SEL_34 IOMUXC XBAR_INOUT34 function direction select 2 1 read-write IOMUXC_XBAR_DIR_SEL_35 IOMUXC XBAR_INOUT35 function direction select 3 1 read-write IOMUXC_XBAR_DIR_SEL_36 IOMUXC XBAR_INOUT36 function direction select 4 1 read-write IOMUXC_XBAR_DIR_SEL_37 IOMUXC XBAR_INOUT37 function direction select 5 1 read-write IOMUXC_XBAR_DIR_SEL_38 IOMUXC XBAR_INOUT38 function direction select 6 1 read-write IOMUXC_XBAR_DIR_SEL_39 IOMUXC XBAR_INOUT39 function direction select 7 1 read-write IOMUXC_XBAR_DIR_SEL_40 IOMUXC XBAR_INOUT40 function direction select 8 1 read-write IOMUXC_XBAR_DIR_SEL_41 IOMUXC XBAR_INOUT41 function direction select 9 1 read-write IOMUXC_XBAR_DIR_SEL_42 IOMUXC XBAR_INOUT42 function direction select 10 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR22 GPR22 General Purpose Register 0x58 32 read-write 0 0xFFFFFFFF REF_1M_CLK_GPT1 GPT1 1 MHz clock source select 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR23 GPR23 General Purpose Register 0x5C 32 read-write 0 0xFFFFFFFF REF_1M_CLK_GPT2 GPT2 1 MHz clock source select 0 1 read-write GPT2_CAPIN1_SEL GPT2 input capture channel 1 source select 1 1 read-write GPT2_CAPIN2_SEL GPT2 input capture channel 2 source select 2 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR24 GPR24 General Purpose Register 0x60 32 read-write 0 0xFFFFFFFF REF_1M_CLK_GPT3 GPT3 1 MHz clock source select 0 1 read-write GPT3_CAPIN1_SEL GPT3 input capture channel 1 source select 1 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR25 GPR25 General Purpose Register 0x64 32 read-write 0 0xFFFFFFFF REF_1M_CLK_GPT4 GPT4 1 MHz clock source select 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR26 GPR26 General Purpose Register 0x68 32 read-write 0 0xFFFFFFFF REF_1M_CLK_GPT5 GPT5 1 MHz clock source select 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR27 GPR27 General Purpose Register 0x6C 32 read-write 0 0xFFFFFFFF REF_1M_CLK_GPT6 GPT6 1 MHz clock source select 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR28 GPR28 General Purpose Register 0x70 32 read-write 0 0xFFFFFFFF ARCACHE_USDHC uSDHC block cacheable attribute value of AXI read transactions 0 1 read-write AWCACHE_USDHC uSDHC block cacheable attribute value of AXI write transactions 1 1 read-write CACHE_ENET1G no description available 5 1 read-write CACHE_ENET ENET block cacheable attribute value of AXI transactions 7 1 read-write CACHE_USB USB block cacheable attribute value of AXI transactions 13 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR29 GPR29 General Purpose Register 0x74 32 read-write 0x1 0xFFFFFFFF USBPHY1_IPG_CLK_ACTIVE USBPHY1 register access clock enable 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR30 GPR30 General Purpose Register 0x78 32 read-write 0x1 0xFFFFFFFF USBPHY2_IPG_CLK_ACTIVE USBPHY2 register access clock enable 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR31 GPR31 General Purpose Register 0x7C 32 read-write 0x12 0xFFFFFFFF RMW2_WAIT_BVALID_CPL OCRAM M7 RMW wait enable 0 1 read-write OCRAM_M7_CLK_GATING OCRAM M7 clock gating enable 2 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR32 GPR32 General Purpose Register 0x80 32 read-write 0 0xFFFFFFFF RMW1_WAIT_BVALID_CPL OCRAM1 RMW wait enable 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR33 GPR33 General Purpose Register 0x84 32 read-write 0 0xFFFFFFFF RMW2_WAIT_BVALID_CPL OCRAM2 RMW wait enable 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR34 GPR34 General Purpose Register 0x88 32 read-write 0 0xFFFFFFFF XECC_FLEXSPI1_WAIT_BVALID_CPL XECC_FLEXSPI1 RMW wait enable 0 1 read-write FLEXSPI1_OTFAD_EN FlexSPI1 OTFAD enable 1 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR35 GPR35 General Purpose Register 0x8C 32 read-write 0 0xFFFFFFFF XECC_FLEXSPI2_WAIT_BVALID_CPL XECC_FLEXSPI2 RMW wait enable 0 1 read-write FLEXSPI2_OTFAD_EN FlexSPI2 OTFAD enable 1 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR36 GPR36 General Purpose Register 0x90 32 read-write 0 0xFFFFFFFF XECC_SEMC_WAIT_BVALID_CPL XECC_SEMC RMW wait enable 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR37 GPR37 General Purpose Register 0x94 32 read-write 0x17 0xFFFFFFFF NIDEN ARM non-secure (non-invasive) debug enable 0 1 read-write DBG_EN ARM invasive debug enable 1 1 read-write EXC_MON Exclusive monitor response select of illegal command 3 1 read-write M7_DBG_ACK_MASK CM7 debug halt mask 5 1 read-write M4_DBG_ACK_MASK CM4 debug halt mask 6 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR38 GPR38 General Purpose Register 0x98 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR39 GPR39 General Purpose Register 0x9C 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR40 GPR40 General Purpose Register 0xA0 32 read-write 0 0xFFFFFFFF GPIO_MUX2_GPIO_SEL_LOW GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function. 0 16 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR41 GPR41 General Purpose Register 0xA4 32 read-write 0 0xFFFFFFFF GPIO_MUX2_GPIO_SEL_HIGH GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function. 0 16 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR42 GPR42 General Purpose Register 0xA8 32 read-write 0 0xFFFFFFFF GPIO_MUX3_GPIO_SEL_LOW GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function. 0 16 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR43 GPR43 General Purpose Register 0xAC 32 read-write 0 0xFFFFFFFF GPIO_MUX3_GPIO_SEL_HIGH GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function. 0 16 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR44 GPR44 General Purpose Register 0xB0 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR45 GPR45 General Purpose Register 0xB4 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR46 GPR46 General Purpose Register 0xB8 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR47 GPR47 General Purpose Register 0xBC 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR48 GPR48 General Purpose Register 0xC0 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR49 GPR49 General Purpose Register 0xC4 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR50 GPR50 General Purpose Register 0xC8 32 read-write 0 0xFFFFFFFF CAAM_IPS_MGR CAAM manager processor identifier 0 5 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR51 GPR51 General Purpose Register 0xCC 32 read-write 0 0xFFFFFFFF M7_NMI_CLEAR Clear CM7 NMI holding register 0 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR52 GPR52 General Purpose Register 0xD0 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR53 GPR53 General Purpose Register 0xD4 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR54 GPR54 General Purpose Register 0xD8 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR55 GPR55 General Purpose Register 0xDC 32 read-write 0 0xFFFFFFFF DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR59 GPR59 General Purpose Register 0xEC 32 read-write 0x550 0xFFFFFFFF MIPI_CSI_AUTO_PD_EN Powers down inactive lanes reported by CSI2X_CFG_NUM_LANES. 0 1 read-write MIPI_CSI_SOFT_RST_N MIPI CSI APB clock domain and User interface clock domain software reset bit 1 1 read-write ASSERT Assert reset 0 DEAST De-assert reset 0x1 MIPI_CSI_CONT_CLK_MODE Enables the slave clock lane feature to maintain HS reception state during continuous clock mode operation, despite line glitches. 2 1 read-write MIPI_CSI_DDRCLK_EN When high, enables received DDR clock on CLK_DRXHS 3 1 read-write MIPI_CSI_PD_RX Power Down input for MIPI CSI PHY. 4 1 read-write MIPI_CSI_RX_ENABLE Assert to enable MIPI CSI Receive Enable 5 1 read-write MIPI_CSI_RX_RCAL MIPI CSI PHY on-chip termination control bits 6 2 read-write MIPI_CSI_RXCDRP Programming bits that adjust the threshold voltage of LP-CD, default setting 2'b01 8 2 read-write VAL0 344mV 0 VAL01 325mV (Default) 0x1 VAL10 307mV 0x2 VAL11 Invalid 0x3 MIPI_CSI_RXLPRP Programming bits that adjust the threshold voltage of LP-RX, default setting 2'b01 10 2 read-write MIPI_CSI_S_PRG_RXHS_SETTLE Bits used to program T_HS_SETTLE. 12 6 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR62 GPR62 General Purpose Register 0xF8 32 read-write 0x2DB 0xFFFFFFFF MIPI_DSI_CLK_TM MIPI DSI Clock Lane triming bits 0 3 read-write MIPI_DSI_D0_TM MIPI DSI Data Lane 0 triming bits 3 3 read-write MIPI_DSI_D1_TM MIPI DSI Data Lane 1 triming bits 6 3 read-write MIPI_DSI_TX_RCAL MIPI DSI PHY on-chip termination control bits 9 2 read-write MIPI_DSI_TX_ULPS_ENABLE DSI transmit ULPS mode enable 11 3 read-write MIPI_DSI_PCLK_SOFT_RESET_N MIPI DSI APB clock domain software reset bit 16 1 read-write ASSERT Assert reset 0 DEASSERT De-assert reset 0x1 MIPI_DSI_BYTE_SOFT_RESET_N MIPI DSI Byte clock domain software reset bit 17 1 read-write ASSERT Assert reset 0 DEASSERT De-assert reset 0x1 MIPI_DSI_DPI_SOFT_RESET_N MIPI DSI Pixel clock domain software reset bit 18 1 read-write ASSERT Assert reset 0 DEASSERT De-assert reset 0x1 MIPI_DSI_ESC_SOFT_RESET_N MIPI DSI Escape clock domain software reset bit 19 1 read-write ASSERT Assert reset 0 DEASSERT De-assert reset 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR63 GPR63 General Purpose Register 0xFC 32 read-only 0 0xFFFFFFFF MIPI_DSI_TX_ULPS_ACTIVE DSI transmit ULPS mode active flag 0 3 read-only GPR64 GPR64 General Purpose Register 0x100 32 read-write 0x4000 0xFFFFFFFF GPIO_DISP1_FREEZE Compensation code freeze 0 1 read-write GPIO_DISP1_COMPTQ COMPEN and COMPTQ control the operating modes of the compensation cell 1 1 read-write GPIO_DISP1_COMPEN COMPEN and COMPTQ control the operating modes of the compensation cell 2 1 read-write GPIO_DISP1_FASTFRZ_EN Compensation code fast freeze 3 1 read-write GPIO_DISP1_RASRCP GPIO_DISP_B1 IO bank's 4-bit PMOS compensation codes from core 4 4 read-write GPIO_DISP1_RASRCN GPIO_DISP_B1 IO bank's 4-bit NMOS compensation codes from core 8 4 read-write GPIO_DISP1_SELECT_NASRC GPIO_DISP1_NASRC selection 12 1 read-write GPIO_DISP1_REFGEN_SLEEP GPIO_DISP_B1 IO bank reference voltage generator cell sleep enable 13 1 read-write GPIO_DISP1_SUPLYDET_LATCH GPIO_DISP_B1 IO bank power supply mode latch enable 14 1 read-write GPIO_DISP1_COMPOK GPIO_DISP_B1 IO bank compensation OK flag 20 1 read-only GPIO_DISP1_NASRC GPIO_DISP_B1 IO bank compensation codes 21 4 read-only DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR65 GPR65 General Purpose Register 0x104 32 read-write 0x4000 0xFFFFFFFF GPIO_EMC1_FREEZE Compensation code freeze 0 1 read-write GPIO_EMC1_COMPTQ COMPEN and COMPTQ control the operating modes of the compensation cell 1 1 read-write GPIO_EMC1_COMPEN COMPEN and COMPTQ control the operating modes of the compensation cell 2 1 read-write GPIO_EMC1_FASTFRZ_EN Compensation code fast freeze 3 1 read-write GPIO_EMC1_RASRCP GPIO_EMC_B1 IO bank's 4-bit PMOS compensation codes from core 4 4 read-write GPIO_EMC1_RASRCN GPIO_EMC_B1 IO bank's 4-bit NMOS compensation codes from core 8 4 read-write GPIO_EMC1_SELECT_NASRC GPIO_EMC1_NASRC selection 12 1 read-write GPIO_EMC1_REFGEN_SLEEP GPIO_EMC_B1 IO bank reference voltage generator cell sleep enable 13 1 read-write GPIO_EMC1_SUPLYDET_LATCH GPIO_EMC_B1 IO bank power supply mode latch enable 14 1 read-write GPIO_EMC1_COMPOK GPIO_EMC_B1 IO bank compensation OK flag 20 1 read-only GPIO_EMC1_NASRC GPIO_EMC_B1 IO bank compensation codes 21 4 read-only DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR66 GPR66 General Purpose Register 0x108 32 read-write 0x4000 0xFFFFFFFF GPIO_EMC2_FREEZE Compensation code freeze 0 1 read-write GPIO_EMC2_COMPTQ COMPEN and COMPTQ control the operating modes of the compensation cell 1 1 read-write GPIO_EMC2_COMPEN COMPEN and COMPTQ control the operating modes of the compensation cell 2 1 read-write GPIO_EMC2_FASTFRZ_EN Compensation code fast freeze 3 1 read-write GPIO_EMC2_RASRCP GPIO_EMC_B2 IO bank's 4-bit PMOS compensation codes from core 4 4 read-write GPIO_EMC2_RASRCN GPIO_EMC_B2 IO bank's 4-bit NMOS compensation codes from core 8 4 read-write GPIO_EMC2_SELECT_NASRC GPIO_EMC2_NASRC selection 12 1 read-write GPIO_EMC2_REFGEN_SLEEP GPIO_EMC_B2 IO bank reference voltage generator cell sleep enable 13 1 read-write GPIO_EMC2_SUPLYDET_LATCH GPIO_EMC_B2 IO bank power supply mode latch enable 14 1 read-write GPIO_EMC2_COMPOK GPIO_EMC_B2 IO bank compensation OK flag 20 1 read-only GPIO_EMC2_NASRC GPIO_EMC_B2 IO bank compensation codes 21 4 read-only DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR67 GPR67 General Purpose Register 0x10C 32 read-write 0x4000 0xFFFFFFFF GPIO_SD1_FREEZE Compensation code freeze 0 1 read-write GPIO_SD1_COMPTQ COMPEN and COMPTQ control the operating modes of the compensation cell 1 1 read-write GPIO_SD1_COMPEN COMPEN and COMPTQ control the operating modes of the compensation cell 2 1 read-write GPIO_SD1_FASTFRZ_EN Compensation code fast freeze 3 1 read-write GPIO_SD1_RASRCP GPIO_SD_B1 IO bank's 4-bit PMOS compensation codes from core 4 4 read-write GPIO_SD1_RASRCN GPIO_SD_B1 IO bank's 4-bit NMOS compensation codes from core 8 4 read-write GPIO_SD1_SELECT_NASRC GPIO_SD1_NASRC selection 12 1 read-write GPIO_SD1_REFGEN_SLEEP GPIO_SD_B1 IO bank reference voltage generator cell sleep enable 13 1 read-write GPIO_SD1_SUPLYDET_LATCH GPIO_SD_B1 IO bank power supply mode latch enable 14 1 read-write GPIO_SD1_COMPOK GPIO_SD_B1 IO bank compensation OK flag 20 1 read-only GPIO_SD1_NASRC GPIO_SD_B1 IO bank compensation codes 21 4 read-only DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR68 GPR68 General Purpose Register 0x110 32 read-write 0x4000 0xFFFFFFFF GPIO_SD2_FREEZE Compensation code freeze 0 1 read-write GPIO_SD2_COMPTQ COMPEN and COMPTQ control the operating modes of the compensation cell 1 1 read-write GPIO_SD2_COMPEN COMPEN and COMPTQ control the operating modes of the compensation cell 2 1 read-write GPIO_SD2_FASTFRZ_EN Compensation code fast freeze 3 1 read-write GPIO_SD2_RASRCP GPIO_SD_B2 IO bank's 4-bit PMOS compensation codes from core 4 4 read-write GPIO_SD2_RASRCN GPIO_SD_B2 IO bank's 4-bit NMOS compensation codes from core 8 4 read-write GPIO_SD2_SELECT_NASRC GPIO_SD2_NASRC selection 12 1 read-write GPIO_SD2_REFGEN_SLEEP GPIO_SD_B2 IO bank reference voltage generator cell sleep enable 13 1 read-write GPIO_SD2_SUPLYDET_LATCH GPIO_SD_B2 IO bank power supply mode latch enable 14 1 read-write GPIO_SD2_COMPOK GPIO_SD_B2 IO bank compensation OK flag 20 1 read-only GPIO_SD2_NASRC GPIO_SD_B2 IO bank compensation codes 21 4 read-only DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR69 GPR69 General Purpose Register 0x114 32 read-write 0 0xFFFFFFFF GPIO_DISP2_HIGH_RANGE GPIO_DISP_B2 IO bank supply voltage range selection 1 1 read-write GPIO_DISP2_LOW_RANGE GPIO_DISP_B2 IO bank supply voltage range selection 2 1 read-write GPIO_AD0_HIGH_RANGE GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17 4 1 read-write GPIO_AD0_LOW_RANGE GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17 5 1 read-write GPIO_AD1_HIGH_RANGE GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35 7 1 read-write GPIO_AD1_LOW_RANGE GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35 8 1 read-write SUPLYDET_DISP1_SLEEP GPIO_DISP_B1 IO bank supply voltage detector sleep mode enable 9 1 read-write SUPLYDET_EMC1_SLEEP GPIO_EMC_B1 IO bank supply voltage detector sleep mode enable 10 1 read-write SUPLYDET_EMC2_SLEEP GPIO_EMC_B2 IO bank supply voltage detector sleep mode enable 11 1 read-write SUPLYDET_SD1_SLEEP GPIO_SD_B1 IO bank supply voltage detector sleep mode enable 12 1 read-write SUPLYDET_SD2_SLEEP GPIO_SD_B2 IO bank supply voltage detector sleep mode enable 13 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR70 GPR70 General Purpose Register 0x118 32 read-write 0 0xFFFFFFFF ADC1_IPG_DOZE ADC1 doze mode 0 1 read-write ADC1_STOP_REQ ADC1 stop request 1 1 read-write ADC1_IPG_STOP_MODE ADC1 stop mode selection, cannot change when ADC1_STOP_REQ is asserted. 2 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 ADC2_IPG_DOZE ADC2 doze mode 3 1 read-write ADC2_STOP_REQ ADC2 stop request 4 1 read-write ADC2_IPG_STOP_MODE ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted. 5 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 CAAM_IPG_DOZE CAN3 doze mode 6 1 read-write CAAM_STOP_REQ CAAM stop request 7 1 read-write CAN1_IPG_DOZE CAN1 doze mode 8 1 read-write CAN1_STOP_REQ CAN1 stop request 9 1 read-write CAN2_IPG_DOZE CAN2 doze mode 10 1 read-write CAN2_STOP_REQ CAN2 stop request 11 1 read-write CAN3_IPG_DOZE CAN3 doze mode 12 1 read-write CAN3_STOP_REQ CAN3 stop request 13 1 read-write EDMA_STOP_REQ EDMA stop request 15 1 read-write EDMA_LPSR_STOP_REQ EDMA_LPSR stop request 16 1 read-write ENET_IPG_DOZE ENET doze mode 17 1 read-write ENET_STOP_REQ ENET stop request 18 1 read-write ENET1G_IPG_DOZE ENET1G doze mode 19 1 read-write ENET1G_STOP_REQ ENET1G stop request 20 1 read-write FLEXIO1_IPG_DOZE FLEXIO2 doze mode 21 1 read-write FLEXIO2_IPG_DOZE FLEXIO2 doze mode 22 1 read-write FLEXSPI1_IPG_DOZE FLEXSPI1 doze mode 23 1 read-write FLEXSPI1_STOP_REQ FLEXSPI1 stop request 24 1 read-write FLEXSPI2_IPG_DOZE FLEXSPI2 doze mode 25 1 read-write FLEXSPI2_STOP_REQ FLEXSPI2 stop request 26 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR71 GPR71 General Purpose Register 0x11C 32 read-write 0 0xFFFFFFFF GPT1_IPG_DOZE GPT1 doze mode 0 1 read-write GPT2_IPG_DOZE GPT2 doze mode 1 1 read-write GPT3_IPG_DOZE GPT3 doze mode 2 1 read-write GPT4_IPG_DOZE GPT4 doze mode 3 1 read-write GPT5_IPG_DOZE GPT5 doze mode 4 1 read-write GPT6_IPG_DOZE GPT6 doze mode 5 1 read-write LPI2C1_IPG_DOZE LPI2C1 doze mode 6 1 read-write LPI2C1_STOP_REQ LPI2C1 stop request 7 1 read-write LPI2C1_IPG_STOP_MODE LPI2C1 stop mode selection, cannot change when LPI2C1_STOP_REQ is asserted. 8 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPI2C2_IPG_DOZE LPI2C2 doze mode 9 1 read-write LPI2C2_STOP_REQ LPI2C2 stop request 10 1 read-write LPI2C2_IPG_STOP_MODE LPI2C2 stop mode selection, cannot change when LPI2C2_STOP_REQ is asserted. 11 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPI2C3_IPG_DOZE LPI2C3 doze mode 12 1 read-write LPI2C3_STOP_REQ LPI2C3 stop request 13 1 read-write LPI2C3_IPG_STOP_MODE LPI2C3 stop mode selection, cannot change when LPI2C3_STOP_REQ is asserted. 14 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPI2C4_IPG_DOZE LPI2C4 doze mode 15 1 read-write LPI2C4_STOP_REQ LPI2C4 stop request 16 1 read-write LPI2C4_IPG_STOP_MODE LPI2C4 stop mode selection, cannot change when LPI2C4_STOP_REQ is asserted. 17 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPI2C5_IPG_DOZE LPI2C5 doze mode 18 1 read-write LPI2C5_STOP_REQ LPI2C5 stop request 19 1 read-write LPI2C5_IPG_STOP_MODE LPI2C5 stop mode selection, cannot change when LPI2C5_STOP_REQ is asserted. 20 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPI2C6_IPG_DOZE LPI2C6 doze mode 21 1 read-write LPI2C6_STOP_REQ LPI2C6 stop request 22 1 read-write LPI2C6_IPG_STOP_MODE LPI2C6 stop mode selection, cannot change when LPI2C6_STOP_REQ is asserted. 23 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPSPI1_IPG_DOZE LPSPI1 doze mode 24 1 read-write LPSPI1_STOP_REQ LPSPI1 stop request 25 1 read-write LPSPI1_IPG_STOP_MODE LPSPI1 stop mode selection, cannot change when LPSPI1_STOP_REQ is asserted. 26 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR72 GPR72 General Purpose Register 0x120 32 read-write 0 0xFFFFFFFF LPSPI2_IPG_DOZE LPSPI2 doze mode 0 1 read-write LPSPI2_STOP_REQ LPSPI2 stop request 1 1 read-write LPSPI2_IPG_STOP_MODE LPSPI2 stop mode selection, cannot change when LPSPI2_STOP_REQ is asserted. 2 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPSPI3_IPG_DOZE LPSPI3 doze mode 3 1 read-write LPSPI3_STOP_REQ LPSPI3 stop request 4 1 read-write LPSPI3_IPG_STOP_MODE LPSPI3 stop mode selection, cannot change when LPSPI3_STOP_REQ is asserted. 5 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPSPI4_IPG_DOZE LPSPI4 doze mode 6 1 read-write LPSPI4_STOP_REQ LPSPI4 stop request 7 1 read-write LPSPI4_IPG_STOP_MODE LPSPI4 stop mode selection, cannot change when LPSPI4_STOP_REQ is asserted. 8 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPSPI5_IPG_DOZE LPSPI5 doze mode 9 1 read-write LPSPI5_STOP_REQ LPSPI5 stop request 10 1 read-write LPSPI5_IPG_STOP_MODE LPSPI5 stop mode selection, cannot change when LPSPI5_STOP_REQ is asserted. 11 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPSPI6_IPG_DOZE LPSPI6 doze mode 12 1 read-write LPSPI6_STOP_REQ LPSPI6 stop request 13 1 read-write LPSPI6_IPG_STOP_MODE LPSPI6 stop mode selection, cannot change when LPSPI6_STOP_REQ is asserted. 14 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART1_IPG_DOZE LPUART1 doze mode 15 1 read-write LPUART1_STOP_REQ LPUART1 stop request 16 1 read-write LPUART1_IPG_STOP_MODE LPUART1 stop mode selection, cannot change when LPUART1_STOP_REQ is asserted. 17 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART2_IPG_DOZE LPUART2 doze mode 18 1 read-write LPUART2_STOP_REQ LPUART2 stop request 19 1 read-write LPUART2_IPG_STOP_MODE LPUART2 stop mode selection, cannot change when LPUART2_STOP_REQ is asserted. 20 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART3_IPG_DOZE LPUART3 doze mode 21 1 read-write LPUART3_STOP_REQ LPUART3 stop request 22 1 read-write LPUART3_IPG_STOP_MODE LPUART3 stop mode selection, cannot change when LPUART3_STOP_REQ is asserted. 23 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART4_IPG_DOZE LPUART4 doze mode 24 1 read-write LPUART4_STOP_REQ LPUART4 stop request 25 1 read-write LPUART4_IPG_STOP_MODE LPUART4 stop mode selection, cannot change when LPUART4_STOP_REQ is asserted. 26 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR73 GPR73 General Purpose Register 0x124 32 read-write 0 0xFFFFFFFF LPUART5_IPG_DOZE LPUART5 doze mode 0 1 read-write LPUART5_STOP_REQ LPUART5 stop request 1 1 read-write LPUART5_IPG_STOP_MODE LPUART5 stop mode selection, cannot change when LPUART5_STOP_REQ is asserted. 2 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART6_IPG_DOZE LPUART6 doze mode 3 1 read-write LPUART6_STOP_REQ LPUART6 stop request 4 1 read-write LPUART6_IPG_STOP_MODE LPUART6 stop mode selection, cannot change when LPUART6_STOP_REQ is asserted. 5 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART7_IPG_DOZE LPUART7 doze mode 6 1 read-write LPUART7_STOP_REQ LPUART7 stop request 7 1 read-write LPUART7_IPG_STOP_MODE LPUART7 stop mode selection, cannot change when LPUART7_STOP_REQ is asserted. 8 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART8_IPG_DOZE LPUART8 doze mode 9 1 read-write LPUART8_STOP_REQ LPUART8 stop request 10 1 read-write LPUART8_IPG_STOP_MODE LPUART8 stop mode selection, cannot change when LPUART8_STOP_REQ is asserted. 11 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART9_IPG_DOZE LPUART9 doze mode 12 1 read-write LPUART9_STOP_REQ LPUART9 stop request 13 1 read-write LPUART9_IPG_STOP_MODE LPUART9 stop mode selection, cannot change when LPUART9_STOP_REQ is asserted. 14 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART10_IPG_DOZE LPUART10 doze mode 15 1 read-write LPUART10_STOP_REQ LPUART10 stop request 16 1 read-write LPUART10_IPG_STOP_MODE LPUART10 stop mode selection, cannot change when LPUART10_STOP_REQ is asserted. 17 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART11_IPG_DOZE LPUART11 doze mode 18 1 read-write LPUART11_STOP_REQ LPUART11 stop request 19 1 read-write LPUART11_IPG_STOP_MODE LPUART11 stop mode selection, cannot change when LPUART11_STOP_REQ is asserted. 20 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART12_IPG_DOZE LPUART12 doze mode 21 1 read-write LPUART12_STOP_REQ LPUART12 stop request 22 1 read-write LPUART12_IPG_STOP_MODE LPUART12 stop mode selection, cannot change when LPUART12_STOP_REQ is asserted. 23 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 MIC_IPG_DOZE MIC doze mode 24 1 read-write MIC_STOP_REQ MIC stop request 25 1 read-write MIC_IPG_STOP_MODE MIC stop mode selection, cannot change when MIC_STOP_REQ is asserted. 26 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR74 GPR74 General Purpose Register 0x128 32 read-write 0 0xFFFFFFFF PIT1_STOP_REQ PIT1 stop request 1 1 read-write PIT2_STOP_REQ PIT2 stop request 2 1 read-write SEMC_STOP_REQ SEMC stop request 3 1 read-write SIM1_IPG_DOZE SIM1 doze mode 4 1 read-write SIM2_IPG_DOZE SIM2 doze mode 5 1 read-write SNVS_HP_IPG_DOZE SNVS_HP doze mode 6 1 read-write SNVS_HP_STOP_REQ SNVS_HP stop request 7 1 read-write WDOG1_IPG_DOZE WDOG1 doze mode 8 1 read-write WDOG2_IPG_DOZE WDOG2 doze mode 9 1 read-write SAI1_STOP_REQ SAI1 stop request 10 1 read-write SAI2_STOP_REQ SAI2 stop request 11 1 read-write SAI3_STOP_REQ SAI3 stop request 12 1 read-write SAI4_STOP_REQ SAI4 stop request 13 1 read-write FLEXIO1_STOP_REQ_BUS FLEXIO1 bus clock domain stop request 14 1 read-write FLEXIO1_STOP_REQ_PER FLEXIO1 peripheral clock domain stop request 15 1 read-write FLEXIO2_STOP_REQ_BUS FLEXIO2 bus clock domain stop request 16 1 read-write FLEXIO2_STOP_REQ_PER FLEXIO2 peripheral clock domain stop request 17 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR75 GPR75 General Purpose Register 0x12C 32 read-only 0 0xFFFFFFFF ADC1_STOP_ACK ADC1 stop acknowledge 0 1 read-only ADC2_STOP_ACK ADC2 stop acknowledge 1 1 read-only CAAM_STOP_ACK CAAM stop acknowledge 2 1 read-only CAN1_STOP_ACK CAN1 stop acknowledge 3 1 read-only CAN2_STOP_ACK CAN2 stop acknowledge 4 1 read-only CAN3_STOP_ACK CAN3 stop acknowledge 5 1 read-only EDMA_STOP_ACK EDMA stop acknowledge 6 1 read-only EDMA_LPSR_STOP_ACK EDMA_LPSR stop acknowledge 7 1 read-only ENET_STOP_ACK ENET stop acknowledge 8 1 read-only ENET1G_STOP_ACK ENET1G stop acknowledge 9 1 read-only FLEXSPI1_STOP_ACK FLEXSPI1 stop acknowledge 10 1 read-only FLEXSPI2_STOP_ACK FLEXSPI2 stop acknowledge 11 1 read-only LPI2C1_STOP_ACK LPI2C1 stop acknowledge 12 1 read-only LPI2C2_STOP_ACK LPI2C2 stop acknowledge 13 1 read-only LPI2C3_STOP_ACK LPI2C3 stop acknowledge 14 1 read-only LPI2C4_STOP_ACK LPI2C4 stop acknowledge 15 1 read-only LPI2C5_STOP_ACK LPI2C5 stop acknowledge 16 1 read-only LPI2C6_STOP_ACK LPI2C6 stop acknowledge 17 1 read-only LPSPI1_STOP_ACK LPSPI1 stop acknowledge 18 1 read-only LPSPI2_STOP_ACK LPSPI2 stop acknowledge 19 1 read-only LPSPI3_STOP_ACK LPSPI3 stop acknowledge 20 1 read-only LPSPI4_STOP_ACK LPSPI4 stop acknowledge 21 1 read-only LPSPI5_STOP_ACK LPSPI5 stop acknowledge 22 1 read-only LPSPI6_STOP_ACK LPSPI6 stop acknowledge 23 1 read-only LPUART1_STOP_ACK LPUART1 stop acknowledge 24 1 read-only LPUART2_STOP_ACK LPUART2 stop acknowledge 25 1 read-only LPUART3_STOP_ACK LPUART3 stop acknowledge 26 1 read-only LPUART4_STOP_ACK LPUART4 stop acknowledge 27 1 read-only LPUART5_STOP_ACK LPUART5 stop acknowledge 28 1 read-only LPUART6_STOP_ACK LPUART6 stop acknowledge 29 1 read-only LPUART7_STOP_ACK LPUART7 stop acknowledge 30 1 read-only LPUART8_STOP_ACK LPUART8 stop acknowledge 31 1 read-only GPR76 GPR76 General Purpose Register 0x130 32 read-only 0 0xFFFFFFFF LPUART9_STOP_ACK LPUART9 stop acknowledge 0 1 read-only LPUART10_STOP_ACK LPUART10 stop acknowledge 1 1 read-only LPUART11_STOP_ACK LPUART11 stop acknowledge 2 1 read-only LPUART12_STOP_ACK LPUART12 stop acknowledge 3 1 read-only MIC_STOP_ACK MIC stop acknowledge 4 1 read-only PIT1_STOP_ACK PIT1 stop acknowledge 5 1 read-only PIT2_STOP_ACK PIT2 stop acknowledge 6 1 read-only SEMC_STOP_ACK SEMC stop acknowledge 7 1 read-only SNVS_HP_STOP_ACK SNVS_HP stop acknowledge 8 1 read-only SAI1_STOP_ACK SAI1 stop acknowledge 9 1 read-only SAI2_STOP_ACK SAI2 stop acknowledge 10 1 read-only SAI3_STOP_ACK SAI3 stop acknowledge 11 1 read-only SAI4_STOP_ACK SAI4 stop acknowledge 12 1 read-only FLEXIO1_STOP_ACK_BUS FLEXIO1 stop acknowledge of bus clock domain 13 1 read-only FLEXIO1_STOP_ACK_PER FLEXIO1 stop acknowledge of peripheral clock domain 14 1 read-only FLEXIO2_STOP_ACK_BUS FLEXIO2 stop acknowledge of bus clock domain 15 1 read-only FLEXIO2_STOP_ACK_PER FLEXIO2 stop acknowledge of peripheral clock domain 16 1 read-only IOMUXC IOMUXC IOMUXC 0x400E8000 0 0x718 registers SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register 0x10 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA0 Select mux mode: ALT0 mux port: SEMC_DATA00 of instance: SEMC 0 ALT1_flexpwm4_PWMA0 Select mux mode: ALT1 mux port: FLEXPWM4_PWM0_A of instance: FLEXPWM4 0x1 ALT5_gpio_mux1_IO0 Select mux mode: ALT5 mux port: GPIO_MUX1_IO00 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO0 Select mux mode: ALT8 mux port: FLEXIO1_D00 of instance: FLEXIO1 0x8 ALT10_gpio7_IO0 Select mux mode: ALT10 mux port: GPIO7_IO00 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_00 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_01 SW_MUX_CTL_PAD_GPIO_EMC_B1_01 SW MUX Control Register 0x14 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA1 Select mux mode: ALT0 mux port: SEMC_DATA01 of instance: SEMC 0 ALT1_flexpwm4_PWMB0 Select mux mode: ALT1 mux port: FLEXPWM4_PWM0_B of instance: FLEXPWM4 0x1 ALT5_gpio_mux1_IO1 Select mux mode: ALT5 mux port: GPIO_MUX1_IO01 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO1 Select mux mode: ALT8 mux port: FLEXIO1_D01 of instance: FLEXIO1 0x8 ALT10_gpio7_IO1 Select mux mode: ALT10 mux port: GPIO7_IO01 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_01 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_02 SW_MUX_CTL_PAD_GPIO_EMC_B1_02 SW MUX Control Register 0x18 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA2 Select mux mode: ALT0 mux port: SEMC_DATA02 of instance: SEMC 0 ALT1_flexpwm4_PWMA1 Select mux mode: ALT1 mux port: FLEXPWM4_PWM1_A of instance: FLEXPWM4 0x1 ALT5_gpio_mux1_IO2 Select mux mode: ALT5 mux port: GPIO_MUX1_IO02 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO2 Select mux mode: ALT8 mux port: FLEXIO1_D02 of instance: FLEXIO1 0x8 ALT10_gpio7_IO2 Select mux mode: ALT10 mux port: GPIO7_IO02 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_02 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_03 SW_MUX_CTL_PAD_GPIO_EMC_B1_03 SW MUX Control Register 0x1C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA3 Select mux mode: ALT0 mux port: SEMC_DATA03 of instance: SEMC 0 ALT1_flexpwm4_PWMB1 Select mux mode: ALT1 mux port: FLEXPWM4_PWM1_B of instance: FLEXPWM4 0x1 ALT5_gpio_mux1_IO3 Select mux mode: ALT5 mux port: GPIO_MUX1_IO03 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO3 Select mux mode: ALT8 mux port: FLEXIO1_D03 of instance: FLEXIO1 0x8 ALT10_gpio7_IO3 Select mux mode: ALT10 mux port: GPIO7_IO03 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_03 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_04 SW_MUX_CTL_PAD_GPIO_EMC_B1_04 SW MUX Control Register 0x20 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA4 Select mux mode: ALT0 mux port: SEMC_DATA04 of instance: SEMC 0 ALT1_flexpwm4_PWMA2 Select mux mode: ALT1 mux port: FLEXPWM4_PWM2_A of instance: FLEXPWM4 0x1 ALT5_gpio_mux1_IO4 Select mux mode: ALT5 mux port: GPIO_MUX1_IO04 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO4 Select mux mode: ALT8 mux port: FLEXIO1_D04 of instance: FLEXIO1 0x8 ALT10_gpio7_IO4 Select mux mode: ALT10 mux port: GPIO7_IO04 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_04 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_05 SW_MUX_CTL_PAD_GPIO_EMC_B1_05 SW MUX Control Register 0x24 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA5 Select mux mode: ALT0 mux port: SEMC_DATA05 of instance: SEMC 0 ALT1_flexpwm4_PWMB2 Select mux mode: ALT1 mux port: FLEXPWM4_PWM2_B of instance: FLEXPWM4 0x1 ALT5_gpio_mux1_IO5 Select mux mode: ALT5 mux port: GPIO_MUX1_IO05 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO5 Select mux mode: ALT8 mux port: FLEXIO1_D05 of instance: FLEXIO1 0x8 ALT10_gpio7_IO5 Select mux mode: ALT10 mux port: GPIO7_IO05 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_05 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_06 SW_MUX_CTL_PAD_GPIO_EMC_B1_06 SW MUX Control Register 0x28 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA6 Select mux mode: ALT0 mux port: SEMC_DATA06 of instance: SEMC 0 ALT1_flexpwm2_PWMA0 Select mux mode: ALT1 mux port: FLEXPWM2_PWM0_A of instance: FLEXPWM2 0x1 ALT5_gpio_mux1_IO6 Select mux mode: ALT5 mux port: GPIO_MUX1_IO06 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO6 Select mux mode: ALT8 mux port: FLEXIO1_D06 of instance: FLEXIO1 0x8 ALT10_gpio7_IO6 Select mux mode: ALT10 mux port: GPIO7_IO06 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_06 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_07 SW_MUX_CTL_PAD_GPIO_EMC_B1_07 SW MUX Control Register 0x2C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA7 Select mux mode: ALT0 mux port: SEMC_DATA07 of instance: SEMC 0 ALT1_flexpwm2_PWMB0 Select mux mode: ALT1 mux port: FLEXPWM2_PWM0_B of instance: FLEXPWM2 0x1 ALT5_gpio_mux1_IO7 Select mux mode: ALT5 mux port: GPIO_MUX1_IO07 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO7 Select mux mode: ALT8 mux port: FLEXIO1_D07 of instance: FLEXIO1 0x8 ALT10_gpio7_IO7 Select mux mode: ALT10 mux port: GPIO7_IO07 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_07 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_08 SW_MUX_CTL_PAD_GPIO_EMC_B1_08 SW MUX Control Register 0x30 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DM0 Select mux mode: ALT0 mux port: SEMC_DM00 of instance: SEMC 0 ALT1_flexpwm2_PWMA1 Select mux mode: ALT1 mux port: FLEXPWM2_PWM1_A of instance: FLEXPWM2 0x1 ALT5_gpio_mux1_IO8 Select mux mode: ALT5 mux port: GPIO_MUX1_IO08 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO8 Select mux mode: ALT8 mux port: FLEXIO1_D08 of instance: FLEXIO1 0x8 ALT10_gpio7_IO8 Select mux mode: ALT10 mux port: GPIO7_IO08 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_08 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_09 SW_MUX_CTL_PAD_GPIO_EMC_B1_09 SW MUX Control Register 0x34 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR0 Select mux mode: ALT0 mux port: SEMC_ADDR00 of instance: SEMC 0 ALT1_flexpwm2_PWMB1 Select mux mode: ALT1 mux port: FLEXPWM2_PWM1_B of instance: FLEXPWM2 0x1 ALT2_gpt5_CAPTURE1 Select mux mode: ALT2 mux port: GPT5_CAPTURE1 of instance: GPT5 0x2 ALT5_gpio_mux1_IO9 Select mux mode: ALT5 mux port: GPIO_MUX1_IO09 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO9 Select mux mode: ALT8 mux port: FLEXIO1_D09 of instance: FLEXIO1 0x8 ALT10_gpio7_IO9 Select mux mode: ALT10 mux port: GPIO7_IO09 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_09 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_10 SW_MUX_CTL_PAD_GPIO_EMC_B1_10 SW MUX Control Register 0x38 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR1 Select mux mode: ALT0 mux port: SEMC_ADDR01 of instance: SEMC 0 ALT1_flexpwm2_PWMA2 Select mux mode: ALT1 mux port: FLEXPWM2_PWM2_A of instance: FLEXPWM2 0x1 ALT2_gpt5_CAPTURE2 Select mux mode: ALT2 mux port: GPT5_CAPTURE2 of instance: GPT5 0x2 ALT5_gpio_mux1_IO10 Select mux mode: ALT5 mux port: GPIO_MUX1_IO10 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO10 Select mux mode: ALT8 mux port: FLEXIO1_D10 of instance: FLEXIO1 0x8 ALT10_gpio7_IO10 Select mux mode: ALT10 mux port: GPIO7_IO10 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_10 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_11 SW_MUX_CTL_PAD_GPIO_EMC_B1_11 SW MUX Control Register 0x3C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR2 Select mux mode: ALT0 mux port: SEMC_ADDR02 of instance: SEMC 0 ALT1_flexpwm2_PWMB2 Select mux mode: ALT1 mux port: FLEXPWM2_PWM2_B of instance: FLEXPWM2 0x1 ALT2_gpt5_COMPARE1 Select mux mode: ALT2 mux port: GPT5_COMPARE1 of instance: GPT5 0x2 ALT5_gpio_mux1_IO11 Select mux mode: ALT5 mux port: GPIO_MUX1_IO11 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO11 Select mux mode: ALT8 mux port: FLEXIO1_D11 of instance: FLEXIO1 0x8 ALT10_gpio7_IO11 Select mux mode: ALT10 mux port: GPIO7_IO11 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_11 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_12 SW_MUX_CTL_PAD_GPIO_EMC_B1_12 SW MUX Control Register 0x40 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR3 Select mux mode: ALT0 mux port: SEMC_ADDR03 of instance: SEMC 0 ALT1_XBAR1_INOUT4 Select mux mode: ALT1 mux port: XBAR1_INOUT04 of instance: XBAR1 0x1 ALT2_gpt5_COMPARE2 Select mux mode: ALT2 mux port: GPT5_COMPARE2 of instance: GPT5 0x2 ALT5_gpio_mux1_IO12 Select mux mode: ALT5 mux port: GPIO_MUX1_IO12 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO12 Select mux mode: ALT8 mux port: FLEXIO1_D12 of instance: FLEXIO1 0x8 ALT10_gpio7_IO12 Select mux mode: ALT10 mux port: GPIO7_IO12 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_12 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_13 SW_MUX_CTL_PAD_GPIO_EMC_B1_13 SW MUX Control Register 0x44 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR4 Select mux mode: ALT0 mux port: SEMC_ADDR04 of instance: SEMC 0 ALT1_XBAR1_INOUT5 Select mux mode: ALT1 mux port: XBAR1_INOUT05 of instance: XBAR1 0x1 ALT2_gpt5_COMPARE3 Select mux mode: ALT2 mux port: GPT5_COMPARE3 of instance: GPT5 0x2 ALT5_gpio_mux1_IO13 Select mux mode: ALT5 mux port: GPIO_MUX1_IO13 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO13 Select mux mode: ALT8 mux port: FLEXIO1_D13 of instance: FLEXIO1 0x8 ALT10_gpio7_IO13 Select mux mode: ALT10 mux port: GPIO7_IO13 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_13 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_14 SW_MUX_CTL_PAD_GPIO_EMC_B1_14 SW MUX Control Register 0x48 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR5 Select mux mode: ALT0 mux port: SEMC_ADDR05 of instance: SEMC 0 ALT1_XBAR1_INOUT6 Select mux mode: ALT1 mux port: XBAR1_INOUT06 of instance: XBAR1 0x1 ALT2_gpt5_CLK Select mux mode: ALT2 mux port: GPT5_CLK of instance: GPT5 0x2 ALT5_gpio_mux1_IO14 Select mux mode: ALT5 mux port: GPIO_MUX1_IO14 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO14 Select mux mode: ALT8 mux port: FLEXIO1_D14 of instance: FLEXIO1 0x8 ALT10_gpio7_IO14 Select mux mode: ALT10 mux port: GPIO7_IO14 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_14 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_15 SW_MUX_CTL_PAD_GPIO_EMC_B1_15 SW MUX Control Register 0x4C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR6 Select mux mode: ALT0 mux port: SEMC_ADDR06 of instance: SEMC 0 ALT1_XBAR1_INOUT7 Select mux mode: ALT1 mux port: XBAR1_INOUT07 of instance: XBAR1 0x1 ALT5_gpio_mux1_IO15 Select mux mode: ALT5 mux port: GPIO_MUX1_IO15 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO15 Select mux mode: ALT8 mux port: FLEXIO1_D15 of instance: FLEXIO1 0x8 ALT10_gpio7_IO15 Select mux mode: ALT10 mux port: GPIO7_IO15 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_15 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_16 SW_MUX_CTL_PAD_GPIO_EMC_B1_16 SW MUX Control Register 0x50 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR7 Select mux mode: ALT0 mux port: SEMC_ADDR07 of instance: SEMC 0 ALT1_XBAR1_INOUT8 Select mux mode: ALT1 mux port: XBAR1_INOUT08 of instance: XBAR1 0x1 ALT5_gpio_mux1_IO16 Select mux mode: ALT5 mux port: GPIO_MUX1_IO16 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO16 Select mux mode: ALT8 mux port: FLEXIO1_D16 of instance: FLEXIO1 0x8 ALT10_gpio7_IO16 Select mux mode: ALT10 mux port: GPIO7_IO16 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_16 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_17 SW_MUX_CTL_PAD_GPIO_EMC_B1_17 SW MUX Control Register 0x54 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR8 Select mux mode: ALT0 mux port: SEMC_ADDR08 of instance: SEMC 0 ALT1_flexpwm4_PWMA3 Select mux mode: ALT1 mux port: FLEXPWM4_PWM3_A of instance: FLEXPWM4 0x1 ALT2_qtimer1_TIMER0 Select mux mode: ALT2 mux port: TMR1_TIMER0 of instance: TMR1 0x2 ALT5_gpio_mux1_IO17 Select mux mode: ALT5 mux port: GPIO_MUX1_IO17 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO17 Select mux mode: ALT8 mux port: FLEXIO1_D17 of instance: FLEXIO1 0x8 ALT10_gpio7_IO17 Select mux mode: ALT10 mux port: GPIO7_IO17 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_17 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_18 SW_MUX_CTL_PAD_GPIO_EMC_B1_18 SW MUX Control Register 0x58 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR9 Select mux mode: ALT0 mux port: SEMC_ADDR09 of instance: SEMC 0 ALT1_flexpwm4_PWMB3 Select mux mode: ALT1 mux port: FLEXPWM4_PWM3_B of instance: FLEXPWM4 0x1 ALT2_qtimer2_TIMER0 Select mux mode: ALT2 mux port: TMR2_TIMER0 of instance: TMR2 0x2 ALT5_gpio_mux1_IO18 Select mux mode: ALT5 mux port: GPIO_MUX1_IO18 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO18 Select mux mode: ALT8 mux port: FLEXIO1_D18 of instance: FLEXIO1 0x8 ALT10_gpio7_IO18 Select mux mode: ALT10 mux port: GPIO7_IO18 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_18 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_19 SW_MUX_CTL_PAD_GPIO_EMC_B1_19 SW MUX Control Register 0x5C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR11 Select mux mode: ALT0 mux port: SEMC_ADDR11 of instance: SEMC 0 ALT1_flexpwm2_PWMA3 Select mux mode: ALT1 mux port: FLEXPWM2_PWM3_A of instance: FLEXPWM2 0x1 ALT2_qtimer3_TIMER0 Select mux mode: ALT2 mux port: TMR3_TIMER0 of instance: TMR3 0x2 ALT5_gpio_mux1_IO19 Select mux mode: ALT5 mux port: GPIO_MUX1_IO19 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO19 Select mux mode: ALT8 mux port: FLEXIO1_D19 of instance: FLEXIO1 0x8 ALT10_gpio7_IO19 Select mux mode: ALT10 mux port: GPIO7_IO19 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_19 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_20 SW_MUX_CTL_PAD_GPIO_EMC_B1_20 SW MUX Control Register 0x60 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR12 Select mux mode: ALT0 mux port: SEMC_ADDR12 of instance: SEMC 0 ALT1_flexpwm2_PWMB3 Select mux mode: ALT1 mux port: FLEXPWM2_PWM3_B of instance: FLEXPWM2 0x1 ALT2_qtimer4_TIMER0 Select mux mode: ALT2 mux port: TMR4_TIMER0 of instance: TMR4 0x2 ALT5_gpio_mux1_IO20 Select mux mode: ALT5 mux port: GPIO_MUX1_IO20 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO20 Select mux mode: ALT8 mux port: FLEXIO1_D20 of instance: FLEXIO1 0x8 ALT10_gpio7_IO20 Select mux mode: ALT10 mux port: GPIO7_IO20 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_20 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_21 SW_MUX_CTL_PAD_GPIO_EMC_B1_21 SW MUX Control Register 0x64 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_BA0 Select mux mode: ALT0 mux port: SEMC_BA0 of instance: SEMC 0 ALT1_flexpwm3_PWMA3 Select mux mode: ALT1 mux port: FLEXPWM3_PWM3_A of instance: FLEXPWM3 0x1 ALT5_gpio_mux1_IO21 Select mux mode: ALT5 mux port: GPIO_MUX1_IO21 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO21 Select mux mode: ALT8 mux port: FLEXIO1_D21 of instance: FLEXIO1 0x8 ALT10_gpio7_IO21 Select mux mode: ALT10 mux port: GPIO7_IO21 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_21 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_22 SW_MUX_CTL_PAD_GPIO_EMC_B1_22 SW MUX Control Register 0x68 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_BA1 Select mux mode: ALT0 mux port: SEMC_BA1 of instance: SEMC 0 ALT1_flexpwm3_PWMB3 Select mux mode: ALT1 mux port: FLEXPWM3_PWM3_B of instance: FLEXPWM3 0x1 ALT5_gpio_mux1_IO22 Select mux mode: ALT5 mux port: GPIO_MUX1_IO22 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO22 Select mux mode: ALT8 mux port: FLEXIO1_D22 of instance: FLEXIO1 0x8 ALT10_gpio7_IO22 Select mux mode: ALT10 mux port: GPIO7_IO22 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_22 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_23 SW_MUX_CTL_PAD_GPIO_EMC_B1_23 SW MUX Control Register 0x6C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_ADDR10 Select mux mode: ALT0 mux port: SEMC_ADDR10 of instance: SEMC 0 ALT1_flexpwm1_PWMA0 Select mux mode: ALT1 mux port: FLEXPWM1_PWM0_A of instance: FLEXPWM1 0x1 ALT5_gpio_mux1_IO23 Select mux mode: ALT5 mux port: GPIO_MUX1_IO23 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO23 Select mux mode: ALT8 mux port: FLEXIO1_D23 of instance: FLEXIO1 0x8 ALT10_gpio7_IO23 Select mux mode: ALT10 mux port: GPIO7_IO23 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_23 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_24 SW_MUX_CTL_PAD_GPIO_EMC_B1_24 SW MUX Control Register 0x70 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_CAS Select mux mode: ALT0 mux port: SEMC_CAS of instance: SEMC 0 ALT1_flexpwm1_PWMB0 Select mux mode: ALT1 mux port: FLEXPWM1_PWM0_B of instance: FLEXPWM1 0x1 ALT5_gpio_mux1_IO24 Select mux mode: ALT5 mux port: GPIO_MUX1_IO24 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO24 Select mux mode: ALT8 mux port: FLEXIO1_D24 of instance: FLEXIO1 0x8 ALT10_gpio7_IO24 Select mux mode: ALT10 mux port: GPIO7_IO24 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_24 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_25 SW_MUX_CTL_PAD_GPIO_EMC_B1_25 SW MUX Control Register 0x74 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_RAS Select mux mode: ALT0 mux port: SEMC_RAS of instance: SEMC 0 ALT1_flexpwm1_PWMA1 Select mux mode: ALT1 mux port: FLEXPWM1_PWM1_A of instance: FLEXPWM1 0x1 ALT5_gpio_mux1_IO25 Select mux mode: ALT5 mux port: GPIO_MUX1_IO25 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO25 Select mux mode: ALT8 mux port: FLEXIO1_D25 of instance: FLEXIO1 0x8 ALT10_gpio7_IO25 Select mux mode: ALT10 mux port: GPIO7_IO25 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_25 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_26 SW_MUX_CTL_PAD_GPIO_EMC_B1_26 SW MUX Control Register 0x78 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_CLK Select mux mode: ALT0 mux port: SEMC_CLK of instance: SEMC 0 ALT1_flexpwm1_PWMB1 Select mux mode: ALT1 mux port: FLEXPWM1_PWM1_B of instance: FLEXPWM1 0x1 ALT5_gpio_mux1_IO26 Select mux mode: ALT5 mux port: GPIO_MUX1_IO26 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO26 Select mux mode: ALT8 mux port: FLEXIO1_D26 of instance: FLEXIO1 0x8 ALT10_gpio7_IO26 Select mux mode: ALT10 mux port: GPIO7_IO26 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_26 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_27 SW_MUX_CTL_PAD_GPIO_EMC_B1_27 SW MUX Control Register 0x7C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_CKE Select mux mode: ALT0 mux port: SEMC_CKE of instance: SEMC 0 ALT1_flexpwm1_PWMA2 Select mux mode: ALT1 mux port: FLEXPWM1_PWM2_A of instance: FLEXPWM1 0x1 ALT5_gpio_mux1_IO27 Select mux mode: ALT5 mux port: GPIO_MUX1_IO27 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO27 Select mux mode: ALT8 mux port: FLEXIO1_D27 of instance: FLEXIO1 0x8 ALT10_gpio7_IO27 Select mux mode: ALT10 mux port: GPIO7_IO27 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_27 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_28 SW_MUX_CTL_PAD_GPIO_EMC_B1_28 SW MUX Control Register 0x80 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_WE Select mux mode: ALT0 mux port: SEMC_WE of instance: SEMC 0 ALT1_flexpwm1_PWMB2 Select mux mode: ALT1 mux port: FLEXPWM1_PWM2_B of instance: FLEXPWM1 0x1 ALT5_gpio_mux1_IO28 Select mux mode: ALT5 mux port: GPIO_MUX1_IO28 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO28 Select mux mode: ALT8 mux port: FLEXIO1_D28 of instance: FLEXIO1 0x8 ALT10_gpio7_IO28 Select mux mode: ALT10 mux port: GPIO7_IO28 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_28 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_29 SW_MUX_CTL_PAD_GPIO_EMC_B1_29 SW MUX Control Register 0x84 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_CS0 Select mux mode: ALT0 mux port: SEMC_CS0 of instance: SEMC 0 ALT1_flexpwm3_PWMA0 Select mux mode: ALT1 mux port: FLEXPWM3_PWM0_A of instance: FLEXPWM3 0x1 ALT5_gpio_mux1_IO29 Select mux mode: ALT5 mux port: GPIO_MUX1_IO29 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO29 Select mux mode: ALT8 mux port: FLEXIO1_D29 of instance: FLEXIO1 0x8 ALT10_gpio7_IO29 Select mux mode: ALT10 mux port: GPIO7_IO29 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_29 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_30 SW_MUX_CTL_PAD_GPIO_EMC_B1_30 SW MUX Control Register 0x88 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA8 Select mux mode: ALT0 mux port: SEMC_DATA08 of instance: SEMC 0 ALT1_flexpwm3_PWMB0 Select mux mode: ALT1 mux port: FLEXPWM3_PWM0_B of instance: FLEXPWM3 0x1 ALT5_gpio_mux1_IO30 Select mux mode: ALT5 mux port: GPIO_MUX1_IO30 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO30 Select mux mode: ALT8 mux port: FLEXIO1_D30 of instance: FLEXIO1 0x8 ALT10_gpio7_IO30 Select mux mode: ALT10 mux port: GPIO7_IO30 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_30 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_31 SW_MUX_CTL_PAD_GPIO_EMC_B1_31 SW MUX Control Register 0x8C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA9 Select mux mode: ALT0 mux port: SEMC_DATA09 of instance: SEMC 0 ALT1_flexpwm3_PWMA1 Select mux mode: ALT1 mux port: FLEXPWM3_PWM1_A of instance: FLEXPWM3 0x1 ALT5_gpio_mux1_IO31 Select mux mode: ALT5 mux port: GPIO_MUX1_IO31 of instance: GPIO_MUX1 0x5 ALT8_flexio1_FLEXIO31 Select mux mode: ALT8 mux port: FLEXIO1_D31 of instance: FLEXIO1 0x8 ALT10_gpio7_IO31 Select mux mode: ALT10 mux port: GPIO7_IO31 of instance: GPIO7 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_31 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_32 SW_MUX_CTL_PAD_GPIO_EMC_B1_32 SW MUX Control Register 0x90 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA10 Select mux mode: ALT0 mux port: SEMC_DATA10 of instance: SEMC 0 ALT1_flexpwm3_PWMB1 Select mux mode: ALT1 mux port: FLEXPWM3_PWM1_B of instance: FLEXPWM3 0x1 ALT5_gpio_mux2_IO0 Select mux mode: ALT5 mux port: GPIO_MUX2_IO00 of instance: GPIO_MUX2 0x5 ALT10_gpio8_IO0 Select mux mode: ALT10 mux port: GPIO8_IO00 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_32 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_33 SW_MUX_CTL_PAD_GPIO_EMC_B1_33 SW MUX Control Register 0x94 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA11 Select mux mode: ALT0 mux port: SEMC_DATA11 of instance: SEMC 0 ALT1_flexpwm3_PWMA2 Select mux mode: ALT1 mux port: FLEXPWM3_PWM2_A of instance: FLEXPWM3 0x1 ALT5_gpio_mux2_IO1 Select mux mode: ALT5 mux port: GPIO_MUX2_IO01 of instance: GPIO_MUX2 0x5 ALT10_gpio8_IO1 Select mux mode: ALT10 mux port: GPIO8_IO01 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_33 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_34 SW_MUX_CTL_PAD_GPIO_EMC_B1_34 SW MUX Control Register 0x98 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA12 Select mux mode: ALT0 mux port: SEMC_DATA12 of instance: SEMC 0 ALT1_flexpwm3_PWMB2 Select mux mode: ALT1 mux port: FLEXPWM3_PWM2_B of instance: FLEXPWM3 0x1 ALT5_gpio_mux2_IO2 Select mux mode: ALT5 mux port: GPIO_MUX2_IO02 of instance: GPIO_MUX2 0x5 ALT10_gpio8_IO2 Select mux mode: ALT10 mux port: GPIO8_IO02 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_34 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_35 SW_MUX_CTL_PAD_GPIO_EMC_B1_35 SW MUX Control Register 0x9C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA13 Select mux mode: ALT0 mux port: SEMC_DATA13 of instance: SEMC 0 ALT1_XBAR1_INOUT9 Select mux mode: ALT1 mux port: XBAR1_INOUT09 of instance: XBAR1 0x1 ALT5_gpio_mux2_IO3 Select mux mode: ALT5 mux port: GPIO_MUX2_IO03 of instance: GPIO_MUX2 0x5 ALT10_gpio8_IO3 Select mux mode: ALT10 mux port: GPIO8_IO03 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_35 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_36 SW_MUX_CTL_PAD_GPIO_EMC_B1_36 SW MUX Control Register 0xA0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA14 Select mux mode: ALT0 mux port: SEMC_DATA14 of instance: SEMC 0 ALT1_XBAR1_INOUT10 Select mux mode: ALT1 mux port: XBAR1_INOUT10 of instance: XBAR1 0x1 ALT5_gpio_mux2_IO4 Select mux mode: ALT5 mux port: GPIO_MUX2_IO04 of instance: GPIO_MUX2 0x5 ALT10_gpio8_IO4 Select mux mode: ALT10 mux port: GPIO8_IO04 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_36 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_37 SW_MUX_CTL_PAD_GPIO_EMC_B1_37 SW MUX Control Register 0xA4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA15 Select mux mode: ALT0 mux port: SEMC_DATA15 of instance: SEMC 0 ALT1_XBAR1_INOUT11 Select mux mode: ALT1 mux port: XBAR1_INOUT11 of instance: XBAR1 0x1 ALT5_gpio_mux2_IO5 Select mux mode: ALT5 mux port: GPIO_MUX2_IO05 of instance: GPIO_MUX2 0x5 ALT10_gpio8_IO5 Select mux mode: ALT10 mux port: GPIO8_IO05 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_37 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_38 SW_MUX_CTL_PAD_GPIO_EMC_B1_38 SW MUX Control Register 0xA8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DM1 Select mux mode: ALT0 mux port: SEMC_DM01 of instance: SEMC 0 ALT1_flexpwm1_PWMA3 Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_A of instance: FLEXPWM1 0x1 ALT2_qtimer1_TIMER1 Select mux mode: ALT2 mux port: TMR1_TIMER1 of instance: TMR1 0x2 ALT5_gpio_mux2_IO6 Select mux mode: ALT5 mux port: GPIO_MUX2_IO06 of instance: GPIO_MUX2 0x5 ALT10_gpio8_IO6 Select mux mode: ALT10 mux port: GPIO8_IO06 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_38 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_39 SW_MUX_CTL_PAD_GPIO_EMC_B1_39 SW MUX Control Register 0xAC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DQS Select mux mode: ALT0 mux port: SEMC_DQS of instance: SEMC 0 ALT1_flexpwm1_PWMB3 Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_B of instance: FLEXPWM1 0x1 ALT2_qtimer2_TIMER1 Select mux mode: ALT2 mux port: TMR2_TIMER1 of instance: TMR2 0x2 ALT5_gpio_mux2_IO7 Select mux mode: ALT5 mux port: GPIO_MUX2_IO07 of instance: GPIO_MUX2 0x5 ALT10_gpio8_IO7 Select mux mode: ALT10 mux port: GPIO8_IO07 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_39 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_40 SW_MUX_CTL_PAD_GPIO_EMC_B1_40 SW MUX Control Register 0xB0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_RDY Select mux mode: ALT0 mux port: SEMC_RDY of instance: SEMC 0 ALT1_XBAR1_INOUT12 Select mux mode: ALT1 mux port: XBAR1_INOUT12 of instance: XBAR1 0x1 ALT2_mqs_RIGHT Select mux mode: ALT2 mux port: MQS_RIGHT of instance: MQS 0x2 ALT3_lpuart6_TX Select mux mode: ALT3 mux port: LPUART6_TXD of instance: LPUART6 0x3 ALT5_gpio_mux2_IO8 Select mux mode: ALT5 mux port: GPIO_MUX2_IO08 of instance: GPIO_MUX2 0x5 ALT7_enet_1g_MDC Select mux mode: ALT7 mux port: ENET_1G_MDC of instance: ENET_1G 0x7 ALT9_CCM_CLKO1 Select mux mode: ALT9 mux port: CCM_CLKO1 of instance: CCM 0x9 ALT10_gpio8_IO8 Select mux mode: ALT10 mux port: GPIO8_IO08 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_40 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B1_41 SW_MUX_CTL_PAD_GPIO_EMC_B1_41 SW MUX Control Register 0xB4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_CSX0 Select mux mode: ALT0 mux port: SEMC_CSX00 of instance: SEMC 0 ALT1_XBAR1_INOUT13 Select mux mode: ALT1 mux port: XBAR1_INOUT13 of instance: XBAR1 0x1 ALT2_mqs_LEFT Select mux mode: ALT2 mux port: MQS_LEFT of instance: MQS 0x2 ALT3_lpuart6_RX Select mux mode: ALT3 mux port: LPUART6_RXD of instance: LPUART6 0x3 ALT4_flexspi2_B_DATA7 Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA07 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO9 Select mux mode: ALT5 mux port: GPIO_MUX2_IO09 of instance: GPIO_MUX2 0x5 ALT7_enet_1g_MDIO Select mux mode: ALT7 mux port: ENET_1G_MDIO of instance: ENET_1G 0x7 ALT9_CCM_CLKO2 Select mux mode: ALT9 mux port: CCM_CLKO2 of instance: CCM 0x9 ALT10_gpio8_IO9 Select mux mode: ALT10 mux port: GPIO8_IO09 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B1_41 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_00 SW_MUX_CTL_PAD_GPIO_EMC_B2_00 SW MUX Control Register 0xB8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA16 Select mux mode: ALT0 mux port: SEMC_DATA16 of instance: SEMC 0 ALT1_CCM_ENET_REF_CLK_25M Select mux mode: ALT1 mux port: CCM_ENET_REF_CLK_25M of instance: CCM 0x1 ALT2_qtimer3_TIMER1 Select mux mode: ALT2 mux port: TMR3_TIMER1 of instance: TMR3 0x2 ALT3_lpuart6_CTS_B Select mux mode: ALT3 mux port: LPUART6_CTS_B of instance: LPUART6 0x3 ALT4_flexspi2_B_DATA6 Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA06 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO10 Select mux mode: ALT5 mux port: GPIO_MUX2_IO10 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT20 Select mux mode: ALT6 mux port: XBAR1_INOUT20 of instance: XBAR1 0x6 ALT7_enet_qos_1588_EVENT1_OUT Select mux mode: ALT7 mux port: ENET_QOS_1588_EVENT1_OUT of instance: ENET_QOS 0x7 ALT8_lpspi1_SCK Select mux mode: ALT8 mux port: LPSPI1_SCK of instance: LPSPI1 0x8 ALT9_lpi2c2_SCL Select mux mode: ALT9 mux port: LPI2C2_SCL of instance: LPI2C2 0x9 ALT10_gpio8_IO10 Select mux mode: ALT10 mux port: GPIO8_IO10 of instance: GPIO8 0xA ALT11_flexpwm3_PWMA0 Select mux mode: ALT11 mux port: FLEXPWM3_PWM0_A of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_00 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_01 SW_MUX_CTL_PAD_GPIO_EMC_B2_01 SW MUX Control Register 0xBC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA17 Select mux mode: ALT0 mux port: SEMC_DATA17 of instance: SEMC 0 ALT1_usdhc2_CD_B Select mux mode: ALT1 mux port: USDHC2_CD_B of instance: USDHC2 0x1 ALT2_qtimer4_TIMER1 Select mux mode: ALT2 mux port: TMR4_TIMER1 of instance: TMR4 0x2 ALT3_lpuart6_RTS_B Select mux mode: ALT3 mux port: LPUART6_RTS_B of instance: LPUART6 0x3 ALT4_flexspi2_B_DATA5 Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA05 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO11 Select mux mode: ALT5 mux port: GPIO_MUX2_IO11 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT21 Select mux mode: ALT6 mux port: XBAR1_INOUT21 of instance: XBAR1 0x6 ALT7_enet_qos_1588_EVENT1_IN Select mux mode: ALT7 mux port: ENET_QOS_1588_EVENT1_IN of instance: ENET_QOS 0x7 ALT8_lpspi1_PCS0 Select mux mode: ALT8 mux port: LPSPI1_PCS0 of instance: LPSPI1 0x8 ALT9_lpi2c2_SDA Select mux mode: ALT9 mux port: LPI2C2_SDA of instance: LPI2C2 0x9 ALT10_gpio8_IO11 Select mux mode: ALT10 mux port: GPIO8_IO11 of instance: GPIO8 0xA ALT11_flexpwm3_PWMB0 Select mux mode: ALT11 mux port: FLEXPWM3_PWM0_B of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_01 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_02 SW_MUX_CTL_PAD_GPIO_EMC_B2_02 SW MUX Control Register 0xC0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA18 Select mux mode: ALT0 mux port: SEMC_DATA18 of instance: SEMC 0 ALT1_usdhc2_WP Select mux mode: ALT1 mux port: USDHC2_WP of instance: USDHC2 0x1 ALT3_video_mux_CSI_DATA23 Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA23 of instance: VIDEO_MUX 0x3 ALT4_flexspi2_B_DATA4 Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA04 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO12 Select mux mode: ALT5 mux port: GPIO_MUX2_IO12 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT22 Select mux mode: ALT6 mux port: XBAR1_INOUT22 of instance: XBAR1 0x6 ALT7_enet_qos_1588_EVENT1_AUX_IN Select mux mode: ALT7 mux port: ENET_QOS_1588_EVENT1_AUX_IN of instance: ENET_QOS 0x7 ALT8_lpspi1_SDO Select mux mode: ALT8 mux port: LPSPI1_SOUT of instance: LPSPI1 0x8 ALT10_gpio8_IO12 Select mux mode: ALT10 mux port: GPIO8_IO12 of instance: GPIO8 0xA ALT11_flexpwm3_PWMA1 Select mux mode: ALT11 mux port: FLEXPWM3_PWM1_A of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_02 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_03 SW_MUX_CTL_PAD_GPIO_EMC_B2_03 SW MUX Control Register 0xC4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA19 Select mux mode: ALT0 mux port: SEMC_DATA19 of instance: SEMC 0 ALT1_usdhc2_VSELECT Select mux mode: ALT1 mux port: USDHC2_VSELECT of instance: USDHC2 0x1 ALT3_video_mux_CSI_DATA22 Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA22 of instance: VIDEO_MUX 0x3 ALT4_flexspi2_B_DATA3 Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA03 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO13 Select mux mode: ALT5 mux port: GPIO_MUX2_IO13 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT23 Select mux mode: ALT6 mux port: XBAR1_INOUT23 of instance: XBAR1 0x6 ALT7_ENET_1G_TX_DATA3 Select mux mode: ALT7 mux port: ENET_1G_TX_DATA03 of instance: ENET_1G 0x7 ALT8_lpspi1_SDI Select mux mode: ALT8 mux port: LPSPI1_SIN of instance: LPSPI1 0x8 ALT10_gpio8_IO13 Select mux mode: ALT10 mux port: GPIO8_IO13 of instance: GPIO8 0xA ALT11_flexpwm3_PWMB1 Select mux mode: ALT11 mux port: FLEXPWM3_PWM1_B of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_03 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_04 SW_MUX_CTL_PAD_GPIO_EMC_B2_04 SW MUX Control Register 0xC8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA20 Select mux mode: ALT0 mux port: SEMC_DATA20 of instance: SEMC 0 ALT1_usdhc2_RESET_B Select mux mode: ALT1 mux port: USDHC2_RESET_B of instance: USDHC2 0x1 ALT2_sai2_MCLK Select mux mode: ALT2 mux port: SAI2_MCLK of instance: SAI2 0x2 ALT3_video_mux_CSI_DATA21 Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA21 of instance: VIDEO_MUX 0x3 ALT4_flexspi2_B_DATA2 Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA02 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO14 Select mux mode: ALT5 mux port: GPIO_MUX2_IO14 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT24 Select mux mode: ALT6 mux port: XBAR1_INOUT24 of instance: XBAR1 0x6 ALT7_ENET_1G_TX_DATA2 Select mux mode: ALT7 mux port: ENET_1G_TX_DATA02 of instance: ENET_1G 0x7 ALT8_lpspi3_SCK Select mux mode: ALT8 mux port: LPSPI3_SCK of instance: LPSPI3 0x8 ALT10_gpio8_IO14 Select mux mode: ALT10 mux port: GPIO8_IO14 of instance: GPIO8 0xA ALT11_flexpwm3_PWMA2 Select mux mode: ALT11 mux port: FLEXPWM3_PWM2_A of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_04 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_05 SW_MUX_CTL_PAD_GPIO_EMC_B2_05 SW MUX Control Register 0xCC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA21 Select mux mode: ALT0 mux port: SEMC_DATA21 of instance: SEMC 0 ALT1_gpt3_CLK Select mux mode: ALT1 mux port: GPT3_CLK of instance: GPT3 0x1 ALT2_sai2_RX_SYNC Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: SAI2 0x2 ALT3_video_mux_CSI_DATA20 Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA20 of instance: VIDEO_MUX 0x3 ALT4_flexspi2_B_DATA1 Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA01 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO15 Select mux mode: ALT5 mux port: GPIO_MUX2_IO15 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT25 Select mux mode: ALT6 mux port: XBAR1_INOUT25 of instance: XBAR1 0x6 ALT7_enet_1g_RX_CLK Select mux mode: ALT7 mux port: ENET_1G_RX_CLK of instance: ENET_1G 0x7 ALT8_lpspi3_PCS0 Select mux mode: ALT8 mux port: LPSPI3_PCS0 of instance: LPSPI3 0x8 ALT9_pit1_TRIGGER0 Select mux mode: ALT9 mux port: PIT1_TRIGGER0 of instance: PIT1 0x9 ALT10_gpio8_IO15 Select mux mode: ALT10 mux port: GPIO8_IO15 of instance: GPIO8 0xA ALT11_flexpwm3_PWMB2 Select mux mode: ALT11 mux port: FLEXPWM3_PWM2_B of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_05 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_06 SW_MUX_CTL_PAD_GPIO_EMC_B2_06 SW MUX Control Register 0xD0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA22 Select mux mode: ALT0 mux port: SEMC_DATA22 of instance: SEMC 0 ALT1_gpt3_CAPTURE1 Select mux mode: ALT1 mux port: GPT3_CAPTURE1 of instance: GPT3 0x1 ALT2_sai2_RX_BCLK Select mux mode: ALT2 mux port: SAI2_RX_BCLK of instance: SAI2 0x2 ALT3_video_mux_CSI_DATA19 Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA19 of instance: VIDEO_MUX 0x3 ALT4_flexspi2_B_DATA0 Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA00 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO16 Select mux mode: ALT5 mux port: GPIO_MUX2_IO16 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT26 Select mux mode: ALT6 mux port: XBAR1_INOUT26 of instance: XBAR1 0x6 ALT7_enet_1g_TX_ER Select mux mode: ALT7 mux port: ENET_1G_TX_ER of instance: ENET_1G 0x7 ALT8_lpspi3_SDO Select mux mode: ALT8 mux port: LPSPI3_SOUT of instance: LPSPI3 0x8 ALT9_pit1_TRIGGER1 Select mux mode: ALT9 mux port: PIT1_TRIGGER1 of instance: PIT1 0x9 ALT10_gpio8_IO16 Select mux mode: ALT10 mux port: GPIO8_IO16 of instance: GPIO8 0xA ALT11_flexpwm3_PWMA3 Select mux mode: ALT11 mux port: FLEXPWM3_PWM3_A of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_06 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_07 SW_MUX_CTL_PAD_GPIO_EMC_B2_07 SW MUX Control Register 0xD4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA23 Select mux mode: ALT0 mux port: SEMC_DATA23 of instance: SEMC 0 ALT1_gpt3_CAPTURE2 Select mux mode: ALT1 mux port: GPT3_CAPTURE2 of instance: GPT3 0x1 ALT2_sai2_RX_DATA Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: SAI2 0x2 ALT3_video_mux_CSI_DATA18 Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA18 of instance: VIDEO_MUX 0x3 ALT4_flexspi2_B_DQS Select mux mode: ALT4 mux port: FLEXSPI2_B_DQS of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO17 Select mux mode: ALT5 mux port: GPIO_MUX2_IO17 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT27 Select mux mode: ALT6 mux port: XBAR1_INOUT27 of instance: XBAR1 0x6 ALT7_ENET_1G_RX_DATA3 Select mux mode: ALT7 mux port: ENET_1G_RX_DATA03 of instance: ENET_1G 0x7 ALT8_lpspi3_SDI Select mux mode: ALT8 mux port: LPSPI3_SIN of instance: LPSPI3 0x8 ALT9_pit1_TRIGGER2 Select mux mode: ALT9 mux port: PIT1_TRIGGER2 of instance: PIT1 0x9 ALT10_gpio8_IO17 Select mux mode: ALT10 mux port: GPIO8_IO17 of instance: GPIO8 0xA ALT11_flexpwm3_PWMB3 Select mux mode: ALT11 mux port: FLEXPWM3_PWM3_B of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_07 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_08 SW_MUX_CTL_PAD_GPIO_EMC_B2_08 SW MUX Control Register 0xD8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DM2 Select mux mode: ALT0 mux port: SEMC_DM02 of instance: SEMC 0 ALT1_gpt3_COMPARE1 Select mux mode: ALT1 mux port: GPT3_COMPARE1 of instance: GPT3 0x1 ALT2_sai2_TX_DATA Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: SAI2 0x2 ALT3_video_mux_CSI_DATA17 Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA17 of instance: VIDEO_MUX 0x3 ALT4_flexspi2_B_SS0_B Select mux mode: ALT4 mux port: FLEXSPI2_B_SS0_B of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO18 Select mux mode: ALT5 mux port: GPIO_MUX2_IO18 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT28 Select mux mode: ALT6 mux port: XBAR1_INOUT28 of instance: XBAR1 0x6 ALT7_ENET_1G_RX_DATA2 Select mux mode: ALT7 mux port: ENET_1G_RX_DATA02 of instance: ENET_1G 0x7 ALT8_lpspi3_PCS1 Select mux mode: ALT8 mux port: LPSPI3_PCS1 of instance: LPSPI3 0x8 ALT9_pit1_TRIGGER3 Select mux mode: ALT9 mux port: PIT1_TRIGGER3 of instance: PIT1 0x9 ALT10_gpio8_IO18 Select mux mode: ALT10 mux port: GPIO8_IO18 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_08 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_09 SW_MUX_CTL_PAD_GPIO_EMC_B2_09 SW MUX Control Register 0xDC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA24 Select mux mode: ALT0 mux port: SEMC_DATA24 of instance: SEMC 0 ALT1_gpt3_COMPARE2 Select mux mode: ALT1 mux port: GPT3_COMPARE2 of instance: GPT3 0x1 ALT2_sai2_TX_BCLK Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: SAI2 0x2 ALT3_video_mux_CSI_DATA16 Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA16 of instance: VIDEO_MUX 0x3 ALT4_flexspi2_B_SCLK Select mux mode: ALT4 mux port: FLEXSPI2_B_SCLK of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO19 Select mux mode: ALT5 mux port: GPIO_MUX2_IO19 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT29 Select mux mode: ALT6 mux port: XBAR1_INOUT29 of instance: XBAR1 0x6 ALT7_enet_1g_CRS Select mux mode: ALT7 mux port: ENET_1G_CRS of instance: ENET_1G 0x7 ALT8_lpspi3_PCS2 Select mux mode: ALT8 mux port: LPSPI3_PCS2 of instance: LPSPI3 0x8 ALT9_qtimer1_TIMER0 Select mux mode: ALT9 mux port: TMR1_TIMER0 of instance: TMR1 0x9 ALT10_gpio8_IO19 Select mux mode: ALT10 mux port: GPIO8_IO19 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_09 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_10 SW_MUX_CTL_PAD_GPIO_EMC_B2_10 SW MUX Control Register 0xE0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA25 Select mux mode: ALT0 mux port: SEMC_DATA25 of instance: SEMC 0 ALT1_gpt3_COMPARE3 Select mux mode: ALT1 mux port: GPT3_COMPARE3 of instance: GPT3 0x1 ALT2_sai2_TX_SYNC Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: SAI2 0x2 ALT3_video_mux_CSI_FIELD Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_FIELD of instance: VIDEO_MUX 0x3 ALT4_flexspi2_A_SCLK Select mux mode: ALT4 mux port: FLEXSPI2_A_SCLK of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO20 Select mux mode: ALT5 mux port: GPIO_MUX2_IO20 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT30 Select mux mode: ALT6 mux port: XBAR1_INOUT30 of instance: XBAR1 0x6 ALT7_enet_1g_COL Select mux mode: ALT7 mux port: ENET_1G_COL of instance: ENET_1G 0x7 ALT8_lpspi3_PCS3 Select mux mode: ALT8 mux port: LPSPI3_PCS3 of instance: LPSPI3 0x8 ALT9_qtimer1_TIMER1 Select mux mode: ALT9 mux port: TMR1_TIMER1 of instance: TMR1 0x9 ALT10_gpio8_IO20 Select mux mode: ALT10 mux port: GPIO8_IO20 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_10 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_11 SW_MUX_CTL_PAD_GPIO_EMC_B2_11 SW MUX Control Register 0xE4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA26 Select mux mode: ALT0 mux port: SEMC_DATA26 of instance: SEMC 0 ALT1_spdif_IN Select mux mode: ALT1 mux port: SPDIF_IN of instance: SPDIF 0x1 ALT2_ENET_1G_TX_DATA0 Select mux mode: ALT2 mux port: ENET_1G_TX_DATA00 of instance: ENET_1G 0x2 ALT3_sai3_RX_SYNC Select mux mode: ALT3 mux port: SAI3_RX_SYNC of instance: SAI3 0x3 ALT4_flexspi2_A_SS0_B Select mux mode: ALT4 mux port: FLEXSPI2_A_SS0_B of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO21 Select mux mode: ALT5 mux port: GPIO_MUX2_IO21 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT31 Select mux mode: ALT6 mux port: XBAR1_INOUT31 of instance: XBAR1 0x6 ALT8_EMVSIM1_TRXD Select mux mode: ALT8 mux port: EMVSIM1_IO of instance: EMVSIM1 0x8 ALT9_qtimer1_TIMER2 Select mux mode: ALT9 mux port: TMR1_TIMER2 of instance: TMR1 0x9 ALT10_gpio8_IO21 Select mux mode: ALT10 mux port: GPIO8_IO21 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_11 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_12 SW_MUX_CTL_PAD_GPIO_EMC_B2_12 SW MUX Control Register 0xE8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA27 Select mux mode: ALT0 mux port: SEMC_DATA27 of instance: SEMC 0 ALT1_spdif_OUT Select mux mode: ALT1 mux port: SPDIF_OUT of instance: SPDIF 0x1 ALT2_ENET_1G_TX_DATA1 Select mux mode: ALT2 mux port: ENET_1G_TX_DATA01 of instance: ENET_1G 0x2 ALT3_sai3_RX_BCLK Select mux mode: ALT3 mux port: SAI3_RX_BCLK of instance: SAI3 0x3 ALT4_flexspi2_A_DQS Select mux mode: ALT4 mux port: FLEXSPI2_A_DQS of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO22 Select mux mode: ALT5 mux port: GPIO_MUX2_IO22 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT32 Select mux mode: ALT6 mux port: XBAR1_INOUT32 of instance: XBAR1 0x6 ALT8_EMVSIM1_CLK Select mux mode: ALT8 mux port: EMVSIM1_CLK of instance: EMVSIM1 0x8 ALT9_qtimer1_TIMER3 Select mux mode: ALT9 mux port: TMR1_TIMER3 of instance: TMR1 0x9 ALT10_gpio8_IO22 Select mux mode: ALT10 mux port: GPIO8_IO22 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_12 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_13 SW_MUX_CTL_PAD_GPIO_EMC_B2_13 SW MUX Control Register 0xEC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA28 Select mux mode: ALT0 mux port: SEMC_DATA28 of instance: SEMC 0 ALT2_enet_1g_TX_EN Select mux mode: ALT2 mux port: ENET_1G_TX_EN of instance: ENET_1G 0x2 ALT3_sai3_RX_DATA Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: SAI3 0x3 ALT4_flexspi2_A_DATA0 Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA00 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO23 Select mux mode: ALT5 mux port: GPIO_MUX2_IO23 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT33 Select mux mode: ALT6 mux port: XBAR1_INOUT33 of instance: XBAR1 0x6 ALT8_EMVSIM1_RST_B Select mux mode: ALT8 mux port: EMVSIM1_RST of instance: EMVSIM1 0x8 ALT9_qtimer2_TIMER0 Select mux mode: ALT9 mux port: TMR2_TIMER0 of instance: TMR2 0x9 ALT10_gpio8_IO23 Select mux mode: ALT10 mux port: GPIO8_IO23 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_13 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_14 SW_MUX_CTL_PAD_GPIO_EMC_B2_14 SW MUX Control Register 0xF0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA29 Select mux mode: ALT0 mux port: SEMC_DATA29 of instance: SEMC 0 ALT2_enet_1g_TX_CLK_IO Select mux mode: ALT2 mux port: ENET_1G_TX_CLK_IO of instance: ENET_1G 0x2 ALT3_sai3_TX_DATA Select mux mode: ALT3 mux port: SAI3_TX_DATA of instance: SAI3 0x3 ALT4_flexspi2_A_DATA1 Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA01 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO24 Select mux mode: ALT5 mux port: GPIO_MUX2_IO24 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT34 Select mux mode: ALT6 mux port: XBAR1_INOUT34 of instance: XBAR1 0x6 ALT7_sfa_ipp_do_atx_clk_under_test Select mux mode: ALT7 mux port: SFA_ipp_do_atx_clk_under_test of instance: sfa 0x7 ALT8_EMVSIM1_SVEN Select mux mode: ALT8 mux port: EMVSIM1_SVEN of instance: EMVSIM1 0x8 ALT9_qtimer2_TIMER1 Select mux mode: ALT9 mux port: TMR2_TIMER1 of instance: TMR2 0x9 ALT10_gpio8_IO24 Select mux mode: ALT10 mux port: GPIO8_IO24 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_14 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_15 SW_MUX_CTL_PAD_GPIO_EMC_B2_15 SW MUX Control Register 0xF4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA30 Select mux mode: ALT0 mux port: SEMC_DATA30 of instance: SEMC 0 ALT2_ENET_1G_RX_DATA0 Select mux mode: ALT2 mux port: ENET_1G_RX_DATA00 of instance: ENET_1G 0x2 ALT3_sai3_TX_BCLK Select mux mode: ALT3 mux port: SAI3_TX_BCLK of instance: SAI3 0x3 ALT4_flexspi2_A_DATA2 Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA02 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO25 Select mux mode: ALT5 mux port: GPIO_MUX2_IO25 of instance: GPIO_MUX2 0x5 ALT6_XBAR1_INOUT35 Select mux mode: ALT6 mux port: XBAR1_INOUT35 of instance: XBAR1 0x6 ALT8_EMVSIM1_PD Select mux mode: ALT8 mux port: EMVSIM1_PD of instance: EMVSIM1 0x8 ALT9_qtimer2_TIMER2 Select mux mode: ALT9 mux port: TMR2_TIMER2 of instance: TMR2 0x9 ALT10_gpio8_IO25 Select mux mode: ALT10 mux port: GPIO8_IO25 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_15 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_16 SW_MUX_CTL_PAD_GPIO_EMC_B2_16 SW MUX Control Register 0xF8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DATA31 Select mux mode: ALT0 mux port: SEMC_DATA31 of instance: SEMC 0 ALT1_XBAR1_INOUT14 Select mux mode: ALT1 mux port: XBAR1_INOUT14 of instance: XBAR1 0x1 ALT2_ENET_1G_RX_DATA1 Select mux mode: ALT2 mux port: ENET_1G_RX_DATA01 of instance: ENET_1G 0x2 ALT3_sai3_TX_SYNC Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: SAI3 0x3 ALT4_flexspi2_A_DATA3 Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA03 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO26 Select mux mode: ALT5 mux port: GPIO_MUX2_IO26 of instance: GPIO_MUX2 0x5 ALT8_EMVSIM1_POWER_FAIL Select mux mode: ALT8 mux port: EMVSIM1_POWER_FAIL of instance: EMVSIM1 0x8 ALT9_qtimer2_TIMER3 Select mux mode: ALT9 mux port: TMR2_TIMER3 of instance: TMR2 0x9 ALT10_gpio8_IO26 Select mux mode: ALT10 mux port: GPIO8_IO26 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_16 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_17 SW_MUX_CTL_PAD_GPIO_EMC_B2_17 SW MUX Control Register 0xFC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DM3 Select mux mode: ALT0 mux port: SEMC_DM03 of instance: SEMC 0 ALT1_XBAR1_INOUT15 Select mux mode: ALT1 mux port: XBAR1_INOUT15 of instance: XBAR1 0x1 ALT2_enet_1g_RX_EN Select mux mode: ALT2 mux port: ENET_1G_RX_EN of instance: ENET_1G 0x2 ALT3_sai3_MCLK Select mux mode: ALT3 mux port: SAI3_MCLK of instance: SAI3 0x3 ALT4_flexspi2_A_DATA4 Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA04 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO27 Select mux mode: ALT5 mux port: GPIO_MUX2_IO27 of instance: GPIO_MUX2 0x5 ALT8_WDOG1_ANY Select mux mode: ALT8 mux port: WDOG1_ANY of instance: WDOG1 0x8 ALT9_qtimer3_TIMER0 Select mux mode: ALT9 mux port: TMR3_TIMER0 of instance: TMR3 0x9 ALT10_gpio8_IO27 Select mux mode: ALT10 mux port: GPIO8_IO27 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_17 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_18 SW_MUX_CTL_PAD_GPIO_EMC_B2_18 SW MUX Control Register 0x100 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_DQS4 Select mux mode: ALT0 mux port: SEMC_DQS4 of instance: SEMC 0 ALT1_XBAR1_INOUT16 Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: XBAR1 0x1 ALT2_enet_1g_RX_ER Select mux mode: ALT2 mux port: ENET_1G_RX_ER of instance: ENET_1G 0x2 ALT3_EWM_OUT_B Select mux mode: ALT3 mux port: EWM_OUT_B of instance: EWM 0x3 ALT4_flexspi2_A_DATA5 Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA05 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO28 Select mux mode: ALT5 mux port: GPIO_MUX2_IO28 of instance: GPIO_MUX2 0x5 ALT6_flexspi1_A_DQS Select mux mode: ALT6 mux port: FLEXSPI1_A_DQS of instance: FLEXSPI1 0x6 ALT8_WDOG1_B Select mux mode: ALT8 mux port: WDOG1_B of instance: WDOG1 0x8 ALT9_qtimer3_TIMER1 Select mux mode: ALT9 mux port: TMR3_TIMER1 of instance: TMR3 0x9 ALT10_gpio8_IO28 Select mux mode: ALT10 mux port: GPIO8_IO28 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_18 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_19 SW_MUX_CTL_PAD_GPIO_EMC_B2_19 SW MUX Control Register 0x104 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_CLKX0 Select mux mode: ALT0 mux port: SEMC_CLKX00 of instance: SEMC 0 ALT1_enet_MDC Select mux mode: ALT1 mux port: ENET_MDC of instance: ENET 0x1 ALT2_enet_1g_MDC Select mux mode: ALT2 mux port: ENET_1G_MDC of instance: ENET_1G 0x2 ALT3_enet_1g_REF_CLK Select mux mode: ALT3 mux port: ENET_1G_REF_CLK of instance: ENET_1G 0x3 ALT4_flexspi2_A_DATA6 Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA06 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO29 Select mux mode: ALT5 mux port: GPIO_MUX2_IO29 of instance: GPIO_MUX2 0x5 ALT8_enet_qos_MDC Select mux mode: ALT8 mux port: ENET_QOS_MDC of instance: ENET_QOS 0x8 ALT9_qtimer3_TIMER2 Select mux mode: ALT9 mux port: TMR3_TIMER2 of instance: TMR3 0x9 ALT10_gpio8_IO29 Select mux mode: ALT10 mux port: GPIO8_IO29 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_19 0x1 SW_MUX_CTL_PAD_GPIO_EMC_B2_20 SW_MUX_CTL_PAD_GPIO_EMC_B2_20 SW MUX Control Register 0x108 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_semc_CLKX1 Select mux mode: ALT0 mux port: SEMC_CLKX01 of instance: SEMC 0 ALT1_enet_MDIO Select mux mode: ALT1 mux port: ENET_MDIO of instance: ENET 0x1 ALT2_enet_1g_MDIO Select mux mode: ALT2 mux port: ENET_1G_MDIO of instance: ENET_1G 0x2 ALT3_CCM_enet_qos_clock_generate_REF_CLK Select mux mode: ALT3 mux port: ENET_QOS_REF_CLK of instance: ENET_QOS 0x3 ALT4_flexspi2_A_DATA7 Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA07 of instance: FLEXSPI2 0x4 ALT5_gpio_mux2_IO30 Select mux mode: ALT5 mux port: GPIO_MUX2_IO30 of instance: GPIO_MUX2 0x5 ALT8_enet_qos_MDIO Select mux mode: ALT8 mux port: ENET_QOS_MDIO of instance: ENET_QOS 0x8 ALT9_qtimer3_TIMER3 Select mux mode: ALT9 mux port: TMR3_TIMER3 of instance: TMR3 0x9 ALT10_gpio8_IO30 Select mux mode: ALT10 mux port: GPIO8_IO30 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_EMC_B2_20 0x1 SW_MUX_CTL_PAD_GPIO_AD_00 SW_MUX_CTL_PAD_GPIO_AD_00 SW MUX Control Register 0x10C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_EMVSIM1_TRXD Select mux mode: ALT0 mux port: EMVSIM1_IO of instance: EMVSIM1 0 ALT1_can2_TX Select mux mode: ALT1 mux port: FLEXCAN2_TX of instance: FLEXCAN2 0x1 ALT2_enet_1g_1588_EVENT1_IN Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT1_IN of instance: ENET_1G 0x2 ALT3_gpt2_CAPTURE1 Select mux mode: ALT3 mux port: GPT2_CAPTURE1 of instance: GPT2 0x3 ALT4_flexpwm1_PWMA0 Select mux mode: ALT4 mux port: FLEXPWM1_PWM0_A of instance: FLEXPWM1 0x4 ALT5_gpio_mux2_IO31 Select mux mode: ALT5 mux port: GPIO_MUX2_IO31 of instance: GPIO_MUX2 0x5 ALT6_lpuart7_TX Select mux mode: ALT6 mux port: LPUART7_TXD of instance: LPUART7 0x6 ALT8_flexio2_FLEXIO0 Select mux mode: ALT8 mux port: FLEXIO2_D00 of instance: FLEXIO2 0x8 ALT9_flexspi2_B_SS1_B Select mux mode: ALT9 mux port: FLEXSPI2_B_SS1_B of instance: FLEXSPI2 0x9 ALT10_gpio8_IO31 Select mux mode: ALT10 mux port: GPIO8_IO31 of instance: GPIO8 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_00 0x1 SW_MUX_CTL_PAD_GPIO_AD_01 SW_MUX_CTL_PAD_GPIO_AD_01 SW MUX Control Register 0x110 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_EMVSIM1_CLK Select mux mode: ALT0 mux port: EMVSIM1_CLK of instance: EMVSIM1 0 ALT1_can2_RX Select mux mode: ALT1 mux port: FLEXCAN2_RX of instance: FLEXCAN2 0x1 ALT2_enet_1g_1588_EVENT1_OUT Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT1_OUT of instance: ENET_1G 0x2 ALT3_gpt2_CAPTURE2 Select mux mode: ALT3 mux port: GPT2_CAPTURE2 of instance: GPT2 0x3 ALT4_flexpwm1_PWMB0 Select mux mode: ALT4 mux port: FLEXPWM1_PWM0_B of instance: FLEXPWM1 0x4 ALT5_gpio_mux3_IO0 Select mux mode: ALT5 mux port: GPIO_MUX3_IO00 of instance: GPIO_MUX3 0x5 ALT6_lpuart7_RX Select mux mode: ALT6 mux port: LPUART7_RXD of instance: LPUART7 0x6 ALT8_flexio2_FLEXIO1 Select mux mode: ALT8 mux port: FLEXIO2_D01 of instance: FLEXIO2 0x8 ALT9_flexspi2_A_SS1_B Select mux mode: ALT9 mux port: FLEXSPI2_A_SS1_B of instance: FLEXSPI2 0x9 ALT10_gpio9_IO0 Select mux mode: ALT10 mux port: GPIO9_IO00 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_01 0x1 SW_MUX_CTL_PAD_GPIO_AD_02 SW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control Register 0x114 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_EMVSIM1_RST_B Select mux mode: ALT0 mux port: EMVSIM1_RST of instance: EMVSIM1 0 ALT1_lpuart7_CTS_B Select mux mode: ALT1 mux port: LPUART7_CTS_B of instance: LPUART7 0x1 ALT2_enet_1g_1588_EVENT2_IN Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT2_IN of instance: ENET_1G 0x2 ALT3_gpt2_COMPARE1 Select mux mode: ALT3 mux port: GPT2_COMPARE1 of instance: GPT2 0x3 ALT4_flexpwm1_PWMA1 Select mux mode: ALT4 mux port: FLEXPWM1_PWM1_A of instance: FLEXPWM1 0x4 ALT5_gpio_mux3_IO1 Select mux mode: ALT5 mux port: GPIO_MUX3_IO01 of instance: GPIO_MUX3 0x5 ALT6_lpuart8_TX Select mux mode: ALT6 mux port: LPUART8_TXD of instance: LPUART8 0x6 ALT8_flexio2_FLEXIO2 Select mux mode: ALT8 mux port: FLEXIO2_D02 of instance: FLEXIO2 0x8 ALT9_video_mux_EXT_DCIC1 Select mux mode: ALT9 mux port: VIDEO_MUX_EXT_DCIC1 of instance: VIDEO_MUX 0x9 ALT10_gpio9_IO1 Select mux mode: ALT10 mux port: GPIO9_IO01 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_02 0x1 SW_MUX_CTL_PAD_GPIO_AD_03 SW_MUX_CTL_PAD_GPIO_AD_03 SW MUX Control Register 0x118 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_EMVSIM1_SVEN Select mux mode: ALT0 mux port: EMVSIM1_SVEN of instance: EMVSIM1 0 ALT1_lpuart7_RTS_B Select mux mode: ALT1 mux port: LPUART7_RTS_B of instance: LPUART7 0x1 ALT2_enet_1g_1588_EVENT2_OUT Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT2_OUT of instance: ENET_1G 0x2 ALT3_gpt2_COMPARE2 Select mux mode: ALT3 mux port: GPT2_COMPARE2 of instance: GPT2 0x3 ALT4_flexpwm1_PWMB1 Select mux mode: ALT4 mux port: FLEXPWM1_PWM1_B of instance: FLEXPWM1 0x4 ALT5_gpio_mux3_IO2 Select mux mode: ALT5 mux port: GPIO_MUX3_IO02 of instance: GPIO_MUX3 0x5 ALT6_lpuart8_RX Select mux mode: ALT6 mux port: LPUART8_RXD of instance: LPUART8 0x6 ALT8_flexio2_FLEXIO3 Select mux mode: ALT8 mux port: FLEXIO2_D03 of instance: FLEXIO2 0x8 ALT9_video_mux_EXT_DCIC2 Select mux mode: ALT9 mux port: VIDEO_MUX_EXT_DCIC2 of instance: VIDEO_MUX 0x9 ALT10_gpio9_IO2 Select mux mode: ALT10 mux port: GPIO9_IO02 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_03 0x1 SW_MUX_CTL_PAD_GPIO_AD_04 SW_MUX_CTL_PAD_GPIO_AD_04 SW MUX Control Register 0x11C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_EMVSIM1_PD Select mux mode: ALT0 mux port: EMVSIM1_PD of instance: EMVSIM1 0 ALT1_lpuart8_CTS_B Select mux mode: ALT1 mux port: LPUART8_CTS_B of instance: LPUART8 0x1 ALT2_enet_1g_1588_EVENT3_IN Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT3_IN of instance: ENET_1G 0x2 ALT3_gpt2_COMPARE3 Select mux mode: ALT3 mux port: GPT2_COMPARE3 of instance: GPT2 0x3 ALT4_flexpwm1_PWMA2 Select mux mode: ALT4 mux port: FLEXPWM1_PWM2_A of instance: FLEXPWM1 0x4 ALT5_gpio_mux3_IO3 Select mux mode: ALT5 mux port: GPIO_MUX3_IO03 of instance: GPIO_MUX3 0x5 ALT6_WDOG1_B Select mux mode: ALT6 mux port: WDOG1_B of instance: WDOG1 0x6 ALT8_flexio2_FLEXIO4 Select mux mode: ALT8 mux port: FLEXIO2_D04 of instance: FLEXIO2 0x8 ALT9_qtimer4_TIMER0 Select mux mode: ALT9 mux port: TMR4_TIMER0 of instance: TMR4 0x9 ALT10_gpio9_IO3 Select mux mode: ALT10 mux port: GPIO9_IO03 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_04 0x1 SW_MUX_CTL_PAD_GPIO_AD_05 SW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control Register 0x120 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_EMVSIM1_POWER_FAIL Select mux mode: ALT0 mux port: EMVSIM1_POWER_FAIL of instance: EMVSIM1 0 ALT1_lpuart8_RTS_B Select mux mode: ALT1 mux port: LPUART8_RTS_B of instance: LPUART8 0x1 ALT2_enet_1g_1588_EVENT3_OUT Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT3_OUT of instance: ENET_1G 0x2 ALT3_gpt2_CLK Select mux mode: ALT3 mux port: GPT2_CLK of instance: GPT2 0x3 ALT4_flexpwm1_PWMB2 Select mux mode: ALT4 mux port: FLEXPWM1_PWM2_B of instance: FLEXPWM1 0x4 ALT5_gpio_mux3_IO4 Select mux mode: ALT5 mux port: GPIO_MUX3_IO04 of instance: GPIO_MUX3 0x5 ALT6_WDOG2_B Select mux mode: ALT6 mux port: WDOG2_B of instance: WDOG2 0x6 ALT8_flexio2_FLEXIO5 Select mux mode: ALT8 mux port: FLEXIO2_D05 of instance: FLEXIO2 0x8 ALT9_qtimer4_TIMER1 Select mux mode: ALT9 mux port: TMR4_TIMER1 of instance: TMR4 0x9 ALT10_gpio9_IO4 Select mux mode: ALT10 mux port: GPIO9_IO04 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_05 0x1 SW_MUX_CTL_PAD_GPIO_AD_06 SW_MUX_CTL_PAD_GPIO_AD_06 SW MUX Control Register 0x124 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usb_OTG2_OC Select mux mode: ALT0 mux port: USB_OTG2_OC of instance: USB 0 ALT1_can1_TX Select mux mode: ALT1 mux port: FLEXCAN1_TX of instance: FLEXCAN1 0x1 ALT2_EMVSIM2_TRXD Select mux mode: ALT2 mux port: EMVSIM2_IO of instance: EMVSIM2 0x2 ALT3_gpt3_CAPTURE1 Select mux mode: ALT3 mux port: GPT3_CAPTURE1 of instance: GPT3 0x3 ALT4_video_mux_CSI_DATA15 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA15 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO5 Select mux mode: ALT5 mux port: GPIO_MUX3_IO05 of instance: GPIO_MUX3 0x5 ALT6_enet_1588_EVENT1_IN Select mux mode: ALT6 mux port: ENET_1588_EVENT1_IN of instance: ENET 0x6 ALT8_flexio2_FLEXIO6 Select mux mode: ALT8 mux port: FLEXIO2_D06 of instance: FLEXIO2 0x8 ALT9_qtimer4_TIMER2 Select mux mode: ALT9 mux port: TMR4_TIMER2 of instance: TMR4 0x9 ALT10_gpio9_IO5 Select mux mode: ALT10 mux port: GPIO9_IO05 of instance: GPIO9 0xA ALT11_flexpwm1_PWMX0 Select mux mode: ALT11 mux port: FLEXPWM1_PWM0_X of instance: FLEXPWM1 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_06 0x1 SW_MUX_CTL_PAD_GPIO_AD_07 SW_MUX_CTL_PAD_GPIO_AD_07 SW MUX Control Register 0x128 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usb_OTG2_PWR Select mux mode: ALT0 mux port: USB_OTG2_PWR of instance: USB 0 ALT1_can1_RX Select mux mode: ALT1 mux port: FLEXCAN1_RX of instance: FLEXCAN1 0x1 ALT2_EMVSIM2_CLK Select mux mode: ALT2 mux port: EMVSIM2_CLK of instance: EMVSIM2 0x2 ALT3_gpt3_CAPTURE2 Select mux mode: ALT3 mux port: GPT3_CAPTURE2 of instance: GPT3 0x3 ALT4_video_mux_CSI_DATA14 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA14 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO6 Select mux mode: ALT5 mux port: GPIO_MUX3_IO06 of instance: GPIO_MUX3 0x5 ALT6_enet_1588_EVENT1_OUT Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: ENET 0x6 ALT8_flexio2_FLEXIO7 Select mux mode: ALT8 mux port: FLEXIO2_D07 of instance: FLEXIO2 0x8 ALT9_qtimer4_TIMER3 Select mux mode: ALT9 mux port: TMR4_TIMER3 of instance: TMR4 0x9 ALT10_gpio9_IO6 Select mux mode: ALT10 mux port: GPIO9_IO06 of instance: GPIO9 0xA ALT11_flexpwm1_PWMX1 Select mux mode: ALT11 mux port: FLEXPWM1_PWM1_X of instance: FLEXPWM1 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_07 0x1 SW_MUX_CTL_PAD_GPIO_AD_08 SW_MUX_CTL_PAD_GPIO_AD_08 SW MUX Control Register 0x12C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usbphy2_OTG_ID Select mux mode: ALT0 mux port: USBPHY2_OTG_ID of instance: USBPHY2 0 ALT1_lpi2c1_SCL Select mux mode: ALT1 mux port: LPI2C1_SCL of instance: LPI2C1 0x1 ALT2_EMVSIM2_RST_B Select mux mode: ALT2 mux port: EMVSIM2_RST of instance: EMVSIM2 0x2 ALT3_gpt3_COMPARE1 Select mux mode: ALT3 mux port: GPT3_COMPARE1 of instance: GPT3 0x3 ALT4_video_mux_CSI_DATA13 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA13 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO7 Select mux mode: ALT5 mux port: GPIO_MUX3_IO07 of instance: GPIO_MUX3 0x5 ALT6_enet_1588_EVENT2_IN Select mux mode: ALT6 mux port: ENET_1588_EVENT2_IN of instance: ENET 0x6 ALT8_flexio2_FLEXIO8 Select mux mode: ALT8 mux port: FLEXIO2_D08 of instance: FLEXIO2 0x8 ALT10_gpio9_IO7 Select mux mode: ALT10 mux port: GPIO9_IO07 of instance: GPIO9 0xA ALT11_flexpwm1_PWMX2 Select mux mode: ALT11 mux port: FLEXPWM1_PWM2_X of instance: FLEXPWM1 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_08 0x1 SW_MUX_CTL_PAD_GPIO_AD_09 SW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control Register 0x130 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usbphy1_OTG_ID Select mux mode: ALT0 mux port: USBPHY1_OTG_ID of instance: USBPHY1 0 ALT1_lpi2c1_SDA Select mux mode: ALT1 mux port: LPI2C1_SDA of instance: LPI2C1 0x1 ALT2_EMVSIM2_SVEN Select mux mode: ALT2 mux port: EMVSIM2_SVEN of instance: EMVSIM2 0x2 ALT3_gpt3_COMPARE2 Select mux mode: ALT3 mux port: GPT3_COMPARE2 of instance: GPT3 0x3 ALT4_video_mux_CSI_DATA12 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA12 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO8 Select mux mode: ALT5 mux port: GPIO_MUX3_IO08 of instance: GPIO_MUX3 0x5 ALT6_enet_1588_EVENT2_OUT Select mux mode: ALT6 mux port: ENET_1588_EVENT2_OUT of instance: ENET 0x6 ALT8_flexio2_FLEXIO9 Select mux mode: ALT8 mux port: FLEXIO2_D09 of instance: FLEXIO2 0x8 ALT10_gpio9_IO8 Select mux mode: ALT10 mux port: GPIO9_IO08 of instance: GPIO9 0xA ALT11_flexpwm1_PWMX3 Select mux mode: ALT11 mux port: FLEXPWM1_PWM3_X of instance: FLEXPWM1 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_09 0x1 SW_MUX_CTL_PAD_GPIO_AD_10 SW_MUX_CTL_PAD_GPIO_AD_10 SW MUX Control Register 0x134 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usb_OTG1_PWR Select mux mode: ALT0 mux port: USB_OTG1_PWR of instance: USB 0 ALT1_lpi2c1_SCLS Select mux mode: ALT1 mux port: LPI2C1_SCLS of instance: LPI2C1 0x1 ALT2_EMVSIM2_PD Select mux mode: ALT2 mux port: EMVSIM2_PD of instance: EMVSIM2 0x2 ALT3_gpt3_COMPARE3 Select mux mode: ALT3 mux port: GPT3_COMPARE3 of instance: GPT3 0x3 ALT4_video_mux_CSI_DATA11 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA11 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO9 Select mux mode: ALT5 mux port: GPIO_MUX3_IO09 of instance: GPIO_MUX3 0x5 ALT6_enet_1588_EVENT3_IN Select mux mode: ALT6 mux port: ENET_1588_EVENT3_IN of instance: ENET 0x6 ALT8_flexio2_FLEXIO10 Select mux mode: ALT8 mux port: FLEXIO2_D10 of instance: FLEXIO2 0x8 ALT10_gpio9_IO9 Select mux mode: ALT10 mux port: GPIO9_IO09 of instance: GPIO9 0xA ALT11_flexpwm2_PWMX0 Select mux mode: ALT11 mux port: FLEXPWM2_PWM0_X of instance: FLEXPWM2 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_10 0x1 SW_MUX_CTL_PAD_GPIO_AD_11 SW_MUX_CTL_PAD_GPIO_AD_11 SW MUX Control Register 0x138 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usb_OTG1_OC Select mux mode: ALT0 mux port: USB_OTG1_OC of instance: USB 0 ALT1_lpi2c1_SDAS Select mux mode: ALT1 mux port: LPI2C1_SDAS of instance: LPI2C1 0x1 ALT2_EMVSIM2_POWER_FAIL Select mux mode: ALT2 mux port: EMVSIM2_POWER_FAIL of instance: EMVSIM2 0x2 ALT3_gpt3_CLK Select mux mode: ALT3 mux port: GPT3_CLK of instance: GPT3 0x3 ALT4_video_mux_CSI_DATA10 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA10 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO10 Select mux mode: ALT5 mux port: GPIO_MUX3_IO10 of instance: GPIO_MUX3 0x5 ALT6_enet_1588_EVENT3_OUT Select mux mode: ALT6 mux port: ENET_1588_EVENT3_OUT of instance: ENET 0x6 ALT8_flexio2_FLEXIO11 Select mux mode: ALT8 mux port: FLEXIO2_D11 of instance: FLEXIO2 0x8 ALT10_gpio9_IO10 Select mux mode: ALT10 mux port: GPIO9_IO10 of instance: GPIO9 0xA ALT11_flexpwm2_PWMX1 Select mux mode: ALT11 mux port: FLEXPWM2_PWM1_X of instance: FLEXPWM2 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_11 0x1 SW_MUX_CTL_PAD_GPIO_AD_12 SW_MUX_CTL_PAD_GPIO_AD_12 SW MUX Control Register 0x13C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_spdif_LOCK Select mux mode: ALT0 mux port: SPDIF_LOCK of instance: SPDIF 0 ALT1_lpi2c1_HREQ Select mux mode: ALT1 mux port: LPI2C1_HREQ of instance: LPI2C1 0x1 ALT2_gpt1_CAPTURE1 Select mux mode: ALT2 mux port: GPT1_CAPTURE1 of instance: GPT1 0x2 ALT3_flexspi1_B_DATA3 Select mux mode: ALT3 mux port: FLEXSPI1_B_DATA03 of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_PIXCLK Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_PIXCLK of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO11 Select mux mode: ALT5 mux port: GPIO_MUX3_IO11 of instance: GPIO_MUX3 0x5 ALT6_ENET_TX_DATA3 Select mux mode: ALT6 mux port: ENET_TX_DATA03 of instance: ENET 0x6 ALT8_flexio2_FLEXIO12 Select mux mode: ALT8 mux port: FLEXIO2_D12 of instance: FLEXIO2 0x8 ALT9_EWM_OUT_B Select mux mode: ALT9 mux port: EWM_OUT_B of instance: EWM 0x9 ALT10_gpio9_IO11 Select mux mode: ALT10 mux port: GPIO9_IO11 of instance: GPIO9 0xA ALT11_flexpwm2_PWMX2 Select mux mode: ALT11 mux port: FLEXPWM2_PWM2_X of instance: FLEXPWM2 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_12 0x1 SW_MUX_CTL_PAD_GPIO_AD_13 SW_MUX_CTL_PAD_GPIO_AD_13 SW MUX Control Register 0x140 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_spdif_SR_CLK Select mux mode: ALT0 mux port: SPDIF_SR_CLK of instance: SPDIF 0 ALT1_pit1_TRIGGER0 Select mux mode: ALT1 mux port: PIT1_TRIGGER0 of instance: PIT1 0x1 ALT2_gpt1_CAPTURE2 Select mux mode: ALT2 mux port: GPT1_CAPTURE2 of instance: GPT1 0x2 ALT3_flexspi1_B_DATA2 Select mux mode: ALT3 mux port: FLEXSPI1_B_DATA02 of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_MCLK Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_MCLK of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO12 Select mux mode: ALT5 mux port: GPIO_MUX3_IO12 of instance: GPIO_MUX3 0x5 ALT6_ENET_TX_DATA2 Select mux mode: ALT6 mux port: ENET_TX_DATA02 of instance: ENET 0x6 ALT8_flexio2_FLEXIO13 Select mux mode: ALT8 mux port: FLEXIO2_D13 of instance: FLEXIO2 0x8 ALT9_anatop_32K_OUT Select mux mode: ALT9 mux port: REF_CLK_32K of instance: XTAL OSC 0x9 ALT10_gpio9_IO12 Select mux mode: ALT10 mux port: GPIO9_IO12 of instance: GPIO9 0xA ALT11_flexpwm2_PWMX3 Select mux mode: ALT11 mux port: FLEXPWM2_PWM3_X of instance: FLEXPWM2 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_13 0x1 SW_MUX_CTL_PAD_GPIO_AD_14 SW_MUX_CTL_PAD_GPIO_AD_14 SW MUX Control Register 0x144 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_spdif_EXT_CLK Select mux mode: ALT0 mux port: SPDIF_EXT_CLK of instance: SPDIF 0 ALT1_anatop_24M_OUT Select mux mode: ALT1 mux port: REF_CLK_24M of instance: XTAL OSC 0x1 ALT2_gpt1_COMPARE1 Select mux mode: ALT2 mux port: GPT1_COMPARE1 of instance: GPT1 0x2 ALT3_flexspi1_B_DATA1 Select mux mode: ALT3 mux port: FLEXSPI1_B_DATA01 of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_VSYNC Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_VSYNC of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO13 Select mux mode: ALT5 mux port: GPIO_MUX3_IO13 of instance: GPIO_MUX3 0x5 ALT6_enet_RX_CLK Select mux mode: ALT6 mux port: ENET_RX_CLK of instance: ENET 0x6 ALT8_flexio2_FLEXIO14 Select mux mode: ALT8 mux port: FLEXIO2_D14 of instance: FLEXIO2 0x8 ALT9_CCM_ENET_REF_CLK_25M Select mux mode: ALT9 mux port: CCM_ENET_REF_CLK_25M of instance: CCM 0x9 ALT10_gpio9_IO13 Select mux mode: ALT10 mux port: GPIO9_IO13 of instance: GPIO9 0xA ALT11_flexpwm3_PWMX0 Select mux mode: ALT11 mux port: FLEXPWM3_PWM0_X of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_14 0x1 SW_MUX_CTL_PAD_GPIO_AD_15 SW_MUX_CTL_PAD_GPIO_AD_15 SW MUX Control Register 0x148 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_spdif_IN Select mux mode: ALT0 mux port: SPDIF_IN of instance: SPDIF 0 ALT1_lpuart10_TX Select mux mode: ALT1 mux port: LPUART10_TXD of instance: LPUART10 0x1 ALT2_gpt1_COMPARE2 Select mux mode: ALT2 mux port: GPT1_COMPARE2 of instance: GPT1 0x2 ALT3_flexspi1_B_DATA0 Select mux mode: ALT3 mux port: FLEXSPI1_B_DATA00 of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_HSYNC Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_HSYNC of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO14 Select mux mode: ALT5 mux port: GPIO_MUX3_IO14 of instance: GPIO_MUX3 0x5 ALT6_enet_TX_ER Select mux mode: ALT6 mux port: ENET_TX_ER of instance: ENET 0x6 ALT8_flexio2_FLEXIO15 Select mux mode: ALT8 mux port: FLEXIO2_D15 of instance: FLEXIO2 0x8 ALT10_gpio9_IO14 Select mux mode: ALT10 mux port: GPIO9_IO14 of instance: GPIO9 0xA ALT11_flexpwm3_PWMX1 Select mux mode: ALT11 mux port: FLEXPWM3_PWM1_X of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_15 0x1 SW_MUX_CTL_PAD_GPIO_AD_16 SW_MUX_CTL_PAD_GPIO_AD_16 SW MUX Control Register 0x14C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_spdif_OUT Select mux mode: ALT0 mux port: SPDIF_OUT of instance: SPDIF 0 ALT1_lpuart10_RX Select mux mode: ALT1 mux port: LPUART10_RXD of instance: LPUART10 0x1 ALT2_gpt1_COMPARE3 Select mux mode: ALT2 mux port: GPT1_COMPARE3 of instance: GPT1 0x2 ALT3_flexspi1_B_SCLK Select mux mode: ALT3 mux port: FLEXSPI1_B_SCLK of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_DATA9 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA09 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO15 Select mux mode: ALT5 mux port: GPIO_MUX3_IO15 of instance: GPIO_MUX3 0x5 ALT6_ENET_RX_DATA3 Select mux mode: ALT6 mux port: ENET_RX_DATA03 of instance: ENET 0x6 ALT8_flexio2_FLEXIO16 Select mux mode: ALT8 mux port: FLEXIO2_D16 of instance: FLEXIO2 0x8 ALT9_enet_1g_MDC Select mux mode: ALT9 mux port: ENET_1G_MDC of instance: ENET_1G 0x9 ALT10_gpio9_IO15 Select mux mode: ALT10 mux port: GPIO9_IO15 of instance: GPIO9 0xA ALT11_flexpwm3_PWMX2 Select mux mode: ALT11 mux port: FLEXPWM3_PWM2_X of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_16 0x1 SW_MUX_CTL_PAD_GPIO_AD_17 SW_MUX_CTL_PAD_GPIO_AD_17 SW MUX Control Register 0x150 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_sai1_MCLK Select mux mode: ALT0 mux port: SAI1_MCLK of instance: SAI1 0 ALT1_ACMP1_OUT Select mux mode: ALT1 mux port: ACMP1_OUT of instance: ACMP1 0x1 ALT2_gpt1_CLK Select mux mode: ALT2 mux port: GPT1_CLK of instance: GPT1 0x2 ALT3_flexspi1_A_DQS Select mux mode: ALT3 mux port: FLEXSPI1_A_DQS of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_DATA8 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA08 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO16 Select mux mode: ALT5 mux port: GPIO_MUX3_IO16 of instance: GPIO_MUX3 0x5 ALT6_ENET_RX_DATA2 Select mux mode: ALT6 mux port: ENET_RX_DATA02 of instance: ENET 0x6 ALT8_flexio2_FLEXIO17 Select mux mode: ALT8 mux port: FLEXIO2_D17 of instance: FLEXIO2 0x8 ALT9_enet_1g_MDIO Select mux mode: ALT9 mux port: ENET_1G_MDIO of instance: ENET_1G 0x9 ALT10_gpio9_IO16 Select mux mode: ALT10 mux port: GPIO9_IO16 of instance: GPIO9 0xA ALT11_flexpwm3_PWMX3 Select mux mode: ALT11 mux port: FLEXPWM3_PWM3_X of instance: FLEXPWM3 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_17 0x1 SW_MUX_CTL_PAD_GPIO_AD_18 SW_MUX_CTL_PAD_GPIO_AD_18 SW MUX Control Register 0x154 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_sai1_RX_SYNC Select mux mode: ALT0 mux port: SAI1_RX_SYNC of instance: SAI1 0 ALT1_ACMP2_OUT Select mux mode: ALT1 mux port: ACMP2_OUT of instance: ACMP2 0x1 ALT2_lpspi1_PCS1 Select mux mode: ALT2 mux port: LPSPI1_PCS1 of instance: LPSPI1 0x2 ALT3_flexspi1_A_SS0_B Select mux mode: ALT3 mux port: FLEXSPI1_A_SS0_B of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_DATA7 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA07 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO17 Select mux mode: ALT5 mux port: GPIO_MUX3_IO17 of instance: GPIO_MUX3 0x5 ALT6_enet_CRS Select mux mode: ALT6 mux port: ENET_CRS of instance: ENET 0x6 ALT8_flexio2_FLEXIO18 Select mux mode: ALT8 mux port: FLEXIO2_D18 of instance: FLEXIO2 0x8 ALT9_lpi2c2_SCL Select mux mode: ALT9 mux port: LPI2C2_SCL of instance: LPI2C2 0x9 ALT10_gpio9_IO17 Select mux mode: ALT10 mux port: GPIO9_IO17 of instance: GPIO9 0xA ALT11_flexpwm4_PWMX0 Select mux mode: ALT11 mux port: FLEXPWM4_PWM0_X of instance: FLEXPWM4 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_18 0x1 SW_MUX_CTL_PAD_GPIO_AD_19 SW_MUX_CTL_PAD_GPIO_AD_19 SW MUX Control Register 0x158 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_sai1_RX_BCLK Select mux mode: ALT0 mux port: SAI1_RX_BCLK of instance: SAI1 0 ALT1_ACMP3_OUT Select mux mode: ALT1 mux port: ACMP3_OUT of instance: ACMP3 0x1 ALT2_lpspi1_PCS2 Select mux mode: ALT2 mux port: LPSPI1_PCS2 of instance: LPSPI1 0x2 ALT3_flexspi1_A_SCLK Select mux mode: ALT3 mux port: FLEXSPI1_A_SCLK of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_DATA6 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA06 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO18 Select mux mode: ALT5 mux port: GPIO_MUX3_IO18 of instance: GPIO_MUX3 0x5 ALT6_enet_COL Select mux mode: ALT6 mux port: ENET_COL of instance: ENET 0x6 ALT8_flexio2_FLEXIO19 Select mux mode: ALT8 mux port: FLEXIO2_D19 of instance: FLEXIO2 0x8 ALT9_lpi2c2_SDA Select mux mode: ALT9 mux port: LPI2C2_SDA of instance: LPI2C2 0x9 ALT10_gpio9_IO18 Select mux mode: ALT10 mux port: GPIO9_IO18 of instance: GPIO9 0xA ALT11_flexpwm4_PWMX1 Select mux mode: ALT11 mux port: FLEXPWM4_PWM1_X of instance: FLEXPWM4 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_19 0x1 SW_MUX_CTL_PAD_GPIO_AD_20 SW_MUX_CTL_PAD_GPIO_AD_20 SW MUX Control Register 0x15C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_sai1_RX_DATA0 Select mux mode: ALT0 mux port: SAI1_RX_DATA00 of instance: SAI1 0 ALT1_ACMP4_OUT Select mux mode: ALT1 mux port: ACMP4_OUT of instance: ACMP4 0x1 ALT2_lpspi1_PCS3 Select mux mode: ALT2 mux port: LPSPI1_PCS3 of instance: LPSPI1 0x2 ALT3_flexspi1_A_DATA0 Select mux mode: ALT3 mux port: FLEXSPI1_A_DATA00 of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_DATA5 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA05 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO19 Select mux mode: ALT5 mux port: GPIO_MUX3_IO19 of instance: GPIO_MUX3 0x5 ALT6_kpp_ROW7 Select mux mode: ALT6 mux port: KPP_ROW07 of instance: KPP 0x6 ALT8_flexio2_FLEXIO20 Select mux mode: ALT8 mux port: FLEXIO2_D20 of instance: FLEXIO2 0x8 ALT9_enet_qos_1588_EVENT2_OUT Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT2_OUT of instance: ENET_QOS 0x9 ALT10_gpio9_IO19 Select mux mode: ALT10 mux port: GPIO9_IO19 of instance: GPIO9 0xA ALT11_flexpwm4_PWMX2 Select mux mode: ALT11 mux port: FLEXPWM4_PWM2_X of instance: FLEXPWM4 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_20 0x1 SW_MUX_CTL_PAD_GPIO_AD_21 SW_MUX_CTL_PAD_GPIO_AD_21 SW MUX Control Register 0x160 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_sai1_TX_DATA0 Select mux mode: ALT0 mux port: SAI1_TX_DATA00 of instance: SAI1 0 ALT2_lpspi2_PCS1 Select mux mode: ALT2 mux port: LPSPI2_PCS1 of instance: LPSPI2 0x2 ALT3_flexspi1_A_DATA1 Select mux mode: ALT3 mux port: FLEXSPI1_A_DATA01 of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_DATA4 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA04 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO20 Select mux mode: ALT5 mux port: GPIO_MUX3_IO20 of instance: GPIO_MUX3 0x5 ALT6_kpp_COL7 Select mux mode: ALT6 mux port: KPP_COL07 of instance: KPP 0x6 ALT8_flexio2_FLEXIO21 Select mux mode: ALT8 mux port: FLEXIO2_D21 of instance: FLEXIO2 0x8 ALT9_enet_qos_1588_EVENT2_IN Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT2_IN of instance: ENET_QOS 0x9 ALT10_gpio9_IO20 Select mux mode: ALT10 mux port: GPIO9_IO20 of instance: GPIO9 0xA ALT11_flexpwm4_PWMX3 Select mux mode: ALT11 mux port: FLEXPWM4_PWM3_X of instance: FLEXPWM4 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_21 0x1 SW_MUX_CTL_PAD_GPIO_AD_22 SW_MUX_CTL_PAD_GPIO_AD_22 SW MUX Control Register 0x164 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_sai1_TX_BCLK Select mux mode: ALT0 mux port: SAI1_TX_BCLK of instance: SAI1 0 ALT2_lpspi2_PCS2 Select mux mode: ALT2 mux port: LPSPI2_PCS2 of instance: LPSPI2 0x2 ALT3_flexspi1_A_DATA2 Select mux mode: ALT3 mux port: FLEXSPI1_A_DATA02 of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_DATA3 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA03 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO21 Select mux mode: ALT5 mux port: GPIO_MUX3_IO21 of instance: GPIO_MUX3 0x5 ALT6_kpp_ROW6 Select mux mode: ALT6 mux port: KPP_ROW06 of instance: KPP 0x6 ALT8_flexio2_FLEXIO22 Select mux mode: ALT8 mux port: FLEXIO2_D22 of instance: FLEXIO2 0x8 ALT9_enet_qos_1588_EVENT3_OUT Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT3_OUT of instance: ENET_QOS 0x9 ALT10_gpio9_IO21 Select mux mode: ALT10 mux port: GPIO9_IO21 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_22 0x1 SW_MUX_CTL_PAD_GPIO_AD_23 SW_MUX_CTL_PAD_GPIO_AD_23 SW MUX Control Register 0x168 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_sai1_TX_SYNC Select mux mode: ALT0 mux port: SAI1_TX_SYNC of instance: SAI1 0 ALT2_lpspi2_PCS3 Select mux mode: ALT2 mux port: LPSPI2_PCS3 of instance: LPSPI2 0x2 ALT3_flexspi1_A_DATA3 Select mux mode: ALT3 mux port: FLEXSPI1_A_DATA03 of instance: FLEXSPI1 0x3 ALT4_video_mux_CSI_DATA2 Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA02 of instance: VIDEO_MUX 0x4 ALT5_gpio_mux3_IO22 Select mux mode: ALT5 mux port: GPIO_MUX3_IO22 of instance: GPIO_MUX3 0x5 ALT6_kpp_COL6 Select mux mode: ALT6 mux port: KPP_COL06 of instance: KPP 0x6 ALT8_flexio2_FLEXIO23 Select mux mode: ALT8 mux port: FLEXIO2_D23 of instance: FLEXIO2 0x8 ALT9_enet_qos_1588_EVENT3_IN Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT3_IN of instance: ENET_QOS 0x9 ALT10_gpio9_IO22 Select mux mode: ALT10 mux port: GPIO9_IO22 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_23 0x1 SW_MUX_CTL_PAD_GPIO_AD_24 SW_MUX_CTL_PAD_GPIO_AD_24 SW MUX Control Register 0x16C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpuart1_TX Select mux mode: ALT0 mux port: LPUART1_TXD of instance: LPUART1 0 ALT1_lpspi2_SCK Select mux mode: ALT1 mux port: LPSPI2_SCK of instance: LPSPI2 0x1 ALT2_video_mux_CSI_DATA0 Select mux mode: ALT2 mux port: VIDEO_MUX_CSI_DATA00 of instance: VIDEO_MUX 0x2 ALT3_enet_RX_EN Select mux mode: ALT3 mux port: ENET_RX_EN of instance: ENET 0x3 ALT4_flexpwm2_PWMA0 Select mux mode: ALT4 mux port: FLEXPWM2_PWM0_A of instance: FLEXPWM2 0x4 ALT5_gpio_mux3_IO23 Select mux mode: ALT5 mux port: GPIO_MUX3_IO23 of instance: GPIO_MUX3 0x5 ALT6_kpp_ROW5 Select mux mode: ALT6 mux port: KPP_ROW05 of instance: KPP 0x6 ALT8_flexio2_FLEXIO24 Select mux mode: ALT8 mux port: FLEXIO2_D24 of instance: FLEXIO2 0x8 ALT9_lpi2c4_SCL Select mux mode: ALT9 mux port: LPI2C4_SCL of instance: LPI2C4 0x9 ALT10_gpio9_IO23 Select mux mode: ALT10 mux port: GPIO9_IO23 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_24 0x1 SW_MUX_CTL_PAD_GPIO_AD_25 SW_MUX_CTL_PAD_GPIO_AD_25 SW MUX Control Register 0x170 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpuart1_RX Select mux mode: ALT0 mux port: LPUART1_RXD of instance: LPUART1 0 ALT1_lpspi2_PCS0 Select mux mode: ALT1 mux port: LPSPI2_PCS0 of instance: LPSPI2 0x1 ALT2_video_mux_CSI_DATA1 Select mux mode: ALT2 mux port: VIDEO_MUX_CSI_DATA01 of instance: VIDEO_MUX 0x2 ALT3_enet_RX_ER Select mux mode: ALT3 mux port: ENET_RX_ER of instance: ENET 0x3 ALT4_flexpwm2_PWMB0 Select mux mode: ALT4 mux port: FLEXPWM2_PWM0_B of instance: FLEXPWM2 0x4 ALT5_gpio_mux3_IO24 Select mux mode: ALT5 mux port: GPIO_MUX3_IO24 of instance: GPIO_MUX3 0x5 ALT6_kpp_COL5 Select mux mode: ALT6 mux port: KPP_COL05 of instance: KPP 0x6 ALT8_flexio2_FLEXIO25 Select mux mode: ALT8 mux port: FLEXIO2_D25 of instance: FLEXIO2 0x8 ALT9_lpi2c4_SDA Select mux mode: ALT9 mux port: LPI2C4_SDA of instance: LPI2C4 0x9 ALT10_gpio9_IO24 Select mux mode: ALT10 mux port: GPIO9_IO24 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_25 0x1 SW_MUX_CTL_PAD_GPIO_AD_26 SW_MUX_CTL_PAD_GPIO_AD_26 SW MUX Control Register 0x174 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpuart1_CTS_B Select mux mode: ALT0 mux port: LPUART1_CTS_B of instance: LPUART1 0 ALT1_lpspi2_SDO Select mux mode: ALT1 mux port: LPSPI2_SOUT of instance: LPSPI2 0x1 ALT2_semc_CSX1 Select mux mode: ALT2 mux port: SEMC_CSX01 of instance: SEMC 0x2 ALT3_ENET_RX_DATA0 Select mux mode: ALT3 mux port: ENET_RX_DATA00 of instance: ENET 0x3 ALT4_flexpwm2_PWMA1 Select mux mode: ALT4 mux port: FLEXPWM2_PWM1_A of instance: FLEXPWM2 0x4 ALT5_gpio_mux3_IO25 Select mux mode: ALT5 mux port: GPIO_MUX3_IO25 of instance: GPIO_MUX3 0x5 ALT6_kpp_ROW4 Select mux mode: ALT6 mux port: KPP_ROW04 of instance: KPP 0x6 ALT8_flexio2_FLEXIO26 Select mux mode: ALT8 mux port: FLEXIO2_D26 of instance: FLEXIO2 0x8 ALT9_enet_qos_MDC Select mux mode: ALT9 mux port: ENET_QOS_MDC of instance: ENET_QOS 0x9 ALT10_gpio9_IO25 Select mux mode: ALT10 mux port: GPIO9_IO25 of instance: GPIO9 0xA ALT11_usdhc2_CD_B Select mux mode: ALT11 mux port: USDHC2_CD_B of instance: USDHC2 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_26 0x1 SW_MUX_CTL_PAD_GPIO_AD_27 SW_MUX_CTL_PAD_GPIO_AD_27 SW MUX Control Register 0x178 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpuart1_RTS_B Select mux mode: ALT0 mux port: LPUART1_RTS_B of instance: LPUART1 0 ALT1_lpspi2_SDI Select mux mode: ALT1 mux port: LPSPI2_SIN of instance: LPSPI2 0x1 ALT2_semc_CSX2 Select mux mode: ALT2 mux port: SEMC_CSX02 of instance: SEMC 0x2 ALT3_ENET_RX_DATA1 Select mux mode: ALT3 mux port: ENET_RX_DATA01 of instance: ENET 0x3 ALT4_flexpwm2_PWMB1 Select mux mode: ALT4 mux port: FLEXPWM2_PWM1_B of instance: FLEXPWM2 0x4 ALT5_gpio_mux3_IO26 Select mux mode: ALT5 mux port: GPIO_MUX3_IO26 of instance: GPIO_MUX3 0x5 ALT6_kpp_COL4 Select mux mode: ALT6 mux port: KPP_COL04 of instance: KPP 0x6 ALT8_flexio2_FLEXIO27 Select mux mode: ALT8 mux port: FLEXIO2_D27 of instance: FLEXIO2 0x8 ALT9_enet_qos_MDIO Select mux mode: ALT9 mux port: ENET_QOS_MDIO of instance: ENET_QOS 0x9 ALT10_gpio9_IO26 Select mux mode: ALT10 mux port: GPIO9_IO26 of instance: GPIO9 0xA ALT11_usdhc2_WP Select mux mode: ALT11 mux port: USDHC2_WP of instance: USDHC2 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_27 0x1 SW_MUX_CTL_PAD_GPIO_AD_28 SW_MUX_CTL_PAD_GPIO_AD_28 SW MUX Control Register 0x17C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpspi1_SCK Select mux mode: ALT0 mux port: LPSPI1_SCK of instance: LPSPI1 0 ALT1_lpuart5_TX Select mux mode: ALT1 mux port: LPUART5_TXD of instance: LPUART5 0x1 ALT2_semc_CSX3 Select mux mode: ALT2 mux port: SEMC_CSX03 of instance: SEMC 0x2 ALT3_enet_TX_EN Select mux mode: ALT3 mux port: ENET_TX_EN of instance: ENET 0x3 ALT4_flexpwm2_PWMA2 Select mux mode: ALT4 mux port: FLEXPWM2_PWM2_A of instance: FLEXPWM2 0x4 ALT5_gpio_mux3_IO27 Select mux mode: ALT5 mux port: GPIO_MUX3_IO27 of instance: GPIO_MUX3 0x5 ALT6_kpp_ROW3 Select mux mode: ALT6 mux port: KPP_ROW03 of instance: KPP 0x6 ALT8_flexio2_FLEXIO28 Select mux mode: ALT8 mux port: FLEXIO2_D28 of instance: FLEXIO2 0x8 ALT9_video_mux_EXT_DCIC1 Select mux mode: ALT9 mux port: VIDEO_MUX_EXT_DCIC1 of instance: VIDEO_MUX 0x9 ALT10_gpio9_IO27 Select mux mode: ALT10 mux port: GPIO9_IO27 of instance: GPIO9 0xA ALT11_usdhc2_VSELECT Select mux mode: ALT11 mux port: USDHC2_VSELECT of instance: USDHC2 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_28 0x1 SW_MUX_CTL_PAD_GPIO_AD_29 SW_MUX_CTL_PAD_GPIO_AD_29 SW MUX Control Register 0x180 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpspi1_PCS0 Select mux mode: ALT0 mux port: LPSPI1_PCS0 of instance: LPSPI1 0 ALT1_lpuart5_RX Select mux mode: ALT1 mux port: LPUART5_RXD of instance: LPUART5 0x1 ALT2_enet_REF_CLK Select mux mode: ALT2 mux port: ENET_REF_CLK of instance: ENET 0x2 ALT3_enet_TX_CLK Select mux mode: ALT3 mux port: ENET_TX_CLK of instance: ENET 0x3 ALT4_flexpwm2_PWMB2 Select mux mode: ALT4 mux port: FLEXPWM2_PWM2_B of instance: FLEXPWM2 0x4 ALT5_gpio_mux3_IO28 Select mux mode: ALT5 mux port: GPIO_MUX3_IO28 of instance: GPIO_MUX3 0x5 ALT6_kpp_COL3 Select mux mode: ALT6 mux port: KPP_COL03 of instance: KPP 0x6 ALT8_flexio2_FLEXIO29 Select mux mode: ALT8 mux port: FLEXIO2_D29 of instance: FLEXIO2 0x8 ALT9_video_mux_EXT_DCIC2 Select mux mode: ALT9 mux port: VIDEO_MUX_EXT_DCIC2 of instance: VIDEO_MUX 0x9 ALT10_gpio9_IO28 Select mux mode: ALT10 mux port: GPIO9_IO28 of instance: GPIO9 0xA ALT11_usdhc2_RESET_B Select mux mode: ALT11 mux port: USDHC2_RESET_B of instance: USDHC2 0xB SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_29 0x1 SW_MUX_CTL_PAD_GPIO_AD_30 SW_MUX_CTL_PAD_GPIO_AD_30 SW MUX Control Register 0x184 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpspi1_SDO Select mux mode: ALT0 mux port: LPSPI1_SOUT of instance: LPSPI1 0 ALT1_usb_OTG2_OC Select mux mode: ALT1 mux port: USB_OTG2_OC of instance: USB 0x1 ALT2_can2_TX Select mux mode: ALT2 mux port: FLEXCAN2_TX of instance: FLEXCAN2 0x2 ALT3_ENET_TX_DATA0 Select mux mode: ALT3 mux port: ENET_TX_DATA00 of instance: ENET 0x3 ALT4_lpuart3_TX Select mux mode: ALT4 mux port: LPUART3_TXD of instance: LPUART3 0x4 ALT5_gpio_mux3_IO29 Select mux mode: ALT5 mux port: GPIO_MUX3_IO29 of instance: GPIO_MUX3 0x5 ALT6_kpp_ROW2 Select mux mode: ALT6 mux port: KPP_ROW02 of instance: KPP 0x6 ALT8_flexio2_FLEXIO30 Select mux mode: ALT8 mux port: FLEXIO2_D30 of instance: FLEXIO2 0x8 ALT9_WDOG2_RESET_B_DEB Select mux mode: ALT9 mux port: WDOG2_RESET_B_DEB of instance: WDOG2 0x9 ALT10_gpio9_IO29 Select mux mode: ALT10 mux port: GPIO9_IO29 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_30 0x1 SW_MUX_CTL_PAD_GPIO_AD_31 SW_MUX_CTL_PAD_GPIO_AD_31 SW MUX Control Register 0x188 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpspi1_SDI Select mux mode: ALT0 mux port: LPSPI1_SIN of instance: LPSPI1 0 ALT1_usb_OTG2_PWR Select mux mode: ALT1 mux port: USB_OTG2_PWR of instance: USB 0x1 ALT2_can2_RX Select mux mode: ALT2 mux port: FLEXCAN2_RX of instance: FLEXCAN2 0x2 ALT3_ENET_TX_DATA1 Select mux mode: ALT3 mux port: ENET_TX_DATA01 of instance: ENET 0x3 ALT4_lpuart3_RX Select mux mode: ALT4 mux port: LPUART3_RXD of instance: LPUART3 0x4 ALT5_gpio_mux3_IO30 Select mux mode: ALT5 mux port: GPIO_MUX3_IO30 of instance: GPIO_MUX3 0x5 ALT6_kpp_COL2 Select mux mode: ALT6 mux port: KPP_COL02 of instance: KPP 0x6 ALT8_flexio2_FLEXIO31 Select mux mode: ALT8 mux port: FLEXIO2_D31 of instance: FLEXIO2 0x8 ALT9_WDOG1_RESET_B_DEB Select mux mode: ALT9 mux port: WDOG1_RESET_B_DEB of instance: WDOG1 0x9 ALT10_gpio9_IO30 Select mux mode: ALT10 mux port: GPIO9_IO30 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_31 0x1 SW_MUX_CTL_PAD_GPIO_AD_32 SW_MUX_CTL_PAD_GPIO_AD_32 SW MUX Control Register 0x18C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpi2c1_SCL Select mux mode: ALT0 mux port: LPI2C1_SCL of instance: LPI2C1 0 ALT1_usbphy2_OTG_ID Select mux mode: ALT1 mux port: USBPHY2_OTG_ID of instance: USBPHY2 0x1 ALT2_pgmc_PMIC_RDY Select mux mode: ALT2 mux port: PGMC_PMIC_RDY of instance: pgmc 0x2 ALT3_enet_MDC Select mux mode: ALT3 mux port: ENET_MDC of instance: ENET 0x3 ALT4_usdhc1_CD_B Select mux mode: ALT4 mux port: USDHC1_CD_B of instance: USDHC1 0x4 ALT5_gpio_mux3_IO31 Select mux mode: ALT5 mux port: GPIO_MUX3_IO31 of instance: GPIO_MUX3 0x5 ALT6_kpp_ROW1 Select mux mode: ALT6 mux port: KPP_ROW01 of instance: KPP 0x6 ALT8_lpuart10_TX Select mux mode: ALT8 mux port: LPUART10_TXD of instance: LPUART10 0x8 ALT9_enet_1g_MDC Select mux mode: ALT9 mux port: ENET_1G_MDC of instance: ENET_1G 0x9 ALT10_gpio9_IO31 Select mux mode: ALT10 mux port: GPIO9_IO31 of instance: GPIO9 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_32 0x1 SW_MUX_CTL_PAD_GPIO_AD_33 SW_MUX_CTL_PAD_GPIO_AD_33 SW MUX Control Register 0x190 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpi2c1_SDA Select mux mode: ALT0 mux port: LPI2C1_SDA of instance: LPI2C1 0 ALT1_usbphy1_OTG_ID Select mux mode: ALT1 mux port: USBPHY1_OTG_ID of instance: USBPHY1 0x1 ALT2_XBAR1_INOUT17 Select mux mode: ALT2 mux port: XBAR1_INOUT17 of instance: XBAR1 0x2 ALT3_enet_MDIO Select mux mode: ALT3 mux port: ENET_MDIO of instance: ENET 0x3 ALT4_usdhc1_WP Select mux mode: ALT4 mux port: USDHC1_WP of instance: USDHC1 0x4 ALT5_gpio_mux4_IO0 Select mux mode: ALT5 mux port: GPIO_MUX4_IO00 of instance: GPIO_MUX4 0x5 ALT6_kpp_COL1 Select mux mode: ALT6 mux port: KPP_COL01 of instance: KPP 0x6 ALT8_lpuart10_RX Select mux mode: ALT8 mux port: LPUART10_RXD of instance: LPUART10 0x8 ALT9_enet_1g_MDIO Select mux mode: ALT9 mux port: ENET_1G_MDIO of instance: ENET_1G 0x9 ALT10_gpio10_IO0 Select mux mode: ALT10 mux port: GPIO10_IO00 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_33 0x1 SW_MUX_CTL_PAD_GPIO_AD_34 SW_MUX_CTL_PAD_GPIO_AD_34 SW MUX Control Register 0x194 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_enet_1g_1588_EVENT0_IN Select mux mode: ALT0 mux port: ENET_1G_1588_EVENT0_IN of instance: ENET_1G 0 ALT1_usb_OTG1_PWR Select mux mode: ALT1 mux port: USB_OTG1_PWR of instance: USB 0x1 ALT2_XBAR1_INOUT18 Select mux mode: ALT2 mux port: XBAR1_INOUT18 of instance: XBAR1 0x2 ALT3_enet_1588_EVENT0_IN Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: ENET 0x3 ALT4_usdhc1_VSELECT Select mux mode: ALT4 mux port: USDHC1_VSELECT of instance: USDHC1 0x4 ALT5_gpio_mux4_IO1 Select mux mode: ALT5 mux port: GPIO_MUX4_IO01 of instance: GPIO_MUX4 0x5 ALT6_kpp_ROW0 Select mux mode: ALT6 mux port: KPP_ROW00 of instance: KPP 0x6 ALT8_lpuart10_CTS_B Select mux mode: ALT8 mux port: LPUART10_CTS_B of instance: LPUART10 0x8 ALT9_WDOG1_ANY Select mux mode: ALT9 mux port: WDOG1_ANY of instance: WDOG1 0x9 ALT10_gpio10_IO1 Select mux mode: ALT10 mux port: GPIO10_IO01 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_34 0x1 SW_MUX_CTL_PAD_GPIO_AD_35 SW_MUX_CTL_PAD_GPIO_AD_35 SW MUX Control Register 0x198 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_enet_1g_1588_EVENT0_OUT Select mux mode: ALT0 mux port: ENET_1G_1588_EVENT0_OUT of instance: ENET_1G 0 ALT1_usb_OTG1_OC Select mux mode: ALT1 mux port: USB_OTG1_OC of instance: USB 0x1 ALT2_XBAR1_INOUT19 Select mux mode: ALT2 mux port: XBAR1_INOUT19 of instance: XBAR1 0x2 ALT3_enet_1588_EVENT0_OUT Select mux mode: ALT3 mux port: ENET_1588_EVENT0_OUT of instance: ENET 0x3 ALT4_usdhc1_RESET_B Select mux mode: ALT4 mux port: USDHC1_RESET_B of instance: USDHC1 0x4 ALT5_gpio_mux4_IO2 Select mux mode: ALT5 mux port: GPIO_MUX4_IO02 of instance: GPIO_MUX4 0x5 ALT6_kpp_COL0 Select mux mode: ALT6 mux port: KPP_COL00 of instance: KPP 0x6 ALT8_lpuart10_RTS_B Select mux mode: ALT8 mux port: LPUART10_RTS_B of instance: LPUART10 0x8 ALT9_flexspi1_B_SS1_B Select mux mode: ALT9 mux port: FLEXSPI1_B_SS1_B of instance: FLEXSPI1 0x9 ALT10_gpio10_IO2 Select mux mode: ALT10 mux port: GPIO10_IO02 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_35 0x1 SW_MUX_CTL_PAD_GPIO_SD_B1_00 SW_MUX_CTL_PAD_GPIO_SD_B1_00 SW MUX Control Register 0x19C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc1_CMD Select mux mode: ALT0 mux port: USDHC1_CMD of instance: USDHC1 0 ALT2_XBAR1_INOUT20 Select mux mode: ALT2 mux port: XBAR1_INOUT20 of instance: XBAR1 0x2 ALT3_gpt4_CAPTURE1 Select mux mode: ALT3 mux port: GPT4_CAPTURE1 of instance: GPT4 0x3 ALT5_gpio_mux4_IO3 Select mux mode: ALT5 mux port: GPIO_MUX4_IO03 of instance: GPIO_MUX4 0x5 ALT6_flexspi2_A_SS0_B Select mux mode: ALT6 mux port: FLEXSPI2_A_SS0_B of instance: FLEXSPI2 0x6 ALT8_kpp_ROW7 Select mux mode: ALT8 mux port: KPP_ROW07 of instance: KPP 0x8 ALT10_gpio10_IO3 Select mux mode: ALT10 mux port: GPIO10_IO03 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B1_00 0x1 SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW MUX Control Register 0x1A0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc1_CLK Select mux mode: ALT0 mux port: USDHC1_CLK of instance: USDHC1 0 ALT2_XBAR1_INOUT21 Select mux mode: ALT2 mux port: XBAR1_INOUT21 of instance: XBAR1 0x2 ALT3_gpt4_CAPTURE2 Select mux mode: ALT3 mux port: GPT4_CAPTURE2 of instance: GPT4 0x3 ALT5_gpio_mux4_IO4 Select mux mode: ALT5 mux port: GPIO_MUX4_IO04 of instance: GPIO_MUX4 0x5 ALT6_flexspi2_A_SCLK Select mux mode: ALT6 mux port: FLEXSPI2_A_SCLK of instance: FLEXSPI2 0x6 ALT8_kpp_COL7 Select mux mode: ALT8 mux port: KPP_COL07 of instance: KPP 0x8 ALT10_gpio10_IO4 Select mux mode: ALT10 mux port: GPIO10_IO04 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B1_01 0x1 SW_MUX_CTL_PAD_GPIO_SD_B1_02 SW_MUX_CTL_PAD_GPIO_SD_B1_02 SW MUX Control Register 0x1A4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc1_DATA0 Select mux mode: ALT0 mux port: USDHC1_DATA0 of instance: USDHC1 0 ALT2_XBAR1_INOUT22 Select mux mode: ALT2 mux port: XBAR1_INOUT22 of instance: XBAR1 0x2 ALT3_gpt4_COMPARE1 Select mux mode: ALT3 mux port: GPT4_COMPARE1 of instance: GPT4 0x3 ALT5_gpio_mux4_IO5 Select mux mode: ALT5 mux port: GPIO_MUX4_IO05 of instance: GPIO_MUX4 0x5 ALT6_flexspi2_A_DATA0 Select mux mode: ALT6 mux port: FLEXSPI2_A_DATA00 of instance: FLEXSPI2 0x6 ALT8_kpp_ROW6 Select mux mode: ALT8 mux port: KPP_ROW06 of instance: KPP 0x8 ALT9_flexspi1_A_SS1_B Select mux mode: ALT9 mux port: FLEXSPI1_A_SS1_B of instance: FLEXSPI1 0x9 ALT10_gpio10_IO5 Select mux mode: ALT10 mux port: GPIO10_IO05 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B1_02 0x1 SW_MUX_CTL_PAD_GPIO_SD_B1_03 SW_MUX_CTL_PAD_GPIO_SD_B1_03 SW MUX Control Register 0x1A8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc1_DATA1 Select mux mode: ALT0 mux port: USDHC1_DATA1 of instance: USDHC1 0 ALT2_XBAR1_INOUT23 Select mux mode: ALT2 mux port: XBAR1_INOUT23 of instance: XBAR1 0x2 ALT3_gpt4_COMPARE2 Select mux mode: ALT3 mux port: GPT4_COMPARE2 of instance: GPT4 0x3 ALT5_gpio_mux4_IO6 Select mux mode: ALT5 mux port: GPIO_MUX4_IO06 of instance: GPIO_MUX4 0x5 ALT6_flexspi2_A_DATA1 Select mux mode: ALT6 mux port: FLEXSPI2_A_DATA01 of instance: FLEXSPI2 0x6 ALT8_kpp_COL6 Select mux mode: ALT8 mux port: KPP_COL06 of instance: KPP 0x8 ALT9_flexspi1_B_SS1_B Select mux mode: ALT9 mux port: FLEXSPI1_B_SS1_B of instance: FLEXSPI1 0x9 ALT10_gpio10_IO6 Select mux mode: ALT10 mux port: GPIO10_IO06 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B1_03 0x1 SW_MUX_CTL_PAD_GPIO_SD_B1_04 SW_MUX_CTL_PAD_GPIO_SD_B1_04 SW MUX Control Register 0x1AC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc1_DATA2 Select mux mode: ALT0 mux port: USDHC1_DATA2 of instance: USDHC1 0 ALT2_XBAR1_INOUT24 Select mux mode: ALT2 mux port: XBAR1_INOUT24 of instance: XBAR1 0x2 ALT3_gpt4_COMPARE3 Select mux mode: ALT3 mux port: GPT4_COMPARE3 of instance: GPT4 0x3 ALT5_gpio_mux4_IO7 Select mux mode: ALT5 mux port: GPIO_MUX4_IO07 of instance: GPIO_MUX4 0x5 ALT6_flexspi2_A_DATA2 Select mux mode: ALT6 mux port: FLEXSPI2_A_DATA02 of instance: FLEXSPI2 0x6 ALT8_flexspi1_B_SS0_B Select mux mode: ALT8 mux port: FLEXSPI1_B_SS0_B of instance: FLEXSPI1 0x8 ALT9_enet_qos_1588_EVENT2_AUX_IN Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT2_AUX_IN of instance: ENET_QOS 0x9 ALT10_gpio10_IO7 Select mux mode: ALT10 mux port: GPIO10_IO07 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B1_04 0x1 SW_MUX_CTL_PAD_GPIO_SD_B1_05 SW_MUX_CTL_PAD_GPIO_SD_B1_05 SW MUX Control Register 0x1B0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc1_DATA3 Select mux mode: ALT0 mux port: USDHC1_DATA3 of instance: USDHC1 0 ALT2_XBAR1_INOUT25 Select mux mode: ALT2 mux port: XBAR1_INOUT25 of instance: XBAR1 0x2 ALT3_gpt4_CLK Select mux mode: ALT3 mux port: GPT4_CLK of instance: GPT4 0x3 ALT5_gpio_mux4_IO8 Select mux mode: ALT5 mux port: GPIO_MUX4_IO08 of instance: GPIO_MUX4 0x5 ALT6_flexspi2_A_DATA3 Select mux mode: ALT6 mux port: FLEXSPI2_A_DATA03 of instance: FLEXSPI2 0x6 ALT8_flexspi1_B_DQS Select mux mode: ALT8 mux port: FLEXSPI1_B_DQS of instance: FLEXSPI1 0x8 ALT9_enet_qos_1588_EVENT3_AUX_IN Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT3_AUX_IN of instance: ENET_QOS 0x9 ALT10_gpio10_IO8 Select mux mode: ALT10 mux port: GPIO10_IO08 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B1_05 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_00 SW_MUX_CTL_PAD_GPIO_SD_B2_00 SW MUX Control Register 0x1B4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_DATA3 Select mux mode: ALT0 mux port: USDHC2_DATA3 of instance: USDHC2 0 ALT1_flexspi1_B_DATA3 Select mux mode: ALT1 mux port: FLEXSPI1_B_DATA03 of instance: FLEXSPI1 0x1 ALT2_enet_1g_RX_EN Select mux mode: ALT2 mux port: ENET_1G_RX_EN of instance: ENET_1G 0x2 ALT3_lpuart9_TX Select mux mode: ALT3 mux port: LPUART9_TXD of instance: LPUART9 0x3 ALT4_lpspi4_SCK Select mux mode: ALT4 mux port: LPSPI4_SCK of instance: LPSPI4 0x4 ALT5_gpio_mux4_IO9 Select mux mode: ALT5 mux port: GPIO_MUX4_IO09 of instance: GPIO_MUX4 0x5 ALT10_gpio10_IO9 Select mux mode: ALT10 mux port: GPIO10_IO09 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_00 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_01 SW_MUX_CTL_PAD_GPIO_SD_B2_01 SW MUX Control Register 0x1B8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_DATA2 Select mux mode: ALT0 mux port: USDHC2_DATA2 of instance: USDHC2 0 ALT1_flexspi1_B_DATA2 Select mux mode: ALT1 mux port: FLEXSPI1_B_DATA02 of instance: FLEXSPI1 0x1 ALT2_enet_1g_RX_CLK Select mux mode: ALT2 mux port: ENET_1G_RX_CLK of instance: ENET_1G 0x2 ALT3_lpuart9_RX Select mux mode: ALT3 mux port: LPUART9_RXD of instance: LPUART9 0x3 ALT4_lpspi4_PCS0 Select mux mode: ALT4 mux port: LPSPI4_PCS0 of instance: LPSPI4 0x4 ALT5_gpio_mux4_IO10 Select mux mode: ALT5 mux port: GPIO_MUX4_IO10 of instance: GPIO_MUX4 0x5 ALT10_gpio10_IO10 Select mux mode: ALT10 mux port: GPIO10_IO10 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_01 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_02 SW_MUX_CTL_PAD_GPIO_SD_B2_02 SW MUX Control Register 0x1BC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_DATA1 Select mux mode: ALT0 mux port: USDHC2_DATA1 of instance: USDHC2 0 ALT1_flexspi1_B_DATA1 Select mux mode: ALT1 mux port: FLEXSPI1_B_DATA01 of instance: FLEXSPI1 0x1 ALT2_ENET_1G_RX_DATA0 Select mux mode: ALT2 mux port: ENET_1G_RX_DATA00 of instance: ENET_1G 0x2 ALT3_lpuart9_CTS_B Select mux mode: ALT3 mux port: LPUART9_CTS_B of instance: LPUART9 0x3 ALT4_lpspi4_SDO Select mux mode: ALT4 mux port: LPSPI4_SOUT of instance: LPSPI4 0x4 ALT5_gpio_mux4_IO11 Select mux mode: ALT5 mux port: GPIO_MUX4_IO11 of instance: GPIO_MUX4 0x5 ALT10_gpio10_IO11 Select mux mode: ALT10 mux port: GPIO10_IO11 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_02 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_03 SW_MUX_CTL_PAD_GPIO_SD_B2_03 SW MUX Control Register 0x1C0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_DATA0 Select mux mode: ALT0 mux port: USDHC2_DATA0 of instance: USDHC2 0 ALT1_flexspi1_B_DATA0 Select mux mode: ALT1 mux port: FLEXSPI1_B_DATA00 of instance: FLEXSPI1 0x1 ALT2_ENET_1G_RX_DATA1 Select mux mode: ALT2 mux port: ENET_1G_RX_DATA01 of instance: ENET_1G 0x2 ALT3_lpuart9_RTS_B Select mux mode: ALT3 mux port: LPUART9_RTS_B of instance: LPUART9 0x3 ALT4_lpspi4_SDI Select mux mode: ALT4 mux port: LPSPI4_SIN of instance: LPSPI4 0x4 ALT5_gpio_mux4_IO12 Select mux mode: ALT5 mux port: GPIO_MUX4_IO12 of instance: GPIO_MUX4 0x5 ALT10_gpio10_IO12 Select mux mode: ALT10 mux port: GPIO10_IO12 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_03 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_04 SW_MUX_CTL_PAD_GPIO_SD_B2_04 SW MUX Control Register 0x1C4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_CLK Select mux mode: ALT0 mux port: USDHC2_CLK of instance: USDHC2 0 ALT1_flexspi1_B_SCLK Select mux mode: ALT1 mux port: FLEXSPI1_B_SCLK of instance: FLEXSPI1 0x1 ALT2_ENET_1G_RX_DATA2 Select mux mode: ALT2 mux port: ENET_1G_RX_DATA02 of instance: ENET_1G 0x2 ALT3_flexspi1_A_SS1_B Select mux mode: ALT3 mux port: FLEXSPI1_A_SS1_B of instance: FLEXSPI1 0x3 ALT4_lpspi4_PCS1 Select mux mode: ALT4 mux port: LPSPI4_PCS1 of instance: LPSPI4 0x4 ALT5_gpio_mux4_IO13 Select mux mode: ALT5 mux port: GPIO_MUX4_IO13 of instance: GPIO_MUX4 0x5 ALT10_gpio10_IO13 Select mux mode: ALT10 mux port: GPIO10_IO13 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_04 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_05 SW_MUX_CTL_PAD_GPIO_SD_B2_05 SW MUX Control Register 0x1C8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_CMD Select mux mode: ALT0 mux port: USDHC2_CMD of instance: USDHC2 0 ALT1_flexspi1_A_DQS Select mux mode: ALT1 mux port: FLEXSPI1_A_DQS of instance: FLEXSPI1 0x1 ALT2_ENET_1G_RX_DATA3 Select mux mode: ALT2 mux port: ENET_1G_RX_DATA03 of instance: ENET_1G 0x2 ALT3_flexspi1_B_SS0_B Select mux mode: ALT3 mux port: FLEXSPI1_B_SS0_B of instance: FLEXSPI1 0x3 ALT4_lpspi4_PCS2 Select mux mode: ALT4 mux port: LPSPI4_PCS2 of instance: LPSPI4 0x4 ALT5_gpio_mux4_IO14 Select mux mode: ALT5 mux port: GPIO_MUX4_IO14 of instance: GPIO_MUX4 0x5 ALT10_gpio10_IO14 Select mux mode: ALT10 mux port: GPIO10_IO14 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_05 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_06 SW_MUX_CTL_PAD_GPIO_SD_B2_06 SW MUX Control Register 0x1CC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_RESET_B Select mux mode: ALT0 mux port: USDHC2_RESET_B of instance: USDHC2 0 ALT1_flexspi1_A_SS0_B Select mux mode: ALT1 mux port: FLEXSPI1_A_SS0_B of instance: FLEXSPI1 0x1 ALT2_ENET_1G_TX_DATA3 Select mux mode: ALT2 mux port: ENET_1G_TX_DATA03 of instance: ENET_1G 0x2 ALT3_lpspi4_PCS3 Select mux mode: ALT3 mux port: LPSPI4_PCS3 of instance: LPSPI4 0x3 ALT4_gpt6_CAPTURE1 Select mux mode: ALT4 mux port: GPT6_CAPTURE1 of instance: GPT6 0x4 ALT5_gpio_mux4_IO15 Select mux mode: ALT5 mux port: GPIO_MUX4_IO15 of instance: GPIO_MUX4 0x5 ALT10_gpio10_IO15 Select mux mode: ALT10 mux port: GPIO10_IO15 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_06 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_07 SW_MUX_CTL_PAD_GPIO_SD_B2_07 SW MUX Control Register 0x1D0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_STROBE Select mux mode: ALT0 mux port: USDHC2_STROBE of instance: USDHC2 0 ALT1_flexspi1_A_SCLK Select mux mode: ALT1 mux port: FLEXSPI1_A_SCLK of instance: FLEXSPI1 0x1 ALT2_ENET_1G_TX_DATA2 Select mux mode: ALT2 mux port: ENET_1G_TX_DATA02 of instance: ENET_1G 0x2 ALT3_lpuart3_CTS_B Select mux mode: ALT3 mux port: LPUART3_CTS_B of instance: LPUART3 0x3 ALT4_gpt6_CAPTURE2 Select mux mode: ALT4 mux port: GPT6_CAPTURE2 of instance: GPT6 0x4 ALT5_gpio_mux4_IO16 Select mux mode: ALT5 mux port: GPIO_MUX4_IO16 of instance: GPIO_MUX4 0x5 ALT6_lpspi2_SCK Select mux mode: ALT6 mux port: LPSPI2_SCK of instance: LPSPI2 0x6 ALT8_enet_TX_ER Select mux mode: ALT8 mux port: ENET_TX_ER of instance: ENET 0x8 ALT9_CCM_enet_qos_clock_generate_REF_CLK Select mux mode: ALT9 mux port: ENET_QOS_REF_CLK of instance: ENET_QOS 0x9 ALT10_gpio10_IO16 Select mux mode: ALT10 mux port: GPIO10_IO16 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_07 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_08 SW_MUX_CTL_PAD_GPIO_SD_B2_08 SW MUX Control Register 0x1D4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_DATA4 Select mux mode: ALT0 mux port: USDHC2_DATA4 of instance: USDHC2 0 ALT1_flexspi1_A_DATA0 Select mux mode: ALT1 mux port: FLEXSPI1_A_DATA00 of instance: FLEXSPI1 0x1 ALT2_ENET_1G_TX_DATA1 Select mux mode: ALT2 mux port: ENET_1G_TX_DATA01 of instance: ENET_1G 0x2 ALT3_lpuart3_RTS_B Select mux mode: ALT3 mux port: LPUART3_RTS_B of instance: LPUART3 0x3 ALT4_gpt6_COMPARE1 Select mux mode: ALT4 mux port: GPT6_COMPARE1 of instance: GPT6 0x4 ALT5_gpio_mux4_IO17 Select mux mode: ALT5 mux port: GPIO_MUX4_IO17 of instance: GPIO_MUX4 0x5 ALT6_lpspi2_PCS0 Select mux mode: ALT6 mux port: LPSPI2_PCS0 of instance: LPSPI2 0x6 ALT10_gpio10_IO17 Select mux mode: ALT10 mux port: GPIO10_IO17 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_08 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_09 SW_MUX_CTL_PAD_GPIO_SD_B2_09 SW MUX Control Register 0x1D8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_DATA5 Select mux mode: ALT0 mux port: USDHC2_DATA5 of instance: USDHC2 0 ALT1_flexspi1_A_DATA1 Select mux mode: ALT1 mux port: FLEXSPI1_A_DATA01 of instance: FLEXSPI1 0x1 ALT2_ENET_1G_TX_DATA0 Select mux mode: ALT2 mux port: ENET_1G_TX_DATA00 of instance: ENET_1G 0x2 ALT3_lpuart5_CTS_B Select mux mode: ALT3 mux port: LPUART5_CTS_B of instance: LPUART5 0x3 ALT4_gpt6_COMPARE2 Select mux mode: ALT4 mux port: GPT6_COMPARE2 of instance: GPT6 0x4 ALT5_gpio_mux4_IO18 Select mux mode: ALT5 mux port: GPIO_MUX4_IO18 of instance: GPIO_MUX4 0x5 ALT6_lpspi2_SDO Select mux mode: ALT6 mux port: LPSPI2_SOUT of instance: LPSPI2 0x6 ALT10_gpio10_IO18 Select mux mode: ALT10 mux port: GPIO10_IO18 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_09 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_10 SW_MUX_CTL_PAD_GPIO_SD_B2_10 SW MUX Control Register 0x1DC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_DATA6 Select mux mode: ALT0 mux port: USDHC2_DATA6 of instance: USDHC2 0 ALT1_flexspi1_A_DATA2 Select mux mode: ALT1 mux port: FLEXSPI1_A_DATA02 of instance: FLEXSPI1 0x1 ALT2_enet_1g_TX_EN Select mux mode: ALT2 mux port: ENET_1G_TX_EN of instance: ENET_1G 0x2 ALT3_lpuart5_RTS_B Select mux mode: ALT3 mux port: LPUART5_RTS_B of instance: LPUART5 0x3 ALT4_gpt6_COMPARE3 Select mux mode: ALT4 mux port: GPT6_COMPARE3 of instance: GPT6 0x4 ALT5_gpio_mux4_IO19 Select mux mode: ALT5 mux port: GPIO_MUX4_IO19 of instance: GPIO_MUX4 0x5 ALT6_lpspi2_SDI Select mux mode: ALT6 mux port: LPSPI2_SIN of instance: LPSPI2 0x6 ALT10_gpio10_IO19 Select mux mode: ALT10 mux port: GPIO10_IO19 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_10 0x1 SW_MUX_CTL_PAD_GPIO_SD_B2_11 SW_MUX_CTL_PAD_GPIO_SD_B2_11 SW MUX Control Register 0x1E0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_usdhc2_DATA7 Select mux mode: ALT0 mux port: USDHC2_DATA7 of instance: USDHC2 0 ALT1_flexspi1_A_DATA3 Select mux mode: ALT1 mux port: FLEXSPI1_A_DATA03 of instance: FLEXSPI1 0x1 ALT2_enet_1g_TX_CLK_IO Select mux mode: ALT2 mux port: ENET_1G_TX_CLK_IO of instance: ENET_1G 0x2 ALT3_enet_1g_REF_CLK Select mux mode: ALT3 mux port: ENET_1G_REF_CLK of instance: ENET_1G 0x3 ALT4_gpt6_CLK Select mux mode: ALT4 mux port: GPT6_CLK of instance: GPT6 0x4 ALT5_gpio_mux4_IO20 Select mux mode: ALT5 mux port: GPIO_MUX4_IO20 of instance: GPIO_MUX4 0x5 ALT6_lpspi2_PCS1 Select mux mode: ALT6 mux port: LPSPI2_PCS1 of instance: LPSPI2 0x6 ALT10_gpio10_IO20 Select mux mode: ALT10 mux port: GPIO10_IO20 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_B2_11 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_00 SW_MUX_CTL_PAD_GPIO_DISP_B1_00 SW MUX Control Register 0x1E4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_CLK Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_CLK of instance: VIDEO_MUX 0 ALT1_enet_1g_RX_EN Select mux mode: ALT1 mux port: ENET_1G_RX_EN of instance: ENET_1G 0x1 ALT3_qtimer1_TIMER0 Select mux mode: ALT3 mux port: TMR1_TIMER0 of instance: TMR1 0x3 ALT4_XBAR1_INOUT26 Select mux mode: ALT4 mux port: XBAR1_INOUT26 of instance: XBAR1 0x4 ALT5_gpio_mux4_IO21 Select mux mode: ALT5 mux port: GPIO_MUX4_IO21 of instance: GPIO_MUX4 0x5 ALT8_enet_qos_RX_EN Select mux mode: ALT8 mux port: ENET_QOS_RX_EN of instance: ENET_QOS 0x8 ALT10_gpio10_IO21 Select mux mode: ALT10 mux port: GPIO10_IO21 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_00 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_01 SW_MUX_CTL_PAD_GPIO_DISP_B1_01 SW MUX Control Register 0x1E8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_ENABLE Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_ENABLE of instance: VIDEO_MUX 0 ALT1_enet_1g_RX_CLK Select mux mode: ALT1 mux port: ENET_1G_RX_CLK of instance: ENET_1G 0x1 ALT2_enet_1g_RX_ER Select mux mode: ALT2 mux port: ENET_1G_RX_ER of instance: ENET_1G 0x2 ALT3_qtimer1_TIMER1 Select mux mode: ALT3 mux port: TMR1_TIMER1 of instance: TMR1 0x3 ALT4_XBAR1_INOUT27 Select mux mode: ALT4 mux port: XBAR1_INOUT27 of instance: XBAR1 0x4 ALT5_gpio_mux4_IO22 Select mux mode: ALT5 mux port: GPIO_MUX4_IO22 of instance: GPIO_MUX4 0x5 ALT8_CCM_enet_qos_clock_generate_RX_CLK Select mux mode: ALT8 mux port: ENET_QOS_RX_CLK of instance: ENET_QOS 0x8 ALT9_enet_qos_RX_ER Select mux mode: ALT9 mux port: ENET_QOS_RX_ER of instance: ENET_QOS 0x9 ALT10_gpio10_IO22 Select mux mode: ALT10 mux port: GPIO10_IO22 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_01 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_02 SW_MUX_CTL_PAD_GPIO_DISP_B1_02 SW MUX Control Register 0x1EC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_HSYNC Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_HSYNC of instance: VIDEO_MUX 0 ALT1_ENET_1G_RX_DATA0 Select mux mode: ALT1 mux port: ENET_1G_RX_DATA00 of instance: ENET_1G 0x1 ALT2_lpi2c3_SCL Select mux mode: ALT2 mux port: LPI2C3_SCL of instance: LPI2C3 0x2 ALT3_qtimer1_TIMER2 Select mux mode: ALT3 mux port: TMR1_TIMER2 of instance: TMR1 0x3 ALT4_XBAR1_INOUT28 Select mux mode: ALT4 mux port: XBAR1_INOUT28 of instance: XBAR1 0x4 ALT5_gpio_mux4_IO23 Select mux mode: ALT5 mux port: GPIO_MUX4_IO23 of instance: GPIO_MUX4 0x5 ALT8_ENET_QOS_RX_DATA0 Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA00 of instance: ENET_QOS 0x8 ALT9_lpuart1_TX Select mux mode: ALT9 mux port: LPUART1_TXD of instance: LPUART1 0x9 ALT10_gpio10_IO23 Select mux mode: ALT10 mux port: GPIO10_IO23 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_02 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_03 SW_MUX_CTL_PAD_GPIO_DISP_B1_03 SW MUX Control Register 0x1F0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_VSYNC Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_VSYNC of instance: VIDEO_MUX 0 ALT1_ENET_1G_RX_DATA1 Select mux mode: ALT1 mux port: ENET_1G_RX_DATA01 of instance: ENET_1G 0x1 ALT2_lpi2c3_SDA Select mux mode: ALT2 mux port: LPI2C3_SDA of instance: LPI2C3 0x2 ALT3_qtimer2_TIMER0 Select mux mode: ALT3 mux port: TMR2_TIMER0 of instance: TMR2 0x3 ALT4_XBAR1_INOUT29 Select mux mode: ALT4 mux port: XBAR1_INOUT29 of instance: XBAR1 0x4 ALT5_gpio_mux4_IO24 Select mux mode: ALT5 mux port: GPIO_MUX4_IO24 of instance: GPIO_MUX4 0x5 ALT8_ENET_QOS_RX_DATA1 Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA01 of instance: ENET_QOS 0x8 ALT9_lpuart1_RX Select mux mode: ALT9 mux port: LPUART1_RXD of instance: LPUART1 0x9 ALT10_gpio10_IO24 Select mux mode: ALT10 mux port: GPIO10_IO24 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_03 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_04 SW_MUX_CTL_PAD_GPIO_DISP_B1_04 SW MUX Control Register 0x1F4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA0 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA00 of instance: VIDEO_MUX 0 ALT1_ENET_1G_RX_DATA2 Select mux mode: ALT1 mux port: ENET_1G_RX_DATA02 of instance: ENET_1G 0x1 ALT2_lpuart4_RX Select mux mode: ALT2 mux port: LPUART4_RXD of instance: LPUART4 0x2 ALT3_qtimer2_TIMER1 Select mux mode: ALT3 mux port: TMR2_TIMER1 of instance: TMR2 0x3 ALT4_XBAR1_INOUT30 Select mux mode: ALT4 mux port: XBAR1_INOUT30 of instance: XBAR1 0x4 ALT5_gpio_mux4_IO25 Select mux mode: ALT5 mux port: GPIO_MUX4_IO25 of instance: GPIO_MUX4 0x5 ALT8_ENET_QOS_RX_DATA2 Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA02 of instance: ENET_QOS 0x8 ALT9_lpspi3_SCK Select mux mode: ALT9 mux port: LPSPI3_SCK of instance: LPSPI3 0x9 ALT10_gpio10_IO25 Select mux mode: ALT10 mux port: GPIO10_IO25 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_04 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_05 SW_MUX_CTL_PAD_GPIO_DISP_B1_05 SW MUX Control Register 0x1F8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA1 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA01 of instance: VIDEO_MUX 0 ALT1_ENET_1G_RX_DATA3 Select mux mode: ALT1 mux port: ENET_1G_RX_DATA03 of instance: ENET_1G 0x1 ALT2_lpuart4_CTS_B Select mux mode: ALT2 mux port: LPUART4_CTS_B of instance: LPUART4 0x2 ALT3_qtimer2_TIMER2 Select mux mode: ALT3 mux port: TMR2_TIMER2 of instance: TMR2 0x3 ALT4_XBAR1_INOUT31 Select mux mode: ALT4 mux port: XBAR1_INOUT31 of instance: XBAR1 0x4 ALT5_gpio_mux4_IO26 Select mux mode: ALT5 mux port: GPIO_MUX4_IO26 of instance: GPIO_MUX4 0x5 ALT8_ENET_QOS_RX_DATA3 Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA03 of instance: ENET_QOS 0x8 ALT9_lpspi3_SDI Select mux mode: ALT9 mux port: LPSPI3_SIN of instance: LPSPI3 0x9 ALT10_gpio10_IO26 Select mux mode: ALT10 mux port: GPIO10_IO26 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_05 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_06 SW_MUX_CTL_PAD_GPIO_DISP_B1_06 SW MUX Control Register 0x1FC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA2 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA02 of instance: VIDEO_MUX 0 ALT1_ENET_1G_TX_DATA3 Select mux mode: ALT1 mux port: ENET_1G_TX_DATA03 of instance: ENET_1G 0x1 ALT2_lpuart4_TX Select mux mode: ALT2 mux port: LPUART4_TXD of instance: LPUART4 0x2 ALT3_qtimer3_TIMER0 Select mux mode: ALT3 mux port: TMR3_TIMER0 of instance: TMR3 0x3 ALT4_XBAR1_INOUT32 Select mux mode: ALT4 mux port: XBAR1_INOUT32 of instance: XBAR1 0x4 ALT5_gpio_mux4_IO27 Select mux mode: ALT5 mux port: GPIO_MUX4_IO27 of instance: GPIO_MUX4 0x5 ALT6_src_BT_CFG0 Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: SRC 0x6 ALT8_ENET_QOS_TX_DATA3 Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA03 of instance: ENET_QOS 0x8 ALT9_lpspi3_SDO Select mux mode: ALT9 mux port: LPSPI3_SOUT of instance: LPSPI3 0x9 ALT10_gpio10_IO27 Select mux mode: ALT10 mux port: GPIO10_IO27 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_06 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_07 SW_MUX_CTL_PAD_GPIO_DISP_B1_07 SW MUX Control Register 0x200 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA3 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA03 of instance: VIDEO_MUX 0 ALT1_ENET_1G_TX_DATA2 Select mux mode: ALT1 mux port: ENET_1G_TX_DATA02 of instance: ENET_1G 0x1 ALT2_lpuart4_RTS_B Select mux mode: ALT2 mux port: LPUART4_RTS_B of instance: LPUART4 0x2 ALT3_qtimer3_TIMER1 Select mux mode: ALT3 mux port: TMR3_TIMER1 of instance: TMR3 0x3 ALT4_XBAR1_INOUT33 Select mux mode: ALT4 mux port: XBAR1_INOUT33 of instance: XBAR1 0x4 ALT5_gpio_mux4_IO28 Select mux mode: ALT5 mux port: GPIO_MUX4_IO28 of instance: GPIO_MUX4 0x5 ALT6_src_BT_CFG1 Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: SRC 0x6 ALT8_ENET_QOS_TX_DATA2 Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA02 of instance: ENET_QOS 0x8 ALT9_lpspi3_PCS0 Select mux mode: ALT9 mux port: LPSPI3_PCS0 of instance: LPSPI3 0x9 ALT10_gpio10_IO28 Select mux mode: ALT10 mux port: GPIO10_IO28 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_07 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_08 SW_MUX_CTL_PAD_GPIO_DISP_B1_08 SW MUX Control Register 0x204 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA4 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA04 of instance: VIDEO_MUX 0 ALT1_ENET_1G_TX_DATA1 Select mux mode: ALT1 mux port: ENET_1G_TX_DATA01 of instance: ENET_1G 0x1 ALT2_usdhc1_CD_B Select mux mode: ALT2 mux port: USDHC1_CD_B of instance: USDHC1 0x2 ALT3_qtimer3_TIMER2 Select mux mode: ALT3 mux port: TMR3_TIMER2 of instance: TMR3 0x3 ALT4_XBAR1_INOUT34 Select mux mode: ALT4 mux port: XBAR1_INOUT34 of instance: XBAR1 0x4 ALT5_gpio_mux4_IO29 Select mux mode: ALT5 mux port: GPIO_MUX4_IO29 of instance: GPIO_MUX4 0x5 ALT6_src_BT_CFG2 Select mux mode: ALT6 mux port: SRC_BT_CFG02 of instance: SRC 0x6 ALT8_ENET_QOS_TX_DATA1 Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA01 of instance: ENET_QOS 0x8 ALT9_lpspi3_PCS1 Select mux mode: ALT9 mux port: LPSPI3_PCS1 of instance: LPSPI3 0x9 ALT10_gpio10_IO29 Select mux mode: ALT10 mux port: GPIO10_IO29 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_08 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_09 SW_MUX_CTL_PAD_GPIO_DISP_B1_09 SW MUX Control Register 0x208 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA5 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA05 of instance: VIDEO_MUX 0 ALT1_ENET_1G_TX_DATA0 Select mux mode: ALT1 mux port: ENET_1G_TX_DATA00 of instance: ENET_1G 0x1 ALT2_usdhc1_WP Select mux mode: ALT2 mux port: USDHC1_WP of instance: USDHC1 0x2 ALT3_qtimer4_TIMER0 Select mux mode: ALT3 mux port: TMR4_TIMER0 of instance: TMR4 0x3 ALT4_XBAR1_INOUT35 Select mux mode: ALT4 mux port: XBAR1_INOUT35 of instance: XBAR1 0x4 ALT5_gpio_mux4_IO30 Select mux mode: ALT5 mux port: GPIO_MUX4_IO30 of instance: GPIO_MUX4 0x5 ALT6_src_BT_CFG3 Select mux mode: ALT6 mux port: SRC_BT_CFG03 of instance: SRC 0x6 ALT8_ENET_QOS_TX_DATA0 Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA00 of instance: ENET_QOS 0x8 ALT9_lpspi3_PCS2 Select mux mode: ALT9 mux port: LPSPI3_PCS2 of instance: LPSPI3 0x9 ALT10_gpio10_IO30 Select mux mode: ALT10 mux port: GPIO10_IO30 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_09 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_10 SW_MUX_CTL_PAD_GPIO_DISP_B1_10 SW MUX Control Register 0x20C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA6 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA06 of instance: VIDEO_MUX 0 ALT1_enet_1g_TX_EN Select mux mode: ALT1 mux port: ENET_1G_TX_EN of instance: ENET_1G 0x1 ALT2_usdhc1_RESET_B Select mux mode: ALT2 mux port: USDHC1_RESET_B of instance: USDHC1 0x2 ALT3_qtimer4_TIMER1 Select mux mode: ALT3 mux port: TMR4_TIMER1 of instance: TMR4 0x3 ALT4_XBAR1_INOUT36 Select mux mode: ALT4 mux port: XBAR1_INOUT36 of instance: XBAR1 0x4 ALT5_gpio_mux4_IO31 Select mux mode: ALT5 mux port: GPIO_MUX4_IO31 of instance: GPIO_MUX4 0x5 ALT6_src_BT_CFG4 Select mux mode: ALT6 mux port: SRC_BT_CFG04 of instance: SRC 0x6 ALT8_enet_qos_TX_EN Select mux mode: ALT8 mux port: ENET_QOS_TX_EN of instance: ENET_QOS 0x8 ALT9_lpspi3_PCS3 Select mux mode: ALT9 mux port: LPSPI3_PCS3 of instance: LPSPI3 0x9 ALT10_gpio10_IO31 Select mux mode: ALT10 mux port: GPIO10_IO31 of instance: GPIO10 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_10 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B1_11 SW_MUX_CTL_PAD_GPIO_DISP_B1_11 SW MUX Control Register 0x210 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA7 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA07 of instance: VIDEO_MUX 0 ALT1_enet_1g_TX_CLK_IO Select mux mode: ALT1 mux port: ENET_1G_TX_CLK_IO of instance: ENET_1G 0x1 ALT2_enet_1g_REF_CLK Select mux mode: ALT2 mux port: ENET_1G_REF_CLK of instance: ENET_1G 0x2 ALT3_qtimer4_TIMER2 Select mux mode: ALT3 mux port: TMR4_TIMER2 of instance: TMR4 0x3 ALT4_XBAR1_INOUT37 Select mux mode: ALT4 mux port: XBAR1_INOUT37 of instance: XBAR1 0x4 ALT5_gpio_mux5_IO0 Select mux mode: ALT5 mux port: GPIO_MUX5_IO00 of instance: GPIO_MUX5 0x5 ALT6_src_BT_CFG5 Select mux mode: ALT6 mux port: SRC_BT_CFG05 of instance: SRC 0x6 ALT8_CCM_enet_qos_clock_generate_TX_CLK Select mux mode: ALT8 mux port: ENET_QOS_TX_CLK of instance: ENET_QOS 0x8 ALT9_CCM_enet_qos_clock_generate_REF_CLK Select mux mode: ALT9 mux port: ENET_QOS_REF_CLK of instance: ENET_QOS 0x9 ALT10_gpio11_IO0 Select mux mode: ALT10 mux port: GPIO11_IO00 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B1_11 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_00 SW_MUX_CTL_PAD_GPIO_DISP_B2_00 SW MUX Control Register 0x214 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA8 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA08 of instance: VIDEO_MUX 0 ALT1_WDOG1_B Select mux mode: ALT1 mux port: WDOG1_B of instance: WDOG1 0x1 ALT2_mqs_RIGHT Select mux mode: ALT2 mux port: MQS_RIGHT of instance: MQS 0x2 ALT3_enet_1g_TX_ER Select mux mode: ALT3 mux port: ENET_1G_TX_ER of instance: ENET_1G 0x3 ALT4_sai1_TX_DATA3 Select mux mode: ALT4 mux port: SAI1_TX_DATA03 of instance: SAI1 0x4 ALT5_gpio_mux5_IO1 Select mux mode: ALT5 mux port: GPIO_MUX5_IO01 of instance: GPIO_MUX5 0x5 ALT6_src_BT_CFG6 Select mux mode: ALT6 mux port: SRC_BT_CFG06 of instance: SRC 0x6 ALT8_enet_qos_TX_ER Select mux mode: ALT8 mux port: ENET_QOS_TX_ER of instance: ENET_QOS 0x8 ALT10_gpio11_IO1 Select mux mode: ALT10 mux port: GPIO11_IO01 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_00 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_01 SW_MUX_CTL_PAD_GPIO_DISP_B2_01 SW MUX Control Register 0x218 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA9 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA09 of instance: VIDEO_MUX 0 ALT1_usdhc1_VSELECT Select mux mode: ALT1 mux port: USDHC1_VSELECT of instance: USDHC1 0x1 ALT2_mqs_LEFT Select mux mode: ALT2 mux port: MQS_LEFT of instance: MQS 0x2 ALT3_WDOG2_B Select mux mode: ALT3 mux port: WDOG2_B of instance: WDOG2 0x3 ALT4_sai1_TX_DATA2 Select mux mode: ALT4 mux port: SAI1_TX_DATA02 of instance: SAI1 0x4 ALT5_gpio_mux5_IO2 Select mux mode: ALT5 mux port: GPIO_MUX5_IO02 of instance: GPIO_MUX5 0x5 ALT6_src_BT_CFG7 Select mux mode: ALT6 mux port: SRC_BT_CFG07 of instance: SRC 0x6 ALT8_EWM_OUT_B Select mux mode: ALT8 mux port: EWM_OUT_B of instance: EWM 0x8 ALT9_CCM_ENET_REF_CLK_25M Select mux mode: ALT9 mux port: CCM_ENET_REF_CLK_25M of instance: CCM 0x9 ALT10_gpio11_IO2 Select mux mode: ALT10 mux port: GPIO11_IO02 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_01 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_02 SW_MUX_CTL_PAD_GPIO_DISP_B2_02 SW MUX Control Register 0x21C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA10 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA10 of instance: VIDEO_MUX 0 ALT1_ENET_TX_DATA0 Select mux mode: ALT1 mux port: ENET_TX_DATA00 of instance: ENET 0x1 ALT2_pit1_TRIGGER3 Select mux mode: ALT2 mux port: PIT1_TRIGGER3 of instance: PIT1 0x2 ALT3_ARM_TRACE0 Select mux mode: ALT3 mux port: ARM_TRACE00 of instance: ARM 0x3 ALT4_sai1_TX_DATA1 Select mux mode: ALT4 mux port: SAI1_TX_DATA01 of instance: SAI1 0x4 ALT5_gpio_mux5_IO3 Select mux mode: ALT5 mux port: GPIO_MUX5_IO03 of instance: GPIO_MUX5 0x5 ALT6_src_BT_CFG8 Select mux mode: ALT6 mux port: SRC_BT_CFG08 of instance: SRC 0x6 ALT8_ENET_QOS_TX_DATA0 Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA00 of instance: ENET_QOS 0x8 ALT10_gpio11_IO3 Select mux mode: ALT10 mux port: GPIO11_IO03 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_02 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_03 SW_MUX_CTL_PAD_GPIO_DISP_B2_03 SW MUX Control Register 0x220 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA11 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA11 of instance: VIDEO_MUX 0 ALT1_ENET_TX_DATA1 Select mux mode: ALT1 mux port: ENET_TX_DATA01 of instance: ENET 0x1 ALT2_pit1_TRIGGER2 Select mux mode: ALT2 mux port: PIT1_TRIGGER2 of instance: PIT1 0x2 ALT3_ARM_TRACE1 Select mux mode: ALT3 mux port: ARM_TRACE01 of instance: ARM 0x3 ALT4_sai1_MCLK Select mux mode: ALT4 mux port: SAI1_MCLK of instance: SAI1 0x4 ALT5_gpio_mux5_IO4 Select mux mode: ALT5 mux port: GPIO_MUX5_IO04 of instance: GPIO_MUX5 0x5 ALT6_src_BT_CFG9 Select mux mode: ALT6 mux port: SRC_BT_CFG09 of instance: SRC 0x6 ALT8_ENET_QOS_TX_DATA1 Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA01 of instance: ENET_QOS 0x8 ALT10_gpio11_IO4 Select mux mode: ALT10 mux port: GPIO11_IO04 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_03 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_04 SW_MUX_CTL_PAD_GPIO_DISP_B2_04 SW MUX Control Register 0x224 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA12 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA12 of instance: VIDEO_MUX 0 ALT1_enet_TX_EN Select mux mode: ALT1 mux port: ENET_TX_EN of instance: ENET 0x1 ALT2_pit1_TRIGGER1 Select mux mode: ALT2 mux port: PIT1_TRIGGER1 of instance: PIT1 0x2 ALT3_ARM_TRACE2 Select mux mode: ALT3 mux port: ARM_TRACE02 of instance: ARM 0x3 ALT4_sai1_RX_SYNC Select mux mode: ALT4 mux port: SAI1_RX_SYNC of instance: SAI1 0x4 ALT5_gpio_mux5_IO5 Select mux mode: ALT5 mux port: GPIO_MUX5_IO05 of instance: GPIO_MUX5 0x5 ALT6_src_BT_CFG10 Select mux mode: ALT6 mux port: SRC_BT_CFG10 of instance: SRC 0x6 ALT8_enet_qos_TX_EN Select mux mode: ALT8 mux port: ENET_QOS_TX_EN of instance: ENET_QOS 0x8 ALT10_gpio11_IO5 Select mux mode: ALT10 mux port: GPIO11_IO05 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_04 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_05 SW_MUX_CTL_PAD_GPIO_DISP_B2_05 SW MUX Control Register 0x228 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA13 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA13 of instance: VIDEO_MUX 0 ALT1_enet_TX_CLK Select mux mode: ALT1 mux port: ENET_TX_CLK of instance: ENET 0x1 ALT2_enet_REF_CLK Select mux mode: ALT2 mux port: ENET_REF_CLK of instance: ENET 0x2 ALT3_ARM_TRACE3 Select mux mode: ALT3 mux port: ARM_TRACE03 of instance: ARM 0x3 ALT4_sai1_RX_BCLK Select mux mode: ALT4 mux port: SAI1_RX_BCLK of instance: SAI1 0x4 ALT5_gpio_mux5_IO6 Select mux mode: ALT5 mux port: GPIO_MUX5_IO06 of instance: GPIO_MUX5 0x5 ALT6_src_BT_CFG11 Select mux mode: ALT6 mux port: SRC_BT_CFG11 of instance: SRC 0x6 ALT8_CCM_enet_qos_clock_generate_TX_CLK Select mux mode: ALT8 mux port: ENET_QOS_TX_CLK of instance: ENET_QOS 0x8 ALT10_gpio11_IO6 Select mux mode: ALT10 mux port: GPIO11_IO06 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_05 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_06 SW_MUX_CTL_PAD_GPIO_DISP_B2_06 SW MUX Control Register 0x22C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA14 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA14 of instance: VIDEO_MUX 0 ALT1_ENET_RX_DATA0 Select mux mode: ALT1 mux port: ENET_RX_DATA00 of instance: ENET 0x1 ALT2_lpuart7_TX Select mux mode: ALT2 mux port: LPUART7_TXD of instance: LPUART7 0x2 ALT3_ARM_TRACE_CLK Select mux mode: ALT3 mux port: ARM_TRACE_CLK of instance: ARM 0x3 ALT4_sai1_RX_DATA0 Select mux mode: ALT4 mux port: SAI1_RX_DATA00 of instance: SAI1 0x4 ALT5_gpio_mux5_IO7 Select mux mode: ALT5 mux port: GPIO_MUX5_IO07 of instance: GPIO_MUX5 0x5 ALT8_ENET_QOS_RX_DATA0 Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA00 of instance: ENET_QOS 0x8 ALT10_gpio11_IO7 Select mux mode: ALT10 mux port: GPIO11_IO07 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_06 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_07 SW_MUX_CTL_PAD_GPIO_DISP_B2_07 SW MUX Control Register 0x230 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA15 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA15 of instance: VIDEO_MUX 0 ALT1_ENET_RX_DATA1 Select mux mode: ALT1 mux port: ENET_RX_DATA01 of instance: ENET 0x1 ALT2_lpuart7_RX Select mux mode: ALT2 mux port: LPUART7_RXD of instance: LPUART7 0x2 ALT3_ARM_TRACE_SWO Select mux mode: ALT3 mux port: ARM_TRACE_SWO of instance: ARM 0x3 ALT4_sai1_TX_DATA0 Select mux mode: ALT4 mux port: SAI1_TX_DATA00 of instance: SAI1 0x4 ALT5_gpio_mux5_IO8 Select mux mode: ALT5 mux port: GPIO_MUX5_IO08 of instance: GPIO_MUX5 0x5 ALT8_ENET_QOS_RX_DATA1 Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA01 of instance: ENET_QOS 0x8 ALT10_gpio11_IO8 Select mux mode: ALT10 mux port: GPIO11_IO08 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_07 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_08 SW_MUX_CTL_PAD_GPIO_DISP_B2_08 SW MUX Control Register 0x234 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA16 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA16 of instance: VIDEO_MUX 0 ALT1_enet_RX_EN Select mux mode: ALT1 mux port: ENET_RX_EN of instance: ENET 0x1 ALT2_lpuart8_TX Select mux mode: ALT2 mux port: LPUART8_TXD of instance: LPUART8 0x2 ALT3_cm7_imxrt_TXEV Select mux mode: ALT3 mux port: ARM_CM7_EVENTO of instance: CM7 0x3 ALT4_sai1_TX_BCLK Select mux mode: ALT4 mux port: SAI1_TX_BCLK of instance: SAI1 0x4 ALT5_gpio_mux5_IO9 Select mux mode: ALT5 mux port: GPIO_MUX5_IO09 of instance: GPIO_MUX5 0x5 ALT8_enet_qos_RX_EN Select mux mode: ALT8 mux port: ENET_QOS_RX_EN of instance: ENET_QOS 0x8 ALT9_lpuart1_TX Select mux mode: ALT9 mux port: LPUART1_TXD of instance: LPUART1 0x9 ALT10_gpio11_IO9 Select mux mode: ALT10 mux port: GPIO11_IO09 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_08 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_09 SW_MUX_CTL_PAD_GPIO_DISP_B2_09 SW MUX Control Register 0x238 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA17 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA17 of instance: VIDEO_MUX 0 ALT1_enet_RX_ER Select mux mode: ALT1 mux port: ENET_RX_ER of instance: ENET 0x1 ALT2_lpuart8_RX Select mux mode: ALT2 mux port: LPUART8_RXD of instance: LPUART8 0x2 ALT3_cm7_imxrt_RXEV Select mux mode: ALT3 mux port: ARM_CM7_EVENTI of instance: CM7 0x3 ALT4_sai1_TX_SYNC Select mux mode: ALT4 mux port: SAI1_TX_SYNC of instance: SAI1 0x4 ALT5_gpio_mux5_IO10 Select mux mode: ALT5 mux port: GPIO_MUX5_IO10 of instance: GPIO_MUX5 0x5 ALT8_enet_qos_RX_ER Select mux mode: ALT8 mux port: ENET_QOS_RX_ER of instance: ENET_QOS 0x8 ALT9_lpuart1_RX Select mux mode: ALT9 mux port: LPUART1_RXD of instance: LPUART1 0x9 ALT10_gpio11_IO10 Select mux mode: ALT10 mux port: GPIO11_IO10 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_09 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_10 SW_MUX_CTL_PAD_GPIO_DISP_B2_10 SW MUX Control Register 0x23C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA18 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA18 of instance: VIDEO_MUX 0 ALT1_EMVSIM2_TRXD Select mux mode: ALT1 mux port: EMVSIM2_IO of instance: EMVSIM2 0x1 ALT2_lpuart2_TX Select mux mode: ALT2 mux port: LPUART2_TXD of instance: LPUART2 0x2 ALT3_WDOG2_RESET_B_DEB Select mux mode: ALT3 mux port: WDOG2_RESET_B_DEB of instance: WDOG2 0x3 ALT4_XBAR1_INOUT38 Select mux mode: ALT4 mux port: XBAR1_INOUT38 of instance: XBAR1 0x4 ALT5_gpio_mux5_IO11 Select mux mode: ALT5 mux port: GPIO_MUX5_IO11 of instance: GPIO_MUX5 0x5 ALT6_lpi2c3_SCL Select mux mode: ALT6 mux port: LPI2C3_SCL of instance: LPI2C3 0x6 ALT8_enet_qos_RX_ER Select mux mode: ALT8 mux port: ENET_QOS_RX_ER of instance: ENET_QOS 0x8 ALT9_spdif_IN Select mux mode: ALT9 mux port: SPDIF_IN of instance: SPDIF 0x9 ALT10_gpio11_IO11 Select mux mode: ALT10 mux port: GPIO11_IO11 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_10 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_11 SW_MUX_CTL_PAD_GPIO_DISP_B2_11 SW MUX Control Register 0x240 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA19 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA19 of instance: VIDEO_MUX 0 ALT1_EMVSIM2_CLK Select mux mode: ALT1 mux port: EMVSIM2_CLK of instance: EMVSIM2 0x1 ALT2_lpuart2_RX Select mux mode: ALT2 mux port: LPUART2_RXD of instance: LPUART2 0x2 ALT3_WDOG1_RESET_B_DEB Select mux mode: ALT3 mux port: WDOG1_RESET_B_DEB of instance: WDOG1 0x3 ALT4_XBAR1_INOUT39 Select mux mode: ALT4 mux port: XBAR1_INOUT39 of instance: XBAR1 0x4 ALT5_gpio_mux5_IO12 Select mux mode: ALT5 mux port: GPIO_MUX5_IO12 of instance: GPIO_MUX5 0x5 ALT6_lpi2c3_SDA Select mux mode: ALT6 mux port: LPI2C3_SDA of instance: LPI2C3 0x6 ALT8_enet_qos_CRS Select mux mode: ALT8 mux port: ENET_QOS_CRS of instance: ENET_QOS 0x8 ALT9_spdif_OUT Select mux mode: ALT9 mux port: SPDIF_OUT of instance: SPDIF 0x9 ALT10_gpio11_IO12 Select mux mode: ALT10 mux port: GPIO11_IO12 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_11 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_12 SW_MUX_CTL_PAD_GPIO_DISP_B2_12 SW MUX Control Register 0x244 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA20 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA20 of instance: VIDEO_MUX 0 ALT1_EMVSIM2_RST_B Select mux mode: ALT1 mux port: EMVSIM2_RST of instance: EMVSIM2 0x1 ALT2_can1_TX Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: FLEXCAN1 0x2 ALT3_lpuart2_CTS_B Select mux mode: ALT3 mux port: LPUART2_CTS_B of instance: LPUART2 0x3 ALT4_XBAR1_INOUT40 Select mux mode: ALT4 mux port: XBAR1_INOUT40 of instance: XBAR1 0x4 ALT5_gpio_mux5_IO13 Select mux mode: ALT5 mux port: GPIO_MUX5_IO13 of instance: GPIO_MUX5 0x5 ALT6_lpi2c4_SCL Select mux mode: ALT6 mux port: LPI2C4_SCL of instance: LPI2C4 0x6 ALT8_enet_qos_COL Select mux mode: ALT8 mux port: ENET_QOS_COL of instance: ENET_QOS 0x8 ALT9_lpspi4_SCK Select mux mode: ALT9 mux port: LPSPI4_SCK of instance: LPSPI4 0x9 ALT10_gpio11_IO13 Select mux mode: ALT10 mux port: GPIO11_IO13 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_12 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_13 SW_MUX_CTL_PAD_GPIO_DISP_B2_13 SW MUX Control Register 0x248 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA21 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA21 of instance: VIDEO_MUX 0 ALT1_EMVSIM2_SVEN Select mux mode: ALT1 mux port: EMVSIM2_SVEN of instance: EMVSIM2 0x1 ALT2_can1_RX Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: FLEXCAN1 0x2 ALT3_lpuart2_RTS_B Select mux mode: ALT3 mux port: LPUART2_RTS_B of instance: LPUART2 0x3 ALT4_enet_REF_CLK Select mux mode: ALT4 mux port: ENET_REF_CLK of instance: ENET 0x4 ALT5_gpio_mux5_IO14 Select mux mode: ALT5 mux port: GPIO_MUX5_IO14 of instance: GPIO_MUX5 0x5 ALT6_lpi2c4_SDA Select mux mode: ALT6 mux port: LPI2C4_SDA of instance: LPI2C4 0x6 ALT8_enet_qos_1588_EVENT0_OUT Select mux mode: ALT8 mux port: ENET_QOS_1588_EVENT0_OUT of instance: ENET_QOS 0x8 ALT9_lpspi4_SDI Select mux mode: ALT9 mux port: LPSPI4_SIN of instance: LPSPI4 0x9 ALT10_gpio11_IO14 Select mux mode: ALT10 mux port: GPIO11_IO14 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_13 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_14 SW_MUX_CTL_PAD_GPIO_DISP_B2_14 SW MUX Control Register 0x24C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA22 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA22 of instance: VIDEO_MUX 0 ALT1_EMVSIM2_PD Select mux mode: ALT1 mux port: EMVSIM2_PD of instance: EMVSIM2 0x1 ALT2_WDOG2_B Select mux mode: ALT2 mux port: WDOG2_B of instance: WDOG2 0x2 ALT3_video_mux_EXT_DCIC1 Select mux mode: ALT3 mux port: VIDEO_MUX_EXT_DCIC1 of instance: VIDEO_MUX 0x3 ALT4_enet_1g_REF_CLK Select mux mode: ALT4 mux port: ENET_1G_REF_CLK of instance: ENET_1G 0x4 ALT5_gpio_mux5_IO15 Select mux mode: ALT5 mux port: GPIO_MUX5_IO15 of instance: GPIO_MUX5 0x5 ALT6_can1_TX Select mux mode: ALT6 mux port: FLEXCAN1_TX of instance: FLEXCAN1 0x6 ALT8_enet_qos_1588_EVENT0_IN Select mux mode: ALT8 mux port: ENET_QOS_1588_EVENT0_IN of instance: ENET_QOS 0x8 ALT9_lpspi4_SDO Select mux mode: ALT9 mux port: LPSPI4_SOUT of instance: LPSPI4 0x9 ALT10_gpio11_IO15 Select mux mode: ALT10 mux port: GPIO11_IO15 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_14 0x1 SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register 0x250 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_video_mux_LCDIF_DATA23 Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA23 of instance: VIDEO_MUX 0 ALT1_EMVSIM2_POWER_FAIL Select mux mode: ALT1 mux port: EMVSIM2_POWER_FAIL of instance: EMVSIM2 0x1 ALT2_WDOG1_B Select mux mode: ALT2 mux port: WDOG1_B of instance: WDOG1 0x2 ALT3_video_mux_EXT_DCIC2 Select mux mode: ALT3 mux port: VIDEO_MUX_EXT_DCIC2 of instance: VIDEO_MUX 0x3 ALT4_pit1_TRIGGER0 Select mux mode: ALT4 mux port: PIT1_TRIGGER0 of instance: PIT1 0x4 ALT5_gpio_mux5_IO16 Select mux mode: ALT5 mux port: GPIO_MUX5_IO16 of instance: GPIO_MUX5 0x5 ALT6_can1_RX Select mux mode: ALT6 mux port: FLEXCAN1_RX of instance: FLEXCAN1 0x6 ALT8_enet_qos_1588_EVENT0_AUX_IN Select mux mode: ALT8 mux port: ENET_QOS_1588_EVENT0_AUX_IN of instance: ENET_QOS 0x8 ALT9_lpspi4_PCS0 Select mux mode: ALT9 mux port: LPSPI4_PCS0 of instance: LPSPI4 0x9 ALT10_gpio11_IO16 Select mux mode: ALT10 mux port: GPIO11_IO16 of instance: GPIO11 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_DISP_B2_15 0x1 SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register 0x254 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_01 SW_PAD_CTL_PAD_GPIO_EMC_B1_01 SW PAD Control Register 0x258 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_02 SW_PAD_CTL_PAD_GPIO_EMC_B1_02 SW PAD Control Register 0x25C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_03 SW_PAD_CTL_PAD_GPIO_EMC_B1_03 SW PAD Control Register 0x260 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_04 SW_PAD_CTL_PAD_GPIO_EMC_B1_04 SW PAD Control Register 0x264 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_05 SW_PAD_CTL_PAD_GPIO_EMC_B1_05 SW PAD Control Register 0x268 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_06 SW_PAD_CTL_PAD_GPIO_EMC_B1_06 SW PAD Control Register 0x26C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_07 SW_PAD_CTL_PAD_GPIO_EMC_B1_07 SW PAD Control Register 0x270 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_08 SW_PAD_CTL_PAD_GPIO_EMC_B1_08 SW PAD Control Register 0x274 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_09 SW_PAD_CTL_PAD_GPIO_EMC_B1_09 SW PAD Control Register 0x278 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_10 SW_PAD_CTL_PAD_GPIO_EMC_B1_10 SW PAD Control Register 0x27C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_11 SW_PAD_CTL_PAD_GPIO_EMC_B1_11 SW PAD Control Register 0x280 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_12 SW_PAD_CTL_PAD_GPIO_EMC_B1_12 SW PAD Control Register 0x284 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_13 SW_PAD_CTL_PAD_GPIO_EMC_B1_13 SW PAD Control Register 0x288 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_14 SW_PAD_CTL_PAD_GPIO_EMC_B1_14 SW PAD Control Register 0x28C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_15 SW_PAD_CTL_PAD_GPIO_EMC_B1_15 SW PAD Control Register 0x290 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_16 SW_PAD_CTL_PAD_GPIO_EMC_B1_16 SW PAD Control Register 0x294 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_17 SW_PAD_CTL_PAD_GPIO_EMC_B1_17 SW PAD Control Register 0x298 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_18 SW_PAD_CTL_PAD_GPIO_EMC_B1_18 SW PAD Control Register 0x29C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_19 SW_PAD_CTL_PAD_GPIO_EMC_B1_19 SW PAD Control Register 0x2A0 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_20 SW_PAD_CTL_PAD_GPIO_EMC_B1_20 SW PAD Control Register 0x2A4 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_21 SW_PAD_CTL_PAD_GPIO_EMC_B1_21 SW PAD Control Register 0x2A8 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_22 SW_PAD_CTL_PAD_GPIO_EMC_B1_22 SW PAD Control Register 0x2AC 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_23 SW_PAD_CTL_PAD_GPIO_EMC_B1_23 SW PAD Control Register 0x2B0 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_24 SW_PAD_CTL_PAD_GPIO_EMC_B1_24 SW PAD Control Register 0x2B4 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_25 SW_PAD_CTL_PAD_GPIO_EMC_B1_25 SW PAD Control Register 0x2B8 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_26 SW_PAD_CTL_PAD_GPIO_EMC_B1_26 SW PAD Control Register 0x2BC 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_27 SW_PAD_CTL_PAD_GPIO_EMC_B1_27 SW PAD Control Register 0x2C0 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_28 SW_PAD_CTL_PAD_GPIO_EMC_B1_28 SW PAD Control Register 0x2C4 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_29 SW_PAD_CTL_PAD_GPIO_EMC_B1_29 SW PAD Control Register 0x2C8 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_30 SW_PAD_CTL_PAD_GPIO_EMC_B1_30 SW PAD Control Register 0x2CC 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_31 SW_PAD_CTL_PAD_GPIO_EMC_B1_31 SW PAD Control Register 0x2D0 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_32 SW_PAD_CTL_PAD_GPIO_EMC_B1_32 SW PAD Control Register 0x2D4 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_33 SW_PAD_CTL_PAD_GPIO_EMC_B1_33 SW PAD Control Register 0x2D8 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_34 SW_PAD_CTL_PAD_GPIO_EMC_B1_34 SW PAD Control Register 0x2DC 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_35 SW_PAD_CTL_PAD_GPIO_EMC_B1_35 SW PAD Control Register 0x2E0 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_36 SW_PAD_CTL_PAD_GPIO_EMC_B1_36 SW PAD Control Register 0x2E4 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_37 SW_PAD_CTL_PAD_GPIO_EMC_B1_37 SW PAD Control Register 0x2E8 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_38 SW_PAD_CTL_PAD_GPIO_EMC_B1_38 SW PAD Control Register 0x2EC 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_39 SW_PAD_CTL_PAD_GPIO_EMC_B1_39 SW PAD Control Register 0x2F0 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_40 SW_PAD_CTL_PAD_GPIO_EMC_B1_40 SW PAD Control Register 0x2F4 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B1_41 SW_PAD_CTL_PAD_GPIO_EMC_B1_41 SW PAD Control Register 0x2F8 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_00 SW_PAD_CTL_PAD_GPIO_EMC_B2_00 SW PAD Control Register 0x2FC 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_01 SW_PAD_CTL_PAD_GPIO_EMC_B2_01 SW PAD Control Register 0x300 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_02 SW_PAD_CTL_PAD_GPIO_EMC_B2_02 SW PAD Control Register 0x304 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_03 SW_PAD_CTL_PAD_GPIO_EMC_B2_03 SW PAD Control Register 0x308 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_04 SW_PAD_CTL_PAD_GPIO_EMC_B2_04 SW PAD Control Register 0x30C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_05 SW_PAD_CTL_PAD_GPIO_EMC_B2_05 SW PAD Control Register 0x310 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_06 SW_PAD_CTL_PAD_GPIO_EMC_B2_06 SW PAD Control Register 0x314 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_07 SW_PAD_CTL_PAD_GPIO_EMC_B2_07 SW PAD Control Register 0x318 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_08 SW_PAD_CTL_PAD_GPIO_EMC_B2_08 SW PAD Control Register 0x31C 32 read-write 0x4 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_09 SW_PAD_CTL_PAD_GPIO_EMC_B2_09 SW PAD Control Register 0x320 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_10 SW_PAD_CTL_PAD_GPIO_EMC_B2_10 SW PAD Control Register 0x324 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_11 SW_PAD_CTL_PAD_GPIO_EMC_B2_11 SW PAD Control Register 0x328 32 read-write 0x4 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_12 SW_PAD_CTL_PAD_GPIO_EMC_B2_12 SW PAD Control Register 0x32C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_13 SW_PAD_CTL_PAD_GPIO_EMC_B2_13 SW PAD Control Register 0x330 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_14 SW_PAD_CTL_PAD_GPIO_EMC_B2_14 SW PAD Control Register 0x334 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_15 SW_PAD_CTL_PAD_GPIO_EMC_B2_15 SW PAD Control Register 0x338 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_16 SW_PAD_CTL_PAD_GPIO_EMC_B2_16 SW PAD Control Register 0x33C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_17 SW_PAD_CTL_PAD_GPIO_EMC_B2_17 SW PAD Control Register 0x340 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_18 SW_PAD_CTL_PAD_GPIO_EMC_B2_18 SW PAD Control Register 0x344 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_19 SW_PAD_CTL_PAD_GPIO_EMC_B2_19 SW PAD Control Register 0x348 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_EMC_B2_20 SW_PAD_CTL_PAD_GPIO_EMC_B2_20 SW PAD Control Register 0x34C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_00 SW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control Register 0x350 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_01 SW_PAD_CTL_PAD_GPIO_AD_01 SW PAD Control Register 0x354 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_02 SW_PAD_CTL_PAD_GPIO_AD_02 SW PAD Control Register 0x358 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_03 SW_PAD_CTL_PAD_GPIO_AD_03 SW PAD Control Register 0x35C 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_04 SW_PAD_CTL_PAD_GPIO_AD_04 SW PAD Control Register 0x360 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_05 SW_PAD_CTL_PAD_GPIO_AD_05 SW PAD Control Register 0x364 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_06 SW_PAD_CTL_PAD_GPIO_AD_06 SW PAD Control Register 0x368 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_07 SW_PAD_CTL_PAD_GPIO_AD_07 SW PAD Control Register 0x36C 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_08 SW_PAD_CTL_PAD_GPIO_AD_08 SW PAD Control Register 0x370 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_09 SW_PAD_CTL_PAD_GPIO_AD_09 SW PAD Control Register 0x374 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_10 SW_PAD_CTL_PAD_GPIO_AD_10 SW PAD Control Register 0x378 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_11 SW_PAD_CTL_PAD_GPIO_AD_11 SW PAD Control Register 0x37C 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_12 SW_PAD_CTL_PAD_GPIO_AD_12 SW PAD Control Register 0x380 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_13 SW_PAD_CTL_PAD_GPIO_AD_13 SW PAD Control Register 0x384 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_14 SW_PAD_CTL_PAD_GPIO_AD_14 SW PAD Control Register 0x388 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_15 SW_PAD_CTL_PAD_GPIO_AD_15 SW PAD Control Register 0x38C 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_16 SW_PAD_CTL_PAD_GPIO_AD_16 SW PAD Control Register 0x390 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_17 SW_PAD_CTL_PAD_GPIO_AD_17 SW PAD Control Register 0x394 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_18 SW_PAD_CTL_PAD_GPIO_AD_18 SW PAD Control Register 0x398 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_19 SW_PAD_CTL_PAD_GPIO_AD_19 SW PAD Control Register 0x39C 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_20 SW_PAD_CTL_PAD_GPIO_AD_20 SW PAD Control Register 0x3A0 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_21 SW_PAD_CTL_PAD_GPIO_AD_21 SW PAD Control Register 0x3A4 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_22 SW_PAD_CTL_PAD_GPIO_AD_22 SW PAD Control Register 0x3A8 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_23 SW_PAD_CTL_PAD_GPIO_AD_23 SW PAD Control Register 0x3AC 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_24 SW_PAD_CTL_PAD_GPIO_AD_24 SW PAD Control Register 0x3B0 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_25 SW_PAD_CTL_PAD_GPIO_AD_25 SW PAD Control Register 0x3B4 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_26 SW_PAD_CTL_PAD_GPIO_AD_26 SW PAD Control Register 0x3B8 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_27 SW_PAD_CTL_PAD_GPIO_AD_27 SW PAD Control Register 0x3BC 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_28 SW_PAD_CTL_PAD_GPIO_AD_28 SW PAD Control Register 0x3C0 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_29 SW_PAD_CTL_PAD_GPIO_AD_29 SW PAD Control Register 0x3C4 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_30 SW_PAD_CTL_PAD_GPIO_AD_30 SW PAD Control Register 0x3C8 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_31 SW_PAD_CTL_PAD_GPIO_AD_31 SW PAD Control Register 0x3CC 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_32 SW_PAD_CTL_PAD_GPIO_AD_32 SW PAD Control Register 0x3D0 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_33 SW_PAD_CTL_PAD_GPIO_AD_33 SW PAD Control Register 0x3D4 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_34 SW_PAD_CTL_PAD_GPIO_AD_34 SW PAD Control Register 0x3D8 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_AD_35 SW_PAD_CTL_PAD_GPIO_AD_35 SW PAD Control Register 0x3DC 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B1_00 SW_PAD_CTL_PAD_GPIO_SD_B1_00 SW PAD Control Register 0x3E0 32 read-write 0x4 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B1_01 SW_PAD_CTL_PAD_GPIO_SD_B1_01 SW PAD Control Register 0x3E4 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B1_02 SW_PAD_CTL_PAD_GPIO_SD_B1_02 SW PAD Control Register 0x3E8 32 read-write 0x4 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B1_03 SW_PAD_CTL_PAD_GPIO_SD_B1_03 SW PAD Control Register 0x3EC 32 read-write 0x4 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B1_04 SW_PAD_CTL_PAD_GPIO_SD_B1_04 SW PAD Control Register 0x3F0 32 read-write 0x4 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B1_05 SW_PAD_CTL_PAD_GPIO_SD_B1_05 SW PAD Control Register 0x3F4 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_00 SW_PAD_CTL_PAD_GPIO_SD_B2_00 SW PAD Control Register 0x3F8 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_01 SW_PAD_CTL_PAD_GPIO_SD_B2_01 SW PAD Control Register 0x3FC 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_02 SW_PAD_CTL_PAD_GPIO_SD_B2_02 SW PAD Control Register 0x400 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_03 SW_PAD_CTL_PAD_GPIO_SD_B2_03 SW PAD Control Register 0x404 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_04 SW_PAD_CTL_PAD_GPIO_SD_B2_04 SW PAD Control Register 0x408 32 read-write 0x4 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_05 SW_PAD_CTL_PAD_GPIO_SD_B2_05 SW PAD Control Register 0x40C 32 read-write 0x4 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_06 SW_PAD_CTL_PAD_GPIO_SD_B2_06 SW PAD Control Register 0x410 32 read-write 0x4 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_07 SW_PAD_CTL_PAD_GPIO_SD_B2_07 SW PAD Control Register 0x414 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_08 SW_PAD_CTL_PAD_GPIO_SD_B2_08 SW PAD Control Register 0x418 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_09 SW_PAD_CTL_PAD_GPIO_SD_B2_09 SW PAD Control Register 0x41C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_10 SW_PAD_CTL_PAD_GPIO_SD_B2_10 SW PAD Control Register 0x420 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SD_B2_11 SW_PAD_CTL_PAD_GPIO_SD_B2_11 SW PAD Control Register 0x424 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_00 SW_PAD_CTL_PAD_GPIO_DISP_B1_00 SW PAD Control Register 0x428 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_01 SW_PAD_CTL_PAD_GPIO_DISP_B1_01 SW PAD Control Register 0x42C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_02 SW_PAD_CTL_PAD_GPIO_DISP_B1_02 SW PAD Control Register 0x430 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_03 SW_PAD_CTL_PAD_GPIO_DISP_B1_03 SW PAD Control Register 0x434 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_04 SW_PAD_CTL_PAD_GPIO_DISP_B1_04 SW PAD Control Register 0x438 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_05 SW_PAD_CTL_PAD_GPIO_DISP_B1_05 SW PAD Control Register 0x43C 32 read-write 0x8 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_06 SW_PAD_CTL_PAD_GPIO_DISP_B1_06 SW PAD Control Register 0x440 32 read-write 0xC 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_07 SW_PAD_CTL_PAD_GPIO_DISP_B1_07 SW PAD Control Register 0x444 32 read-write 0xC 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_08 SW_PAD_CTL_PAD_GPIO_DISP_B1_08 SW PAD Control Register 0x448 32 read-write 0xC 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_09 SW_PAD_CTL_PAD_GPIO_DISP_B1_09 SW PAD Control Register 0x44C 32 read-write 0xC 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_10 SW_PAD_CTL_PAD_GPIO_DISP_B1_10 SW PAD Control Register 0x450 32 read-write 0xC 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B1_11 SW_PAD_CTL_PAD_GPIO_DISP_B1_11 SW PAD Control Register 0x454 32 read-write 0xC 0xFFFFFFFF PDRV PDRV Field 1 1 read-write PDRV_0_high_driver high drive strength 0 PDRV_1_normal_driver normal drive strength 0x1 PULL Pull Down Pull Up Field 2 2 read-write PULL_0_Forbidden Forbidden 0 PULL_1_PU Internal pullup resistor enabled 0x1 PULL_2_PD Internal pulldown resistor enabled 0x2 PULL_3_No_Pull No Pull 0x3 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_00 SW_PAD_CTL_PAD_GPIO_DISP_B2_00 SW PAD Control Register 0x458 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_01 SW_PAD_CTL_PAD_GPIO_DISP_B2_01 SW PAD Control Register 0x45C 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_02 SW_PAD_CTL_PAD_GPIO_DISP_B2_02 SW PAD Control Register 0x460 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_03 SW_PAD_CTL_PAD_GPIO_DISP_B2_03 SW PAD Control Register 0x464 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_04 SW_PAD_CTL_PAD_GPIO_DISP_B2_04 SW PAD Control Register 0x468 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_05 SW_PAD_CTL_PAD_GPIO_DISP_B2_05 SW PAD Control Register 0x46C 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_06 SW_PAD_CTL_PAD_GPIO_DISP_B2_06 SW PAD Control Register 0x470 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_07 SW_PAD_CTL_PAD_GPIO_DISP_B2_07 SW PAD Control Register 0x474 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_08 SW_PAD_CTL_PAD_GPIO_DISP_B2_08 SW PAD Control Register 0x478 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_09 SW_PAD_CTL_PAD_GPIO_DISP_B2_09 SW PAD Control Register 0x47C 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_10 SW_PAD_CTL_PAD_GPIO_DISP_B2_10 SW PAD Control Register 0x480 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_11 SW_PAD_CTL_PAD_GPIO_DISP_B2_11 SW PAD Control Register 0x484 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_12 SW_PAD_CTL_PAD_GPIO_DISP_B2_12 SW PAD Control Register 0x488 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_13 SW_PAD_CTL_PAD_GPIO_DISP_B2_13 SW PAD Control Register 0x48C 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_14 SW_PAD_CTL_PAD_GPIO_DISP_B2_14 SW PAD Control Register 0x490 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register 0x494 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal drive strength 0 DSE_1_high_driver high drive strength 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Pull_Disable__Highz Pull Disable, Highz 0 PUE_1_Pull_Enable Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE Open Drain Field 4 1 read-write ODE_0_Disabled Disabled 0 ODE_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 FLEXCAN1_RX_SELECT_INPUT FLEXCAN1_RX_SELECT_INPUT DAISY Register 0x498 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_AD_07_ALT1 Selecting Pad: GPIO_AD_07 for Mode: ALT1 0 SELECT_GPIO_DISP_B2_13_ALT2 Selecting Pad: GPIO_DISP_B2_13 for Mode: ALT2 0x1 SELECT_GPIO_DISP_B2_15_ALT6 Selecting Pad: GPIO_DISP_B2_15 for Mode: ALT6 0x2 FLEXCAN2_RX_SELECT_INPUT FLEXCAN2_RX_SELECT_INPUT DAISY Register 0x49C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_01_ALT1 Selecting Pad: GPIO_AD_01 for Mode: ALT1 0 SELECT_GPIO_AD_31_ALT2 Selecting Pad: GPIO_AD_31 for Mode: ALT2 0x1 CCM_ENET_QOS_REF_CLK_SELECT_INPUT CCM_ENET_QOS_REF_CLK_SELECT_INPUT DAISY Register 0x4A0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_20_ALT3 Selecting Pad: GPIO_EMC_B2_20 for Mode: ALT3 0 SELECT_GPIO_SD_B2_07_ALT9 Selecting Pad: GPIO_SD_B2_07 for Mode: ALT9 0x1 SELECT_GPIO_DISP_B1_11_ALT9 Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT9 0x2 CCM_ENET_QOS_TX_CLK_SELECT_INPUT CCM_ENET_QOS_TX_CLK_SELECT_INPUT DAISY Register 0x4A4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_DISP_B1_11_ALT8 Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT8 0 SELECT_GPIO_DISP_B2_05_ALT8 Selecting Pad: GPIO_DISP_B2_05 for Mode: ALT8 0x1 ENET_IPG_CLK_RMII_SELECT_INPUT ENET_IPG_CLK_RMII_SELECT_INPUT DAISY Register 0x4A8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_AD_29_ALT2 Selecting Pad: GPIO_AD_29 for Mode: ALT2 0 SELECT_GPIO_DISP_B2_05_ALT2 Selecting Pad: GPIO_DISP_B2_05 for Mode: ALT2 0x1 SELECT_GPIO_DISP_B2_13_ALT4 Selecting Pad: GPIO_DISP_B2_13 for Mode: ALT4 0x2 ENET_MAC0_MDIO_SELECT_INPUT ENET_MAC0_MDIO_SELECT_INPUT DAISY Register 0x4AC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_20_ALT1 Selecting Pad: GPIO_EMC_B2_20 for Mode: ALT1 0 SELECT_GPIO_AD_33_ALT3 Selecting Pad: GPIO_AD_33 for Mode: ALT3 0x1 ENET_MAC0_RXDATA_SELECT_INPUT_0 ENET_MAC0_RXDATA_SELECT_INPUT_0 DAISY Register 0x4B0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_26_ALT3 Selecting Pad: GPIO_AD_26 for Mode: ALT3 0 SELECT_GPIO_DISP_B2_06_ALT1 Selecting Pad: GPIO_DISP_B2_06 for Mode: ALT1 0x1 ENET_MAC0_RXDATA_SELECT_INPUT_1 ENET_MAC0_RXDATA_SELECT_INPUT_1 DAISY Register 0x4B4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_27_ALT3 Selecting Pad: GPIO_AD_27 for Mode: ALT3 0 SELECT_GPIO_DISP_B2_07_ALT1 Selecting Pad: GPIO_DISP_B2_07 for Mode: ALT1 0x1 ENET_MAC0_RXEN_SELECT_INPUT ENET_MAC0_RXEN_SELECT_INPUT DAISY Register 0x4B8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_24_ALT3 Selecting Pad: GPIO_AD_24 for Mode: ALT3 0 SELECT_GPIO_DISP_B2_08_ALT1 Selecting Pad: GPIO_DISP_B2_08 for Mode: ALT1 0x1 ENET_MAC0_RXERR_SELECT_INPUT ENET_MAC0_RXERR_SELECT_INPUT DAISY Register 0x4BC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_25_ALT3 Selecting Pad: GPIO_AD_25 for Mode: ALT3 0 SELECT_GPIO_DISP_B2_09_ALT1 Selecting Pad: GPIO_DISP_B2_09 for Mode: ALT1 0x1 ENET_MAC0_TXCLK_SELECT_INPUT ENET_MAC0_TXCLK_SELECT_INPUT DAISY Register 0x4C0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_29_ALT3 Selecting Pad: GPIO_AD_29 for Mode: ALT3 0 SELECT_GPIO_DISP_B2_05_ALT1 Selecting Pad: GPIO_DISP_B2_05 for Mode: ALT1 0x1 ENET_1G_IPG_CLK_RMII_SELECT_INPUT ENET_1G_IPG_CLK_RMII_SELECT_INPUT DAISY Register 0x4C4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_19_ALT3 Selecting Pad: GPIO_EMC_B2_19 for Mode: ALT3 0 SELECT_GPIO_SD_B2_11_ALT3 Selecting Pad: GPIO_SD_B2_11 for Mode: ALT3 0x1 SELECT_GPIO_DISP_B1_11_ALT2 Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT2 0x2 SELECT_GPIO_DISP_B2_14_ALT4 Selecting Pad: GPIO_DISP_B2_14 for Mode: ALT4 0x3 ENET_1G_MAC0_MDIO_SELECT_INPUT ENET_1G_MAC0_MDIO_SELECT_INPUT DAISY Register 0x4C8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B1_41_ALT7 Selecting Pad: GPIO_EMC_B1_41 for Mode: ALT7 0 SELECT_GPIO_EMC_B2_20_ALT2 Selecting Pad: GPIO_EMC_B2_20 for Mode: ALT2 0x1 SELECT_GPIO_AD_17_ALT9 Selecting Pad: GPIO_AD_17 for Mode: ALT9 0x2 SELECT_GPIO_AD_33_ALT9 Selecting Pad: GPIO_AD_33 for Mode: ALT9 0x3 ENET_1G_MAC0_RXCLK_SELECT_INPUT ENET_1G_MAC0_RXCLK_SELECT_INPUT DAISY Register 0x4CC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_05_ALT7 Selecting Pad: GPIO_EMC_B2_05 for Mode: ALT7 0 SELECT_GPIO_SD_B2_01_ALT2 Selecting Pad: GPIO_SD_B2_01 for Mode: ALT2 0x1 SELECT_GPIO_DISP_B1_01_ALT1 Selecting Pad: GPIO_DISP_B1_01 for Mode: ALT1 0x2 ENET_1G_MAC0_RXDATA_0_SELECT_INPUT ENET_1G_MAC0_RXDATA_0_SELECT_INPUT DAISY Register 0x4D0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_15_ALT2 Selecting Pad: GPIO_EMC_B2_15 for Mode: ALT2 0 SELECT_GPIO_SD_B2_02_ALT2 Selecting Pad: GPIO_SD_B2_02 for Mode: ALT2 0x1 SELECT_GPIO_DISP_B1_02_ALT1 Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT1 0x2 ENET_1G_MAC0_RXDATA_1_SELECT_INPUT ENET_1G_MAC0_RXDATA_1_SELECT_INPUT DAISY Register 0x4D4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_16_ALT2 Selecting Pad: GPIO_EMC_B2_16 for Mode: ALT2 0 SELECT_GPIO_SD_B2_03_ALT2 Selecting Pad: GPIO_SD_B2_03 for Mode: ALT2 0x1 SELECT_GPIO_DISP_B1_03_ALT1 Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT1 0x2 ENET_1G_MAC0_RXDATA_2_SELECT_INPUT ENET_1G_MAC0_RXDATA_2_SELECT_INPUT DAISY Register 0x4D8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_08_ALT7 Selecting Pad: GPIO_EMC_B2_08 for Mode: ALT7 0 SELECT_GPIO_SD_B2_04_ALT2 Selecting Pad: GPIO_SD_B2_04 for Mode: ALT2 0x1 SELECT_GPIO_DISP_B1_04_ALT1 Selecting Pad: GPIO_DISP_B1_04 for Mode: ALT1 0x2 ENET_1G_MAC0_RXDATA_3_SELECT_INPUT ENET_1G_MAC0_RXDATA_3_SELECT_INPUT DAISY Register 0x4DC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_07_ALT7 Selecting Pad: GPIO_EMC_B2_07 for Mode: ALT7 0 SELECT_GPIO_SD_B2_05_ALT2 Selecting Pad: GPIO_SD_B2_05 for Mode: ALT2 0x1 SELECT_GPIO_DISP_B1_05_ALT1 Selecting Pad: GPIO_DISP_B1_05 for Mode: ALT1 0x2 ENET_1G_MAC0_RXEN_SELECT_INPUT ENET_1G_MAC0_RXEN_SELECT_INPUT DAISY Register 0x4E0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_17_ALT2 Selecting Pad: GPIO_EMC_B2_17 for Mode: ALT2 0 SELECT_GPIO_SD_B2_00_ALT2 Selecting Pad: GPIO_SD_B2_00 for Mode: ALT2 0x1 SELECT_GPIO_DISP_B1_00_ALT1 Selecting Pad: GPIO_DISP_B1_00 for Mode: ALT1 0x2 ENET_1G_MAC0_RXERR_SELECT_INPUT ENET_1G_MAC0_RXERR_SELECT_INPUT DAISY Register 0x4E4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_18_ALT2 Selecting Pad: GPIO_EMC_B2_18 for Mode: ALT2 0 SELECT_GPIO_DISP_B1_01_ALT2 Selecting Pad: GPIO_DISP_B1_01 for Mode: ALT2 0x1 ENET_1G_MAC0_TXCLK_SELECT_INPUT ENET_1G_MAC0_TXCLK_SELECT_INPUT DAISY Register 0x4E8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_14_ALT2 Selecting Pad: GPIO_EMC_B2_14 for Mode: ALT2 0 SELECT_GPIO_SD_B2_11_ALT2 Selecting Pad: GPIO_SD_B2_11 for Mode: ALT2 0x1 SELECT_GPIO_DISP_B1_11_ALT1 Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT1 0x2 ENET_QOS_GMII_MDI_I_SELECT_INPUT ENET_QOS_GMII_MDI_I_SELECT_INPUT DAISY Register 0x4EC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_20_ALT8 Selecting Pad: GPIO_EMC_B2_20 for Mode: ALT8 0 SELECT_GPIO_AD_27_ALT9 Selecting Pad: GPIO_AD_27 for Mode: ALT9 0x1 ENET_QOS_PHY_RXD_I_SELECT_INPUT_0 ENET_QOS_PHY_RXD_I_SELECT_INPUT_0 DAISY Register 0x4F0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_DISP_B1_02_ALT8 Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT8 0 SELECT_GPIO_DISP_B2_06_ALT8 Selecting Pad: GPIO_DISP_B2_06 for Mode: ALT8 0x1 ENET_QOS_PHY_RXD_I_SELECT_INPUT_1 ENET_QOS_PHY_RXD_I_SELECT_INPUT_1 DAISY Register 0x4F4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_DISP_B1_03_ALT8 Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT8 0 SELECT_GPIO_DISP_B2_07_ALT8 Selecting Pad: GPIO_DISP_B2_07 for Mode: ALT8 0x1 ENET_QOS_PHY_RXDV_I_SELECT_INPUT ENET_QOS_PHY_RXDV_I_SELECT_INPUT DAISY Register 0x4F8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_DISP_B1_00_ALT8 Selecting Pad: GPIO_DISP_B1_00 for Mode: ALT8 0 SELECT_GPIO_DISP_B2_08_ALT8 Selecting Pad: GPIO_DISP_B2_08 for Mode: ALT8 0x1 ENET_QOS_PHY_RXER_I_SELECT_INPUT ENET_QOS_PHY_RXER_I_SELECT_INPUT DAISY Register 0x4FC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_DISP_B1_01_ALT9 Selecting Pad: GPIO_DISP_B1_01 for Mode: ALT9 0 SELECT_GPIO_DISP_B2_09_ALT8 Selecting Pad: GPIO_DISP_B2_09 for Mode: ALT8 0x1 SELECT_GPIO_DISP_B2_10_ALT8 Selecting Pad: GPIO_DISP_B2_10 for Mode: ALT8 0x2 FLEXPWM1_PWMA_SELECT_INPUT_0 FLEXPWM1_PWMA_SELECT_INPUT_0 DAISY Register 0x500 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_23_ALT1 Selecting Pad: GPIO_EMC_B1_23 for Mode: ALT1 0 SELECT_GPIO_AD_00_ALT4 Selecting Pad: GPIO_AD_00 for Mode: ALT4 0x1 FLEXPWM1_PWMA_SELECT_INPUT_1 FLEXPWM1_PWMA_SELECT_INPUT_1 DAISY Register 0x504 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_25_ALT1 Selecting Pad: GPIO_EMC_B1_25 for Mode: ALT1 0 SELECT_GPIO_AD_02_ALT4 Selecting Pad: GPIO_AD_02 for Mode: ALT4 0x1 FLEXPWM1_PWMA_SELECT_INPUT_2 FLEXPWM1_PWMA_SELECT_INPUT_2 DAISY Register 0x508 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_27_ALT1 Selecting Pad: GPIO_EMC_B1_27 for Mode: ALT1 0 SELECT_GPIO_AD_04_ALT4 Selecting Pad: GPIO_AD_04 for Mode: ALT4 0x1 FLEXPWM1_PWMB_SELECT_INPUT_0 FLEXPWM1_PWMB_SELECT_INPUT_0 DAISY Register 0x50C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_24_ALT1 Selecting Pad: GPIO_EMC_B1_24 for Mode: ALT1 0 SELECT_GPIO_AD_01_ALT4 Selecting Pad: GPIO_AD_01 for Mode: ALT4 0x1 FLEXPWM1_PWMB_SELECT_INPUT_1 FLEXPWM1_PWMB_SELECT_INPUT_1 DAISY Register 0x510 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_26_ALT1 Selecting Pad: GPIO_EMC_B1_26 for Mode: ALT1 0 SELECT_GPIO_AD_03_ALT4 Selecting Pad: GPIO_AD_03 for Mode: ALT4 0x1 FLEXPWM1_PWMB_SELECT_INPUT_2 FLEXPWM1_PWMB_SELECT_INPUT_2 DAISY Register 0x514 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_28_ALT1 Selecting Pad: GPIO_EMC_B1_28 for Mode: ALT1 0 SELECT_GPIO_AD_05_ALT4 Selecting Pad: GPIO_AD_05 for Mode: ALT4 0x1 FLEXPWM2_PWMA_SELECT_INPUT_0 FLEXPWM2_PWMA_SELECT_INPUT_0 DAISY Register 0x518 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_06_ALT1 Selecting Pad: GPIO_EMC_B1_06 for Mode: ALT1 0 SELECT_GPIO_AD_24_ALT4 Selecting Pad: GPIO_AD_24 for Mode: ALT4 0x1 FLEXPWM2_PWMA_SELECT_INPUT_1 FLEXPWM2_PWMA_SELECT_INPUT_1 DAISY Register 0x51C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_08_ALT1 Selecting Pad: GPIO_EMC_B1_08 for Mode: ALT1 0 SELECT_GPIO_AD_26_ALT4 Selecting Pad: GPIO_AD_26 for Mode: ALT4 0x1 FLEXPWM2_PWMA_SELECT_INPUT_2 FLEXPWM2_PWMA_SELECT_INPUT_2 DAISY Register 0x520 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_10_ALT1 Selecting Pad: GPIO_EMC_B1_10 for Mode: ALT1 0 SELECT_GPIO_AD_28_ALT4 Selecting Pad: GPIO_AD_28 for Mode: ALT4 0x1 FLEXPWM2_PWMB_SELECT_INPUT_0 FLEXPWM2_PWMB_SELECT_INPUT_0 DAISY Register 0x524 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_07_ALT1 Selecting Pad: GPIO_EMC_B1_07 for Mode: ALT1 0 SELECT_GPIO_AD_25_ALT4 Selecting Pad: GPIO_AD_25 for Mode: ALT4 0x1 FLEXPWM2_PWMB_SELECT_INPUT_1 FLEXPWM2_PWMB_SELECT_INPUT_1 DAISY Register 0x528 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_09_ALT1 Selecting Pad: GPIO_EMC_B1_09 for Mode: ALT1 0 SELECT_GPIO_AD_27_ALT4 Selecting Pad: GPIO_AD_27 for Mode: ALT4 0x1 FLEXPWM2_PWMB_SELECT_INPUT_2 FLEXPWM2_PWMB_SELECT_INPUT_2 DAISY Register 0x52C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_11_ALT1 Selecting Pad: GPIO_EMC_B1_11 for Mode: ALT1 0 SELECT_GPIO_AD_29_ALT4 Selecting Pad: GPIO_AD_29 for Mode: ALT4 0x1 FLEXPWM3_PWMA_SELECT_INPUT_0 FLEXPWM3_PWMA_SELECT_INPUT_0 DAISY Register 0x530 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_29_ALT1 Selecting Pad: GPIO_EMC_B1_29 for Mode: ALT1 0 SELECT_GPIO_EMC_B2_00_ALT11 Selecting Pad: GPIO_EMC_B2_00 for Mode: ALT11 0x1 FLEXPWM3_PWMA_SELECT_INPUT_1 FLEXPWM3_PWMA_SELECT_INPUT_1 DAISY Register 0x534 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_31_ALT1 Selecting Pad: GPIO_EMC_B1_31 for Mode: ALT1 0 SELECT_GPIO_EMC_B2_02_ALT11 Selecting Pad: GPIO_EMC_B2_02 for Mode: ALT11 0x1 FLEXPWM3_PWMA_SELECT_INPUT_2 FLEXPWM3_PWMA_SELECT_INPUT_2 DAISY Register 0x538 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_33_ALT1 Selecting Pad: GPIO_EMC_B1_33 for Mode: ALT1 0 SELECT_GPIO_EMC_B2_04_ALT11 Selecting Pad: GPIO_EMC_B2_04 for Mode: ALT11 0x1 FLEXPWM3_PWMA_SELECT_INPUT_3 FLEXPWM3_PWMA_SELECT_INPUT_3 DAISY Register 0x53C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_21_ALT1 Selecting Pad: GPIO_EMC_B1_21 for Mode: ALT1 0 SELECT_GPIO_EMC_B2_06_ALT11 Selecting Pad: GPIO_EMC_B2_06 for Mode: ALT11 0x1 FLEXPWM3_PWMB_SELECT_INPUT_0 FLEXPWM3_PWMB_SELECT_INPUT_0 DAISY Register 0x540 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_30_ALT1 Selecting Pad: GPIO_EMC_B1_30 for Mode: ALT1 0 SELECT_GPIO_EMC_B2_01_ALT11 Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT11 0x1 FLEXPWM3_PWMB_SELECT_INPUT_1 FLEXPWM3_PWMB_SELECT_INPUT_1 DAISY Register 0x544 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_32_ALT1 Selecting Pad: GPIO_EMC_B1_32 for Mode: ALT1 0 SELECT_GPIO_EMC_B2_03_ALT11 Selecting Pad: GPIO_EMC_B2_03 for Mode: ALT11 0x1 FLEXPWM3_PWMB_SELECT_INPUT_2 FLEXPWM3_PWMB_SELECT_INPUT_2 DAISY Register 0x548 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_34_ALT1 Selecting Pad: GPIO_EMC_B1_34 for Mode: ALT1 0 SELECT_GPIO_EMC_B2_05_ALT11 Selecting Pad: GPIO_EMC_B2_05 for Mode: ALT11 0x1 FLEXPWM3_PWMB_SELECT_INPUT_3 FLEXPWM3_PWMB_SELECT_INPUT_3 DAISY Register 0x54C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B1_22_ALT1 Selecting Pad: GPIO_EMC_B1_22 for Mode: ALT1 0 SELECT_GPIO_EMC_B2_07_ALT11 Selecting Pad: GPIO_EMC_B2_07 for Mode: ALT11 0x1 FLEXSPI1_I_DQS_FA_SELECT_INPUT FLEXSPI1_I_DQS_FA_SELECT_INPUT DAISY Register 0x550 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_18_ALT6 Selecting Pad: GPIO_EMC_B2_18 for Mode: ALT6 0 SELECT_GPIO_AD_17_ALT3 Selecting Pad: GPIO_AD_17 for Mode: ALT3 0x1 SELECT_GPIO_SD_B2_05_ALT1 Selecting Pad: GPIO_SD_B2_05 for Mode: ALT1 0x2 FLEXSPI1_I_IO_FA_SELECT_INPUT_0 FLEXSPI1_I_IO_FA_SELECT_INPUT_0 DAISY Register 0x554 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_20_ALT3 Selecting Pad: GPIO_AD_20 for Mode: ALT3 0 SELECT_GPIO_SD_B2_08_ALT1 Selecting Pad: GPIO_SD_B2_08 for Mode: ALT1 0x1 FLEXSPI1_I_IO_FA_SELECT_INPUT_1 FLEXSPI1_I_IO_FA_SELECT_INPUT_1 DAISY Register 0x558 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_21_ALT3 Selecting Pad: GPIO_AD_21 for Mode: ALT3 0 SELECT_GPIO_SD_B2_09_ALT1 Selecting Pad: GPIO_SD_B2_09 for Mode: ALT1 0x1 FLEXSPI1_I_IO_FA_SELECT_INPUT_2 FLEXSPI1_I_IO_FA_SELECT_INPUT_2 DAISY Register 0x55C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_22_ALT3 Selecting Pad: GPIO_AD_22 for Mode: ALT3 0 SELECT_GPIO_SD_B2_10_ALT1 Selecting Pad: GPIO_SD_B2_10 for Mode: ALT1 0x1 FLEXSPI1_I_IO_FA_SELECT_INPUT_3 FLEXSPI1_I_IO_FA_SELECT_INPUT_3 DAISY Register 0x560 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_23_ALT3 Selecting Pad: GPIO_AD_23 for Mode: ALT3 0 SELECT_GPIO_SD_B2_11_ALT1 Selecting Pad: GPIO_SD_B2_11 for Mode: ALT1 0x1 FLEXSPI1_I_IO_FB_SELECT_INPUT_0 FLEXSPI1_I_IO_FB_SELECT_INPUT_0 DAISY Register 0x564 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_15_ALT3 Selecting Pad: GPIO_AD_15 for Mode: ALT3 0 SELECT_GPIO_SD_B2_03_ALT1 Selecting Pad: GPIO_SD_B2_03 for Mode: ALT1 0x1 FLEXSPI1_I_IO_FB_SELECT_INPUT_1 FLEXSPI1_I_IO_FB_SELECT_INPUT_1 DAISY Register 0x568 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_14_ALT3 Selecting Pad: GPIO_AD_14 for Mode: ALT3 0 SELECT_GPIO_SD_B2_02_ALT1 Selecting Pad: GPIO_SD_B2_02 for Mode: ALT1 0x1 FLEXSPI1_I_IO_FB_SELECT_INPUT_2 FLEXSPI1_I_IO_FB_SELECT_INPUT_2 DAISY Register 0x56C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_13_ALT3 Selecting Pad: GPIO_AD_13 for Mode: ALT3 0 SELECT_GPIO_SD_B2_01_ALT1 Selecting Pad: GPIO_SD_B2_01 for Mode: ALT1 0x1 FLEXSPI1_I_IO_FB_SELECT_INPUT_3 FLEXSPI1_I_IO_FB_SELECT_INPUT_3 DAISY Register 0x570 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_12_ALT3 Selecting Pad: GPIO_AD_12 for Mode: ALT3 0 SELECT_GPIO_SD_B2_00_ALT1 Selecting Pad: GPIO_SD_B2_00 for Mode: ALT1 0x1 FLEXSPI1_I_SCK_FA_SELECT_INPUT FLEXSPI1_I_SCK_FA_SELECT_INPUT DAISY Register 0x574 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_19_ALT3 Selecting Pad: GPIO_AD_19 for Mode: ALT3 0 SELECT_GPIO_SD_B2_07_ALT1 Selecting Pad: GPIO_SD_B2_07 for Mode: ALT1 0x1 FLEXSPI1_I_SCK_FB_SELECT_INPUT FLEXSPI1_I_SCK_FB_SELECT_INPUT DAISY Register 0x578 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_16_ALT3 Selecting Pad: GPIO_AD_16 for Mode: ALT3 0 SELECT_GPIO_SD_B2_04_ALT1 Selecting Pad: GPIO_SD_B2_04 for Mode: ALT1 0x1 FLEXSPI2_I_IO_FA_SELECT_INPUT_0 FLEXSPI2_I_IO_FA_SELECT_INPUT_0 DAISY Register 0x57C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_13_ALT4 Selecting Pad: GPIO_EMC_B2_13 for Mode: ALT4 0 SELECT_GPIO_SD_B1_02_ALT6 Selecting Pad: GPIO_SD_B1_02 for Mode: ALT6 0x1 FLEXSPI2_I_IO_FA_SELECT_INPUT_1 FLEXSPI2_I_IO_FA_SELECT_INPUT_1 DAISY Register 0x580 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_14_ALT4 Selecting Pad: GPIO_EMC_B2_14 for Mode: ALT4 0 SELECT_GPIO_SD_B1_03_ALT6 Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6 0x1 FLEXSPI2_I_IO_FA_SELECT_INPUT_2 FLEXSPI2_I_IO_FA_SELECT_INPUT_2 DAISY Register 0x584 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_15_ALT4 Selecting Pad: GPIO_EMC_B2_15 for Mode: ALT4 0 SELECT_GPIO_SD_B1_04_ALT6 Selecting Pad: GPIO_SD_B1_04 for Mode: ALT6 0x1 FLEXSPI2_I_IO_FA_SELECT_INPUT_3 FLEXSPI2_I_IO_FA_SELECT_INPUT_3 DAISY Register 0x588 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_16_ALT4 Selecting Pad: GPIO_EMC_B2_16 for Mode: ALT4 0 SELECT_GPIO_SD_B1_05_ALT6 Selecting Pad: GPIO_SD_B1_05 for Mode: ALT6 0x1 FLEXSPI2_I_SCK_FA_SELECT_INPUT FLEXSPI2_I_SCK_FA_SELECT_INPUT DAISY Register 0x58C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_10_ALT4 Selecting Pad: GPIO_EMC_B2_10 for Mode: ALT4 0 SELECT_GPIO_SD_B1_01_ALT6 Selecting Pad: GPIO_SD_B1_01 for Mode: ALT6 0x1 GPT3_CAPIN1_SELECT_INPUT GPT3_CAPIN1_SELECT_INPUT DAISY Register 0x590 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_06_ALT1 Selecting Pad: GPIO_EMC_B2_06 for Mode: ALT1 0 SELECT_GPIO_AD_06_ALT3 Selecting Pad: GPIO_AD_06 for Mode: ALT3 0x1 GPT3_CAPIN2_SELECT_INPUT GPT3_CAPIN2_SELECT_INPUT DAISY Register 0x594 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_07_ALT1 Selecting Pad: GPIO_EMC_B2_07 for Mode: ALT1 0 SELECT_GPIO_AD_07_ALT3 Selecting Pad: GPIO_AD_07 for Mode: ALT3 0x1 GPT3_CLKIN_SELECT_INPUT GPT3_CLKIN_SELECT_INPUT DAISY Register 0x598 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_05_ALT1 Selecting Pad: GPIO_EMC_B2_05 for Mode: ALT1 0 SELECT_GPIO_AD_11_ALT3 Selecting Pad: GPIO_AD_11 for Mode: ALT3 0x1 KPP_COL_SELECT_INPUT_6 KPP_COL_SELECT_INPUT_6 DAISY Register 0x59C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_23_ALT6 Selecting Pad: GPIO_AD_23 for Mode: ALT6 0 SELECT_GPIO_SD_B1_03_ALT8 Selecting Pad: GPIO_SD_B1_03 for Mode: ALT8 0x1 KPP_COL_SELECT_INPUT_7 KPP_COL_SELECT_INPUT_7 DAISY Register 0x5A0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_21_ALT6 Selecting Pad: GPIO_AD_21 for Mode: ALT6 0 SELECT_GPIO_SD_B1_01_ALT8 Selecting Pad: GPIO_SD_B1_01 for Mode: ALT8 0x1 KPP_ROW_SELECT_INPUT_6 KPP_ROW_SELECT_INPUT_6 DAISY Register 0x5A4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_22_ALT6 Selecting Pad: GPIO_AD_22 for Mode: ALT6 0 SELECT_GPIO_SD_B1_02_ALT8 Selecting Pad: GPIO_SD_B1_02 for Mode: ALT8 0x1 KPP_ROW_SELECT_INPUT_7 KPP_ROW_SELECT_INPUT_7 DAISY Register 0x5A8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_20_ALT6 Selecting Pad: GPIO_AD_20 for Mode: ALT6 0 SELECT_GPIO_SD_B1_00_ALT8 Selecting Pad: GPIO_SD_B1_00 for Mode: ALT8 0x1 LPI2C1_LPI2C_SCL_SELECT_INPUT LPI2C1_LPI2C_SCL_SELECT_INPUT DAISY Register 0x5AC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_08_ALT1 Selecting Pad: GPIO_AD_08 for Mode: ALT1 0 SELECT_GPIO_AD_32_ALT0 Selecting Pad: GPIO_AD_32 for Mode: ALT0 0x1 LPI2C1_LPI2C_SDA_SELECT_INPUT LPI2C1_LPI2C_SDA_SELECT_INPUT DAISY Register 0x5B0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_09_ALT1 Selecting Pad: GPIO_AD_09 for Mode: ALT1 0 SELECT_GPIO_AD_33_ALT0 Selecting Pad: GPIO_AD_33 for Mode: ALT0 0x1 LPI2C2_LPI2C_SCL_SELECT_INPUT LPI2C2_LPI2C_SCL_SELECT_INPUT DAISY Register 0x5B4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_00_ALT9 Selecting Pad: GPIO_EMC_B2_00 for Mode: ALT9 0 SELECT_GPIO_AD_18_ALT9 Selecting Pad: GPIO_AD_18 for Mode: ALT9 0x1 LPI2C2_LPI2C_SDA_SELECT_INPUT LPI2C2_LPI2C_SDA_SELECT_INPUT DAISY Register 0x5B8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_01_ALT9 Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT9 0 SELECT_GPIO_AD_19_ALT9 Selecting Pad: GPIO_AD_19 for Mode: ALT9 0x1 LPI2C3_LPI2C_SCL_SELECT_INPUT LPI2C3_LPI2C_SCL_SELECT_INPUT DAISY Register 0x5BC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_DISP_B1_02_ALT2 Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT2 0 SELECT_GPIO_DISP_B2_10_ALT6 Selecting Pad: GPIO_DISP_B2_10 for Mode: ALT6 0x1 LPI2C3_LPI2C_SDA_SELECT_INPUT LPI2C3_LPI2C_SDA_SELECT_INPUT DAISY Register 0x5C0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_DISP_B1_03_ALT2 Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT2 0 SELECT_GPIO_DISP_B2_11_ALT6 Selecting Pad: GPIO_DISP_B2_11 for Mode: ALT6 0x1 LPI2C4_LPI2C_SCL_SELECT_INPUT LPI2C4_LPI2C_SCL_SELECT_INPUT DAISY Register 0x5C4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_24_ALT9 Selecting Pad: GPIO_AD_24 for Mode: ALT9 0 SELECT_GPIO_DISP_B2_12_ALT6 Selecting Pad: GPIO_DISP_B2_12 for Mode: ALT6 0x1 LPI2C4_LPI2C_SDA_SELECT_INPUT LPI2C4_LPI2C_SDA_SELECT_INPUT DAISY Register 0x5C8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_25_ALT9 Selecting Pad: GPIO_AD_25 for Mode: ALT9 0 SELECT_GPIO_DISP_B2_13_ALT6 Selecting Pad: GPIO_DISP_B2_13 for Mode: ALT6 0x1 LPSPI1_LPSPI_PCS_SELECT_INPUT_0 LPSPI1_LPSPI_PCS_SELECT_INPUT_0 DAISY Register 0x5CC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_01_ALT8 Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT8 0 SELECT_GPIO_AD_29_ALT0 Selecting Pad: GPIO_AD_29 for Mode: ALT0 0x1 LPSPI1_LPSPI_SCK_SELECT_INPUT LPSPI1_LPSPI_SCK_SELECT_INPUT DAISY Register 0x5D0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_00_ALT8 Selecting Pad: GPIO_EMC_B2_00 for Mode: ALT8 0 SELECT_GPIO_AD_28_ALT0 Selecting Pad: GPIO_AD_28 for Mode: ALT0 0x1 LPSPI1_LPSPI_SDI_SELECT_INPUT LPSPI1_LPSPI_SDI_SELECT_INPUT DAISY Register 0x5D4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_03_ALT8 Selecting Pad: GPIO_EMC_B2_03 for Mode: ALT8 0 SELECT_GPIO_AD_31_ALT0 Selecting Pad: GPIO_AD_31 for Mode: ALT0 0x1 LPSPI1_LPSPI_SDO_SELECT_INPUT LPSPI1_LPSPI_SDO_SELECT_INPUT DAISY Register 0x5D8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_02_ALT8 Selecting Pad: GPIO_EMC_B2_02 for Mode: ALT8 0 SELECT_GPIO_AD_30_ALT0 Selecting Pad: GPIO_AD_30 for Mode: ALT0 0x1 LPSPI2_LPSPI_PCS_SELECT_INPUT_0 LPSPI2_LPSPI_PCS_SELECT_INPUT_0 DAISY Register 0x5DC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_25_ALT1 Selecting Pad: GPIO_AD_25 for Mode: ALT1 0 SELECT_GPIO_SD_B2_08_ALT6 Selecting Pad: GPIO_SD_B2_08 for Mode: ALT6 0x1 LPSPI2_LPSPI_PCS_SELECT_INPUT_1 LPSPI2_LPSPI_PCS_SELECT_INPUT_1 DAISY Register 0x5E0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_21_ALT2 Selecting Pad: GPIO_AD_21 for Mode: ALT2 0 SELECT_GPIO_SD_B2_11_ALT6 Selecting Pad: GPIO_SD_B2_11 for Mode: ALT6 0x1 LPSPI2_LPSPI_SCK_SELECT_INPUT LPSPI2_LPSPI_SCK_SELECT_INPUT DAISY Register 0x5E4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_24_ALT1 Selecting Pad: GPIO_AD_24 for Mode: ALT1 0 SELECT_GPIO_SD_B2_07_ALT6 Selecting Pad: GPIO_SD_B2_07 for Mode: ALT6 0x1 LPSPI2_LPSPI_SDI_SELECT_INPUT LPSPI2_LPSPI_SDI_SELECT_INPUT DAISY Register 0x5E8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_27_ALT1 Selecting Pad: GPIO_AD_27 for Mode: ALT1 0 SELECT_GPIO_SD_B2_10_ALT6 Selecting Pad: GPIO_SD_B2_10 for Mode: ALT6 0x1 LPSPI2_LPSPI_SDO_SELECT_INPUT LPSPI2_LPSPI_SDO_SELECT_INPUT DAISY Register 0x5EC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_26_ALT1 Selecting Pad: GPIO_AD_26 for Mode: ALT1 0 SELECT_GPIO_SD_B2_09_ALT6 Selecting Pad: GPIO_SD_B2_09 for Mode: ALT6 0x1 LPSPI3_LPSPI_PCS_SELECT_INPUT_0 LPSPI3_LPSPI_PCS_SELECT_INPUT_0 DAISY Register 0x5F0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_05_ALT8 Selecting Pad: GPIO_EMC_B2_05 for Mode: ALT8 0 SELECT_GPIO_DISP_B1_07_ALT9 Selecting Pad: GPIO_DISP_B1_07 for Mode: ALT9 0x1 LPSPI3_LPSPI_PCS_SELECT_INPUT_1 LPSPI3_LPSPI_PCS_SELECT_INPUT_1 DAISY Register 0x5F4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_08_ALT8 Selecting Pad: GPIO_EMC_B2_08 for Mode: ALT8 0 SELECT_GPIO_DISP_B1_08_ALT9 Selecting Pad: GPIO_DISP_B1_08 for Mode: ALT9 0x1 LPSPI3_LPSPI_PCS_SELECT_INPUT_2 LPSPI3_LPSPI_PCS_SELECT_INPUT_2 DAISY Register 0x5F8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_09_ALT8 Selecting Pad: GPIO_EMC_B2_09 for Mode: ALT8 0 SELECT_GPIO_DISP_B1_09_ALT9 Selecting Pad: GPIO_DISP_B1_09 for Mode: ALT9 0x1 LPSPI3_LPSPI_PCS_SELECT_INPUT_3 LPSPI3_LPSPI_PCS_SELECT_INPUT_3 DAISY Register 0x5FC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_10_ALT8 Selecting Pad: GPIO_EMC_B2_10 for Mode: ALT8 0 SELECT_GPIO_DISP_B1_10_ALT9 Selecting Pad: GPIO_DISP_B1_10 for Mode: ALT9 0x1 LPSPI3_LPSPI_SCK_SELECT_INPUT LPSPI3_LPSPI_SCK_SELECT_INPUT DAISY Register 0x600 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_04_ALT8 Selecting Pad: GPIO_EMC_B2_04 for Mode: ALT8 0 SELECT_GPIO_DISP_B1_04_ALT9 Selecting Pad: GPIO_DISP_B1_04 for Mode: ALT9 0x1 LPSPI3_LPSPI_SDI_SELECT_INPUT LPSPI3_LPSPI_SDI_SELECT_INPUT DAISY Register 0x604 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_07_ALT8 Selecting Pad: GPIO_EMC_B2_07 for Mode: ALT8 0 SELECT_GPIO_DISP_B1_05_ALT9 Selecting Pad: GPIO_DISP_B1_05 for Mode: ALT9 0x1 LPSPI3_LPSPI_SDO_SELECT_INPUT LPSPI3_LPSPI_SDO_SELECT_INPUT DAISY Register 0x608 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_06_ALT8 Selecting Pad: GPIO_EMC_B2_06 for Mode: ALT8 0 SELECT_GPIO_DISP_B1_06_ALT9 Selecting Pad: GPIO_DISP_B1_06 for Mode: ALT9 0x1 LPSPI4_LPSPI_PCS_SELECT_INPUT_0 LPSPI4_LPSPI_PCS_SELECT_INPUT_0 DAISY Register 0x60C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_SD_B2_01_ALT4 Selecting Pad: GPIO_SD_B2_01 for Mode: ALT4 0 SELECT_GPIO_DISP_B2_15_ALT9 Selecting Pad: GPIO_DISP_B2_15 for Mode: ALT9 0x1 LPSPI4_LPSPI_SCK_SELECT_INPUT LPSPI4_LPSPI_SCK_SELECT_INPUT DAISY Register 0x610 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_SD_B2_00_ALT4 Selecting Pad: GPIO_SD_B2_00 for Mode: ALT4 0 SELECT_GPIO_DISP_B2_12_ALT9 Selecting Pad: GPIO_DISP_B2_12 for Mode: ALT9 0x1 LPSPI4_LPSPI_SDI_SELECT_INPUT LPSPI4_LPSPI_SDI_SELECT_INPUT DAISY Register 0x614 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_SD_B2_03_ALT4 Selecting Pad: GPIO_SD_B2_03 for Mode: ALT4 0 SELECT_GPIO_DISP_B2_13_ALT9 Selecting Pad: GPIO_DISP_B2_13 for Mode: ALT9 0x1 LPSPI4_LPSPI_SDO_SELECT_INPUT LPSPI4_LPSPI_SDO_SELECT_INPUT DAISY Register 0x618 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_SD_B2_02_ALT4 Selecting Pad: GPIO_SD_B2_02 for Mode: ALT4 0 SELECT_GPIO_DISP_B2_14_ALT9 Selecting Pad: GPIO_DISP_B2_14 for Mode: ALT9 0x1 LPUART1_LPUART_RXD_SELECT_INPUT LPUART1_LPUART_RXD_SELECT_INPUT DAISY Register 0x61C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_AD_25_ALT0 Selecting Pad: GPIO_AD_25 for Mode: ALT0 0 SELECT_GPIO_DISP_B1_03_ALT9 Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT9 0x1 SELECT_GPIO_DISP_B2_09_ALT9 Selecting Pad: GPIO_DISP_B2_09 for Mode: ALT9 0x2 LPUART1_LPUART_TXD_SELECT_INPUT LPUART1_LPUART_TXD_SELECT_INPUT DAISY Register 0x620 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_AD_24_ALT0 Selecting Pad: GPIO_AD_24 for Mode: ALT0 0 SELECT_GPIO_DISP_B1_02_ALT9 Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT9 0x1 SELECT_GPIO_DISP_B2_08_ALT9 Selecting Pad: GPIO_DISP_B2_08 for Mode: ALT9 0x2 LPUART10_LPUART_RXD_SELECT_INPUT LPUART10_LPUART_RXD_SELECT_INPUT DAISY Register 0x624 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_16_ALT1 Selecting Pad: GPIO_AD_16 for Mode: ALT1 0 SELECT_GPIO_AD_33_ALT8 Selecting Pad: GPIO_AD_33 for Mode: ALT8 0x1 LPUART10_LPUART_TXD_SELECT_INPUT LPUART10_LPUART_TXD_SELECT_INPUT DAISY Register 0x628 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_15_ALT1 Selecting Pad: GPIO_AD_15 for Mode: ALT1 0 SELECT_GPIO_AD_32_ALT8 Selecting Pad: GPIO_AD_32 for Mode: ALT8 0x1 LPUART7_LPUART_RXD_SELECT_INPUT LPUART7_LPUART_RXD_SELECT_INPUT DAISY Register 0x62C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_01_ALT6 Selecting Pad: GPIO_AD_01 for Mode: ALT6 0 SELECT_GPIO_DISP_B2_07_ALT2 Selecting Pad: GPIO_DISP_B2_07 for Mode: ALT2 0x1 LPUART7_LPUART_TXD_SELECT_INPUT LPUART7_LPUART_TXD_SELECT_INPUT DAISY Register 0x630 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_00_ALT6 Selecting Pad: GPIO_AD_00 for Mode: ALT6 0 SELECT_GPIO_DISP_B2_06_ALT2 Selecting Pad: GPIO_DISP_B2_06 for Mode: ALT2 0x1 LPUART8_LPUART_RXD_SELECT_INPUT LPUART8_LPUART_RXD_SELECT_INPUT DAISY Register 0x634 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_03_ALT6 Selecting Pad: GPIO_AD_03 for Mode: ALT6 0 SELECT_GPIO_DISP_B2_09_ALT2 Selecting Pad: GPIO_DISP_B2_09 for Mode: ALT2 0x1 LPUART8_LPUART_TXD_SELECT_INPUT LPUART8_LPUART_TXD_SELECT_INPUT DAISY Register 0x638 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_02_ALT6 Selecting Pad: GPIO_AD_02 for Mode: ALT6 0 SELECT_GPIO_DISP_B2_08_ALT2 Selecting Pad: GPIO_DISP_B2_08 for Mode: ALT2 0x1 QTIMER1_TMR0_INPUT_SELECT_INPUT QTIMER1_TMR0_INPUT_SELECT_INPUT DAISY Register 0x63C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B1_17_ALT2 Selecting Pad: GPIO_EMC_B1_17 for Mode: ALT2 0 SELECT_GPIO_EMC_B2_09_ALT9 Selecting Pad: GPIO_EMC_B2_09 for Mode: ALT9 0x1 SELECT_GPIO_DISP_B1_00_ALT3 Selecting Pad: GPIO_DISP_B1_00 for Mode: ALT3 0x2 QTIMER1_TMR1_INPUT_SELECT_INPUT QTIMER1_TMR1_INPUT_SELECT_INPUT DAISY Register 0x640 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B1_38_ALT2 Selecting Pad: GPIO_EMC_B1_38 for Mode: ALT2 0 SELECT_GPIO_EMC_B2_10_ALT9 Selecting Pad: GPIO_EMC_B2_10 for Mode: ALT9 0x1 SELECT_GPIO_DISP_B1_01_ALT3 Selecting Pad: GPIO_DISP_B1_01 for Mode: ALT3 0x2 QTIMER1_TMR2_INPUT_SELECT_INPUT QTIMER1_TMR2_INPUT_SELECT_INPUT DAISY Register 0x644 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_11_ALT9 Selecting Pad: GPIO_EMC_B2_11 for Mode: ALT9 0 SELECT_GPIO_DISP_B1_02_ALT3 Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT3 0x1 QTIMER2_TMR0_INPUT_SELECT_INPUT QTIMER2_TMR0_INPUT_SELECT_INPUT DAISY Register 0x648 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B1_18_ALT2 Selecting Pad: GPIO_EMC_B1_18 for Mode: ALT2 0 SELECT_GPIO_EMC_B2_13_ALT9 Selecting Pad: GPIO_EMC_B2_13 for Mode: ALT9 0x1 SELECT_GPIO_DISP_B1_03_ALT3 Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT3 0x2 QTIMER2_TMR1_INPUT_SELECT_INPUT QTIMER2_TMR1_INPUT_SELECT_INPUT DAISY Register 0x64C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B1_39_ALT2 Selecting Pad: GPIO_EMC_B1_39 for Mode: ALT2 0 SELECT_GPIO_EMC_B2_14_ALT9 Selecting Pad: GPIO_EMC_B2_14 for Mode: ALT9 0x1 SELECT_GPIO_DISP_B1_04_ALT3 Selecting Pad: GPIO_DISP_B1_04 for Mode: ALT3 0x2 QTIMER2_TMR2_INPUT_SELECT_INPUT QTIMER2_TMR2_INPUT_SELECT_INPUT DAISY Register 0x650 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_15_ALT9 Selecting Pad: GPIO_EMC_B2_15 for Mode: ALT9 0 SELECT_GPIO_DISP_B1_05_ALT3 Selecting Pad: GPIO_DISP_B1_05 for Mode: ALT3 0x1 QTIMER3_TMR0_INPUT_SELECT_INPUT QTIMER3_TMR0_INPUT_SELECT_INPUT DAISY Register 0x654 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B1_19_ALT2 Selecting Pad: GPIO_EMC_B1_19 for Mode: ALT2 0 SELECT_GPIO_EMC_B2_17_ALT9 Selecting Pad: GPIO_EMC_B2_17 for Mode: ALT9 0x1 SELECT_GPIO_DISP_B1_06_ALT3 Selecting Pad: GPIO_DISP_B1_06 for Mode: ALT3 0x2 QTIMER3_TMR1_INPUT_SELECT_INPUT QTIMER3_TMR1_INPUT_SELECT_INPUT DAISY Register 0x658 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_00_ALT2 Selecting Pad: GPIO_EMC_B2_00 for Mode: ALT2 0 SELECT_GPIO_EMC_B2_18_ALT9 Selecting Pad: GPIO_EMC_B2_18 for Mode: ALT9 0x1 SELECT_GPIO_DISP_B1_07_ALT3 Selecting Pad: GPIO_DISP_B1_07 for Mode: ALT3 0x2 QTIMER3_TMR2_INPUT_SELECT_INPUT QTIMER3_TMR2_INPUT_SELECT_INPUT DAISY Register 0x65C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_19_ALT9 Selecting Pad: GPIO_EMC_B2_19 for Mode: ALT9 0 SELECT_GPIO_DISP_B1_08_ALT3 Selecting Pad: GPIO_DISP_B1_08 for Mode: ALT3 0x1 QTIMER4_TMR0_INPUT_SELECT_INPUT QTIMER4_TMR0_INPUT_SELECT_INPUT DAISY Register 0x660 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B1_20_ALT2 Selecting Pad: GPIO_EMC_B1_20 for Mode: ALT2 0 SELECT_GPIO_AD_04_ALT9 Selecting Pad: GPIO_AD_04 for Mode: ALT9 0x1 SELECT_GPIO_DISP_B1_09_ALT3 Selecting Pad: GPIO_DISP_B1_09 for Mode: ALT3 0x2 QTIMER4_TMR1_INPUT_SELECT_INPUT QTIMER4_TMR1_INPUT_SELECT_INPUT DAISY Register 0x664 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_01_ALT2 Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT2 0 SELECT_GPIO_AD_05_ALT9 Selecting Pad: GPIO_AD_05 for Mode: ALT9 0x1 SELECT_GPIO_DISP_B1_10_ALT3 Selecting Pad: GPIO_DISP_B1_10 for Mode: ALT3 0x2 QTIMER4_TMR2_INPUT_SELECT_INPUT QTIMER4_TMR2_INPUT_SELECT_INPUT DAISY Register 0x668 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_06_ALT9 Selecting Pad: GPIO_AD_06 for Mode: ALT9 0 SELECT_GPIO_DISP_B1_11_ALT3 Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT3 0x1 SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT DAISY Register 0x66C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_17_ALT0 Selecting Pad: GPIO_AD_17 for Mode: ALT0 0 SELECT_GPIO_DISP_B2_03_ALT4 Selecting Pad: GPIO_DISP_B2_03 for Mode: ALT4 0x1 SAI1_SAI_RXBCLK_SELECT_INPUT SAI1_SAI_RXBCLK_SELECT_INPUT DAISY Register 0x670 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_19_ALT0 Selecting Pad: GPIO_AD_19 for Mode: ALT0 0 SELECT_GPIO_DISP_B2_05_ALT4 Selecting Pad: GPIO_DISP_B2_05 for Mode: ALT4 0x1 SAI1_SAI_RXDATA_SELECT_INPUT_0 SAI1_SAI_RXDATA_SELECT_INPUT_0 DAISY Register 0x674 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_20_ALT0 Selecting Pad: GPIO_AD_20 for Mode: ALT0 0 SELECT_GPIO_DISP_B2_06_ALT4 Selecting Pad: GPIO_DISP_B2_06 for Mode: ALT4 0x1 SAI1_SAI_RXSYNC_SELECT_INPUT SAI1_SAI_RXSYNC_SELECT_INPUT DAISY Register 0x678 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_18_ALT0 Selecting Pad: GPIO_AD_18 for Mode: ALT0 0 SELECT_GPIO_DISP_B2_04_ALT4 Selecting Pad: GPIO_DISP_B2_04 for Mode: ALT4 0x1 SAI1_SAI_TXBCLK_SELECT_INPUT SAI1_SAI_TXBCLK_SELECT_INPUT DAISY Register 0x67C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_22_ALT0 Selecting Pad: GPIO_AD_22 for Mode: ALT0 0 SELECT_GPIO_DISP_B2_08_ALT4 Selecting Pad: GPIO_DISP_B2_08 for Mode: ALT4 0x1 SAI1_SAI_TXSYNC_SELECT_INPUT SAI1_SAI_TXSYNC_SELECT_INPUT DAISY Register 0x680 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_23_ALT0 Selecting Pad: GPIO_AD_23 for Mode: ALT0 0 SELECT_GPIO_DISP_B2_09_ALT4 Selecting Pad: GPIO_DISP_B2_09 for Mode: ALT4 0x1 EMVSIM1_SIO_SELECT_INPUT EMVSIM1_SIO_SELECT_INPUT DAISY Register 0x69C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_11_ALT8 Selecting Pad: GPIO_EMC_B2_11 for Mode: ALT8 0 SELECT_GPIO_AD_00_ALT0 Selecting Pad: GPIO_AD_00 for Mode: ALT0 0x1 EMVSIM1_IPP_SIMPD_SELECT_INPUT EMVSIM1_IPP_SIMPD_SELECT_INPUT DAISY Register 0x6A0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_15_ALT8 Selecting Pad: GPIO_EMC_B2_15 for Mode: ALT8 0 SELECT_GPIO_AD_04_ALT0 Selecting Pad: GPIO_AD_04 for Mode: ALT0 0x1 EMVSIM1_POWER_FAIL_SELECT_INPUT EMVSIM1_POWER_FAIL_SELECT_INPUT DAISY Register 0x6A4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_16_ALT8 Selecting Pad: GPIO_EMC_B2_16 for Mode: ALT8 0 SELECT_GPIO_AD_05_ALT0 Selecting Pad: GPIO_AD_05 for Mode: ALT0 0x1 EMVSIM2_SIO_SELECT_INPUT EMVSIM2_SIO_SELECT_INPUT DAISY Register 0x6A8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_06_ALT2 Selecting Pad: GPIO_AD_06 for Mode: ALT2 0 SELECT_GPIO_DISP_B2_10_ALT1 Selecting Pad: GPIO_DISP_B2_10 for Mode: ALT1 0x1 EMVSIM2_IPP_SIMPD_SELECT_INPUT EMVSIM2_IPP_SIMPD_SELECT_INPUT DAISY Register 0x6AC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_10_ALT2 Selecting Pad: GPIO_AD_10 for Mode: ALT2 0 SELECT_GPIO_DISP_B2_14_ALT1 Selecting Pad: GPIO_DISP_B2_14 for Mode: ALT1 0x1 EMVSIM2_POWER_FAIL_SELECT_INPUT EMVSIM2_POWER_FAIL_SELECT_INPUT DAISY Register 0x6B0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_11_ALT2 Selecting Pad: GPIO_AD_11 for Mode: ALT2 0 SELECT_GPIO_DISP_B2_15_ALT1 Selecting Pad: GPIO_DISP_B2_15 for Mode: ALT1 0x1 SPDIF_SPDIF_IN1_SELECT_INPUT SPDIF_SPDIF_IN1_SELECT_INPUT DAISY Register 0x6B4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_EMC_B2_11_ALT1 Selecting Pad: GPIO_EMC_B2_11 for Mode: ALT1 0 SELECT_GPIO_AD_15_ALT0 Selecting Pad: GPIO_AD_15 for Mode: ALT0 0x1 SELECT_GPIO_DISP_B2_10_ALT9 Selecting Pad: GPIO_DISP_B2_10 for Mode: ALT9 0x2 USB_OTG2_OC_SELECT_INPUT USB_OTG2_OC_SELECT_INPUT DAISY Register 0x6B8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_06_ALT0 Selecting Pad: GPIO_AD_06 for Mode: ALT0 0 SELECT_GPIO_AD_30_ALT1 Selecting Pad: GPIO_AD_30 for Mode: ALT1 0x1 USB_OTG_OC_SELECT_INPUT USB_OTG_OC_SELECT_INPUT DAISY Register 0x6BC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_11_ALT0 Selecting Pad: GPIO_AD_11 for Mode: ALT0 0 SELECT_GPIO_AD_35_ALT1 Selecting Pad: GPIO_AD_35 for Mode: ALT1 0x1 USBPHY1_USB_ID_SELECT_INPUT USBPHY1_USB_ID_SELECT_INPUT DAISY Register 0x6C0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_09_ALT0 Selecting Pad: GPIO_AD_09 for Mode: ALT0 0 SELECT_GPIO_AD_33_ALT1 Selecting Pad: GPIO_AD_33 for Mode: ALT1 0x1 USBPHY2_USB_ID_SELECT_INPUT USBPHY2_USB_ID_SELECT_INPUT DAISY Register 0x6C4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_08_ALT0 Selecting Pad: GPIO_AD_08 for Mode: ALT0 0 SELECT_GPIO_AD_32_ALT1 Selecting Pad: GPIO_AD_32 for Mode: ALT1 0x1 USDHC1_IPP_CARD_DET_SELECT_INPUT USDHC1_IPP_CARD_DET_SELECT_INPUT DAISY Register 0x6C8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_32_ALT4 Selecting Pad: GPIO_AD_32 for Mode: ALT4 0 SELECT_GPIO_DISP_B1_08_ALT2 Selecting Pad: GPIO_DISP_B1_08 for Mode: ALT2 0x1 USDHC1_IPP_WP_ON_SELECT_INPUT USDHC1_IPP_WP_ON_SELECT_INPUT DAISY Register 0x6CC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_AD_33_ALT4 Selecting Pad: GPIO_AD_33 for Mode: ALT4 0 SELECT_GPIO_DISP_B1_09_ALT2 Selecting Pad: GPIO_DISP_B1_09 for Mode: ALT2 0x1 USDHC2_IPP_CARD_DET_SELECT_INPUT USDHC2_IPP_CARD_DET_SELECT_INPUT DAISY Register 0x6D0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_01_ALT1 Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT1 0 SELECT_GPIO_AD_26_ALT11 Selecting Pad: GPIO_AD_26 for Mode: ALT11 0x1 USDHC2_IPP_WP_ON_SELECT_INPUT USDHC2_IPP_WP_ON_SELECT_INPUT DAISY Register 0x6D4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_02_ALT1 Selecting Pad: GPIO_EMC_B2_02 for Mode: ALT1 0 SELECT_GPIO_AD_27_ALT11 Selecting Pad: GPIO_AD_27 for Mode: ALT11 0x1 XBAR1_IN_SELECT_INPUT_20 XBAR1_IN_SELECT_INPUT_20 DAISY Register 0x6D8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_00_ALT6 Selecting Pad: GPIO_EMC_B2_00 for Mode: ALT6 0 SELECT_GPIO_SD_B1_00_ALT2 Selecting Pad: GPIO_SD_B1_00 for Mode: ALT2 0x1 XBAR1_IN_SELECT_INPUT_21 XBAR1_IN_SELECT_INPUT_21 DAISY Register 0x6DC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_01_ALT6 Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT6 0 SELECT_GPIO_SD_B1_01_ALT2 Selecting Pad: GPIO_SD_B1_01 for Mode: ALT2 0x1 XBAR1_IN_SELECT_INPUT_22 XBAR1_IN_SELECT_INPUT_22 DAISY Register 0x6E0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_02_ALT6 Selecting Pad: GPIO_EMC_B2_02 for Mode: ALT6 0 SELECT_GPIO_SD_B1_02_ALT2 Selecting Pad: GPIO_SD_B1_02 for Mode: ALT2 0x1 XBAR1_IN_SELECT_INPUT_23 XBAR1_IN_SELECT_INPUT_23 DAISY Register 0x6E4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_03_ALT6 Selecting Pad: GPIO_EMC_B2_03 for Mode: ALT6 0 SELECT_GPIO_SD_B1_03_ALT2 Selecting Pad: GPIO_SD_B1_03 for Mode: ALT2 0x1 XBAR1_IN_SELECT_INPUT_24 XBAR1_IN_SELECT_INPUT_24 DAISY Register 0x6E8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_04_ALT6 Selecting Pad: GPIO_EMC_B2_04 for Mode: ALT6 0 SELECT_GPIO_SD_B1_04_ALT2 Selecting Pad: GPIO_SD_B1_04 for Mode: ALT2 0x1 XBAR1_IN_SELECT_INPUT_25 XBAR1_IN_SELECT_INPUT_25 DAISY Register 0x6EC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_05_ALT6 Selecting Pad: GPIO_EMC_B2_05 for Mode: ALT6 0 SELECT_GPIO_SD_B1_05_ALT2 Selecting Pad: GPIO_SD_B1_05 for Mode: ALT2 0x1 XBAR1_IN_SELECT_INPUT_26 XBAR1_IN_SELECT_INPUT_26 DAISY Register 0x6F0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_06_ALT6 Selecting Pad: GPIO_EMC_B2_06 for Mode: ALT6 0 SELECT_GPIO_DISP_B1_00_ALT4 Selecting Pad: GPIO_DISP_B1_00 for Mode: ALT4 0x1 XBAR1_IN_SELECT_INPUT_27 XBAR1_IN_SELECT_INPUT_27 DAISY Register 0x6F4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_07_ALT6 Selecting Pad: GPIO_EMC_B2_07 for Mode: ALT6 0 SELECT_GPIO_DISP_B1_01_ALT4 Selecting Pad: GPIO_DISP_B1_01 for Mode: ALT4 0x1 XBAR1_IN_SELECT_INPUT_28 XBAR1_IN_SELECT_INPUT_28 DAISY Register 0x6F8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_08_ALT6 Selecting Pad: GPIO_EMC_B2_08 for Mode: ALT6 0 SELECT_GPIO_DISP_B1_02_ALT4 Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT4 0x1 XBAR1_IN_SELECT_INPUT_29 XBAR1_IN_SELECT_INPUT_29 DAISY Register 0x6FC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_09_ALT6 Selecting Pad: GPIO_EMC_B2_09 for Mode: ALT6 0 SELECT_GPIO_DISP_B1_03_ALT4 Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT4 0x1 XBAR1_IN_SELECT_INPUT_30 XBAR1_IN_SELECT_INPUT_30 DAISY Register 0x700 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_10_ALT6 Selecting Pad: GPIO_EMC_B2_10 for Mode: ALT6 0 SELECT_GPIO_DISP_B1_04_ALT4 Selecting Pad: GPIO_DISP_B1_04 for Mode: ALT4 0x1 XBAR1_IN_SELECT_INPUT_31 XBAR1_IN_SELECT_INPUT_31 DAISY Register 0x704 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_11_ALT6 Selecting Pad: GPIO_EMC_B2_11 for Mode: ALT6 0 SELECT_GPIO_DISP_B1_05_ALT4 Selecting Pad: GPIO_DISP_B1_05 for Mode: ALT4 0x1 XBAR1_IN_SELECT_INPUT_32 XBAR1_IN_SELECT_INPUT_32 DAISY Register 0x708 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_12_ALT6 Selecting Pad: GPIO_EMC_B2_12 for Mode: ALT6 0 SELECT_GPIO_DISP_B1_06_ALT4 Selecting Pad: GPIO_DISP_B1_06 for Mode: ALT4 0x1 XBAR1_IN_SELECT_INPUT_33 XBAR1_IN_SELECT_INPUT_33 DAISY Register 0x70C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_13_ALT6 Selecting Pad: GPIO_EMC_B2_13 for Mode: ALT6 0 SELECT_GPIO_DISP_B1_07_ALT4 Selecting Pad: GPIO_DISP_B1_07 for Mode: ALT4 0x1 XBAR1_IN_SELECT_INPUT_34 XBAR1_IN_SELECT_INPUT_34 DAISY Register 0x710 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_14_ALT6 Selecting Pad: GPIO_EMC_B2_14 for Mode: ALT6 0 SELECT_GPIO_DISP_B1_08_ALT4 Selecting Pad: GPIO_DISP_B1_08 for Mode: ALT4 0x1 XBAR1_IN_SELECT_INPUT_35 XBAR1_IN_SELECT_INPUT_35 DAISY Register 0x714 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_EMC_B2_15_ALT6 Selecting Pad: GPIO_EMC_B2_15 for Mode: ALT6 0 SELECT_GPIO_DISP_B1_09_ALT4 Selecting Pad: GPIO_DISP_B1_09 for Mode: ALT4 0x1 GPT1 GPT GPT GPT 0x400EC000 0 0x28 registers GPT1 119 CR GPT Control Register 0 32 read-write 0 0xFFFFFFFF EN GPT Enable 0 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 ENMOD GPT Enable Mode 1 1 read-write RESUME_COUNT Restart counting from their frozen values after GPT is enabled (EN=1). 0 ZERO_COUNT Reset counting from 0 after GPT is enabled (EN=1). 0x1 DBGEN GPT Debug Mode Enable 2 1 read-write DEBUG_DIS Disable in Debug mode 0 DEBUG_EN Enable in Debug mode 0x1 WAITEN GPT Wait Mode Enable 3 1 read-write WAIT_DIS Disable in Wait mode 0 WAIT_EN Enable in Wait mode 0x1 DOZEEN GPT Doze Mode Enable 4 1 read-write DOZE_DIS Disable in Doze mode 0 DOZE_EN Enable in Doze mode 0x1 STOPEN GPT Stop Mode Enable 5 1 read-write STOP_DIS Disable in Stop mode 0 STOP_EN Enable in Stop mode 0x1 CLKSRC Clock Source Select 6 3 read-write NO_CLOCK No clock 0 CLOCK_001 Peripheral Clock (ipg_clk) 0x1 CLOCK_010 High Frequency Reference Clock (ipg_clk_highfreq) 0x2 CLOCK_011 External Clock 0x3 CLOCK_100 Low Frequency Reference Clock (ipg_clk_32k) 0x4 CLOCK_101 Oscillator as Reference Clock (ipg_clk_16M) 0x5 FRR Free-Run or Restart Mode 9 1 read-write RESTART Restart mode. After a compare event, the counter resets to 0x0000_0000 and resumes counting. 0 FREE_RUN Free-Run mode. After a compare event, the counter continues counting until 0xFFFF_FFFF and then rolls over to 0. 0x1 EN_24M Enable Oscillator Clock Input 10 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 SWR Software Reset 15 1 read-write NOT_SWRESET GPT is not in software reset state 0 SWRESET GPT is in software reset state 0x1 IM1 Input Capture Operating Mode for Channel 1 16 2 read-write DISABLED Capture disabled 0 RISING Capture on rising edge only 0x1 FALLING Capture on falling edge only 0x2 BOTH Capture on both edges 0x3 IM2 Input Capture Operating Mode for Channel 2 18 2 read-write DISABLED Capture disabled 0 RISING Capture on rising edge only 0x1 FALLING Capture on falling edge only 0x2 BOTH Capture on both edges 0x3 OM1 Output Compare Operating Mode for Channel 1 20 3 read-write DISABLED Output disabled. No response on pin. 0 TOGGLE Toggle output pin 0x1 CLEAR Clear output pin 0x2 SET Set output pin 0x3 PULSE Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register. #1xx OM2 Output Compare Operating Mode for Channel 2 23 3 read-write DISABLED Output disabled. No response on pin. 0 TOGGLE Toggle output pin 0x1 CLEAR Clear output pin 0x2 SET Set output pin 0x3 PULSE Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register. #1xx OM3 Output Compare Operating Mode for Channel 3 26 3 read-write DISABLED Output disabled. No response on pin. 0 TOGGLE Toggle output pin 0x1 CLEAR Clear output pin 0x2 SET Set output pin 0x3 PULSE Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register. #1xx FO1 Force Output Compare for Channel 1 29 1 read-write NO_FORCE No effect 0 FORCE Trigger the programmed response on the pin 0x1 FO2 Force Output Compare for Channel 2 30 1 read-write NO_FORCE No effect 0 FORCE Trigger the programmed response on the pin 0x1 FO3 Force Output Compare for Channel 3 31 1 read-write NO_FORCE No effect 0 FORCE Trigger the programmed response on the pin 0x1 PR GPT Prescaler Register 0x4 32 read-write 0 0xFFFFFFFF PRESCALER Prescaler divide value 0 12 read-write DIV_BY_1 Divide by 1 0 DIV_BY_2 Divide by 2 0x1 DIV_BY_4096 Divide by 4096 0xFFF PRESCALER24M Prescaler divide value for the oscillator clock 12 4 read-write DIV_BY_1 Divide by 1 0 DIV_BY_2 Divide by 2 0x1 DIV_BY_16 Divide by 16 0xF SR GPT Status Register 0x8 32 read-write 0 0xFFFFFFFF oneToClear OF1 Output Compare Flag for Channel 1 0 1 read-write oneToClear NO_EVENT Compare event has not occurred. 0 EVENT Compare event has occurred. 0x1 OF2 Output Compare Flag for Channel 2 1 1 read-write oneToClear NO_EVENT Compare event has not occurred. 0 EVENT Compare event has occurred. 0x1 OF3 Output Compare Flag for Channel 3 2 1 read-write oneToClear NO_EVENT Compare event has not occurred. 0 EVENT Compare event has occurred. 0x1 IF1 Input Capture Flag for Channel 1 3 1 read-write oneToClear NO_EVENT Capture event has not occurred. 0 EVENT Capture event has occurred. 0x1 IF2 Input Capture Flag for Channel 2 4 1 read-write oneToClear NO_EVENT Capture event has not occurred. 0 EVENT Capture event has occurred. 0x1 ROV Rollover Flag 5 1 read-write oneToClear NO_ROLLOVER Rollover has not occurred. 0 ROLLOVER Rollover has occurred. 0x1 IR GPT Interrupt Register 0xC 32 read-write 0 0xFFFFFFFF OF1IE Output Compare Flag for Channel 1 Interrupt Enable 0 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 OF2IE Output Compare Flag for Channel 2 Interrupt Enable 1 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 OF3IE Output Compare Flag for Channel 3 Interrupt Enable 2 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 IF1IE Input Capture Flag for Channel 1 Interrupt Enable 3 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 IF2IE Input Capture Flag for Channel 2 Interrupt Enable 4 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 ROVIE Rollover Interrupt Enable 5 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 3 0x4 1,2,3 OCR%s GPT Output Compare Register 0x10 32 read-write 0xFFFFFFFF 0xFFFFFFFF COMP Compare Value 0 32 read-write 2 0x4 1,2 ICR%s GPT Input Capture Register 0x1C 32 read-only 0 0xFFFFFFFF CAPT Capture Value 0 32 read-only CNT GPT Counter Register 0x24 32 read-only 0 0xFFFFFFFF COUNT Counter Value 0 32 read-only GPT2 GPT GPT 0x400F0000 0 0x28 registers GPT2 120 GPT3 GPT GPT 0x400F4000 0 0x28 registers GPT3 121 GPT4 GPT GPT 0x400F8000 0 0x28 registers GPT4 122 GPT5 GPT GPT 0x400FC000 0 0x28 registers GPT5 123 GPT6 GPT GPT 0x40100000 0 0x28 registers GPT6 124 LPI2C1 LPI2C LPI2C LPI2C 0x40104000 0 0x174 registers LPI2C1 32 VERID Version ID 0 32 read-only 0x1010003 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only MASTER_ONLY Master only, with standard feature set 0x2 MASTER_AND_SLAVE Master and slave, with standard feature set 0x3 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter 0x4 32 read-only 0x202 0xFFFFFFFF MTXFIFO Master Transmit FIFO Size 0 4 read-only MRXFIFO Master Receive FIFO Size 8 4 read-only MCR Master Control 0x10 32 read-write 0 0xFFFFFFFF MEN Master Enable 0 1 read-write DISABLED Master logic is disabled 0 ENABLED Master logic is enabled 0x1 RST Software Reset 1 1 read-write NOT_RESET Master logic is not reset 0 RESET Master logic is reset 0x1 DOZEN Doze mode enable 2 1 read-write ENABLED Master is enabled in Doze mode 0 DISABLED Master is disabled in Doze mode 0x1 DBGEN Debug Enable 3 1 read-write DISABLED Master is disabled in debug mode 0 ENABLED Master is enabled in debug mode 0x1 RTF Reset Transmit FIFO 8 1 read-write NO_EFFECT No effect 0 RESET Transmit FIFO is reset 0x1 RRF Reset Receive FIFO 9 1 read-write NO_EFFECT No effect 0 RESET Receive FIFO is reset 0x1 MSR Master Status 0x14 32 read-write 0x1 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only DISABLED Transmit data is not requested 0 ENABLED Transmit data is requested 0x1 RDF Receive Data Flag 1 1 read-only DISABLED Receive Data is not ready 0 ENABLED Receive data is ready 0x1 EPF End Packet Flag 8 1 read-write oneToClear NO_FLAG Master has not generated a STOP or Repeated START condition 0 FLAG Master has generated a STOP or Repeated START condition 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear NO_FLAG Master has not generated a STOP condition 0 FLAG Master has generated a STOP condition 0x1 NDF NACK Detect Flag 10 1 read-write oneToClear NO_FLAG Unexpected NACK was not detected 0 FLAG Unexpected NACK was detected 0x1 ALF Arbitration Lost Flag 11 1 read-write oneToClear NO_FLAG Master has not lost arbitration 0 FLAG Master has lost arbitration 0x1 FEF FIFO Error Flag 12 1 read-write oneToClear NO_FLAG No error 0 FLAG Master sending or receiving data without a START condition 0x1 PLTF Pin Low Timeout Flag 13 1 read-write oneToClear NO_FLAG Pin low timeout has not occurred or is disabled 0 FLAG Pin low timeout has occurred 0x1 DMF Data Match Flag 14 1 read-write oneToClear NO_FLAG Have not received matching data 0 FLAG Have received matching data 0x1 MBF Master Busy Flag 24 1 read-only IDLE I2C Master is idle 0 BUSY I2C Master is busy 0x1 BBF Bus Busy Flag 25 1 read-only IDLE I2C Bus is idle 0 BUSY I2C Bus is busy 0x1 MIER Master Interrupt Enable 0x18 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 EPIE End Packet Interrupt Enable 8 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 NDIE NACK Detect Interrupt Enable 10 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 ALIE Arbitration Lost Interrupt Enable 11 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 FEIE FIFO Error Interrupt Enable 12 1 read-write ENABLED Enabled 0 DISABLED Disabled 0x1 PLTIE Pin Low Timeout Interrupt Enable 13 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 DMIE Data Match Interrupt Enable 14 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 MDER Master DMA Enable 0x1C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write DISABLED DMA request is disabled 0 ENABLED DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write DISABLED DMA request is disabled 0 ENABLED DMA request is enabled 0x1 MCFGR0 Master Configuration 0 0x20 32 read-write 0 0xFFFFFFFF HREN Host Request Enable 0 1 read-write DISABLED Host request input is disabled 0 ENABLED Host request input is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write ACTIVE_LOW Active low 0 ACTIVE_HIGH Active high 0x1 HRSEL Host Request Select 2 1 read-write DISABLED Host request input is pin HREQ 0 ENABLED Host request input is input trigger 0x1 CIRFIFO Circular FIFO Enable 8 1 read-write DISABLED Circular FIFO is disabled 0 ENABLED Circular FIFO is enabled 0x1 RDMO Receive Data Match Only 9 1 read-write DISABLED Received data is stored in the receive FIFO 0 ENABLED Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set 0x1 MCFGR1 Master Configuration 1 0x24 32 read-write 0 0xFFFFFFFF PRESCALE Prescaler 0 3 read-write DIVIDE_BY_1 Divide by 1 0 DIVIDE_BY_2 Divide by 2 0x1 DIVIDE_BY_4 Divide by 4 0x2 DIVIDE_BY_8 Divide by 8 0x3 DIVIDE_BY_16 Divide by 16 0x4 DIVIDE_BY_32 Divide by 32 0x5 DIVIDE_BY_64 Divide by 64 0x6 DIVIDE_BY_128 Divide by 128 0x7 AUTOSTOP Automatic STOP Generation 8 1 read-write DISABLED No effect 0 ENABLED STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy 0x1 IGNACK IGNACK 9 1 read-write DISABLED LPI2C Master receives ACK and NACK normally 0 ENABLED LPI2C Master treats a received NACK as if it (NACK) was an ACK 0x1 TIMECFG Timeout Configuration 10 1 read-write IF_SCL_LOW MSR[PLTF] sets if SCL is low for longer than the configured timeout 0 IF_SCL_OR_SDA_LOW MSR[PLTF] sets if either SCL or SDA is low for longer than the configured timeout 0x1 MATCFG Match Configuration 16 3 read-write DISABLED Match is disabled 0 FIRST_DATA_WORD_EQUALS_MATCH0_OR_MATCH1 Match is enabled (1st data word equals MDMR[MATCH0] OR MDMR[MATCH1]) 0x2 ANY_DATA_WORD_EQUALS_MATCH0_OR_MATCH1 Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1]) 0x3 FIRST_DATA_WORD_MATCH0_AND_SECOND_DATA_WORD_MATCH1 Match is enabled (1st data word equals MDMR[MATCH0] AND 2nd data word equals MDMR[MATCH1) 0x4 ANY_DATA_WORD_MATCH0_NEXT_DATA_WORD_MATCH1 Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1) 0x5 FIRST_DATA_WORD_AND_MATCH1_EQUALS_MATCH0_AND_MATCH1 Match is enabled (1st data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) 0x6 ANY_DATA_WORD_AND_MATCH1_EQUALS_MATCH0_AND_MATCH1 Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) 0x7 PINCFG Pin Configuration 24 3 read-write OPEN_DRAIN_2_PIN 2-pin open drain mode 0 OUTPUT_2_PIN_ONLY 2-pin output only mode (ultra-fast mode) 0x1 PUSH_PULL_2_PIN 2-pin push-pull mode 0x2 PUSH_PULL_4_PIN 4-pin push-pull mode 0x3 OPEN_DRAIN_2_PIN_W_LPI2C_SLAVE 2-pin open drain mode with separate LPI2C slave 0x4 OUTPUT_2_PIN_ONLY_W_LPI2C_SLAVE 2-pin output only mode (ultra-fast mode) with separate LPI2C slave 0x5 PUSH_PULL_2_PIN_W_LPI2C_SLAVE 2-pin push-pull mode with separate LPI2C slave 0x6 PUSH_PULL_4_PIN_W_LPI2C_SLAVE 4-pin push-pull mode (inverted outputs) 0x7 MCFGR2 Master Configuration 2 0x28 32 read-write 0 0xFFFFFFFF BUSIDLE Bus Idle Timeout 0 12 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write MCFGR3 Master Configuration 3 0x2C 32 read-write 0 0xFFFFFFFF PINLOW Pin Low Timeout 8 12 read-write MDMR Master Data Match 0x40 32 read-write 0 0xFFFFFFFF MATCH0 Match 0 Value 0 8 read-write MATCH1 Match 1 Value 16 8 read-write MCCR0 Master Clock Configuration 0 0x48 32 read-write 0 0xFFFFFFFF CLKLO Clock Low Period 0 6 read-write CLKHI Clock High Period 8 6 read-write SETHOLD Setup Hold Delay 16 6 read-write DATAVD Data Valid Delay 24 6 read-write MCCR1 Master Clock Configuration 1 0x50 32 read-write 0 0xFFFFFFFF CLKLO Clock Low Period 0 6 read-write CLKHI Clock High Period 8 6 read-write SETHOLD Setup Hold Delay 16 6 read-write DATAVD Data Valid Delay 24 6 read-write MFCR Master FIFO Control 0x58 32 read-write 0 0xFFFFFFFF TXWATER Transmit FIFO Watermark 0 2 read-write RXWATER Receive FIFO Watermark 16 2 read-write MFSR Master FIFO Status 0x5C 32 read-only 0 0xFFFFFFFF TXCOUNT Transmit FIFO Count 0 3 read-only RXCOUNT Receive FIFO Count 16 3 read-only MTDR Master Transmit Data 0x60 32 write-only 0 0xFFFFFFFF DATA Transmit Data 0 8 write-only CMD Command Data 8 3 write-only TRANSMIT_DATA_7_THROUGH_0 Transmit DATA[7:0] 0 RECEIVE_DATA_7_THROUGH_0_PLUS_ONE Receive (DATA[7:0] + 1) bytes 0x1 GENERATE_STOP_CONDITION Generate STOP condition 0x2 RECEIVE_AND_DISCARD_DATA_7_THROUGH_0_PLUS_ONE Receive and discard (DATA[7:0] + 1) bytes 0x3 GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0 Generate (repeated) START and transmit address in DATA[7:0] 0x4 GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0_EXPECT_NACK Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. 0x5 GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0_USING_HIGH_SPEED_MODE Generate (repeated) START and transmit address in DATA[7:0] using high speed mode 0x6 GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0_USING_HIGH_SPEED_MODE_EXPECT_NACK Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. 0x7 MRDR Master Receive Data 0x70 32 read-only 0x4000 0xFFFFFFFF DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only NOT_EMPTY Receive FIFO is not empty 0 EMPTY Receive FIFO is empty 0x1 SCR Slave Control 0x110 32 read-write 0 0xFFFFFFFF SEN Slave Enable 0 1 read-write DISABLED I2C Slave mode is disabled 0 ENABLED I2C Slave mode is enabled 0x1 RST Software Reset 1 1 read-write NOT_RESET Slave mode logic is not reset 0 RESET Slave mode logic is reset 0x1 FILTEN Filter Enable 4 1 read-write DISABLE Disable digital filter and output delay counter for slave mode 0 ENABLE Enable digital filter and output delay counter for slave mode 0x1 FILTDZ Filter Doze Enable 5 1 read-write FILTER_ENABLED Filter remains enabled in Doze mode 0 FILTER_DISABLED Filter is disabled in Doze mode 0x1 RTF Reset Transmit FIFO 8 1 read-write NO_EFFECT No effect 0 NOW_EMPTY Transmit Data Register is now empty 0x1 RRF Reset Receive FIFO 9 1 read-write NO_EFFECT No effect 0 NOW_EMPTY Receive Data Register is now empty 0x1 SSR Slave Status 0x114 32 read-write 0 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only NO_FLAG Transmit data not requested 0 FLAG Transmit data is requested 0x1 RDF Receive Data Flag 1 1 read-only NOT_READY Receive data is not ready 0 READY Receive data is ready 0x1 AVF Address Valid Flag 2 1 read-only NOT_VALID Address Status Register is not valid 0 VALID Address Status Register is valid 0x1 TAF Transmit ACK Flag 3 1 read-only NOT_REQUIRED Transmit ACK/NACK is not required 0 REQUIRED Transmit ACK/NACK is required 0x1 RSF Repeated Start Flag 8 1 read-write oneToClear NO_FLAG Slave has not detected a Repeated START condition 0 FLAG Slave has detected a Repeated START condition 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear NO_FLAG Slave has not detected a STOP condition 0 FLAG Slave has detected a STOP condition 0x1 BEF Bit Error Flag 10 1 read-write oneToClear NO_FLAG Slave has not detected a bit error 0 FLAG Slave has detected a bit error 0x1 FEF FIFO Error Flag 11 1 read-write oneToClear NO_FLAG FIFO underflow or overflow was not detected 0 FLAG FIFO underflow or overflow was detected 0x1 AM0F Address Match 0 Flag 12 1 read-only NO_FLAG Have not received an ADDR0 matching address 0 FLAG Have received an ADDR0 matching address 0x1 AM1F Address Match 1 Flag 13 1 read-only NO_FLAG Have not received an ADDR1 or ADDR0/ADDR1 range matching address 0 FLAG Have received an ADDR1 or ADDR0/ADDR1 range matching address 0x1 GCF General Call Flag 14 1 read-only NO_FLAG Slave has not detected the General Call Address or the General Call Address is disabled 0 FLAG Slave has detected the General Call Address 0x1 SARF SMBus Alert Response Flag 15 1 read-only NO_FLAG SMBus Alert Response is disabled or not detected 0 FLAG SMBus Alert Response is enabled and detected 0x1 SBF Slave Busy Flag 24 1 read-only IDLE I2C Slave is idle 0 BUSY I2C Slave is busy 0x1 BBF Bus Busy Flag 25 1 read-only IDLE I2C Bus is idle 0 BUSY I2C Bus is busy 0x1 SIER Slave Interrupt Enable 0x118 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 AVIE Address Valid Interrupt Enable 2 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 TAIE Transmit ACK Interrupt Enable 3 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 RSIE Repeated Start Interrupt Enable 8 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 BEIE Bit Error Interrupt Enable 10 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 FEIE FIFO Error Interrupt Enable 11 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 AM0IE Address Match 0 Interrupt Enable 12 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 AM1IE Address Match 1 Interrupt Enable 13 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 GCIE General Call Interrupt Enable 14 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 SARIE SMBus Alert Response Interrupt Enable 15 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 SDER Slave DMA Enable 0x11C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write DISABLED DMA request is disabled 0 ENABLED DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write DISABLED DMA request is disabled 0 ENABLED DMA request is enabled 0x1 AVDE Address Valid DMA Enable 2 1 read-write DISABLED DMA request is disabled 0 ENABLED DMA request is enabled 0x1 SCFGR1 Slave Configuration 1 0x124 32 read-write 0 0xFFFFFFFF ADRSTALL Address SCL Stall 0 1 read-write DISABLED Clock stretching is disabled 0 ENABLED Clock stretching is enabled 0x1 RXSTALL RX SCL Stall 1 1 read-write DISABLED Clock stretching is disabled 0 ENABLED Clock stretching is enabled 0x1 TXDSTALL TX Data SCL Stall 2 1 read-write DISABLED Clock stretching is disabled 0 ENABLED Clock stretching is enabled 0x1 ACKSTALL ACK SCL Stall 3 1 read-write DISABLED Clock stretching is disabled 0 ENABLED Clock stretching is enabled 0x1 GCEN General Call Enable 8 1 read-write DISABLED General Call address is disabled 0 ENABLED General Call address is enabled 0x1 SAEN SMBus Alert Enable 9 1 read-write DISABLE Disables match on SMBus Alert 0 ENABLE Enables match on SMBus Alert 0x1 TXCFG Transmit Flag Configuration 10 1 read-write ASSERTS_DURING_SLAVE_TRANSMIT_TRANSFER_WHEN_TX_DATA_EMPTY Transmit Data Flag only asserts during a slave-transmit transfer when the Transmit Data register is empty 0 ASSERTS_WHEN_TX_DATA_EMPTY Transmit Data Flag asserts whenever the Transmit Data register is empty 0x1 RXCFG Receive Data Configuration 11 1 read-write RETURNS_RECEIVED_DATA_AND_CLEARS_RX_DATA_FLAG Reading the Receive Data register returns received data and clears the Receive Data flag (MSR[RDF]). 0 WHEN_ADDRESS_VALID_FLAG_SET_RETURNS_ADDRESS_STATUS_AND_CLEARS_ADDRESS_VALID_FLAG Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, returns the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, returns received data and clears the Receive Data flag (MSR[RDF]). 0x1 IGNACK Ignore NACK 12 1 read-write ENDS_TRANSFER_ON_NACK Slave ends transfer when NACK is detected 0 DOES_NOT_END_TRANSFER_ON_NACK Slave does not end transfer when NACK detected 0x1 HSMEN High Speed Mode Enable 13 1 read-write DISABLED Disables detection of HS-mode master code 0 ENABLED Enables detection of HS-mode master code 0x1 ADDRCFG Address Configuration 16 3 read-write ADDRESS_MATCH0_7_BIT Address match 0 (7-bit) 0 ADDRESS_MATCH0_10_BIT Address match 0 (10-bit) 0x1 ADDRESS_MATCH0_7_BIT_OR_ADDRESS_MATCH1_7_BIT Address match 0 (7-bit) or Address match 1 (7-bit) 0x2 ADDRESS_MATCH0_10_BIT_OR_ADDRESS_MATCH1_10_BIT Address match 0 (10-bit) or Address match 1 (10-bit) 0x3 ADDRESS_MATCH0_7_BIT_OR_ADDRESS_MATCH1_10_BIT Address match 0 (7-bit) or Address match 1 (10-bit) 0x4 ADDRESS_MATCH0_10_BIT_OR_ADDRESS_MATCH1_7_BIT Address match 0 (10-bit) or Address match 1 (7-bit) 0x5 FROM_ADDRESS_MATCH0_7_BIT_TO_ADDRESS_MATCH1_7_BIT From Address match 0 (7-bit) to Address match 1 (7-bit) 0x6 FROM_ADDRESS_MATCH0_10_BIT_TO_ADDRESS_MATCH1_10_BIT From Address match 0 (10-bit) to Address match 1 (10-bit) 0x7 SCFGR2 Slave Configuration 2 0x128 32 read-write 0 0xFFFFFFFF CLKHOLD Clock Hold Time 0 4 read-write DATAVD Data Valid Delay 8 6 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write SAMR Slave Address Match 0x140 32 read-write 0 0xFFFFFFFF ADDR0 Address 0 Value 1 10 read-write ADDR1 Address 1 Value 17 10 read-write SASR Slave Address Status 0x150 32 read-only 0x4000 0xFFFFFFFF RADDR Received Address 0 11 read-only ANV Address Not Valid 14 1 read-only VALID Received Address (RADDR) is valid 0 NOT_VALID Received Address (RADDR) is not valid 0x1 STAR Slave Transmit ACK 0x154 32 read-write 0 0xFFFFFFFF TXNACK Transmit NACK 0 1 read-write TRANSMIT_ACK Write a Transmit ACK for each received word 0 TRANSMIT_NACK Write a Transmit NACK for each received word 0x1 STDR Slave Transmit Data 0x160 32 write-only 0 0xFFFFFFFF DATA Transmit Data 0 8 write-only SRDR Slave Receive Data 0x170 32 read-only 0x4000 0xFFFFFFFF DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only NOT_EMPTY The Receive Data Register is not empty 0 EMPTY The Receive Data Register is empty 0x1 SOF Start Of Frame 15 1 read-only NOT_FIRST_DATA_WORD Indicates this is not the first data word since a (repeated) START or STOP condition 0 FIRST_DATA_WORD Indicates this is the first data word since a (repeated) START or STOP condition 0x1 LPI2C2 LPI2C LPI2C 0x40108000 0 0x174 registers LPI2C2 33 LPI2C3 LPI2C LPI2C 0x4010C000 0 0x174 registers LPI2C3 34 LPI2C4 LPI2C LPI2C 0x40110000 0 0x174 registers LPI2C4 35 LPI2C5 LPI2C LPI2C 0x40C34000 0 0x174 registers LPI2C5 36 LPI2C6 LPI2C LPI2C 0x40C38000 0 0x174 registers LPI2C6 37 LPSPI1 LPSPI LPSPI LPSPI 0x40114000 0 0x78 registers LPSPI1 38 VERID Version ID 0 32 read-only 0x1020004 0xFFFFFFFF FEATURE Module Identification Number 0 16 read-only STANDARD Standard feature set supporting a 32-bit shift register. 0x4 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter 0x4 32 read-only 0x40404 0xFFFFFFFF TXFIFO Transmit FIFO Size 0 8 read-only RXFIFO Receive FIFO Size 8 8 read-only PCSNUM PCS Number 16 8 read-only CR Control 0x10 32 read-write 0 0xFFFFFFFF MEN Module Enable 0 1 read-write DISABLED Module is disabled 0 ENABLED Module is enabled 0x1 RST Software Reset 1 1 read-write NOT_RESET Module is not reset 0 RESET Module is reset 0x1 DOZEN Doze Mode Enable 2 1 read-write ENABLED LPSPI module is enabled in Doze mode 0 DISABLED LPSPI module is disabled in Doze mode 0x1 DBGEN Debug Enable 3 1 read-write DISABLED LPSPI module is disabled in debug mode 0 ENABLED LPSPI module is enabled in debug mode 0x1 RTF Reset Transmit FIFO 8 1 write-only NO_EFFECT No effect 0 TXFIFO_RST Reset the Transmit FIFO. The register bit always reads zero. 0x1 RRF Reset Receive FIFO 9 1 write-only NO_EFFECT No effect 0 RXFIFO_RST Reset the Receive FIFO. The register bit always reads zero. 0x1 SR Status 0x14 32 read-write 0x1 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only TXDATA_NOT_REQST Transmit data not requested 0 TXDATA_REQST Transmit data is requested 0x1 RDF Receive Data Flag 1 1 read-only NOTREADY Receive Data is not ready 0 READY Receive data is ready 0x1 WCF Word Complete Flag 8 1 read-write oneToClear NOT_COMPLETED Transfer of a received word has not yet completed 0 COMPLETED Transfer of a received word has completed 0x1 FCF Frame Complete Flag 9 1 read-write oneToClear NOT_COMPLETED Frame transfer has not completed 0 COMPLETED Frame transfer has completed 0x1 TCF Transfer Complete Flag 10 1 read-write oneToClear NOT_COMPLETED All transfers have not completed 0 COMPLETED All transfers have completed 0x1 TEF Transmit Error Flag 11 1 read-write oneToClear NO_UNDERRUN Transmit FIFO underrun has not occurred 0 UNDERRUN Transmit FIFO underrun has occurred 0x1 REF Receive Error Flag 12 1 read-write oneToClear NOT_OVERFLOWED Receive FIFO has not overflowed 0 OVERFLOWED Receive FIFO has overflowed 0x1 DMF Data Match Flag 13 1 read-write oneToClear NO_MATCH Have not received matching data 0 MATCH Have received matching data 0x1 MBF Module Busy Flag 24 1 read-only IDLE LPSPI is idle 0 BUSY LPSPI is busy 0x1 IER Interrupt Enable 0x18 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 WCIE Word Complete Interrupt Enable 8 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 FCIE Frame Complete Interrupt Enable 9 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 TCIE Transfer Complete Interrupt Enable 10 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 TEIE Transmit Error Interrupt Enable 11 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 REIE Receive Error Interrupt Enable 12 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 DMIE Data Match Interrupt Enable 13 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 DER DMA Enable 0x1C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write DISABLED DMA request is disabled 0 ENABLED DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write DISABLED DMA request is disabled 0 ENABLED DMA request is enabled 0x1 CFGR0 Configuration 0 0x20 32 read-write 0 0xFFFFFFFF CIRFIFO Circular FIFO Enable 8 1 read-write DISABLED Circular FIFO is disabled 0 ENABLED Circular FIFO is enabled 0x1 RDMO Receive Data Match Only 9 1 read-write STORED Received data is stored in the receive FIFO as in normal operations 0 DISCARDED Received data is discarded unless the SR[DMF] = 1 0x1 CFGR1 Configuration 1 0x24 32 read-write 0 0xFFFFFFFF MASTER Master Mode 0 1 read-write SLAVE_MODE Slave mode 0 MASTER_MODE Master mode 0x1 SAMPLE Sample Point 1 1 read-write ON_SCK_EDGE Input data is sampled on SCK edge 0 ON_DELAYED_SCK_EDGE Input data is sampled on delayed SCK edge 0x1 AUTOPCS Automatic PCS 2 1 read-write DISABLED Automatic PCS generation is disabled 0 ENABLED Automatic PCS generation is enabled 0x1 NOSTALL No Stall 3 1 read-write DISABLED Transfers stall when the transmit FIFO is empty 0 ENABLED Transfers do not stall, allowing transmit FIFO underruns to occur 0x1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write MATCFG Match Configuration 16 3 read-write DISABLED Match is disabled 0 ENABLED_FIRSTDATAMATCH Match is enabled is 1st data word is MATCH0 or MATCH1 0x2 ENABLED_ANYDATAMATCH Match is enabled on any data word equal MATCH0 or MATCH1 0x3 ENABLED_DATAMATCH_100 Match is enabled on data match sequence 0x4 ENABLED_DATAMATCH_101 Match is enabled on data match sequence 0x5 ENABLED_DATAMATCH_110 Match is enabled 0x6 ENABLED_DATAMATCH_111 Match is enabled 0x7 PINCFG Pin Configuration 24 2 read-write SIN_IN_SOUT_OUT SIN is used for input data and SOUT is used for output data 0 SIN_BOTH_IN_OUT SIN is used for both input and output data, only half-duplex serial transfers are supported 0x1 SOUT_BOTH_IN_OUT SOUT is used for both input and output data, only half-duplex serial transfers are supported 0x2 SOUT_IN_SIN_OUT SOUT is used for input data and SIN is used for output data 0x3 OUTCFG Output Configuration 26 1 read-write RETAIN_LASTVALUE Output data retains last value when chip select is negated 0 TRISTATED Output data is tristated when chip select is negated 0x1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write CHIP_SELECT PCS[3:2] are configured for chip select function 0 HALFDUPLEX4BIT PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) 0x1 DMR0 Data Match 0 0x30 32 read-write 0 0xFFFFFFFF MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match 1 0x34 32 read-write 0 0xFFFFFFFF MATCH1 Match 1 Value 0 32 read-write CCR Clock Configuration 0x40 32 read-write 0 0xFFFFFFFF SCKDIV SCK Divider 0 8 read-write DBT Delay Between Transfers 8 8 read-write PCSSCK PCS-to-SCK Delay 16 8 read-write SCKPCS SCK-to-PCS Delay 24 8 read-write FCR FIFO Control 0x58 32 read-write 0 0xFFFFFFFF TXWATER Transmit FIFO Watermark 0 4 read-write RXWATER Receive FIFO Watermark 16 4 read-write FSR FIFO Status 0x5C 32 read-only 0 0xFFFFFFFF TXCOUNT Transmit FIFO Count 0 5 read-only RXCOUNT Receive FIFO Count 16 5 read-only TCR Transmit Command 0x60 32 read-write 0x1F 0xFFFFFFFF FRAMESZ Frame Size 0 12 read-write WIDTH Transfer Width 16 2 read-write ONEBIT 1 bit transfer 0 TWOBIT 2 bit transfer 0x1 FOURBIT 4 bit transfer 0x2 TXMSK Transmit Data Mask 18 1 read-write NORMAL Normal transfer 0 MASK Mask transmit data 0x1 RXMSK Receive Data Mask 19 1 read-write NORMAL Normal transfer 0 MASK Receive data is masked 0x1 CONTC Continuing Command 20 1 read-write START Command word for start of new transfer 0 CONTINUE Command word for continuing transfer 0x1 CONT Continuous Transfer 21 1 read-write DISABLED Continuous transfer is disabled 0 ENABLED Continuous transfer is enabled 0x1 BYSW Byte Swap 22 1 read-write DISABLED Byte swap is disabled 0 ENABLED Byte swap is enabled 0x1 LSBF LSB First 23 1 read-write MSB_FIRST Data is transferred MSB first 0 LSB_FIRST Data is transferred LSB first 0x1 PCS Peripheral Chip Select 24 2 read-write TX_PCS0 Transfer using PCS[0] 0 TX_PCS1 Transfer using PCS[1] 0x1 TX_PCS2 Transfer using PCS[2] 0x2 TX_PCS3 Transfer using PCS[3] 0x3 PRESCALE Prescaler Value 27 3 read-write DIVIDEBY1 Divide by 1 0 DIVIDEBY2 Divide by 2 0x1 DIVIDEBY4 Divide by 4 0x2 DIVIDEBY8 Divide by 8 0x3 DIVIDEBY16 Divide by 16 0x4 DIVIDEBY32 Divide by 32 0x5 DIVIDEBY64 Divide by 64 0x6 DIVIDEBY128 Divide by 128 0x7 CPHA Clock Phase 30 1 read-write CAPTURED Captured 0 CHANGED Changed 0x1 CPOL Clock Polarity 31 1 read-write INACTIVE_LOW The inactive state value of SCK is low 0 INACTIVE_HIGH The inactive state value of SCK is high 0x1 TDR Transmit Data 0x64 32 write-only 0 0xFFFFFFFF DATA Transmit Data 0 32 write-only RSR Receive Status 0x70 32 read-only 0x2 0xFFFFFFFF SOF Start Of Frame 0 1 read-only NEXT_DATAWORD Subsequent data word received after PCS assertion 0 FIRST_DATAWORD First data word received after PCS assertion 0x1 RXEMPTY RX FIFO Empty 1 1 read-only NOT_EMPTY RX FIFO is not empty 0 EMPTY RX FIFO is empty 0x1 RDR Receive Data 0x74 32 read-only 0 0xFFFFFFFF DATA Receive Data 0 32 read-only LPSPI2 LPSPI LPSPI 0x40118000 0 0x78 registers LPSPI2 39 LPSPI3 LPSPI LPSPI 0x4011C000 0 0x78 registers LPSPI3 40 LPSPI4 LPSPI LPSPI 0x40120000 0 0x78 registers LPSPI4 41 LPSPI5 LPSPI LPSPI 0x40C2C000 0 0x78 registers LPSPI5 42 LPSPI6 LPSPI LPSPI 0x40C30000 0 0x78 registers LPSPI6 43 CCM_OBS CCM_OBS CCM_OBS 0x40150000 0 0x2CC registers 6 0x80 OBSERVE[%s] Clock root section. 0 OBSERVE_CONTROL Observe control 0 32 read-write 0 0xFFFFFFFF SELECT Observe signal selector 0 9 read-write modify RAW Observe raw signal 12 1 read-write modify RAW_0 Select divided signal. 0 RAW_1 Select raw signal. 0x1 INV Invert 13 1 read-write INV_0 Clock phase remain same. 0 INV_1 Invert clock phase before measurement or send to IO. 0x1 RESET Reset observe divider 15 1 read-write RESET_0 No reset 0 RESET_1 Reset observe divider 0x1 DIVIDE Divider for observe signal 16 8 read-write OFF Turn off 24 1 read-write OFF_0 observe slice is on 0 OFF_1 observe slice is off 0x1 OBSERVE_CONTROL_SET Observe control 0x4 32 read-write 0 0xFFFFFFFF oneToSet SELECT Observe signal selector 0 9 read-write oneToSet RAW Observe raw signal 12 1 read-write oneToSet INV Invert 13 1 read-write oneToSet RESET Reset observe divider 15 1 read-write oneToSet DIVIDE Divider for observe signal 16 8 read-write oneToSet OFF Turn off 24 1 read-write oneToSet OBSERVE_CONTROL_CLR Observe control 0x8 32 read-write 0 0xFFFFFFFF oneToClear SELECT Observe signal selector 0 9 read-write oneToClear RAW Observe raw signal 12 1 read-write oneToClear INV Invert 13 1 read-write oneToClear RESET Reset observe divider 15 1 read-write oneToClear DIVIDE Divider for observe signal 16 8 read-write oneToClear OFF Turn off 24 1 read-write oneToClear OBSERVE_CONTROL_TOG Observe control 0xC 32 read-write 0 0xFFFFFFFF oneToToggle SELECT Observe signal selector 0 9 read-write oneToToggle RAW Observe raw signal 12 1 read-write oneToToggle INV Invert 13 1 read-write oneToToggle RESET Reset observe divider 15 1 read-write oneToToggle DIVIDE Divider for observe signal 16 8 read-write oneToToggle OFF Turn off 24 1 read-write oneToToggle OBSERVE_STATUS0 Observe status 0x20 32 read-only 0 0xFFFFFFFF SELECT Select value 0 9 read-only RAW Observe raw signal 12 1 read-only RAW_0 Divided signal is selected 0 RAW_1 Raw signal is selected 0x1 INV Polarity of the observe target 13 1 read-only INV_0 Polarity is not inverted 0 INV_1 Polarity of the observe target is inverted 0x1 RESET Reset state 15 1 read-only RESET_0 Observe divider is not in reset state 0 RESET_1 Observe divider is in reset state 0x1 DIVIDE Divide value status. The clock will be divided by DIVIDE + 1. 16 8 read-only OFF Turn off slice 24 1 read-only OFF_0 observe slice is on 0 OFF_1 observe slice is off 0x1 OBSERVE_AUTHEN Observe access control 0x30 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode. 0 TZ_USER_1 Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST White list 8 4 read-write WHITE_LIST_0 No domain can change. 0 WHITE_LIST_1 Domain 0 can change. 0x1 WHITE_LIST_2 Domain 1 can change. 0x2 WHITE_LIST_3 Domain 0 and domain 1 can change. 0x3 WHITE_LIST_4 Domain 2 can change. 0x4 WHITE_LIST_15 All domain can change. 0xF LOCK_LIST Lock white list 12 1 read-write LOCK_LIST_0 White list is not locked. 0 LOCK_LIST_1 White list is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in domain mode. 0 DOMAIN_MODE_1 Clock works in domain mode. 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 OBSERVE_AUTHEN_SET Observe access control 0x34 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST White list 8 4 read-write oneToSet LOCK_LIST Lock white list 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet OBSERVE_AUTHEN_CLR Observe access control 0x38 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST White list 8 4 read-write oneToClear LOCK_LIST Lock white list 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear OBSERVE_AUTHEN_TOG Observe access control 0x3C 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST White list 8 4 read-write oneToToggle LOCK_LIST Lock white list 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle OBSERVE_FREQUENCY_CURRENT Current frequency detected 0x40 32 read-only 0 0xFFFFFFFF FREQUENCY Frequency 0 32 read-only OBSERVE_FREQUENCY_MIN Minimum frequency detected 0x44 32 read-only 0xFFFFFFC0 0xFFFFFFFF FREQUENCY Frequency 0 32 read-only OBSERVE_FREQUENCY_MAX Maximum frequency detected 0x48 32 read-only 0 0xFFFFFFFF FREQUENCY Frequency 0 32 read-only EMVSIM1 EMVSIM EMVSIM EMVSIM 0x40154000 0 0x4C registers EMVSIM1 204 VER_ID Version ID Register 0 32 read-only 0 0xFFFFFFFF VER Version ID of the module 0 32 read-only PARAM Parameter Register 0x4 32 read-only 0x1010 0xFFFFFFFF RX_FIFO_DEPTH Receive FIFO Depth 0 8 read-only TX_FIFO_DEPTH Transmit FIFO Depth 8 8 read-only CLKCFG Clock Configuration Register 0x8 32 read-write 0 0xFFFFFFFF CLK_PRSC Clock Prescaler Value 0 8 read-write GPCNT1_CLK_SEL General Purpose Counter 1 Clock Select 8 2 read-write disabled Disabled / Reset 0 cardclk Card Clock 0x1 rxclk Receive Clock 0x2 txclk ETU Clock (transmit clock) 0x3 GPCNT0_CLK_SEL General Purpose Counter 0 Clock Select 10 2 read-write disabled Disabled / Reset 0 cardclk Card Clock 0x1 rxclk Receive Clock 0x2 txclk ETU Clock (transmit clock) 0x3 DIVISOR Baud Rate Divisor Register 0xC 32 read-write 0x174 0xFFFFFFFF DIVISOR_VALUE Divisor (F/D) Value 0 9 read-write invalid Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0 invalid Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0x1 invalid Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0x2 invalid Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0x3 invalid Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0x4 valid Divisor value F/D 0x5 valid Divisor value F/D 0x6 valid Divisor value F/D 0x7 valid Divisor value F/D 0x8 valid Divisor value F/D 0x9 CTRL Control Register 0x10 32 read-write 0x1000006 0xFFFFFFFF IC Inverse Convention 0 1 read-write dir_convention Direction convention transfers enabled 0 inv_convention Inverse convention transfers enabled 0x1 ICM Initial Character Mode 1 1 read-write disabled Initial Character Mode disabled 0 enabled Initial Character Mode enabled 0x1 ANACK Auto NACK Enable 2 1 read-write disabled NACK generation on errors disabled 0 enabled NACK generation on errors enabled 0x1 ONACK Overrun NACK Enable 3 1 read-write disabled NACK generation on overrun is disabled 0 enabled NACK generation on overrun is enabled 0x1 FLSH_RX Flush Receiver Bit 8 1 read-write normalop EMVSIM Receiver normal operation 0 resethold EMVSIM Receiver held in Reset 0x1 FLSH_TX Flush Transmitter Bit 9 1 read-write normalop EMVSIM Transmitter normal operation 0 resethold EMVSIM Transmitter held in Reset 0x1 SW_RST Software Reset Bit 10 1 read-write normalop EMVSIM Normal operation 0 resethold EMVSIM held in Reset 0x1 KILL_CLOCKS Kill all internal clocks 11 1 read-write inclk_enabled EMVSIM input clock enabled 0 inclk_disabled EMVSIM input clock is disabled 0x1 DOZE_EN Doze Enable 12 1 read-write doze_gate DOZE instruction gates all internal EMVSIM clocks as well as the Smart Card clock when the transmit FIFO is empty 0 doze_nogate DOZE instruction has no effect on EMVSIM module 0x1 STOP_EN STOP Enable 13 1 read-write stop_all_clks STOP instruction shuts down all EMVSIM clocks 0 only_sck_on STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card) 0x1 RCV_EN Receiver Enable 16 1 read-write disabled EMVSIM Receiver disabled 0 enabled EMVSIM Receiver enabled 0x1 XMT_EN Transmitter Enable 17 1 read-write disabled EMVSIM Transmitter disabled 0 enabled EMVSIM Transmitter enabled 0x1 RCVR_11 Receiver 11 ETU Mode Enable 18 1 read-write rcvr_12 Receiver configured for 12 ETU operation mode 0 rcvr_11 Receiver configured for 11 ETU operation mode 0x1 RX_DMA_EN Receive DMA Enable 19 1 read-write no_dmaread_req No DMA Read Request asserted for Receiver 0 dmaread_req DMA Read Request asserted for Receiver 0x1 TX_DMA_EN Transmit DMA Enable 20 1 read-write no_dmawrite_req No DMA Write Request asserted for Transmitter 0 dmawrite_req DMA Write Request asserted for Transmitter 0x1 INV_CRC_VAL Invert bits in the CRC Output Value 24 1 read-write no_invert Bits in CRC Output value are not inverted. 0 invert Bits in CRC Output value are inverted. 0x1 CRC_OUT_FLIP CRC Output Value Bit Reversal or Flip 25 1 read-write not_reversed Bits within the CRC output bytes are not reversed i.e. 15:0 remains 15:0 0 reversed Bits within the CRC output bytes are reversed i.e. 15:0 becomes {8:15,0:7} 0x1 CRC_IN_FLIP CRC Input Byte's Bit Reversal or Flip Control 26 1 read-write not_reversed Bits in the input byte are not reversed (i.e. 7:0 remain 7:0) before the CRC calculation 0 reversed Bits in the input byte are reversed (i.e. 7:0 becomes 0:7) before CRC calculation 0x1 CWT_EN Character Wait Time Counter Enable 27 1 read-write disabled Character Wait time Counter is disabled 0 enabled Character Wait time counter is enabled 0x1 LRC_EN LRC Enable 28 1 read-write disabled 8-bit Linear Redundancy Checking disabled 0 enabled 8-bit Linear Redundancy Checking enabled 0x1 CRC_EN CRC Enable 29 1 read-write disabled 16-bit Cyclic Redundancy Checking disabled 0 enabled 16-bit Cyclic Redundancy Checking enabled 0x1 XMT_CRC_LRC Transmit CRC or LRC Enable 30 1 read-write no_crc_lrc_tx No CRC or LRC value is transmitted 0 crc_lrc_tx Transmit LRC or CRC info when FIFO empties (whichever is enabled) 0x1 BWT_EN Block Wait Time Counter Enable 31 1 read-write disabled Disable BWT, BGT Counters 0 enabled Enable BWT, BGT Counters 0x1 INT_MASK Interrupt Mask Register 0x14 32 read-write 0xFFFF 0xFFFFFFFF RDT_IM Receive Data Threshold Interrupt Mask 0 1 read-write int_enabled RDTF interrupt enabled 0 int_masked RDTF interrupt masked 0x1 TC_IM Transmit Complete Interrupt Mask 1 1 read-write int_enabled TCF interrupt enabled 0 int_masked TCF interrupt masked 0x1 RFO_IM Receive FIFO Overflow Interrupt Mask 2 1 read-write int_enabled RFO interrupt enabled 0 int_masked RFO interrupt masked 0x1 ETC_IM Early Transmit Complete Interrupt Mask 3 1 read-write int_enabled ETC interrupt enabled 0 int_masked ETC interrupt masked 0x1 TFE_IM Transmit FIFO Empty Interrupt Mask 4 1 read-write int_enabled TFE interrupt enabled 0 int_masked TFE interrupt masked 0x1 TNACK_IM Transmit NACK Threshold Interrupt Mask 5 1 read-write int_enabled TNTE interrupt enabled 0 int_masked TNTE interrupt masked 0x1 TFF_IM Transmit FIFO Full Interrupt Mask 6 1 read-write int_enabled TFF interrupt enabled 0 int_masked TFF interrupt masked 0x1 TDT_IM Transmit Data Threshold Interrupt Mask 7 1 read-write int_enabled TDTF interrupt enabled 0 int_masked TDTF interrupt masked 0x1 GPCNT0_IM General Purpose Timer 0 Timeout Interrupt Mask 8 1 read-write int_enabled GPCNT0_TO interrupt enabled 0 int_masked GPCNT0_TO interrupt masked 0x1 CWT_ERR_IM Character Wait Time Error Interrupt Mask 9 1 read-write int_enabled CWT_ERR interrupt enabled 0 int_disabled CWT_ERR interrupt masked 0x1 RNACK_IM Receiver NACK Threshold Interrupt Mask 10 1 read-write int_enabled RTE interrupt enabled 0 int_masked RTE interrupt masked 0x1 BWT_ERR_IM Block Wait Time Error Interrupt Mask 11 1 read-write int_enabled BWT_ERR interrupt enabled 0 int_masked BWT_ERR interrupt masked 0x1 BGT_ERR_IM Block Guard Time Error Interrupt 12 1 read-write int_enabled BGT_ERR interrupt enabled 0 int_masked BGT_ERR interrupt masked 0x1 GPCNT1_IM General Purpose Counter 1 Timeout Interrupt Mask 13 1 read-write int_enabled GPCNT1_TO interrupt enabled 0 int_masked GPCNT1_TO interrupt masked 0x1 RX_DATA_IM Receive Data Interrupt Mask 14 1 read-write int_enabled RX_DATA interrupt enabled 0 int_masked RX_DATA interrupt masked 0x1 PEF_IM Parity Error Interrupt Mask 15 1 read-write int_enabled PEF interrupt enabled 0 int_masked PEF interrupt masked 0x1 RX_THD Receiver Threshold Register 0x18 32 read-write 0x1 0xFFFFFFFF RDT Receiver Data Threshold Value 0 4 read-write RNCK_THD Receiver NACK Threshold Value 8 4 read-write TX_THD Transmitter Threshold Register 0x1C 32 read-write 0xF 0xFFFFFFFF TDT Transmitter Data Threshold Value 0 4 read-write TNCK_THD Transmitter NACK Threshold Value 8 4 read-write RX_STATUS Receive Status Register 0x20 32 read-write 0 0xFFFFFFFF RFO Receive FIFO Overflow Flag 0 1 read-write oneToClear no_overrun No overrun error has occurred 0 overflow A byte was received when the received FIFO was already full 0x1 RX_DATA Receive Data Interrupt Flag 4 1 read-write oneToClear no_byte_rx No new byte is received 0 byte_rx New byte is received ans stored in Receive FIFO 0x1 RDTF Receive Data Threshold Interrupt Flag 5 1 read-only lessthan_rxthresh Number of unread bytes in receive FIFO less than the value set by RDT 0 greater_eq_rxthresh Number of unread bytes in receive FIFO greater or than equal to value set by RDT. 0x1 LRC_OK LRC Check OK Flag 6 1 read-only lrc_notok Current LRC value does not match remainder. 0 lrc_ok Current calculated LRC value matches the expected result (i.e. zero). 0x1 CRC_OK CRC Check OK Flag 7 1 read-only crc_notok Current CRC value does not match remainder. 0 crc_ok Current calculated CRC value matches the expected result. 0x1 CWT_ERR Character Wait Time Error Flag 8 1 read-write oneToClear no_cwt_err No CWT violation has occurred 0 cwt_err Time between two consecutive characters has exceeded the value in CWT_VAL. 0x1 RTE Received NACK Threshold Error Flag 9 1 read-write oneToClear lessthan_nackthresh Number of NACKs generated by the receiver is less than the value programmed in RNCK_THD 0 greater_eq_nackthresh Number of NACKs generated by the receiver is equal to the value programmed in RNCK_THD 0x1 BWT_ERR Block Wait Time Error Flag 10 1 read-write oneToClear bwt_err_no Block wait time not exceeded 0 bwt_err_yes Block wait time was exceeded 0x1 BGT_ERR Block Guard Time Error Flag 11 1 read-write oneToClear bgt_err_sufficient Block guard time was sufficient 0 bgt_err_toosmall Block guard time was too small 0x1 PEF Parity Error Flag 12 1 read-write oneToClear no_parity_detect No parity error detected 0 parity_detect Parity error detected 0x1 FEF Frame Error Flag 13 1 read-write oneToClear no_fef_detect No frame error detected 0 fef_detect Frame error detected 0x1 RX_WPTR Receive FIFO Write Pointer Value 16 4 read-only RX_CNT Receive FIFO Byte Count 24 4 read-only fifo_empty FIFO is emtpy 0 TX_STATUS Transmitter Status Register 0x24 32 read-write 0xB8 0xFFFFFFFF TNTE Transmit NACK Threshold Error Flag 0 1 read-write oneToClear lessthan_nackthresh Transmit NACK threshold has not been reached 0 greater_eq_nackthresh Transmit NACK threshold reached; transmitter frozen 0x1 TFE Transmit FIFO Empty Flag 3 1 read-write oneToClear fifo_empty Transmit FIFO is not empty 0 fifo_notempty Transmit FIFO is empty 0x1 ETCF Early Transmit Complete Flag 4 1 read-write oneToClear etx_pending Transmit pending or in progress 0 etx_complete Transmit complete 0x1 TCF Transmit Complete Flag 5 1 read-write oneToClear tx_pending Transmit pending or in progress 0 tx_complete Transmit complete 0x1 TFF Transmit FIFO Full Flag 6 1 read-write oneToClear tx_fifo_notfull Transmit FIFO Full condition has not occurred 0 tx_fifo_full A Transmit FIFO Full condition has occurred 0x1 TDTF Transmit Data Threshold Flag 7 1 read-only lessthan_txthresh Number of bytes in FIFO is greater than TDT, or bit has been cleared 0 greater_eq_txthresh Number of bytes in FIFO is less than or equal to TDT 0x1 GPCNT0_TO General Purpose Counter 0 Timeout Flag 8 1 read-write oneToClear gpcnt0_to_notreached GPCNT0 time not reached, or bit has been cleared. 0 gpcnt0_to_reached General Purpose counter has reached the GPCNT0 value 0x1 GPCNT1_TO General Purpose Counter 1 Timeout Flag 9 1 read-write oneToClear gpcnt1_to_notreached GPCNT1 time not reached, or bit has been cleared. 0 gpcnt1_to_reached General Purpose counter has reached the GPCNT1 value 0x1 TX_RPTR Transmit FIFO Read Pointer 16 4 read-only TX_CNT Transmit FIFO Byte Count 24 4 read-only fifo_empty FIFO is emtpy 0 PCSR Port Control and Status Register 0x28 32 read-write 0x1000000 0xFFFFFFFF SAPD Auto Power Down Enable 0 1 read-write disabled Auto power down disabled 0 enabled Auto power down enabled 0x1 SVCC_EN Vcc Enable for Smart Card 1 1 read-write disabled Smart Card Voltage disabled 0 enabled Smart Card Voltage enabled 0x1 VCCENP VCC Enable Polarity Control 2 1 read-write active_high SVCC_EN is active high. Polarity of SVCC_EN is unchanged. 0 active_low SVCC_EN is active low. Polarity of SVCC_EN is inverted. 0x1 SRST Reset to Smart Card 3 1 read-write asserted Smart Card Reset is asserted 0 de_asserted Smart Card Reset is de-asserted 0x1 SCEN Clock Enable for Smart Card 4 1 read-write disabled Smart Card Clock Disabled 0 enabled Smart Card Clock Enabled 0x1 SCSP Smart Card Clock Stop Polarity 5 1 read-write scsp_logic0 Clock is logic 0 when stopped by SCEN 0 scsp_logic1 Clock is logic 1 when stopped by SCEN 0x1 SPD Auto Power Down Control 7 1 read-write no_effect No effect 0 powerdown Start Auto Powerdown or Power Down is in progress 0x1 SPDIM Smart Card Presence Detect Interrupt Mask 24 1 read-write int_enabled SIM presence detect interrupt is enabled 0 int_masked SIM presence detect interrupt is masked 0x1 SPDIF Smart Card Presence Detect Interrupt Flag 25 1 read-write oneToClear no_insert_remove_detect No insertion or removal of Smart Card detected on Port 0 insert_remove_detect Insertion or removal of Smart Card detected on Port 0x1 SPDP Smart Card Presence Detect Pin Status 26 1 read-only logic_low SIM Presence Detect pin is logic low 0 logic_high SIM Presence Detectpin is logic high 0x1 SPDES SIM Presence Detect Edge Select 27 1 read-write falling_edge Falling edge on the pin 0 rising_edge Rising edge on the pin 0x1 RX_BUF Receive Data Read Buffer 0x2C 32 read-only 0 0xFFFFFFFF RX_BYTE Receive Data Byte Read 0 8 read-only TX_BUF Transmit Data Buffer 0x30 32 read-write 0 0xFFFFFFFF TX_BYTE Transmit Data Byte 0 8 read-write TX_GETU Transmitter Guard ETU Value Register 0x34 32 read-write 0 0xFFFFFFFF GETU Transmitter Guard Time Value in ETU 0 8 read-write CWT_VAL Character Wait Time Value Register 0x38 32 read-write 0xFFFF 0xFFFFFFFF CWT Character Wait Time Value 0 16 read-write BWT_VAL Block Wait Time Value Register 0x3C 32 read-write 0xFFFFFFFF 0xFFFFFFFF BWT Block Wait Time Value 0 32 read-write BGT_VAL Block Guard Time Value Register 0x40 32 read-write 0 0xFFFFFFFF BGT Block Guard Time Value 0 16 read-write GPCNT0_VAL General Purpose Counter 0 Timeout Value Register 0x44 32 read-write 0xFFFF 0xFFFFFFFF GPCNT0 General Purpose Counter 0 Timeout Value 0 16 read-write GPCNT1_VAL General Purpose Counter 1 Timeout Value 0x48 32 read-write 0xFFFF 0xFFFFFFFF GPCNT1 General Purpose Counter 1 Timeout Value 0 16 read-write EMVSIM2 EMVSIM EMVSIM 0x40158000 0 0x4C registers EMVSIM2 205 TMR1 TMR TMR TMR 0x4015C000 0 0x7A registers TMR1 171 COMP10 Timer Channel Compare Register 1 0 16 read-write 0 0xFFFF COMPARISON_1 Comparison Value 1 0 16 read-write COMP20 Timer Channel Compare Register 2 0x2 16 read-write 0 0xFFFF COMPARISON_2 Comparison Value 2 0 16 read-write CAPT0 Timer Channel Capture Register 0x4 16 read-write 0 0xFFFF CAPTURE Capture Value 0 16 read-write LOAD0 Timer Channel Load Register 0x6 16 read-write 0 0xFFFF LOAD Timer Load Register 0 16 read-write HOLD0 Timer Channel Hold Register 0x8 16 read-write 0 0xFFFF HOLD HOLD 0 16 read-write CNTR0 Timer Channel Counter Register 0xA 16 read-write 0 0xFFFF COUNTER COUNTER 0 16 read-write CTRL0 Timer Channel Control Register 0xC 16 read-write 0 0xFFFF OUTMODE Output Mode 0 3 read-write COUNTER_ACTIVE Asserted while counter is active 0 CLEAR_OFLAG Clear OFLAG output on successful compare 0x1 SET_OFLAG Set OFLAG output on successful compare 0x2 TOGGLE_OFLAG_SUCCESS Toggle OFLAG output on successful compare 0x3 TOGGLE_OFLAG_ALT Toggle OFLAG output using alternating compare registers 0x4 CLEAR_ON_SECONDARY Set on compare, cleared on secondary source input edge 0x5 CLEAR_ON_ROLLOVER Set on compare, cleared on counter rollover 0x6 ENABLE_GATED_OUT Enable gated clock output while counter is active 0x7 COINIT Co-Channel Initialization 3 1 read-write DISABLE Co-channel counter/timers cannot force a re-initialization of this counter/timer 0 ENABLE Co-channel counter/timers may force a re-initialization of this counter/timer 0x1 DIR Count Direction 4 1 read-write COUNTUP Count up. 0 COUNTDOWN Count down. 0x1 LENGTH Count Length 5 1 read-write UNTIL_ROLLOVER Count until roll over at $FFFF and continue from $0000. 0 UNTIL_COMPARE Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. 0x1 ONCE Count Once 6 1 read-write REPEAT Count repeatedly. 0 UNTIL_COMPARE Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. 0x1 SCS Secondary Count Source 7 2 read-write COUNTER0_IN Counter 0 input pin 0 COUNTER1_IN Counter 1 input pin 0x1 COUNTER2_IN Counter 2 input pin 0x2 COUNTER3_IN Counter 3 input pin 0x3 PCS Primary Count Source 9 4 read-write COUNTER0_IN Counter 0 input pin 0 COUNTER1_IN Counter 1 input pin 0x1 COUNTER2_IN Counter 2 input pin 0x2 COUNTER3_IN Counter 3 input pin 0x3 COUNTER0_OUT Counter 0 output 0x4 COUNTER1_OUT Counter 1 output 0x5 COUNTER2_OUT Counter 2 output 0x6 COUNTER3_OUT Counter 3 output 0x7 BUS_DIVBY1 IP bus clock divide by 1 prescaler 0x8 BUS_DIVBY2 IP bus clock divide by 2 prescaler 0x9 BUS_DIVBY4 IP bus clock divide by 4 prescaler 0xA BUS_DIVBY8 IP bus clock divide by 8 prescaler 0xB BUS_DIVBY16 IP bus clock divide by 16 prescaler 0xC BUS_DIVBY32 IP bus clock divide by 32 prescaler 0xD BUS_DIVBY64 IP bus clock divide by 64 prescaler 0xE BUS_DIVBY128 IP bus clock divide by 128 prescaler 0xF CM Count Mode 13 3 read-write NOOP No operation 0 RISING_ONLY Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. 0x1 RISING_AND_FALLING Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. 0x2 RISING_WHILE_SEC_HIGH Count rising edges of primary source while secondary input high active 0x3 QUADRATURE Quadrature count mode, uses primary and secondary sources 0x4 RISING_SEC_DIR Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. 0x5 SECONDARY Edge of secondary source triggers primary count until compare 0x6 CASCADE Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. 0x7 SCTRL0 Timer Channel Status and Control Register 0xE 16 read-write 0 0xFFFF OEN Output Enable 0 1 read-write INPUT The external pin is configured as an input. 0 OFLAG_OUT The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS. 0x1 OPS Output Polarity Select 1 1 read-write TRUE True polarity. 0 INVERTED Inverted polarity. 0x1 FORCE Force OFLAG Output 2 1 read-write VAL Forced OFLAG Value 3 1 read-write EEOF Enable External OFLAG Force 4 1 read-write MSTR Master Mode 5 1 read-write CAPTURE_MODE Input Capture Mode 6 2 read-write DISABLED Capture function is disabled 0 ENABLE_RISING Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input 0x1 ENABLE_FALLING Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input 0x2 ENABLE_BOTH Load capture register on both edges of input 0x3 INPUT External Input Signal 8 1 read-only IPS Input Polarity Select 9 1 read-write IEFIE Input Edge Flag Interrupt Enable 10 1 read-write IEF Input Edge Flag 11 1 read-write TOFIE Timer Overflow Flag Interrupt Enable 12 1 read-write TOF Timer Overflow Flag 13 1 read-write TCFIE Timer Compare Flag Interrupt Enable 14 1 read-write TCF Timer Compare Flag 15 1 read-write CMPLD10 Timer Channel Comparator Load Register 1 0x10 16 read-write 0 0xFFFF COMPARATOR_LOAD_1 COMPARATOR_LOAD_1 0 16 read-write CMPLD20 Timer Channel Comparator Load Register 2 0x12 16 read-write 0 0xFFFF COMPARATOR_LOAD_2 COMPARATOR_LOAD_2 0 16 read-write CSCTRL0 Timer Channel Comparator Status and Control Register 0x14 16 read-write 0 0xFFFF CL1 Compare Load Control 1 0 2 read-write NEVER Never preload 0 COMP1 Load upon successful compare with the value in COMP1 0x1 COMP2 Load upon successful compare with the value in COMP2 0x2 CL2 Compare Load Control 2 2 2 read-write NEVER Never preload 0 COMP1 Load upon successful compare with the value in COMP1 0x1 COMP2 Load upon successful compare with the value in COMP2 0x2 TCF1 Timer Compare 1 Interrupt Flag 4 1 read-write TCF2 Timer Compare 2 Interrupt Flag 5 1 read-write TCF1EN Timer Compare 1 Interrupt Enable 6 1 read-write TCF2EN Timer Compare 2 Interrupt Enable 7 1 read-write UP Counting Direction Indicator 9 1 read-only DOWN The last count was in the DOWN direction. 0 UP The last count was in the UP direction. 0x1 TCI Triggered Count Initialization Control 10 1 read-write STOP Stop counter upon receiving a second trigger event while still counting from the first trigger event. 0 RELOAD Reload the counter upon receiving a second trigger event while still counting from the first trigger event. 0x1 ROC Reload on Capture 11 1 read-write DISABLE Do not reload the counter on a capture event. 0 ENABLE Reload the counter on a capture event. 0x1 ALT_LOAD Alternative Load Enable 12 1 read-write DISABLE Counter can be re-initialized only with the LOAD register. 0 ENABLE Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. 0x1 FAULT Fault Enable 13 1 read-write DISABLE Fault function disabled. 0 ENABLE Fault function enabled. 0x1 DBG_EN Debug Actions Enable 14 2 read-write NORMAL Continue with normal operation during debug mode. (default) 0 HALT_TMR Halt TMR counter during debug mode. 0x1 FORCE_0 Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). 0x2 HALT_AND_FORCE_0 Both halt counter and force output to 0 during debug mode. 0x3 FILT0 Timer Channel Input Filter Register 0x16 16 read-write 0 0xFFFF FILT_PER Input Filter Sample Period 0 8 read-write FILT_CNT Input Filter Sample Count 8 3 read-write DMA0 Timer Channel DMA Enable Register 0x18 16 read-write 0 0xFFFF IEFDE Input Edge Flag DMA Enable 0 1 read-write CMPLD1DE Comparator Preload Register 1 DMA Enable 1 1 read-write CMPLD2DE Comparator Preload Register 2 DMA Enable 2 1 read-write ENBL Timer Channel Enable Register 0x1E 16 read-write 0xF 0xFFFF ENBL Timer Channel Enable 0 4 read-write DISABLE Timer channel is disabled. 0 ENABLE Timer channel is enabled. (default) 0x1 COMP11 Timer Channel Compare Register 1 0x20 16 read-write 0 0xFFFF COMPARISON_1 Comparison Value 1 0 16 read-write COMP21 Timer Channel Compare Register 2 0x22 16 read-write 0 0xFFFF COMPARISON_2 Comparison Value 2 0 16 read-write CAPT1 Timer Channel Capture Register 0x24 16 read-write 0 0xFFFF CAPTURE Capture Value 0 16 read-write LOAD1 Timer Channel Load Register 0x26 16 read-write 0 0xFFFF LOAD Timer Load Register 0 16 read-write HOLD1 Timer Channel Hold Register 0x28 16 read-write 0 0xFFFF HOLD HOLD 0 16 read-write CNTR1 Timer Channel Counter Register 0x2A 16 read-write 0 0xFFFF COUNTER COUNTER 0 16 read-write CTRL1 Timer Channel Control Register 0x2C 16 read-write 0 0xFFFF OUTMODE Output Mode 0 3 read-write COUNTER_ACTIVE Asserted while counter is active 0 CLEAR_OFLAG Clear OFLAG output on successful compare 0x1 SET_OFLAG Set OFLAG output on successful compare 0x2 TOGGLE_OFLAG_SUCCESS Toggle OFLAG output on successful compare 0x3 TOGGLE_OFLAG_ALT Toggle OFLAG output using alternating compare registers 0x4 CLEAR_ON_SECONDARY Set on compare, cleared on secondary source input edge 0x5 CLEAR_ON_ROLLOVER Set on compare, cleared on counter rollover 0x6 ENABLE_GATED_OUT Enable gated clock output while counter is active 0x7 COINIT Co-Channel Initialization 3 1 read-write DISABLE Co-channel counter/timers cannot force a re-initialization of this counter/timer 0 ENABLE Co-channel counter/timers may force a re-initialization of this counter/timer 0x1 DIR Count Direction 4 1 read-write COUNTUP Count up. 0 COUNTDOWN Count down. 0x1 LENGTH Count Length 5 1 read-write UNTIL_ROLLOVER Count until roll over at $FFFF and continue from $0000. 0 UNTIL_COMPARE Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. 0x1 ONCE Count Once 6 1 read-write REPEAT Count repeatedly. 0 UNTIL_COMPARE Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. 0x1 SCS Secondary Count Source 7 2 read-write COUNTER0_IN Counter 0 input pin 0 COUNTER1_IN Counter 1 input pin 0x1 COUNTER2_IN Counter 2 input pin 0x2 COUNTER3_IN Counter 3 input pin 0x3 PCS Primary Count Source 9 4 read-write COUNTER0_IN Counter 0 input pin 0 COUNTER1_IN Counter 1 input pin 0x1 COUNTER2_IN Counter 2 input pin 0x2 COUNTER3_IN Counter 3 input pin 0x3 COUNTER0_OUT Counter 0 output 0x4 COUNTER1_OUT Counter 1 output 0x5 COUNTER2_OUT Counter 2 output 0x6 COUNTER3_OUT Counter 3 output 0x7 BUS_DIVBY1 IP bus clock divide by 1 prescaler 0x8 BUS_DIVBY2 IP bus clock divide by 2 prescaler 0x9 BUS_DIVBY4 IP bus clock divide by 4 prescaler 0xA BUS_DIVBY8 IP bus clock divide by 8 prescaler 0xB BUS_DIVBY16 IP bus clock divide by 16 prescaler 0xC BUS_DIVBY32 IP bus clock divide by 32 prescaler 0xD BUS_DIVBY64 IP bus clock divide by 64 prescaler 0xE BUS_DIVBY128 IP bus clock divide by 128 prescaler 0xF CM Count Mode 13 3 read-write NOOP No operation 0 RISING_ONLY Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. 0x1 RISING_AND_FALLING Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. 0x2 RISING_WHILE_SEC_HIGH Count rising edges of primary source while secondary input high active 0x3 QUADRATURE Quadrature count mode, uses primary and secondary sources 0x4 RISING_SEC_DIR Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. 0x5 SECONDARY Edge of secondary source triggers primary count until compare 0x6 CASCADE Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. 0x7 SCTRL1 Timer Channel Status and Control Register 0x2E 16 read-write 0 0xFFFF OEN Output Enable 0 1 read-write INPUT The external pin is configured as an input. 0 OFLAG_OUT The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS. 0x1 OPS Output Polarity Select 1 1 read-write TRUE True polarity. 0 INVERTED Inverted polarity. 0x1 FORCE Force OFLAG Output 2 1 read-write VAL Forced OFLAG Value 3 1 read-write EEOF Enable External OFLAG Force 4 1 read-write MSTR Master Mode 5 1 read-write CAPTURE_MODE Input Capture Mode 6 2 read-write DISABLED Capture function is disabled 0 ENABLE_RISING Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input 0x1 ENABLE_FALLING Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input 0x2 ENABLE_BOTH Load capture register on both edges of input 0x3 INPUT External Input Signal 8 1 read-only IPS Input Polarity Select 9 1 read-write IEFIE Input Edge Flag Interrupt Enable 10 1 read-write IEF Input Edge Flag 11 1 read-write TOFIE Timer Overflow Flag Interrupt Enable 12 1 read-write TOF Timer Overflow Flag 13 1 read-write TCFIE Timer Compare Flag Interrupt Enable 14 1 read-write TCF Timer Compare Flag 15 1 read-write CMPLD11 Timer Channel Comparator Load Register 1 0x30 16 read-write 0 0xFFFF COMPARATOR_LOAD_1 COMPARATOR_LOAD_1 0 16 read-write CMPLD21 Timer Channel Comparator Load Register 2 0x32 16 read-write 0 0xFFFF COMPARATOR_LOAD_2 COMPARATOR_LOAD_2 0 16 read-write CSCTRL1 Timer Channel Comparator Status and Control Register 0x34 16 read-write 0 0xFFFF CL1 Compare Load Control 1 0 2 read-write NEVER Never preload 0 COMP1 Load upon successful compare with the value in COMP1 0x1 COMP2 Load upon successful compare with the value in COMP2 0x2 CL2 Compare Load Control 2 2 2 read-write NEVER Never preload 0 COMP1 Load upon successful compare with the value in COMP1 0x1 COMP2 Load upon successful compare with the value in COMP2 0x2 TCF1 Timer Compare 1 Interrupt Flag 4 1 read-write TCF2 Timer Compare 2 Interrupt Flag 5 1 read-write TCF1EN Timer Compare 1 Interrupt Enable 6 1 read-write TCF2EN Timer Compare 2 Interrupt Enable 7 1 read-write UP Counting Direction Indicator 9 1 read-only DOWN The last count was in the DOWN direction. 0 UP The last count was in the UP direction. 0x1 TCI Triggered Count Initialization Control 10 1 read-write STOP Stop counter upon receiving a second trigger event while still counting from the first trigger event. 0 RELOAD Reload the counter upon receiving a second trigger event while still counting from the first trigger event. 0x1 ROC Reload on Capture 11 1 read-write DISABLE Do not reload the counter on a capture event. 0 ENABLE Reload the counter on a capture event. 0x1 ALT_LOAD Alternative Load Enable 12 1 read-write DISABLE Counter can be re-initialized only with the LOAD register. 0 ENABLE Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. 0x1 FAULT Fault Enable 13 1 read-write DISABLE Fault function disabled. 0 ENABLE Fault function enabled. 0x1 DBG_EN Debug Actions Enable 14 2 read-write NORMAL Continue with normal operation during debug mode. (default) 0 HALT_TMR Halt TMR counter during debug mode. 0x1 FORCE_0 Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). 0x2 HALT_AND_FORCE_0 Both halt counter and force output to 0 during debug mode. 0x3 FILT1 Timer Channel Input Filter Register 0x36 16 read-write 0 0xFFFF FILT_PER Input Filter Sample Period 0 8 read-write FILT_CNT Input Filter Sample Count 8 3 read-write DMA1 Timer Channel DMA Enable Register 0x38 16 read-write 0 0xFFFF IEFDE Input Edge Flag DMA Enable 0 1 read-write CMPLD1DE Comparator Preload Register 1 DMA Enable 1 1 read-write CMPLD2DE Comparator Preload Register 2 DMA Enable 2 1 read-write COMP12 Timer Channel Compare Register 1 0x40 16 read-write 0 0xFFFF COMPARISON_1 Comparison Value 1 0 16 read-write COMP22 Timer Channel Compare Register 2 0x42 16 read-write 0 0xFFFF COMPARISON_2 Comparison Value 2 0 16 read-write CAPT2 Timer Channel Capture Register 0x44 16 read-write 0 0xFFFF CAPTURE Capture Value 0 16 read-write LOAD2 Timer Channel Load Register 0x46 16 read-write 0 0xFFFF LOAD Timer Load Register 0 16 read-write HOLD2 Timer Channel Hold Register 0x48 16 read-write 0 0xFFFF HOLD HOLD 0 16 read-write CNTR2 Timer Channel Counter Register 0x4A 16 read-write 0 0xFFFF COUNTER COUNTER 0 16 read-write CTRL2 Timer Channel Control Register 0x4C 16 read-write 0 0xFFFF OUTMODE Output Mode 0 3 read-write COUNTER_ACTIVE Asserted while counter is active 0 CLEAR_OFLAG Clear OFLAG output on successful compare 0x1 SET_OFLAG Set OFLAG output on successful compare 0x2 TOGGLE_OFLAG_SUCCESS Toggle OFLAG output on successful compare 0x3 TOGGLE_OFLAG_ALT Toggle OFLAG output using alternating compare registers 0x4 CLEAR_ON_SECONDARY Set on compare, cleared on secondary source input edge 0x5 CLEAR_ON_ROLLOVER Set on compare, cleared on counter rollover 0x6 ENABLE_GATED_OUT Enable gated clock output while counter is active 0x7 COINIT Co-Channel Initialization 3 1 read-write DISABLE Co-channel counter/timers cannot force a re-initialization of this counter/timer 0 ENABLE Co-channel counter/timers may force a re-initialization of this counter/timer 0x1 DIR Count Direction 4 1 read-write COUNTUP Count up. 0 COUNTDOWN Count down. 0x1 LENGTH Count Length 5 1 read-write UNTIL_ROLLOVER Count until roll over at $FFFF and continue from $0000. 0 UNTIL_COMPARE Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. 0x1 ONCE Count Once 6 1 read-write REPEAT Count repeatedly. 0 UNTIL_COMPARE Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. 0x1 SCS Secondary Count Source 7 2 read-write COUNTER0_IN Counter 0 input pin 0 COUNTER1_IN Counter 1 input pin 0x1 COUNTER2_IN Counter 2 input pin 0x2 COUNTER3_IN Counter 3 input pin 0x3 PCS Primary Count Source 9 4 read-write COUNTER0_IN Counter 0 input pin 0 COUNTER1_IN Counter 1 input pin 0x1 COUNTER2_IN Counter 2 input pin 0x2 COUNTER3_IN Counter 3 input pin 0x3 COUNTER0_OUT Counter 0 output 0x4 COUNTER1_OUT Counter 1 output 0x5 COUNTER2_OUT Counter 2 output 0x6 COUNTER3_OUT Counter 3 output 0x7 BUS_DIVBY1 IP bus clock divide by 1 prescaler 0x8 BUS_DIVBY2 IP bus clock divide by 2 prescaler 0x9 BUS_DIVBY4 IP bus clock divide by 4 prescaler 0xA BUS_DIVBY8 IP bus clock divide by 8 prescaler 0xB BUS_DIVBY16 IP bus clock divide by 16 prescaler 0xC BUS_DIVBY32 IP bus clock divide by 32 prescaler 0xD BUS_DIVBY64 IP bus clock divide by 64 prescaler 0xE BUS_DIVBY128 IP bus clock divide by 128 prescaler 0xF CM Count Mode 13 3 read-write NOOP No operation 0 RISING_ONLY Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. 0x1 RISING_AND_FALLING Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. 0x2 RISING_WHILE_SEC_HIGH Count rising edges of primary source while secondary input high active 0x3 QUADRATURE Quadrature count mode, uses primary and secondary sources 0x4 RISING_SEC_DIR Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. 0x5 SECONDARY Edge of secondary source triggers primary count until compare 0x6 CASCADE Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. 0x7 SCTRL2 Timer Channel Status and Control Register 0x4E 16 read-write 0 0xFFFF OEN Output Enable 0 1 read-write INPUT The external pin is configured as an input. 0 OFLAG_OUT The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS. 0x1 OPS Output Polarity Select 1 1 read-write TRUE True polarity. 0 INVERTED Inverted polarity. 0x1 FORCE Force OFLAG Output 2 1 read-write VAL Forced OFLAG Value 3 1 read-write EEOF Enable External OFLAG Force 4 1 read-write MSTR Master Mode 5 1 read-write CAPTURE_MODE Input Capture Mode 6 2 read-write DISABLED Capture function is disabled 0 ENABLE_RISING Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input 0x1 ENABLE_FALLING Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input 0x2 ENABLE_BOTH Load capture register on both edges of input 0x3 INPUT External Input Signal 8 1 read-only IPS Input Polarity Select 9 1 read-write IEFIE Input Edge Flag Interrupt Enable 10 1 read-write IEF Input Edge Flag 11 1 read-write TOFIE Timer Overflow Flag Interrupt Enable 12 1 read-write TOF Timer Overflow Flag 13 1 read-write TCFIE Timer Compare Flag Interrupt Enable 14 1 read-write TCF Timer Compare Flag 15 1 read-write CMPLD12 Timer Channel Comparator Load Register 1 0x50 16 read-write 0 0xFFFF COMPARATOR_LOAD_1 COMPARATOR_LOAD_1 0 16 read-write CMPLD22 Timer Channel Comparator Load Register 2 0x52 16 read-write 0 0xFFFF COMPARATOR_LOAD_2 COMPARATOR_LOAD_2 0 16 read-write CSCTRL2 Timer Channel Comparator Status and Control Register 0x54 16 read-write 0 0xFFFF CL1 Compare Load Control 1 0 2 read-write NEVER Never preload 0 COMP1 Load upon successful compare with the value in COMP1 0x1 COMP2 Load upon successful compare with the value in COMP2 0x2 CL2 Compare Load Control 2 2 2 read-write NEVER Never preload 0 COMP1 Load upon successful compare with the value in COMP1 0x1 COMP2 Load upon successful compare with the value in COMP2 0x2 TCF1 Timer Compare 1 Interrupt Flag 4 1 read-write TCF2 Timer Compare 2 Interrupt Flag 5 1 read-write TCF1EN Timer Compare 1 Interrupt Enable 6 1 read-write TCF2EN Timer Compare 2 Interrupt Enable 7 1 read-write UP Counting Direction Indicator 9 1 read-only DOWN The last count was in the DOWN direction. 0 UP The last count was in the UP direction. 0x1 TCI Triggered Count Initialization Control 10 1 read-write STOP Stop counter upon receiving a second trigger event while still counting from the first trigger event. 0 RELOAD Reload the counter upon receiving a second trigger event while still counting from the first trigger event. 0x1 ROC Reload on Capture 11 1 read-write DISABLE Do not reload the counter on a capture event. 0 ENABLE Reload the counter on a capture event. 0x1 ALT_LOAD Alternative Load Enable 12 1 read-write DISABLE Counter can be re-initialized only with the LOAD register. 0 ENABLE Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. 0x1 FAULT Fault Enable 13 1 read-write DISABLE Fault function disabled. 0 ENABLE Fault function enabled. 0x1 DBG_EN Debug Actions Enable 14 2 read-write NORMAL Continue with normal operation during debug mode. (default) 0 HALT_TMR Halt TMR counter during debug mode. 0x1 FORCE_0 Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). 0x2 HALT_AND_FORCE_0 Both halt counter and force output to 0 during debug mode. 0x3 FILT2 Timer Channel Input Filter Register 0x56 16 read-write 0 0xFFFF FILT_PER Input Filter Sample Period 0 8 read-write FILT_CNT Input Filter Sample Count 8 3 read-write DMA2 Timer Channel DMA Enable Register 0x58 16 read-write 0 0xFFFF IEFDE Input Edge Flag DMA Enable 0 1 read-write CMPLD1DE Comparator Preload Register 1 DMA Enable 1 1 read-write CMPLD2DE Comparator Preload Register 2 DMA Enable 2 1 read-write COMP13 Timer Channel Compare Register 1 0x60 16 read-write 0 0xFFFF COMPARISON_1 Comparison Value 1 0 16 read-write COMP23 Timer Channel Compare Register 2 0x62 16 read-write 0 0xFFFF COMPARISON_2 Comparison Value 2 0 16 read-write CAPT3 Timer Channel Capture Register 0x64 16 read-write 0 0xFFFF CAPTURE Capture Value 0 16 read-write LOAD3 Timer Channel Load Register 0x66 16 read-write 0 0xFFFF LOAD Timer Load Register 0 16 read-write HOLD3 Timer Channel Hold Register 0x68 16 read-write 0 0xFFFF HOLD HOLD 0 16 read-write CNTR3 Timer Channel Counter Register 0x6A 16 read-write 0 0xFFFF COUNTER COUNTER 0 16 read-write CTRL3 Timer Channel Control Register 0x6C 16 read-write 0 0xFFFF OUTMODE Output Mode 0 3 read-write COUNTER_ACTIVE Asserted while counter is active 0 CLEAR_OFLAG Clear OFLAG output on successful compare 0x1 SET_OFLAG Set OFLAG output on successful compare 0x2 TOGGLE_OFLAG_SUCCESS Toggle OFLAG output on successful compare 0x3 TOGGLE_OFLAG_ALT Toggle OFLAG output using alternating compare registers 0x4 CLEAR_ON_SECONDARY Set on compare, cleared on secondary source input edge 0x5 CLEAR_ON_ROLLOVER Set on compare, cleared on counter rollover 0x6 ENABLE_GATED_OUT Enable gated clock output while counter is active 0x7 COINIT Co-Channel Initialization 3 1 read-write DISABLE Co-channel counter/timers cannot force a re-initialization of this counter/timer 0 ENABLE Co-channel counter/timers may force a re-initialization of this counter/timer 0x1 DIR Count Direction 4 1 read-write COUNTUP Count up. 0 COUNTDOWN Count down. 0x1 LENGTH Count Length 5 1 read-write UNTIL_ROLLOVER Count until roll over at $FFFF and continue from $0000. 0 UNTIL_COMPARE Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. 0x1 ONCE Count Once 6 1 read-write REPEAT Count repeatedly. 0 UNTIL_COMPARE Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. 0x1 SCS Secondary Count Source 7 2 read-write COUNTER0_IN Counter 0 input pin 0 COUNTER1_IN Counter 1 input pin 0x1 COUNTER2_IN Counter 2 input pin 0x2 COUNTER3_IN Counter 3 input pin 0x3 PCS Primary Count Source 9 4 read-write COUNTER0_IN Counter 0 input pin 0 COUNTER1_IN Counter 1 input pin 0x1 COUNTER2_IN Counter 2 input pin 0x2 COUNTER3_IN Counter 3 input pin 0x3 COUNTER0_OUT Counter 0 output 0x4 COUNTER1_OUT Counter 1 output 0x5 COUNTER2_OUT Counter 2 output 0x6 COUNTER3_OUT Counter 3 output 0x7 BUS_DIVBY1 IP bus clock divide by 1 prescaler 0x8 BUS_DIVBY2 IP bus clock divide by 2 prescaler 0x9 BUS_DIVBY4 IP bus clock divide by 4 prescaler 0xA BUS_DIVBY8 IP bus clock divide by 8 prescaler 0xB BUS_DIVBY16 IP bus clock divide by 16 prescaler 0xC BUS_DIVBY32 IP bus clock divide by 32 prescaler 0xD BUS_DIVBY64 IP bus clock divide by 64 prescaler 0xE BUS_DIVBY128 IP bus clock divide by 128 prescaler 0xF CM Count Mode 13 3 read-write NOOP No operation 0 RISING_ONLY Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. 0x1 RISING_AND_FALLING Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. 0x2 RISING_WHILE_SEC_HIGH Count rising edges of primary source while secondary input high active 0x3 QUADRATURE Quadrature count mode, uses primary and secondary sources 0x4 RISING_SEC_DIR Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. 0x5 SECONDARY Edge of secondary source triggers primary count until compare 0x6 CASCADE Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. 0x7 SCTRL3 Timer Channel Status and Control Register 0x6E 16 read-write 0 0xFFFF OEN Output Enable 0 1 read-write INPUT The external pin is configured as an input. 0 OFLAG_OUT The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS. 0x1 OPS Output Polarity Select 1 1 read-write TRUE True polarity. 0 INVERTED Inverted polarity. 0x1 FORCE Force OFLAG Output 2 1 read-write VAL Forced OFLAG Value 3 1 read-write EEOF Enable External OFLAG Force 4 1 read-write MSTR Master Mode 5 1 read-write CAPTURE_MODE Input Capture Mode 6 2 read-write DISABLED Capture function is disabled 0 ENABLE_RISING Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input 0x1 ENABLE_FALLING Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input 0x2 ENABLE_BOTH Load capture register on both edges of input 0x3 INPUT External Input Signal 8 1 read-only IPS Input Polarity Select 9 1 read-write IEFIE Input Edge Flag Interrupt Enable 10 1 read-write IEF Input Edge Flag 11 1 read-write TOFIE Timer Overflow Flag Interrupt Enable 12 1 read-write TOF Timer Overflow Flag 13 1 read-write TCFIE Timer Compare Flag Interrupt Enable 14 1 read-write TCF Timer Compare Flag 15 1 read-write CMPLD13 Timer Channel Comparator Load Register 1 0x70 16 read-write 0 0xFFFF COMPARATOR_LOAD_1 COMPARATOR_LOAD_1 0 16 read-write CMPLD23 Timer Channel Comparator Load Register 2 0x72 16 read-write 0 0xFFFF COMPARATOR_LOAD_2 COMPARATOR_LOAD_2 0 16 read-write CSCTRL3 Timer Channel Comparator Status and Control Register 0x74 16 read-write 0 0xFFFF CL1 Compare Load Control 1 0 2 read-write NEVER Never preload 0 COMP1 Load upon successful compare with the value in COMP1 0x1 COMP2 Load upon successful compare with the value in COMP2 0x2 CL2 Compare Load Control 2 2 2 read-write NEVER Never preload 0 COMP1 Load upon successful compare with the value in COMP1 0x1 COMP2 Load upon successful compare with the value in COMP2 0x2 TCF1 Timer Compare 1 Interrupt Flag 4 1 read-write TCF2 Timer Compare 2 Interrupt Flag 5 1 read-write TCF1EN Timer Compare 1 Interrupt Enable 6 1 read-write TCF2EN Timer Compare 2 Interrupt Enable 7 1 read-write UP Counting Direction Indicator 9 1 read-only DOWN The last count was in the DOWN direction. 0 UP The last count was in the UP direction. 0x1 TCI Triggered Count Initialization Control 10 1 read-write STOP Stop counter upon receiving a second trigger event while still counting from the first trigger event. 0 RELOAD Reload the counter upon receiving a second trigger event while still counting from the first trigger event. 0x1 ROC Reload on Capture 11 1 read-write DISABLE Do not reload the counter on a capture event. 0 ENABLE Reload the counter on a capture event. 0x1 ALT_LOAD Alternative Load Enable 12 1 read-write DISABLE Counter can be re-initialized only with the LOAD register. 0 ENABLE Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. 0x1 FAULT Fault Enable 13 1 read-write DISABLE Fault function disabled. 0 ENABLE Fault function enabled. 0x1 DBG_EN Debug Actions Enable 14 2 read-write NORMAL Continue with normal operation during debug mode. (default) 0 HALT_TMR Halt TMR counter during debug mode. 0x1 FORCE_0 Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). 0x2 HALT_AND_FORCE_0 Both halt counter and force output to 0 during debug mode. 0x3 FILT3 Timer Channel Input Filter Register 0x76 16 read-write 0 0xFFFF FILT_PER Input Filter Sample Period 0 8 read-write FILT_CNT Input Filter Sample Count 8 3 read-write DMA3 Timer Channel DMA Enable Register 0x78 16 read-write 0 0xFFFF IEFDE Input Edge Flag DMA Enable 0 1 read-write CMPLD1DE Comparator Preload Register 1 DMA Enable 1 1 read-write CMPLD2DE Comparator Preload Register 2 DMA Enable 2 1 read-write TMR2 TMR TMR 0x40160000 0 0x7A registers TMR2 172 TMR3 TMR TMR 0x40164000 0 0x7A registers TMR3 173 TMR4 TMR TMR 0x40168000 0 0x7A registers TMR4 174 ENC1 QDC ENC ENC 0x40174000 0 0x34 registers ENC1 165 CTRL Control Register 0 16 read-write 0 0xFFFF CMPIE Compare Interrupt Enable 0 1 read-write CMPIE_0 Disabled 0 CMPIE_1 Enabled 0x1 CMPIRQ Compare Interrupt Request 1 1 read-write oneToClear CMPIRQ_0 No match has occurred (the counter does not match the COMP value) 0 CMPIRQ_1 COMP match has occurred (the counter matches the COMP value) 0x1 WDE Watchdog Enable 2 1 read-write WDE_0 Disabled 0 WDE_1 Enabled 0x1 DIE Watchdog Timeout Interrupt Enable 3 1 read-write DIE_0 Disabled 0 DIE_1 Enabled 0x1 DIRQ Watchdog Timeout Interrupt Request 4 1 read-write oneToClear DIRQ_0 No Watchdog timeout interrupt has occurred 0 DIRQ_1 Watchdog timeout interrupt has occurred 0x1 XNE Use Negative Edge of INDEX Pulse 5 1 read-write XNE_0 Use positive edge of INDEX pulse 0 XNE_1 Use negative edge of INDEX pulse 0x1 XIP INDEX Triggered Initialization of Position Counters UPOS and LPOS 6 1 read-write XIP_0 INDEX pulse does not initialize the position counter 0 XIP_1 INDEX pulse initializes the position counter 0x1 XIE INDEX Pulse Interrupt Enable 7 1 read-write XIE_0 Disabled 0 XIE_1 Enabled 0x1 XIRQ INDEX Pulse Interrupt Request 8 1 read-write oneToClear XIRQ_0 INDEX pulse has not occurred 0 XIRQ_1 INDEX pulse has occurred 0x1 PH1 Enable Signal Phase Count Mode 9 1 read-write PH1_0 Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. 0 PH1_1 Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down 0x1 REV Enable Reverse Direction Counting 10 1 read-write REV_0 Count normally 0 REV_1 Count in the reverse direction 0x1 SWIP Software-Triggered Initialization of Position Counters UPOS and LPOS 11 1 read-write SWIP_0 No action 0 SWIP_1 Initialize position counter (using upper and lower initialization registers, UINIT and LINIT) 0x1 HNE Use Negative Edge of HOME Input 12 1 read-write HNE_0 Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS 0 HNE_1 Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS 0x1 HIP Enable HOME to Initialize Position Counters UPOS and LPOS 13 1 read-write HIP_0 No action 0 HIP_1 HOME signal initializes the position counter 0x1 HIE HOME Interrupt Enable 14 1 read-write HIE_0 Disabled 0 HIE_1 Enabled 0x1 HIRQ HOME Signal Transition Interrupt Request 15 1 read-write oneToClear HIRQ_0 No transition on the HOME signal has occurred 0 HIRQ_1 A transition on the HOME signal has occurred 0x1 FILT Input Filter Register 0x2 16 read-write 0 0xFFFF FILT_PER Input Filter Sample Period 0 8 read-write FILT_CNT Input Filter Sample Count 8 3 read-write FILT_PRSC prescaler divide IPbus clock to FILT clk 13 3 read-write WTR Watchdog Timeout Register 0x4 16 read-write 0 0xFFFF WDOG WDOG 0 16 read-write POSD Position Difference Counter Register 0x6 16 read-write 0 0xFFFF POSD POSD 0 16 read-write POSDH Position Difference Hold Register 0x8 16 read-only 0 0xFFFF POSDH POSDH 0 16 read-only REV Revolution Counter Register 0xA 16 read-write 0 0xFFFF REV REV 0 16 read-write REVH Revolution Hold Register 0xC 16 read-only 0 0xFFFF REVH REVH 0 16 read-only UPOS Upper Position Counter Register 0xE 16 read-write 0 0xFFFF POS POS 0 16 read-write LPOS Lower Position Counter Register 0x10 16 read-write 0 0xFFFF POS POS 0 16 read-write UPOSH Upper Position Hold Register 0x12 16 read-only 0 0xFFFF POSH POSH 0 16 read-only LPOSH Lower Position Hold Register 0x14 16 read-only 0 0xFFFF POSH POSH 0 16 read-only UINIT Upper Initialization Register 0x16 16 read-write 0 0xFFFF INIT INIT 0 16 read-write LINIT Lower Initialization Register 0x18 16 read-write 0 0xFFFF INIT INIT 0 16 read-write IMR Input Monitor Register 0x1A 16 read-only 0 0xFFFF HOME HOME 0 1 read-only INDEX INDEX 1 1 read-only PHB PHB 2 1 read-only PHA PHA 3 1 read-only FHOM FHOM 4 1 read-only FIND FIND 5 1 read-only FPHB FPHB 6 1 read-only FPHA FPHA 7 1 read-only TST Test Register 0x1C 16 read-write 0 0xFFFF TEST_COUNT TEST_COUNT 0 8 read-write TEST_PERIOD TEST_PERIOD 8 5 read-write QDN Quadrature Decoder Negative Signal 13 1 read-write QDN_0 Generates a positive quadrature decoder signal 0 QDN_1 Generates a negative quadrature decoder signal 0x1 TCE Test Counter Enable 14 1 read-write TCE_0 Disabled 0 TCE_1 Enabled 0x1 TEN Test Mode Enable 15 1 read-write TEN_0 Disabled 0 TEN_1 Enabled 0x1 CTRL2 Control 2 Register 0x1E 16 read-write 0 0xFFFF UPDHLD Update Hold Registers 0 1 read-write UPDHLD_0 Disable updates of hold registers on the rising edge of TRIGGER input signal 0 UPDHLD_1 Enable updates of hold registers on the rising edge of TRIGGER input signal 0x1 UPDPOS Update Position Registers 1 1 read-write UPDPOS_0 No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER 0 UPDPOS_1 Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER 0x1 MOD Enable Modulo Counting 2 1 read-write MOD_0 Disable modulo counting 0 MOD_1 Enable modulo counting 0x1 DIR Count Direction Flag 3 1 read-only DIR_0 Last count was in the down direction 0 DIR_1 Last count was in the up direction 0x1 RUIE Roll-under Interrupt Enable 4 1 read-write RUIE_0 Disabled 0 RUIE_1 Enabled 0x1 RUIRQ Roll-under Interrupt Request 5 1 read-write oneToClear RUIRQ_0 No roll-under has occurred 0 RUIRQ_1 Roll-under has occurred 0x1 ROIE Roll-over Interrupt Enable 6 1 read-write ROIE_0 Disabled 0 ROIE_1 Enabled 0x1 ROIRQ Roll-over Interrupt Request 7 1 read-write oneToClear ROIRQ_0 No roll-over has occurred 0 ROIRQ_1 Roll-over has occurred 0x1 REVMOD Revolution Counter Modulus Enable 8 1 read-write REVMOD_0 Use INDEX pulse to increment/decrement revolution counter (REV) 0 REVMOD_1 Use modulus counting roll-over/under to increment/decrement revolution counter (REV) 0x1 OUTCTL Output Control 9 1 read-write OUTCTL_0 POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) 0 OUTCTL_1 POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read 0x1 SABIE Simultaneous PHASEA and PHASEB Change Interrupt Enable 10 1 read-write SABIE_0 Disabled 0 SABIE_1 Enabled 0x1 SABIRQ Simultaneous PHASEA and PHASEB Change Interrupt Request 11 1 read-write oneToClear SABIRQ_0 No simultaneous change of PHASEA and PHASEB has occurred 0 SABIRQ_1 A simultaneous change of PHASEA and PHASEB has occurred 0x1 UMOD Upper Modulus Register 0x20 16 read-write 0 0xFFFF MOD MOD 0 16 read-write LMOD Lower Modulus Register 0x22 16 read-write 0 0xFFFF MOD MOD 0 16 read-write UCOMP Upper Position Compare Register 0x24 16 read-write 0xFFFF 0xFFFF COMP COMP 0 16 read-write LCOMP Lower Position Compare Register 0x26 16 read-write 0xFFFF 0xFFFF COMP COMP 0 16 read-write LASTEDGE Last Edge Time Register 0x28 16 read-only 0xFFFF 0xFFFF LASTEDGE Last Edge Time Counter 0 16 read-only LASTEDGEH Last Edge Time Hold Register 0x2A 16 read-only 0xFFFF 0xFFFF LASTEDGEH Last Edge Time Hold 0 16 read-only POSDPER Position Difference Period Counter Register 0x2C 16 read-only 0xFFFF 0xFFFF POSDPER Position difference period 0 16 read-only POSDPERBFR Position Difference Period Buffer Register 0x2E 16 read-only 0xFFFF 0xFFFF POSDPERBFR Position difference period buffer 0 16 read-only POSDPERH Position Difference Period Hold Register 0x30 16 read-only 0xFFFF 0xFFFF POSDPERH Position difference period hold 0 16 read-only CTRL3 Control 3 Register 0x32 16 read-write 0 0xFFFF PMEN Period measurement function enable 0 1 read-write PMEN_0 Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS, or REV is read. 0 PMEN_1 Period measurement functions are used. POSD is loaded to POSDH and then cleared only when POSD is read. 0x1 PRSC Prescaler 4 4 read-write ENC2 QDC ENC 0x40178000 0 0x34 registers ENC2 166 ENC3 QDC ENC 0x4017C000 0 0x34 registers ENC3 167 ENC4 QDC ENC 0x40180000 0 0x34 registers ENC4 168 PWM1 PWM PWM PWM 0x4018C000 0 0x196 registers PWM1_0 125 PWM1_1 126 PWM1_2 127 PWM1_3 128 PWM1_FAULT 129 4 0x60 SM[%s] no description available 0 SMCNT Counter Register 0 16 read-only 0 0xFFFF CNT Counter Register Bits 0 16 read-only SMINIT Initial Count Register 0x2 16 read-write 0 0xFFFF INIT Initial Count Register Bits 0 16 read-write SMCTRL2 Control 2 Register 0x4 16 read-write 0 0xFFFF CLK_SEL Clock Source Select 0 2 read-write IPBUS The IPBus clock is used as the clock for the local prescaler and counter. 0 EXT_CLK EXT_CLK is used as the clock for the local prescaler and counter. 0x1 AUX_CLK Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. 0x2 RELOAD_SEL Reload Source Select 2 1 read-write LOCAL The local RELOAD signal is used to reload registers. 0 MASTER The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. 0x1 FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write LOCAL The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 0 MASTER The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 0x1 LOCAL_RELOAD The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 0x2 MASTER_RELOAD The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0x3 LOCAL_SYNC The local sync signal from this submodule is used to force updates. 0x4 MASTER_SYNC The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0x5 EXT_FORCE The external force signal, EXT_FORCE, from outside the PWM module causes updates. 0x6 EXT_SYNC The external sync signal, EXT_SYNC, from outside the PWM module causes updates. 0x7 FORCE Force Initialization 6 1 read-write FRCEN FRCEN 7 1 read-write DISABLED Initialization from a FORCE_OUT is disabled. 0 ENABLED Initialization from a FORCE_OUT is enabled. 0x1 INIT_SEL Initialization Control Select 8 2 read-write PWM_X Local sync (PWM_X) causes initialization. 0 MASTER_RELOAD Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 0x1 MASTER_SYNC Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 0x2 EXT_SYNC EXT_SYNC causes initialization. 0x3 PWMX_INIT PWM_X Initial Value 10 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWM23_INIT PWM23 Initial Value 12 1 read-write INDEP Independent or Complementary Pair Operation 13 1 read-write COMPLEMENTARY PWM_A and PWM_B form a complementary PWM pair. 0 INDEPENDENT PWM_A and PWM_B outputs are independent PWMs. 0x1 WAITEN WAIT Enable 14 1 read-write DBGEN Debug Enable 15 1 read-write SMCTRL Control Register 0x6 16 read-write 0x400 0xFFFF DBLEN Double Switching Enable 0 1 read-write DISABLED Double switching disabled. 0 ENABLED Double switching enabled. 0x1 DBLX PWMX Double Switching Enable 1 1 read-write DISABLED PWMX double pulse disabled. 0 ENABLED PWMX double pulse enabled. 0x1 LDMOD Load Mode Select 2 1 read-write NEXT_PWM_RELOAD Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0 MTCTRL_LDOK_SET Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. 0x1 SPLIT Split the DBLPWM signal to PWMA and PWMB 3 1 read-write DISABLED DBLPWM is not split. PWMA and PWMB each have double pulses. 0 ENABLED DBLPWM is split to PWMA and PWMB. 0x1 PRSC Prescaler 4 3 read-write ONE Prescaler 1 0 TWO Prescaler 2 0x1 FOUR Prescaler 4 0x2 EIGHT Prescaler 8 0x3 SIXTEEN Prescaler 16 0x4 THIRTYTWO Prescaler 32 0x5 SIXTYFOUR Prescaler 64 0x6 HUNDREDTWENTYEIGHT Prescaler 128 0x7 COMPMODE Compare Mode 7 1 read-write EQUAL_TO The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0 EQUAL_TO_OR_GREATER_THAN The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. 0x1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write DISABLED Full-cycle reloads disabled. 0 ENABLED Full-cycle reloads enabled. 0x1 HALF Half Cycle Reload 11 1 read-write DISABLED Half-cycle reloads disabled. 0 ENABLED Half-cycle reloads enabled. 0x1 LDFQ Load Frequency 12 4 read-write EVERYPWM Every PWM opportunity 0 EVERY2PWM Every 2 PWM opportunities 0x1 EVERY3PWM Every 3 PWM opportunities 0x2 EVERY4PWM Every 4 PWM opportunities 0x3 EVERY5PWM Every 5 PWM opportunities 0x4 EVERY6PWM Every 6 PWM opportunities 0x5 EVERY7PWM Every 7 PWM opportunities 0x6 EVERY8PWM Every 8 PWM opportunities 0x7 EVERY9PWM Every 9 PWM opportunities 0x8 EVERY10PWM Every 10 PWM opportunities 0x9 EVERY11PWM Every 11 PWM opportunities 0xA EVERY12PWM Every 12 PWM opportunities 0xB EVERY13PWM Every 13 PWM opportunities 0xC EVERY14PWM Every 14 PWM opportunities 0xD EVERY15PWM Every 15 PWM opportunities 0xE EVERY16PWM Every 16 PWM opportunities 0xF SMVAL0 Value Register 0 0xA 16 read-write 0 0xFFFF VAL0 Value Register 0 0 16 read-write SMFRACVAL1 Fractional Value Register 1 0xC 16 read-write 0 0xFFFF FRACVAL1 Fractional Value 1 Register 11 5 read-write SMVAL1 Value Register 1 0xE 16 read-write 0 0xFFFF VAL1 Value Register 1 0 16 read-write SMFRACVAL2 Fractional Value Register 2 0x10 16 read-write 0 0xFFFF FRACVAL2 Fractional Value 2 11 5 read-write SMVAL2 Value Register 2 0x12 16 read-write 0 0xFFFF VAL2 Value Register 2 0 16 read-write SMFRACVAL3 Fractional Value Register 3 0x14 16 read-write 0 0xFFFF FRACVAL3 Fractional Value 3 11 5 read-write SMVAL3 Value Register 3 0x16 16 read-write 0 0xFFFF VAL3 Value Register 3 0 16 read-write SMFRACVAL4 Fractional Value Register 4 0x18 16 read-write 0 0xFFFF FRACVAL4 Fractional Value 4 11 5 read-write SMVAL4 Value Register 4 0x1A 16 read-write 0 0xFFFF VAL4 Value Register 4 0 16 read-write SMFRACVAL5 Fractional Value Register 5 0x1C 16 read-write 0 0xFFFF FRACVAL5 Fractional Value 5 11 5 read-write SMVAL5 Value Register 5 0x1E 16 read-write 0 0xFFFF VAL5 Value Register 5 0 16 read-write SMFRCTRL Fractional Control Register 0x20 16 read-write 0 0xFFFF FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write DISABLED Disable fractional cycle length for the PWM period. 0 ENABLED Enable fractional cycle length for the PWM period. 0x1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write DISABLED Disable fractional cycle placement for PWM_A. 0 ENABLED Enable fractional cycle placement for PWM_A. 0x1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write DISABLED Disable fractional cycle placement for PWM_B. 0 ENABLED Enable fractional cycle placement for PWM_B. 0x1 TEST Test Status Bit 15 1 read-only SMOCTRL Output Control Register 0x22 16 read-write 0 0xFFFF PWMXFS PWM_X Fault State 0 2 read-write LOGIC_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 LOGIC_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 TRISTATED Output is tristated. 0x2 TRISTATED Output is tristated. 0x3 PWMBFS PWM_B Fault State 2 2 read-write LOGIC_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 LOGIC_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 TRISTATED Output is tristated. 0x2 TRISTATED Output is tristated. 0x3 PWMAFS PWM_A Fault State 4 2 read-write LOGIC_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 LOGIC_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 TRISTATED Output is tristated. 0x2 TRISTATED Output is tristated. 0x3 POLX PWM_X Output Polarity 8 1 read-write NOT_INVERTED PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. 0 INVERTED PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. 0x1 POLB PWM_B Output Polarity 9 1 read-write NOT_INVERTED PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. 0 INVERTED PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. 0x1 POLA PWM_A Output Polarity 10 1 read-write NOT_INVERTED PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. 0 INVERTED PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. 0x1 PWMX_IN PWM_X Input 13 1 read-only PWMB_IN PWM_B Input 14 1 read-only PWMA_IN PWM_A Input 15 1 read-only SMSTS Status Register 0x24 16 read-write 0 0xFFFF CMPF Compare Flags 0 6 read-write oneToClear NO_EVENT No compare event has occurred for a particular VALx value. 0 EVENT A compare event has occurred for a particular VALx value. 0x1 CFX0 Capture Flag X0 6 1 read-write oneToClear CFX1 Capture Flag X1 7 1 read-write oneToClear CFB0 Capture Flag B0 8 1 read-write oneToClear CFB1 Capture Flag B1 9 1 read-write oneToClear CFA0 Capture Flag A0 10 1 read-write oneToClear CFA1 Capture Flag A1 11 1 read-write oneToClear RF Reload Flag 12 1 read-write oneToClear NO_FLAG No new reload cycle since last STS[RF] clearing 0 FLAG New reload cycle since last STS[RF] clearing 0x1 REF Reload Error Flag 13 1 read-write oneToClear NO_FLAG No reload error occurred. 0 FLAG Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. 0x1 RUF Registers Updated Flag 14 1 read-only NO_FLAG No register update has occurred since last reload. 0 FLAG At least one of the double buffered registers has been updated since the last reload. 0x1 SMINTEN Interrupt Enable Register 0x26 16 read-write 0 0xFFFF CMPIE Compare Interrupt Enables 0 6 read-write DISABLED The corresponding STS[CMPF] bit will not cause an interrupt request. 0 ENABLED The corresponding STS[CMPF] bit will cause an interrupt request. 0x1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write DISABLED Interrupt request disabled for STS[CFX0]. 0 ENABLED Interrupt request enabled for STS[CFX0]. 0x1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write DISABLED Interrupt request disabled for STS[CFX1]. 0 ENABLED Interrupt request enabled for STS[CFX1]. 0x1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write DISABLED Interrupt request disabled for STS[CFB0]. 0 ENABLED Interrupt request enabled for STS[CFB0]. 0x1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write DISABLED Interrupt request disabled for STS[CFB1]. 0 ENABLED Interrupt request enabled for STS[CFB1]. 0x1 CA0IE Capture A 0 Interrupt Enable 10 1 read-write DISABLED Interrupt request disabled for STS[CFA0]. 0 ENABLED Interrupt request enabled for STS[CFA0]. 0x1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write DISABLED Interrupt request disabled for STS[CFA1]. 0 ENABLED Interrupt request enabled for STS[CFA1]. 0x1 RIE Reload Interrupt Enable 12 1 read-write DISABLED STS[RF] CPU interrupt requests disabled 0 ENABLED STS[RF] CPU interrupt requests enabled 0x1 REIE Reload Error Interrupt Enable 13 1 read-write DISABLED STS[REF] CPU interrupt requests disabled 0 ENABLED STS[REF] CPU interrupt requests enabled 0x1 SMDMAEN DMA Enable Register 0x28 16 read-write 0 0xFFFF CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write DISABLED Read DMA requests disabled. 0 EXCEEDFIFO Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. 0x1 LOCAL_SYNC A local sync (VAL1 matches counter) sets the read DMA request. 0x2 LOCAL_RELOAD A local reload (STS[RF] being set) sets the read DMA request. 0x3 FAND FIFO Watermark AND Control 8 1 read-write OR Selected FIFO watermarks are OR'ed together. 0 AND Selected FIFO watermarks are AND'ed together. 0x1 VALDE Value Registers DMA Enable 9 1 read-write DISABLED DMA write requests disabled 0 ENABLED Enabled 0x1 SMTCTRL Output Trigger Control Register 0x2A 16 read-write 0 0xFFFF OUT_TRIG_EN Output Trigger Enables 0 6 read-write VAL0 PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value. #xxxxx1 TRGFRQ Trigger frequency 12 1 read-write EVERYPWM Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 0 FINALPWM Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 0x1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write PWM_OUT_TRIG1_SIGNAL Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. 0 PWMB_OUTPUT Route the PWMB output to the PWM_OUT_TRIG1 port. 0x1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write PWM_OUT_TRIG0_SIGNAL Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. 0 PWMA_OUTPUT Route the PWMA output to the PWM_OUT_TRIG0 port. 0x1 SMDISMAP0 Fault Disable Mapping Register 0 0x2C 16 read-write 0xFFFF 0xFFFF DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SMDTCNT0 Deadtime Count Register 0 0x30 16 read-write 0x7FF 0xFFFF DTCNT0 DTCNT0 0 16 read-write SMDTCNT1 Deadtime Count Register 1 0x32 16 read-write 0x7FF 0xFFFF DTCNT1 DTCNT1 0 16 read-write SMCAPTCTRLA Capture Control A Register 0x34 16 read-write 0 0xFFFF ARMA Arm A 0 1 read-write DISABLED Input capture operation is disabled. 0 ENABLED Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. 0x1 ONESHOTA One Shot Mode A 1 1 read-write FREE_RUNNING Free Running 0 ONE_SHOT One Shot 0x1 EDGA0 Edge A 0 2 2 read-write DISABLED Disabled 0 FALLING_EDGE Capture falling edges 0x1 RISING_EDGE Capture rising edges 0x2 ANY_EDGE Capture any edge 0x3 EDGA1 Edge A 1 4 2 read-write DISABLED Disabled 0 FALLING_EDGE Capture falling edges 0x1 RISING_EDGE Capture rising edges 0x2 ANY_EDGE Capture any edge 0x3 INP_SELA Input Select A 6 1 read-write PWM_A Raw PWM_A input signal selected as source. 0 EDGE_COUNTER Edge Counter 0x1 EDGCNTA_EN Edge Counter A Enable 7 1 read-write DISABLED Edge counter disabled and held in reset 0 ENABLED Edge counter enabled 0x1 CFAWM Capture A FIFOs Water Mark 8 2 read-write CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only SMCAPTCOMPA Capture Compare A Register 0x36 16 read-write 0 0xFFFF EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SMCAPTCTRLB Capture Control B Register 0x38 16 read-write 0 0xFFFF ARMB Arm B 0 1 read-write DISABLED Input capture operation is disabled. 0 ENABLED Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. 0x1 ONESHOTB One Shot Mode B 1 1 read-write FREE_RUNNING Free Running 0 ONE_SHOT One Shot 0x1 EDGB0 Edge B 0 2 2 read-write DISABLED Disabled 0 FALLING_EDGE Capture falling edges 0x1 RISING_EDGE Capture rising edges 0x2 ANY_EDGE Capture any edge 0x3 EDGB1 Edge B 1 4 2 read-write DISABLED Disabled 0 FALLING_EDGE Capture falling edges 0x1 RISING_EDGE Capture rising edges 0x2 ANY_EDGE Capture any edge 0x3 INP_SELB Input Select B 6 1 read-write PWM_B Raw PWM_B input signal selected as source. 0 EDGE_COUNTER Edge Counter 0x1 EDGCNTB_EN Edge Counter B Enable 7 1 read-write DISABLED Edge counter disabled and held in reset 0 ENABLED Edge counter enabled 0x1 CFBWM Capture B FIFOs Water Mark 8 2 read-write CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only SMCAPTCOMPB Capture Compare B Register 0x3A 16 read-write 0 0xFFFF EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SMCAPTCTRLX Capture Control X Register 0x3C 16 read-write 0 0xFFFF ARMX Arm X 0 1 read-write DISABLED Input capture operation is disabled. 0 ENABLED Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. 0x1 ONESHOTX One Shot Mode Aux 1 1 read-write FREE_RUNNING Free Running 0 ONE_SHOT One Shot 0x1 EDGX0 Edge X 0 2 2 read-write DISABLED Disabled 0 FALLING_EDGE Capture falling edges 0x1 RISING_EDGE Capture rising edges 0x2 ANY_EDGE Capture any edge 0x3 EDGX1 Edge X 1 4 2 read-write DISABLED Disabled 0 FALLING_EDGE Capture falling edges 0x1 RISING_EDGE Capture rising edges 0x2 ANY_EDGE Capture any edge 0x3 INP_SELX Input Select X 6 1 read-write PWM_X Raw PWM_X input signal selected as source. 0 EDGE_COUNTER Edge Counter 0x1 EDGCNTX_EN Edge Counter X Enable 7 1 read-write DISABLED Edge counter disabled and held in reset 0 ENABLED Edge counter enabled 0x1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only SMCAPTCOMPX Capture Compare X Register 0x3E 16 read-write 0 0xFFFF EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SMCVAL0 Capture Value 0 Register 0x40 16 read-only 0 0xFFFF CAPTVAL0 CAPTVAL0 0 16 read-only SMCVAL0CYC Capture Value 0 Cycle Register 0x42 16 read-only 0 0xFFFF CVAL0CYC CVAL0CYC 0 4 read-only SMCVAL1 Capture Value 1 Register 0x44 16 read-only 0 0xFFFF CAPTVAL1 CAPTVAL1 0 16 read-only SMCVAL1CYC Capture Value 1 Cycle Register 0x46 16 read-only 0 0xFFFF CVAL1CYC CVAL1CYC 0 4 read-only SMCVAL2 Capture Value 2 Register 0x48 16 read-only 0 0xFFFF CAPTVAL2 CAPTVAL2 0 16 read-only SMCVAL2CYC Capture Value 2 Cycle Register 0x4A 16 read-only 0 0xFFFF CVAL2CYC CVAL2CYC 0 4 read-only SMCVAL3 Capture Value 3 Register 0x4C 16 read-only 0 0xFFFF CAPTVAL3 CAPTVAL3 0 16 read-only SMCVAL3CYC Capture Value 3 Cycle Register 0x4E 16 read-only 0 0xFFFF CVAL3CYC CVAL3CYC 0 4 read-only SMCVAL4 Capture Value 4 Register 0x50 16 read-only 0 0xFFFF CAPTVAL4 CAPTVAL4 0 16 read-only SMCVAL4CYC Capture Value 4 Cycle Register 0x52 16 read-only 0 0xFFFF CVAL4CYC CVAL4CYC 0 4 read-only SMCVAL5 Capture Value 5 Register 0x54 16 read-only 0 0xFFFF CAPTVAL5 CAPTVAL5 0 16 read-only SMCVAL5CYC Capture Value 5 Cycle Register 0x56 16 read-only 0 0xFFFF CVAL5CYC CVAL5CYC 0 4 read-only OUTEN Output Enable Register 0x180 16 read-write 0 0xFFFF PWMX_EN PWM_X Output Enables 0 4 read-write DISABLED PWM_X output disabled. 0 ENABLED PWM_X output enabled. 0x1 PWMB_EN PWM_B Output Enables 4 4 read-write DISABLED PWM_B output disabled. 0 ENABLED PWM_B output enabled. 0x1 PWMA_EN PWM_A Output Enables 8 4 read-write DISABLED PWM_A output disabled. 0 ENABLED PWM_A output enabled. 0x1 MASK Mask Register 0x182 16 read-write 0 0xFFFF MASKX PWM_X Masks 0 4 read-write NORMAL PWM_X output normal. 0 MASKED PWM_X output masked. 0x1 MASKB PWM_B Masks 4 4 read-write NORMAL PWM_B output normal. 0 MASKED PWM_B output masked. 0x1 MASKA PWM_A Masks 8 4 read-write NORMAL PWM_A output normal. 0 MASKED PWM_A output masked. 0x1 SWCOUT Software Controlled Output Register 0x184 16 read-write 0 0xFFFF SM0OUT45 Submodule 0 Software Controlled Output 45 0 1 read-write LOGIC_0 A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. 0 LOGIC_1 A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. 0x1 SM0OUT23 Submodule 0 Software Controlled Output 23 1 1 read-write LOGIC_0 A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. 0 LOGIC_1 A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. 0x1 SM1OUT45 Submodule 1 Software Controlled Output 45 2 1 read-write LOGIC_0 A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. 0 LOGIC_1 A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. 0x1 SM1OUT23 Submodule 1 Software Controlled Output 23 3 1 read-write LOGIC_0 A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. 0 LOGIC_1 A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. 0x1 SM2OUT45 Submodule 2 Software Controlled Output 45 4 1 read-write LOGIC_0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. 0 LOGIC_1 A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. 0x1 SM2OUT23 Submodule 2 Software Controlled Output 23 5 1 read-write LOGIC_0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. 0 LOGIC_1 A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. 0x1 SM3OUT45 Submodule 3 Software Controlled Output 45 6 1 read-write LOGIC_0 A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. 0 LOGIC_1 A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. 0x1 SM3OUT23 Submodule 3 Software Controlled Output 23 7 1 read-write LOGIC_0 A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. 0 LOGIC_1 A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. 0x1 DTSRCSEL PWM Source Select Register 0x186 16 read-write 0 0xFFFF SM0SEL45 Submodule 0 PWM45 Control Select 0 2 read-write SM0PWM45 Generated SM0PWM45 signal is used by the deadtime logic. 0 INVERTED_SM0PWM45 Inverted generated SM0PWM45 signal is used by the deadtime logic. 0x1 SM0OUT45 SWCOUT[SM0OUT45] is used by the deadtime logic. 0x2 PWM0_EXTB PWM0_EXTB signal is used by the deadtime logic. 0x3 SM0SEL23 Submodule 0 PWM23 Control Select 2 2 read-write SM0PWM23 Generated SM0PWM23 signal is used by the deadtime logic. 0 INVERTED_SM0PWM23 Inverted generated SM0PWM23 signal is used by the deadtime logic. 0x1 SM0OUT23 SWCOUT[SM0OUT23] is used by the deadtime logic. 0x2 PWM0_EXTA PWM0_EXTA signal is used by the deadtime logic. 0x3 SM1SEL45 Submodule 1 PWM45 Control Select 4 2 read-write SM1PWM45 Generated SM1PWM45 signal is used by the deadtime logic. 0 INVERTED_SM1PWM45 Inverted generated SM1PWM45 signal is used by the deadtime logic. 0x1 SM1OUT45 SWCOUT[SM1OUT45] is used by the deadtime logic. 0x2 PWM1_EXTB PWM1_EXTB signal is used by the deadtime logic. 0x3 SM1SEL23 Submodule 1 PWM23 Control Select 6 2 read-write SM1PWM23 Generated SM1PWM23 signal is used by the deadtime logic. 0 INVERTED_SM1PWM23 Inverted generated SM1PWM23 signal is used by the deadtime logic. 0x1 SM1OUT23 SWCOUT[SM1OUT23] is used by the deadtime logic. 0x2 PWM1_EXTA PWM1_EXTA signal is used by the deadtime logic. 0x3 SM2SEL45 Submodule 2 PWM45 Control Select 8 2 read-write SM2PWM45 Generated SM2PWM45 signal is used by the deadtime logic. 0 INVERTED_SM2PWM45 Inverted generated SM2PWM45 signal is used by the deadtime logic. 0x1 SM2OUT45 SWCOUT[SM2OUT45] is used by the deadtime logic. 0x2 PWM2_EXTB PWM2_EXTB signal is used by the deadtime logic. 0x3 SM2SEL23 Submodule 2 PWM23 Control Select 10 2 read-write SM2PWM23 Generated SM2PWM23 signal is used by the deadtime logic. 0 INVERTED_SM2PWM23 Inverted generated SM2PWM23 signal is used by the deadtime logic. 0x1 SM2OUT23 SWCOUT[SM2OUT23] is used by the deadtime logic. 0x2 PWM2_EXTA PWM2_EXTA signal is used by the deadtime logic. 0x3 SM3SEL45 Submodule 3 PWM45 Control Select 12 2 read-write SM3PWM45 Generated SM3PWM45 signal is used by the deadtime logic. 0 INVERTED_SM3PWM45 Inverted generated SM3PWM45 signal is used by the deadtime logic. 0x1 SM3OUT45 SWCOUT[SM3OUT45] is used by the deadtime logic. 0x2 PWM3_EXTB PWM3_EXTB signal is used by the deadtime logic. 0x3 SM3SEL23 Submodule 3 PWM23 Control Select 14 2 read-write SM3PWM23 Generated SM3PWM23 signal is used by the deadtime logic. 0 INVERTED_SM3PWM23 Inverted generated SM3PWM23 signal is used by the deadtime logic. 0x1 SM3OUT23 SWCOUT[SM3OUT23] is used by the deadtime logic. 0x2 PWM3_EXTA PWM3_EXTA signal is used by the deadtime logic. 0x3 MCTRL Master Control Register 0x188 16 read-write 0 0xFFFF LDOK Load Okay 0 4 read-write DISABLED Do not load new values. 0 ENABLED Load prescaler, modulus, and PWM values of the corresponding submodule. 0x1 CLDOK Clear Load Okay 4 4 read-write RUN Run 8 4 read-write DISABLED PWM counter is stopped, but PWM outputs will hold the current state. 0 ENABLED PWM counter is started in the corresponding submodule. 0x1 IPOL Current Polarity 12 4 read-write PWM23 PWM23 is used to generate complementary PWM pair in the corresponding submodule. 0 PWM45 PWM45 is used to generate complementary PWM pair in the corresponding submodule. 0x1 MCTRL2 Master Control 2 Register 0x18A 16 read-write 0 0xFFFF MONPLL Monitor PLL State 0 2 read-write NOTLOCKED_DO_NOT_MON_PLL Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. 0 NOTLOCKED_MON_PLL Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. 0x1 LOCKED_DO_NOT_MON_PLL Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. 0x2 LOCKED_MON_PLL Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. 0x3 FCTRL0 Fault Control Register 0x18C 16 read-write 0 0xFFFF FIE Fault Interrupt Enables 0 4 read-write DISABLED FAULTx CPU interrupt requests disabled. 0 ENABLED FAULTx CPU interrupt requests enabled. 0x1 FSAFE Fault Safety Mode 4 4 read-write NORMAL Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). 0 SAFE Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. 0x1 FAUTO Automatic Fault Clearing 8 4 read-write MANUAL Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL[FSAFE]. 0 AUTOMATIC Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. 0x1 FLVL Fault Level 12 4 read-write LOGIC_0 A logic 0 on the fault input indicates a fault condition. 0 LOGIC_1 A logic 1 on the fault input indicates a fault condition. 0x1 FSTS0 Fault Status Register 0x18E 16 read-write 0 0xFFFF FFLAG Fault Flags 0 4 read-write NO_FLAG No fault on the FAULTx pin. 0 FLAG Fault on the FAULTx pin. 0x1 FFULL Full Cycle 4 4 read-write PWM_OUTPUTS_NOT_REENABLED PWM outputs are not re-enabled at the start of a full cycle 0 PWM_OUTPUTS_REENABLED PWM outputs are re-enabled at the start of a full cycle 0x1 FFPIN Filtered Fault Pins 8 4 read-only FHALF Half Cycle Fault Recovery 12 4 read-write PWM_OUTPUTS_NOT_REENABLED PWM outputs are not re-enabled at the start of a half cycle. 0 PWM_OUTPUTS_REENABLED PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). 0x1 FFILT0 Fault Filter Register 0x190 16 read-write 0 0xFFFF FILT_PER Fault Filter Period 0 8 read-write FILT_CNT Fault Filter Count 8 3 read-write GSTR Fault Glitch Stretch Enable 15 1 read-write DISABLED Fault input glitch stretching is disabled. 0 ENABLED Input fault signals will be stretched to at least 2 IPBus clock cycles. 0x1 FTST0 Fault Test Register 0x192 16 read-write 0 0xFFFF FTEST Fault Test 0 1 read-write NO_FAULT No fault 0 FAULT Cause a simulated fault 0x1 FCTRL20 Fault Control 2 Register 0x194 16 read-write 0 0xFFFF NOCOMB No Combinational Path From Fault Input To PWM Output 0 4 read-write ENABLED There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. 0 DISABLED The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. 0x1 PWM2 PWM PWM 0x40190000 0 0x196 registers PWM2_0 177 PWM2_1 178 PWM2_2 179 PWM2_3 180 PWM2_FAULT 181 PWM3 PWM PWM 0x40194000 0 0x196 registers PWM3_0 182 PWM3_1 183 PWM3_2 184 PWM3_3 185 PWM3_FAULT 186 PWM4 PWM PWM 0x40198000 0 0x196 registers PWM4_0 187 PWM4_1 188 PWM4_2 189 PWM4_3 190 PWM4_FAULT 191 CMP1 CMP CMP CMP 0x401A4000 0 0x18 registers ACMP1 157 VERID Version ID Register 0 32 read-only 0x1000000 0xFFFFFFFF FEATURE Feature Specification Number. This read only filed returns the feature set number. 0 16 read-only MINOR Minor Version Number. This read only field returns the minor version number for the module specification. 16 8 read-only MAJOR Major Version Number. This read only field returns the major version number for the module specification. 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0 0xFFFFFFFF PARAM Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register. 0 32 read-only C0 CMP Control Register 0 0x8 32 read-write 0 0xFFFFFFFF HYSTCTR Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level 0 2 read-write HYSTCTR_0 The hard block output has level 0 hysteresis internally. 0 HYSTCTR_1 The hard block output has level 1 hysteresis internally. 0x1 HYSTCTR_2 The hard block output has level 2 hysteresis internally. 0x2 HYSTCTR_3 The hard block output has level 3 hysteresis internally. 0x3 FILTER_CNT Filter Sample Count 4 3 read-write FILTER_CNT_0 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. 0 FILTER_CNT_1 1 consecutive sample must agree (comparator output is simply sampled). 0x1 FILTER_CNT_2 2 consecutive samples must agree. 0x2 FILTER_CNT_3 3 consecutive samples must agree. 0x3 FILTER_CNT_4 4 consecutive samples must agree. 0x4 FILTER_CNT_5 5 consecutive samples must agree. 0x5 FILTER_CNT_6 6 consecutive samples must agree. 0x6 FILTER_CNT_7 7 consecutive samples must agree. 0x7 EN Comparator Module Enable 8 1 read-write EN_0 Analog Comparator is disabled. 0 EN_1 Analog Comparator is enabled. 0x1 OPE Comparator Output Pin Enable 9 1 read-write OPE_0 When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. 0 OPE_1 When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin. 0x1 COS Comparator Output Select 10 1 read-write COS_0 Set CMPO to equal COUT (filtered comparator output). 0 COS_1 Set CMPO to equal COUTA (unfiltered comparator output). 0x1 INVT Comparator invert 11 1 read-write INVT_0 Does not invert the comparator output. 0 INVT_1 Inverts the comparator output. 0x1 PMODE Power Mode Select 12 1 read-write PMODE_0 Low Speed (LS) comparison mode is selected. 0 PMODE_1 High Speed (HS) comparison mode is selected. 0x1 WE Windowing Enable 14 1 read-write WE_0 Windowing mode is not selected. 0 WE_1 Windowing mode is selected. 0x1 SE Sample Enable 15 1 read-write SE_0 Sampling mode is not selected. 0 SE_1 Sampling mode is selected. 0x1 FPR Filter Sample Period 16 8 read-write COUT Analog Comparator Output 24 1 read-only CFF Analog Comparator Flag Falling 25 1 read-write oneToClear CFF_0 A falling edge has not been detected on COUT. 0 CFF_1 A falling edge on COUT has occurred. 0x1 CFR Analog Comparator Flag Rising 26 1 read-write oneToClear CFR_0 A rising edge has not been detected on COUT. 0 CFR_1 A rising edge on COUT has occurred. 0x1 IEF Comparator Interrupt Enable Falling 27 1 read-write IEF_0 Interrupt is disabled. 0 IEF_1 Interrupt is enabled. 0x1 IER Comparator Interrupt Enable Rising 28 1 read-write IER_0 Interrupt is disabled. 0 IER_1 Interrupt is enabled. 0x1 DMAEN DMA Enable 30 1 read-write DMAEN_0 DMA is disabled. 0 DMAEN_1 DMA is enabled. 0x1 LINKEN CMP to DAC link enable. 31 1 read-write LINKEN_0 CMP to DAC link is disabled 0 LINKEN_1 CMP to DAC link is enabled. 0x1 C1 CMP Control Register 1 0xC 32 read-write 0 0xFFFFFFFF VOSEL DAC Output Voltage Select 0 8 read-write DMODE DAC Mode Selection 8 1 read-write DMODE_0 DAC is selected to work in low speed and low power mode. 0 DMODE_1 DAC is selected to work in high speed high power mode. 0x1 VRSEL Supply Voltage Reference Source Select 9 1 read-write VRSEL_0 Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC. 0 VRSEL_1 Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD. 0x1 DACEN DAC Enable 10 1 read-write DACEN_0 DAC is disabled. 0 DACEN_1 DAC is enabled. 0x1 CHN0 Channel 0 input enable 16 1 read-write CHN1 Channel 1 input enable 17 1 read-write CHN2 Channel 2 input enable 18 1 read-write CHN3 Channel 3 input enable 19 1 read-write CHN4 Channel 4 input enable 20 1 read-write CHN5 Channel 5 input enable 21 1 read-write MSEL Minus Input MUX Control 24 3 read-write MSEL_0 Internal Negative Input 0 for Minus Channel -- Internal Minus Input 0 MSEL_1 External Input 1 for Minus Channel -- Reference Input 0 0x1 MSEL_2 External Input 2 for Minus Channel -- Reference Input 1 0x2 MSEL_3 External Input 3 for Minus Channel -- Reference Input 2 0x3 MSEL_4 External Input 4 for Minus Channel -- Reference Input 3 0x4 MSEL_5 External Input 5 for Minus Channel -- Reference Input 4 0x5 MSEL_6 External Input 6 for Minus Channel -- Reference Input 5 0x6 MSEL_7 Internal 8b DAC output 0x7 PSEL Plus Input MUX Control 28 3 read-write PSEL_0 Internal Positive Input 0 for Plus Channel -- Internal Plus Input 0 PSEL_1 External Input 1 for Plus Channel -- Reference Input 0 0x1 PSEL_2 External Input 2 for Plus Channel -- Reference Input 1 0x2 PSEL_3 External Input 3 for Plus Channel -- Reference Input 2 0x3 PSEL_4 External Input 4 for Plus Channel -- Reference Input 3 0x4 PSEL_5 External Input 5 for Plus Channel -- Reference Input 4 0x5 PSEL_6 External Input 6 for Plus Channel -- Reference Input 5 0x6 PSEL_7 Internal 8b DAC output 0x7 C2 CMP Control Register 2 0x10 32 read-write 0 0xFFFFFFFF ACOn ACOn 0 6 read-write INITMOD Comparator and DAC initialization delay modulus. 8 6 read-write NSAM Number of sample clocks 14 2 read-write NSAM_0 The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. 0 NSAM_1 The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock. 0x1 NSAM_2 The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock. 0x2 NSAM_3 The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock. 0x3 CH0F CH0F 16 1 read-write oneToClear CH1F CH1F 17 1 read-write oneToClear CH2F CH2F 18 1 read-write oneToClear CH3F CH3F 19 1 read-write oneToClear CH4F CH4F 20 1 read-write oneToClear CH5F CH5F 21 1 read-write oneToClear FXMXCH Fixed channel selection 25 3 read-write FXMXCH_0 External Reference Input 0 is selected as the fixed reference input for the fixed mux port. 0 FXMXCH_1 External Reference Input 1 is selected as the fixed reference input for the fixed mux port. 0x1 FXMXCH_2 External Reference Input 2 is selected as the fixed reference input for the fixed mux port. 0x2 FXMXCH_3 External Reference Input 3 is selected as the fixed reference input for the fixed mux port. 0x3 FXMXCH_4 External Reference Input 4 is selected as the fixed reference input for the fixed mux port. 0x4 FXMXCH_5 External Reference Input 5 is selected as the fixed reference input for the fixed mux port. 0x5 FXMXCH_7 The 8bit DAC is selected as the fixed reference input for the fixed mux port. 0x7 FXMP Fixed MUX Port 29 1 read-write FXMP_0 The Plus port is fixed. Only the inputs to the Minus port are swept in each round. 0 FXMP_1 The Minus port is fixed. Only the inputs to the Plus port are swept in each round. 0x1 RRIE Round-Robin interrupt enable 30 1 read-write RRIE_0 The round-robin interrupt is disabled. 0 RRIE_1 The round-robin interrupt is enabled when a comparison result changes from the last sample. 0x1 C3 CMP Control Register 3 0x14 32 read-write 0x11000000 0xFFFFFFFF ACPH2TC Analog Comparator Phase2 Timing Control. 4 3 read-write ACPH2TC_0 Phase2 active time in one sampling period equals to T 0 ACPH2TC_1 Phase2 active time in one sampling period equals to 2*T 0x1 ACPH2TC_2 Phase2 active time in one sampling period equals to 4*T 0x2 ACPH2TC_3 Phase2 active time in one sampling period equals to 8*T 0x3 ACPH2TC_4 Phase2 active time in one sampling period equals to 16*T 0x4 ACPH2TC_5 Phase2 active time in one sampling period equals to 32*T 0x5 ACPH2TC_6 Phase2 active time in one sampling period equals to 64*T 0x6 ACPH2TC_7 Phase2 active time in one sampling period equals to 16*T 0x7 ACPH1TC Analog Comparator Phase1 Timing Control. 8 3 read-write ACPH1TC_0 Phase1 active time in one sampling period equals to T 0 ACPH1TC_1 Phase1 active time in one sampling period equals to 2*T 0x1 ACPH1TC_2 Phase1 active time in one sampling period equals to 4*T 0x2 ACPH1TC_3 Phase1 active time in one sampling period equals to 8*T 0x3 ACPH1TC_4 Phase1 active time in one sampling period equals to T 0x4 ACPH1TC_5 Phase1 active time in one sampling period equals to T 0x5 ACPH1TC_6 Phase1 active time in one sampling period equals to T 0x6 ACPH1TC_7 Phase1 active time in one sampling period equals to 0 0x7 ACSAT Analog Comparator Sampling Time control. 12 3 read-write ACSAT_0 The sampling time equals to T 0 ACSAT_1 The sampling time equasl to 2*T 0x1 ACSAT_2 The sampling time equasl to 4*T 0x2 ACSAT_3 The sampling time equasl to 8*T 0x3 ACSAT_4 The sampling time equasl to 16*T 0x4 ACSAT_5 The sampling time equasl to 32*T 0x5 ACSAT_6 The sampling time equasl to 64*T 0x6 ACSAT_7 The sampling time equasl to 256*T 0x7 DMCS Discrete Mode Clock Selection 16 1 read-write DMCS_0 Slow clock is selected for the timing generation. 0 DMCS_1 Fast clock is selected for the timing generation. 0x1 RDIVE Resistor Divider Enable 20 1 read-write RDIVE_0 The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v. 0 RDIVE_1 The resistor is enabled because the inputs are above 1.8v. 0x1 NCHCTEN Negative Channel Continuous Mode Enable. 24 1 read-write NCHCTEN_0 Negative channel is in Discrete Mode and special timing needs to be configured. 0 NCHCTEN_1 Negative channel is in Continuous Mode and no special timing is requried. 0x1 PCHCTEN Positive Channel Continuous Mode Enable. 28 1 read-write PCHCTEN_0 Positive channel is in Discrete Mode and special timing needs to be configured. 0 PCHCTEN_1 Positive channel is in Continuous Mode and no special timing is requried. 0x1 CMP2 CMP CMP 0x401A8000 0 0x18 registers ACMP2 158 CMP3 CMP CMP 0x401AC000 0 0x18 registers ACMP3 159 CMP4 CMP CMP 0x401B0000 0 0x18 registers ACMP4 160 SPDIF SPDIF SPDIF 0x40400000 0 0x54 registers SPDIF 82 SCR SPDIF Configuration Register 0 32 read-write 0x400 0xFFFFFFFF USrc_Sel USrc_Sel 0 2 read-write none No embedded U channel 0 spdif_rxblock U channel from SPDIF receive block (CD mode) 0x1 chip_transmit U channel from on chip transmitter 0x3 TxSel TxSel 2 3 read-write off_out0 Off and output 0 0 feedthru Feed-through SPDIFIN 0x1 normal_op Tx Normal operation 0x5 ValCtrl ValCtrl 5 1 read-write always_set Outgoing Validity always set 0 always_clear Outgoing Validity always clear 0x1 InputSrcSel InputSrcSel 6 2 read-write spdif_in SPDIF_IN 0 none_sel None 0x1 none_sel None 0x2 none_sel None 0x3 DMA_TX_En DMA_TX_En 8 1 read-write DMA_Rx_En DMA_Rx_En 9 1 read-write TxFIFO_Ctrl TxFIFO_Ctrl 10 2 read-write send_zero Send out digital zero on SPDIF Tx 0 normal Tx Normal operation 0x1 reset_one Reset to 1 sample remaining 0x2 soft_reset soft_reset 12 1 read-write LOW_POWER LOW_POWER 13 1 read-write TxFIFOEmpty_Sel TxFIFOEmpty_Sel 15 2 read-write empty_int_0 Empty interrupt if 0 sample in Tx left and right FIFOs 0 empty_int_4 Empty interrupt if at most 4 sample in Tx left and right FIFOs 0x1 empty_int_8 Empty interrupt if at most 8 sample in Tx left and right FIFOs 0x2 empty_int_12 Empty interrupt if at most 12 sample in Tx left and right FIFOs 0x3 TxAutoSync TxAutoSync 17 1 read-write off Tx FIFO auto sync off 0 on Tx FIFO auto sync on 0x1 RxAutoSync RxAutoSync 18 1 read-write off Rx FIFO auto sync off 0 on RxFIFO auto sync on 0x1 RxFIFOFull_Sel RxFIFOFull_Sel 19 2 read-write full_int_1 Full interrupt if at least 1 sample in Rx left and right FIFOs 0 full_int_4 Full interrupt if at least 4 sample in Rx left and right FIFOs 0x1 full_int_8 Full interrupt if at least 8 sample in Rx left and right FIFOs 0x2 full_int_16 Full interrupt if at least 16 sample in Rx left and right FIFO 0x3 RxFIFO_Rst RxFIFO_Rst 21 1 read-write normal Normal operation 0 reset_one Reset register to 1 sample remaining 0x1 RxFIFO_Off_On RxFIFO_Off_On 22 1 read-write on_0 SPDIF Rx FIFO is on 0 off_1 SPDIF Rx FIFO is off. Does not accept data from interface 0x1 RxFIFO_Ctrl RxFIFO_Ctrl 23 1 read-write normal Normal operation 0 always_zero Always read zero from Rx data register 0x1 SRCD CDText Control Register 0x4 32 read-write 0 0xFFFFFFFF USyncMode USyncMode 1 1 read-write non_cddata Non-CD data 0 cduser_chsubcode CD user channel subcode 0x1 SRPC PhaseConfig Register 0x8 32 read-write 0 0xFFFFFFFF GainSel GainSel 3 3 read-write gainsel_0b000 24*(2**10) 0 gainsel_0b001 16*(2**10) 0x1 gainsel_0b010 12*(2**10) 0x2 gainsel_0b011 8*(2**10) 0x3 gainsel_0b100 6*(2**10) 0x4 gainsel_0b101 4*(2**10) 0x5 gainsel_0b110 3*(2**10) 0x6 LOCK LOCK 6 1 read-only ClkSrc_Sel ClkSrc_Sel 7 4 read-write clksrc_0b0000 if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) 0 clksrc_0b0001 if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) 0x1 clksrc_0b0011 if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK 0x3 clksrc_0b0101 REF_CLK_32K (XTALOSC) 0x5 clksrc_0b0110 tx_clk (SPDIF0_CLK_ROOT) 0x6 clksrc_0b1000 SPDIF_EXT_CLK 0x8 SIE InterruptEn Register 0xC 32 read-write 0 0xFFFFFFFF RxFIFOFul RxFIFOFul 0 1 read-write TxEm TxEm 1 1 read-write LockLoss LockLoss 2 1 read-write RxFIFOResyn RxFIFOResyn 3 1 read-write RxFIFOUnOv RxFIFOUnOv 4 1 read-write UQErr UQErr 5 1 read-write UQSync UQSync 6 1 read-write QRxOv QRxOv 7 1 read-write QRxFul QRxFul 8 1 read-write URxOv URxOv 9 1 read-write URxFul URxFul 10 1 read-write BitErr BitErr 14 1 read-write SymErr SymErr 15 1 read-write ValNoGood ValNoGood 16 1 read-write CNew CNew 17 1 read-write TxResyn TxResyn 18 1 read-write TxUnOv TxUnOv 19 1 read-write Lock Lock 20 1 read-write SIC InterruptClear Register SIC_SIS 0x10 32 write-only 0 0xFFFFFFFF LockLoss LockLoss 2 1 write-only RxFIFOResyn RxFIFOResyn 3 1 write-only RxFIFOUnOv RxFIFOUnOv 4 1 write-only UQErr UQErr 5 1 write-only UQSync UQSync 6 1 write-only QRxOv QRxOv 7 1 write-only URxOv URxOv 9 1 write-only BitErr BitErr 14 1 write-only SymErr SymErr 15 1 write-only ValNoGood ValNoGood 16 1 write-only CNew CNew 17 1 write-only TxResyn TxResyn 18 1 write-only TxUnOv TxUnOv 19 1 write-only Lock Lock 20 1 write-only SIS InterruptStat Register SIC_SIS 0x10 32 read-only 0x2 0xFFFFFFFF RxFIFOFul RxFIFOFul 0 1 read-only TxEm TxEm 1 1 read-only LockLoss LockLoss 2 1 read-only RxFIFOResyn RxFIFOResyn 3 1 read-only RxFIFOUnOv RxFIFOUnOv 4 1 read-only UQErr UQErr 5 1 read-only UQSync UQSync 6 1 read-only QRxOv QRxOv 7 1 read-only QRxFul QRxFul 8 1 read-only URxOv URxOv 9 1 read-only URxFul URxFul 10 1 read-only BitErr BitErr 14 1 read-only SymErr SymErr 15 1 read-only ValNoGood ValNoGood 16 1 read-only CNew CNew 17 1 read-only TxResyn TxResyn 18 1 read-only TxUnOv TxUnOv 19 1 read-only Lock Lock 20 1 read-only SRL SPDIFRxLeft Register 0x14 32 read-only 0 0xFFFFFFFF RxDataLeft RxDataLeft 0 24 read-only SRR SPDIFRxRight Register 0x18 32 read-only 0 0xFFFFFFFF RxDataRight RxDataRight 0 24 read-only SRCSH SPDIFRxCChannel_h Register 0x1C 32 read-only 0 0xFFFFFFFF RxCChannel_h RxCChannel_h 0 24 read-only SRCSL SPDIFRxCChannel_l Register 0x20 32 read-only 0 0xFFFFFFFF RxCChannel_l RxCChannel_l 0 24 read-only SRU UchannelRx Register 0x24 32 read-only 0 0xFFFFFFFF RxUChannel RxUChannel 0 24 read-only SRQ QchannelRx Register 0x28 32 read-only 0 0xFFFFFFFF RxQChannel RxQChannel 0 24 read-only STL SPDIFTxLeft Register 0x2C 32 write-only 0 0xFFFFFFFF TxDataLeft TxDataLeft 0 24 write-only STR SPDIFTxRight Register 0x30 32 write-only 0 0xFFFFFFFF TxDataRight TxDataRight 0 24 write-only STCSCH SPDIFTxCChannelCons_h Register 0x34 32 read-write 0 0xFFFFFFFF TxCChannelCons_h TxCChannelCons_h 0 24 read-write STCSCL SPDIFTxCChannelCons_l Register 0x38 32 read-write 0 0xFFFFFFFF TxCChannelCons_l TxCChannelCons_l 0 24 read-write SRFM FreqMeas Register 0x44 32 read-only 0 0xFFFFFFFF FreqMeas FreqMeas 0 24 read-only STC SPDIFTxClk Register 0x50 32 read-write 0x20F00 0xFFFFFFFF TxClk_DF TxClk_DF 0 7 read-write div1 divider factor is 1 0 div2 divider factor is 2 0x1 div128 divider factor is 128 0x7F tx_all_clk_en tx_all_clk_en 7 1 read-write disable disable transfer clock. 0 enable enable transfer clock. 0x1 TxClk_Source TxClk_Source 8 3 read-write txclk_src_0b000 REF_CLK_32K input (XTALOSC 32 kHz clock) 0 txclk_src_0b001 tx_clk input (from SPDIF0_CLK_ROOT. See clock control block for more information.) 0x1 txclk_src_0b011 SPDIF_EXT_CLK, from pads 0x3 txclk_src_0b101 ipg_clk input (frequency divided) 0x5 SYSCLK_DF SYSCLK_DF 11 9 read-write no_clk no clock signal 0 div2 divider factor is 2 0x1 div512 divider factor is 512 0x1FF SAI1 SAI SAI 0x40404000 0 0xE4 registers SAI1 76 VERID Version ID 0 32 read-only 0x3010000 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only STD Standard feature set. 0 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter 0x4 32 read-only 0x50504 0xFFFFFFFF DATALINE Number of Datalines 0 4 read-only FIFO FIFO Size 8 4 read-only FRAME Frame Size 16 4 read-only TCSR Transmit Control 0x8 32 read-write 0 0xFFFFFFFF FRDE FIFO Request DMA Enable 0 1 read-write DISABLE Disables the DMA request. 0 ENABLE Enables the DMA request. 0x1 FWDE FIFO Warning DMA Enable 1 1 read-write DISABLE Disables the DMA request. 0 ENABLE Enables the DMA request. 0x1 FRIE FIFO Request Interrupt Enable 8 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 FWIE FIFO Warning Interrupt Enable 9 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 FEIE FIFO Error Interrupt Enable 10 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 SEIE Sync Error Interrupt Enable 11 1 read-write DISABLE Disables interrupt. 0 ENABLE Enables interrupt. 0x1 WSIE Word Start Interrupt Enable 12 1 read-write DISABLE Disables interrupt. 0 ENABLE Enables interrupt. 0x1 FRF FIFO Request Flag 16 1 read-only NO_FLAG Transmit FIFO watermark has not been reached. 0 FLAG Transmit FIFO watermark has been reached. 0x1 FWF FIFO Warning Flag 17 1 read-only DISABLE No enabled transmit FIFO is empty. 0 ENABLE Enabled transmit FIFO is empty. 0x1 FEF FIFO Error Flag 18 1 read-write oneToClear NO_FLAG Transmit underrun not detected. 0 FLAG Transmit underrun detected. 0x1 SEF Sync Error Flag 19 1 read-write oneToClear NO_FLAG Sync error not detected. 0 FLAG Frame sync error detected. 0x1 WSF Word Start Flag 20 1 read-write oneToClear NO_FLAG Start of word not detected. 0 FLAG Start of word detected. 0x1 SR Software Reset 24 1 read-write DISABLE No effect. 0 ENABLE Software reset. 0x1 FR FIFO Reset 25 1 read-write NO_EFFECT No effect. 0 RESET FIFO reset. 0x1 BCE Bit Clock Enable 28 1 read-write DISABLE Transmit bit clock is disabled. 0 ENABLE Transmit bit clock is enabled. 0x1 DBGE Debug Enable 29 1 read-write DISABLE Transmitter is disabled in Debug mode, after completing the current frame. 0 ENABLE Transmitter is enabled in Debug mode. 0x1 STOPE Stop Enable 30 1 read-write DISABLE Transmitter disabled in Stop mode. 0 ENABLE Transmitter enabled in Stop mode. 0x1 TE Transmitter Enable 31 1 read-write DISABLE Transmitter is disabled. 0 ENABLE Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. 0x1 TCR1 Transmit Configuration 1 0xC 32 read-write 0 0xFFFFFFFF TFW Transmit FIFO Watermark 0 5 read-write TCR2 Transmit Configuration 2 0x10 32 read-write 0 0xFFFFFFFF DIV Bit Clock Divide 0 8 read-write BYP Bit Clock Bypass 23 1 read-write DISABLE Internal bit clock is generated from bit clock divider. 0 ENABLE Internal bit clock is divide by one of the audio master clock. 0x1 BCD Bit Clock Direction 24 1 read-write EXT_IN_SLAVE Bit clock is generated externally in Slave mode. 0 INT_IN_MASTER Bit clock is generated internally in Master mode. 0x1 BCP Bit Clock Polarity 25 1 read-write ACTIVE_HIGH Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0 ACTIVE_LOW Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. 0x1 MSEL MCLK Select 26 2 read-write BUS_CLOCK Bus Clock selected. 0 MCLK1 Master Clock (MCLK) 1 option selected. 0x1 MCLK2 Master Clock (MCLK) 2 option selected. 0x2 MCLK3 Master Clock (MCLK) 3 option selected. 0x3 BCI Bit Clock Input 28 1 read-write DISABLE No effect. 0 ENABLE Internal logic is clocked as if bit clock was externally generated. 0x1 BCS Bit Clock Swap 29 1 read-write DISABLE Use the normal bit clock source. 0 ENABLE Swap the bit clock source. 0x1 SYNC Synchronous Mode 30 1 read-write ASYNC Asynchronous mode. 0 SYNC_W_RX Synchronous with receiver. 0x1 TCR3 Transmit Configuration 3 0x14 32 read-write 0 0xFFFFFFFF WDFL Word Flag Configuration 0 5 read-write TCE Transmit Channel Enable 16 4 read-write CFR Channel FIFO Reset 24 4 read-write TCR4 Transmit Configuration 4 0x18 32 read-write 0 0xFFFFFFFF FSD Frame Sync Direction 0 1 read-write EXT_IN_SLAVE_MODE Frame sync is generated externally in Slave mode. 0 INT_IN_MASTER_MODE Frame sync is generated internally in Master mode. 0x1 FSP Frame Sync Polarity 1 1 read-write ACTIVE_HIGH Frame sync is active high. 0 ACTIVE_LOW Frame sync is active low. 0x1 ONDEM On Demand Mode 2 1 read-write CONTINUOUS_FRAME_SYNC Internal frame sync is generated continuously. 0 ON_DEMAND_FRAME_SYNC Internal frame sync is generated when the FIFO warning flag is clear. 0x1 FSE Frame Sync Early 3 1 read-write DISABLE Frame sync asserts with the first bit of the frame. 0 ENABLE Frame sync asserts one bit before the first bit of the frame. 0x1 MF MSB First 4 1 read-write DISABLE LSB is transmitted first. 0 ENABLE MSB is transmitted first. 0x1 CHMOD Channel Mode 5 1 read-write TDM_MODE TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. 0 OUTPUT_MODE Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. 0x1 SYWD Sync Width 8 5 read-write FRSZ Frame size 16 5 read-write FPACK FIFO Packing Mode 24 2 read-write DISABLED FIFO packing is disabled. 0 EIGHT_BIT_FIFO_PACKING 8-bit FIFO packing is enabled. 0x2 SIXTEEN_BIT_FIFO_PACKING 16-bit FIFO packing is enabled. 0x3 FCOMB FIFO Combine Mode 26 2 read-write DISABLED FIFO combine mode disabled. 0 ENABLED_ON_FIFO_READS FIFO combine mode enabled on FIFO reads (from transmit shift registers). 0x1 ENABLED_ON_FIFO_WRITES FIFO combine mode enabled on FIFO writes (by software). 0x2 ENABLED_ON_FIFO_READS_WRITES FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). 0x3 FCONT FIFO Continue on Error 28 1 read-write DISABLE On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0 ENABLE On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. 0x1 TCR5 Transmit Configuration 5 0x1C 32 read-write 0 0xFFFFFFFF FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write 4 0x4 TDR[%s] Transmit Data 0x20 32 read-write 0 0xFFFFFFFF TDR Transmit Data Register 0 32 read-write 4 0x4 TFR[%s] Transmit FIFO 0x40 32 read-only 0 0xFFFFFFFF RFP Read FIFO Pointer 0 6 read-only WFP Write FIFO Pointer 16 6 read-only WCP Write Channel Pointer 31 1 read-only DISABLE No effect. 0 ENABLE FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. 0x1 TMR Transmit Mask 0x60 32 read-write 0 0xFFFFFFFF TWM Transmit Word Mask 0 32 read-write WORD_N_ENABLED Word N is enabled. 0 WORD_N_MASKED Word N is masked. The transmit data pins are tri-stated or drive zero when masked. 0x1 RCSR Receive Control 0x88 32 read-write 0 0xFFFFFFFF FRDE FIFO Request DMA Enable 0 1 read-write DISABLE Disables the DMA request. 0 ENABLE Enables the DMA request. 0x1 FWDE FIFO Warning DMA Enable 1 1 read-write DISABLE Disables the DMA request. 0 ENABLE Enables the DMA request. 0x1 FRIE FIFO Request Interrupt Enable 8 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 FWIE FIFO Warning Interrupt Enable 9 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 FEIE FIFO Error Interrupt Enable 10 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 SEIE Sync Error Interrupt Enable 11 1 read-write DISABLE Disables interrupt. 0 ENABLE Enables interrupt. 0x1 WSIE Word Start Interrupt Enable 12 1 read-write DISABLE Disables interrupt. 0 ENABLE Enables interrupt. 0x1 FRF FIFO Request Flag 16 1 read-only BELOW_WATERMARK Receive FIFO watermark not reached. 0 WATERMARK_REACHED Receive FIFO watermark has been reached. 0x1 FWF FIFO Warning Flag 17 1 read-only NOT_FULL No enabled receive FIFO is full. 0 FULL Enabled receive FIFO is full. 0x1 FEF FIFO Error Flag 18 1 read-write oneToClear NO_FLAG Receive overflow not detected. 0 FLAG Receive overflow detected. 0x1 SEF Sync Error Flag 19 1 read-write oneToClear NO_FLAG Sync error not detected. 0 FLAG Frame sync error detected. 0x1 WSF Word Start Flag 20 1 read-write oneToClear NO_FLAG Start of word not detected. 0 FLAG Start of word detected. 0x1 SR Software Reset 24 1 read-write NO_EFFECT No effect. 0 SW_RESET Software reset. 0x1 FR FIFO Reset 25 1 read-write NO_EFFECT No effect. 0 FIFO_RESET FIFO reset. 0x1 BCE Bit Clock Enable 28 1 read-write DISABLE Receive bit clock is disabled. 0 ENABLE Receive bit clock is enabled. 0x1 DBGE Debug Enable 29 1 read-write DISABLE Receiver is disabled in Debug mode, after completing the current frame. 0 ENABLE Receiver is enabled in Debug mode. 0x1 STOPE Stop Enable 30 1 read-write DISABLE Receiver disabled in Stop mode. 0 ENABLE Receiver enabled in Stop mode. 0x1 RE Receiver Enable 31 1 read-write DISABLE Receiver is disabled. 0 ENABLE Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. 0x1 RCR1 Receive Configuration 1 0x8C 32 read-write 0 0xFFFFFFFF RFW Receive FIFO Watermark 0 5 read-write RCR2 Receive Configuration 2 0x90 32 read-write 0 0xFFFFFFFF DIV Bit Clock Divide 0 8 read-write BYP Bit Clock Bypass 23 1 read-write DISABLE Internal bit clock is generated from bit clock divider. 0 ENABLE Internal bit clock is divide by one of the audio master clock. 0x1 BCD Bit Clock Direction 24 1 read-write EXT_SLAVE_MODE Bit clock is generated externally in Slave mode. 0 INT_MASTER_MODE Bit clock is generated internally in Master mode. 0x1 BCP Bit Clock Polarity 25 1 read-write ACTIVE_HIGH Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0 ACTIVE_LOW Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. 0x1 MSEL MCLK Select 26 2 read-write BUS_CLOCK Bus Clock selected. 0 MCLK1 Master Clock (MCLK) 1 option selected. 0x1 MCLK2 Master Clock (MCLK) 2 option selected. 0x2 MCLK3 Master Clock (MCLK) 3 option selected. 0x3 BCI Bit Clock Input 28 1 read-write NO_EFFECT No effect. 0 CLOCKED_AS_IF_EXT_GENERATED Internal logic is clocked as if bit clock was externally generated. 0x1 BCS Bit Clock Swap 29 1 read-write NORMAL Use the normal bit clock source. 0 SWAP_BIT_CLK_SOURCE Swap the bit clock source. 0x1 SYNC Synchronous Mode 30 1 read-write Async Asynchronous mode. 0 SYNC_W_TX Synchronous with transmitter. 0x1 RCR3 Receive Configuration 3 0x94 32 read-write 0 0xFFFFFFFF WDFL Word Flag Configuration 0 5 read-write RCE Receive Channel Enable 16 4 read-write CFR Channel FIFO Reset 24 4 read-write RCR4 Receive Configuration 4 0x98 32 read-write 0 0xFFFFFFFF FSD Frame Sync Direction 0 1 read-write EXT_SLAVE_MODE Frame Sync is generated externally in Slave mode. 0 INT_MASTER_MODE Frame Sync is generated internally in Master mode. 0x1 FSP Frame Sync Polarity 1 1 read-write ACTIVE_HIGH Frame sync is active high. 0 ACTIVE_LOW Frame sync is active low. 0x1 ONDEM On Demand Mode 2 1 read-write DISABLE Internal frame sync is generated continuously. 0 ENABLE Internal frame sync is generated when the FIFO warning flag is clear. 0x1 FSE Frame Sync Early 3 1 read-write DISABLE Frame sync asserts with the first bit of the frame. 0 ENABLE Frame sync asserts one bit before the first bit of the frame. 0x1 MF MSB First 4 1 read-write DISABLE LSB is received first. 0 ENABLE MSB is received first. 0x1 SYWD Sync Width 8 5 read-write FRSZ Frame Size 16 5 read-write FPACK FIFO Packing Mode 24 2 read-write DISABLED FIFO packing is disabled 0 EIGHT_BIT_PACKING 8-bit FIFO packing is enabled 0x2 SIXTEEN_BIT_PACKING 16-bit FIFO packing is enabled 0x3 FCOMB FIFO Combine Mode 26 2 read-write DISABLED FIFO combine mode disabled. 0 ENA_ON_FIFO_WRITES FIFO combine mode enabled on FIFO writes (from receive shift registers). 0x1 ENA_ON_FIFO_READS FIFO combine mode enabled on FIFO reads (by software). 0x2 ENA_ON_FIFO_WRITES_READS FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). 0x3 FCONT FIFO Continue on Error 28 1 read-write DISABLE On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0 ENABLE On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. 0x1 RCR5 Receive Configuration 5 0x9C 32 read-write 0 0xFFFFFFFF FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write 4 0x4 RDR[%s] Receive Data 0xA0 32 read-only 0 0xFFFFFFFF RDR Receive Data Register 0 32 read-only 4 0x4 RFR[%s] Receive FIFO 0xC0 32 read-only 0 0xFFFFFFFF RFP Read FIFO Pointer 0 6 read-only RCP Receive Channel Pointer 15 1 read-only DISABLE No effect. 0 ENABLE FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. 0x1 WFP Write FIFO Pointer 16 6 read-only RMR Receive Mask 0xE0 32 read-write 0 0xFFFFFFFF RWM Receive Word Mask 0 32 read-write WORD_N_ENABLED Word N is enabled. 0 WORD_N_MASKED Word N is masked. 0x1 SAI2 SAI SAI SAI 0x40408000 0 0xE4 registers SAI2 77 VERID Version ID 0 32 read-only 0x3010000 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only STD Standard feature set. 0 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter 0x4 32 read-only 0x50501 0xFFFFFFFF DATALINE Number of Datalines 0 4 read-only FIFO FIFO Size 8 4 read-only FRAME Frame Size 16 4 read-only TCSR Transmit Control 0x8 32 read-write 0 0xFFFFFFFF FRDE FIFO Request DMA Enable 0 1 read-write DISABLE Disables the DMA request. 0 ENABLE Enables the DMA request. 0x1 FWDE FIFO Warning DMA Enable 1 1 read-write DISABLE Disables the DMA request. 0 ENABLE Enables the DMA request. 0x1 FRIE FIFO Request Interrupt Enable 8 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 FWIE FIFO Warning Interrupt Enable 9 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 FEIE FIFO Error Interrupt Enable 10 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 SEIE Sync Error Interrupt Enable 11 1 read-write DISABLE Disables interrupt. 0 ENABLE Enables interrupt. 0x1 WSIE Word Start Interrupt Enable 12 1 read-write DISABLE Disables interrupt. 0 ENABLE Enables interrupt. 0x1 FRF FIFO Request Flag 16 1 read-only NO_FLAG Transmit FIFO watermark has not been reached. 0 FLAG Transmit FIFO watermark has been reached. 0x1 FWF FIFO Warning Flag 17 1 read-only DISABLE No enabled transmit FIFO is empty. 0 ENABLE Enabled transmit FIFO is empty. 0x1 FEF FIFO Error Flag 18 1 read-write oneToClear NO_FLAG Transmit underrun not detected. 0 FLAG Transmit underrun detected. 0x1 SEF Sync Error Flag 19 1 read-write oneToClear NO_FLAG Sync error not detected. 0 FLAG Frame sync error detected. 0x1 WSF Word Start Flag 20 1 read-write oneToClear NO_FLAG Start of word not detected. 0 FLAG Start of word detected. 0x1 SR Software Reset 24 1 read-write DISABLE No effect. 0 ENABLE Software reset. 0x1 FR FIFO Reset 25 1 read-write NO_EFFECT No effect. 0 RESET FIFO reset. 0x1 BCE Bit Clock Enable 28 1 read-write DISABLE Transmit bit clock is disabled. 0 ENABLE Transmit bit clock is enabled. 0x1 DBGE Debug Enable 29 1 read-write DISABLE Transmitter is disabled in Debug mode, after completing the current frame. 0 ENABLE Transmitter is enabled in Debug mode. 0x1 STOPE Stop Enable 30 1 read-write DISABLE Transmitter disabled in Stop mode. 0 ENABLE Transmitter enabled in Stop mode. 0x1 TE Transmitter Enable 31 1 read-write DISABLE Transmitter is disabled. 0 ENABLE Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. 0x1 TCR1 Transmit Configuration 1 0xC 32 read-write 0 0xFFFFFFFF TFW Transmit FIFO Watermark 0 5 read-write TCR2 Transmit Configuration 2 0x10 32 read-write 0 0xFFFFFFFF DIV Bit Clock Divide 0 8 read-write BYP Bit Clock Bypass 23 1 read-write DISABLE Internal bit clock is generated from bit clock divider. 0 ENABLE Internal bit clock is divide by one of the audio master clock. 0x1 BCD Bit Clock Direction 24 1 read-write EXT_IN_SLAVE Bit clock is generated externally in Slave mode. 0 INT_IN_MASTER Bit clock is generated internally in Master mode. 0x1 BCP Bit Clock Polarity 25 1 read-write ACTIVE_HIGH Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0 ACTIVE_LOW Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. 0x1 MSEL MCLK Select 26 2 read-write BUS_CLOCK Bus Clock selected. 0 MCLK1 Master Clock (MCLK) 1 option selected. 0x1 MCLK2 Master Clock (MCLK) 2 option selected. 0x2 MCLK3 Master Clock (MCLK) 3 option selected. 0x3 BCI Bit Clock Input 28 1 read-write DISABLE No effect. 0 ENABLE Internal logic is clocked as if bit clock was externally generated. 0x1 BCS Bit Clock Swap 29 1 read-write DISABLE Use the normal bit clock source. 0 ENABLE Swap the bit clock source. 0x1 SYNC Synchronous Mode 30 1 read-write ASYNC Asynchronous mode. 0 SYNC_W_RX Synchronous with receiver. 0x1 TCR3 Transmit Configuration 3 0x14 32 read-write 0 0xFFFFFFFF WDFL Word Flag Configuration 0 5 read-write TCE Transmit Channel Enable 16 1 read-write TCR4 Transmit Configuration 4 0x18 32 read-write 0 0xFFFFFFFF FSD Frame Sync Direction 0 1 read-write EXT_IN_SLAVE_MODE Frame sync is generated externally in Slave mode. 0 INT_IN_MASTER_MODE Frame sync is generated internally in Master mode. 0x1 FSP Frame Sync Polarity 1 1 read-write ACTIVE_HIGH Frame sync is active high. 0 ACTIVE_LOW Frame sync is active low. 0x1 ONDEM On Demand Mode 2 1 read-write CONTINUOUS_FRAME_SYNC Internal frame sync is generated continuously. 0 ON_DEMAND_FRAME_SYNC Internal frame sync is generated when the FIFO warning flag is clear. 0x1 FSE Frame Sync Early 3 1 read-write DISABLE Frame sync asserts with the first bit of the frame. 0 ENABLE Frame sync asserts one bit before the first bit of the frame. 0x1 MF MSB First 4 1 read-write DISABLE LSB is transmitted first. 0 ENABLE MSB is transmitted first. 0x1 CHMOD Channel Mode 5 1 read-write TDM_MODE TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. 0 OUTPUT_MODE Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. 0x1 SYWD Sync Width 8 5 read-write FRSZ Frame size 16 5 read-write FPACK FIFO Packing Mode 24 2 read-write DISABLED FIFO packing is disabled. 0 EIGHT_BIT_FIFO_PACKING 8-bit FIFO packing is enabled. 0x2 SIXTEEN_BIT_FIFO_PACKING 16-bit FIFO packing is enabled. 0x3 FCONT FIFO Continue on Error 28 1 read-write DISABLE On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0 ENABLE On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. 0x1 TCR5 Transmit Configuration 5 0x1C 32 read-write 0 0xFFFFFFFF FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write TDR0 Transmit Data 0x20 32 read-write 0 0xFFFFFFFF TDR Transmit Data Register 0 32 read-write TFR0 Transmit FIFO 0x40 32 read-only 0 0xFFFFFFFF RFP Read FIFO Pointer 0 6 read-only WFP Write FIFO Pointer 16 6 read-only TMR Transmit Mask 0x60 32 read-write 0 0xFFFFFFFF TWM Transmit Word Mask 0 32 read-write WORD_N_ENABLED Word N is enabled. 0 WORD_N_MASKED Word N is masked. The transmit data pins are tri-stated or drive zero when masked. 0x1 RCSR Receive Control 0x88 32 read-write 0 0xFFFFFFFF FRDE FIFO Request DMA Enable 0 1 read-write DISABLE Disables the DMA request. 0 ENABLE Enables the DMA request. 0x1 FWDE FIFO Warning DMA Enable 1 1 read-write DISABLE Disables the DMA request. 0 ENABLE Enables the DMA request. 0x1 FRIE FIFO Request Interrupt Enable 8 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 FWIE FIFO Warning Interrupt Enable 9 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 FEIE FIFO Error Interrupt Enable 10 1 read-write DISABLE Disables the interrupt. 0 ENABLE Enables the interrupt. 0x1 SEIE Sync Error Interrupt Enable 11 1 read-write DISABLE Disables interrupt. 0 ENABLE Enables interrupt. 0x1 WSIE Word Start Interrupt Enable 12 1 read-write DISABLE Disables interrupt. 0 ENABLE Enables interrupt. 0x1 FRF FIFO Request Flag 16 1 read-only BELOW_WATERMARK Receive FIFO watermark not reached. 0 WATERMARK_REACHED Receive FIFO watermark has been reached. 0x1 FWF FIFO Warning Flag 17 1 read-only NOT_FULL No enabled receive FIFO is full. 0 FULL Enabled receive FIFO is full. 0x1 FEF FIFO Error Flag 18 1 read-write oneToClear NO_FLAG Receive overflow not detected. 0 FLAG Receive overflow detected. 0x1 SEF Sync Error Flag 19 1 read-write oneToClear NO_FLAG Sync error not detected. 0 FLAG Frame sync error detected. 0x1 WSF Word Start Flag 20 1 read-write oneToClear NO_FLAG Start of word not detected. 0 FLAG Start of word detected. 0x1 SR Software Reset 24 1 read-write NO_EFFECT No effect. 0 SW_RESET Software reset. 0x1 FR FIFO Reset 25 1 read-write NO_EFFECT No effect. 0 FIFO_RESET FIFO reset. 0x1 BCE Bit Clock Enable 28 1 read-write DISABLE Receive bit clock is disabled. 0 ENABLE Receive bit clock is enabled. 0x1 DBGE Debug Enable 29 1 read-write DISABLE Receiver is disabled in Debug mode, after completing the current frame. 0 ENABLE Receiver is enabled in Debug mode. 0x1 STOPE Stop Enable 30 1 read-write DISABLE Receiver disabled in Stop mode. 0 ENABLE Receiver enabled in Stop mode. 0x1 RE Receiver Enable 31 1 read-write DISABLE Receiver is disabled. 0 ENABLE Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. 0x1 RCR1 Receive Configuration 1 0x8C 32 read-write 0 0xFFFFFFFF RFW Receive FIFO Watermark 0 5 read-write RCR2 Receive Configuration 2 0x90 32 read-write 0 0xFFFFFFFF DIV Bit Clock Divide 0 8 read-write BYP Bit Clock Bypass 23 1 read-write DISABLE Internal bit clock is generated from bit clock divider. 0 ENABLE Internal bit clock is divide by one of the audio master clock. 0x1 BCD Bit Clock Direction 24 1 read-write EXT_SLAVE_MODE Bit clock is generated externally in Slave mode. 0 INT_MASTER_MODE Bit clock is generated internally in Master mode. 0x1 BCP Bit Clock Polarity 25 1 read-write ACTIVE_HIGH Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0 ACTIVE_LOW Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. 0x1 MSEL MCLK Select 26 2 read-write BUS_CLOCK Bus Clock selected. 0 MCLK1 Master Clock (MCLK) 1 option selected. 0x1 MCLK2 Master Clock (MCLK) 2 option selected. 0x2 MCLK3 Master Clock (MCLK) 3 option selected. 0x3 BCI Bit Clock Input 28 1 read-write NO_EFFECT No effect. 0 CLOCKED_AS_IF_EXT_GENERATED Internal logic is clocked as if bit clock was externally generated. 0x1 BCS Bit Clock Swap 29 1 read-write NORMAL Use the normal bit clock source. 0 SWAP_BIT_CLK_SOURCE Swap the bit clock source. 0x1 SYNC Synchronous Mode 30 1 read-write Async Asynchronous mode. 0 SYNC_W_TX Synchronous with transmitter. 0x1 RCR3 Receive Configuration 3 0x94 32 read-write 0 0xFFFFFFFF WDFL Word Flag Configuration 0 5 read-write RCE Receive Channel Enable 16 1 read-write RCR4 Receive Configuration 4 0x98 32 read-write 0 0xFFFFFFFF FSD Frame Sync Direction 0 1 read-write EXT_SLAVE_MODE Frame Sync is generated externally in Slave mode. 0 INT_MASTER_MODE Frame Sync is generated internally in Master mode. 0x1 FSP Frame Sync Polarity 1 1 read-write ACTIVE_HIGH Frame sync is active high. 0 ACTIVE_LOW Frame sync is active low. 0x1 ONDEM On Demand Mode 2 1 read-write DISABLE Internal frame sync is generated continuously. 0 ENABLE Internal frame sync is generated when the FIFO warning flag is clear. 0x1 FSE Frame Sync Early 3 1 read-write DISABLE Frame sync asserts with the first bit of the frame. 0 ENABLE Frame sync asserts one bit before the first bit of the frame. 0x1 MF MSB First 4 1 read-write DISABLE LSB is received first. 0 ENABLE MSB is received first. 0x1 SYWD Sync Width 8 5 read-write FRSZ Frame Size 16 5 read-write FPACK FIFO Packing Mode 24 2 read-write DISABLED FIFO packing is disabled 0 EIGHT_BIT_PACKING 8-bit FIFO packing is enabled 0x2 SIXTEEN_BIT_PACKING 16-bit FIFO packing is enabled 0x3 FCONT FIFO Continue on Error 28 1 read-write DISABLE On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0 ENABLE On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. 0x1 RCR5 Receive Configuration 5 0x9C 32 read-write 0 0xFFFFFFFF FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write RDR0 Receive Data 0xA0 32 read-only 0 0xFFFFFFFF RDR Receive Data Register 0 32 read-only RFR0 Receive FIFO 0xC0 32 read-only 0 0xFFFFFFFF RFP Read FIFO Pointer 0 6 read-only WFP Write FIFO Pointer 16 6 read-only RMR Receive Mask 0xE0 32 read-write 0 0xFFFFFFFF RWM Receive Word Mask 0 32 read-write WORD_N_ENABLED Word N is enabled. 0 WORD_N_MASKED Word N is masked. 0x1 SAI3 SAI SAI 0x4040C000 0 0xE4 registers SAI3_RX 78 SAI3_TX 79 SAI4 SAI SAI 0x40C40000 0 0xE4 registers SAI4_RX 80 SAI4_TX 81 ASRC ASRC ASRC 0x40414000 0 0xCC registers ASRC 97 ASRCTR ASRC Control Register 0 32 read-write 0 0xFFFFFFFF ASRCEN ASRCEN 0 1 read-write disabled operation of ASRC disabled 0 enabled operation ASRC is enabled 0x1 ASREA ASREA 1 1 read-write disabled operation of conversion A is disabled 0 enabled operation of conversion A is enabled 0x1 ASREB ASREB 2 1 read-write disabled operation of conversion B is disabled 0 enabled operation of conversion B is enabled 0x1 ASREC ASREC 3 1 read-write disabled operation of conversion C is disabled 0 enabled operation of conversion C is enabled 0x1 SRST SRST 4 1 write-only cleared ASRC Software reset cleared 0 reset ASRC Software reset generated. NOTE: This is a self-clear bit 0x1 IDRA IDRA 13 1 read-write idra_measured ASRC internal measured ratio is used 0 idra_ideal Ideal ratio from the interface register ASRIDRHA, ASRIDRLA is used 0x1 USRA USRA 14 1 read-write use_ratio_no Do not use ratio as the input to ASRC for pair A 0 use_ratio Use ratio as the input to ASRC for pair A 0x1 IDRB IDRB 15 1 read-write idra_measured ASRC internal measured ratio is used 0 idra_ideal Ideal ratio from the interface register ASRIDRHB, ASRIDRLB is used 0x1 USRB USRB 16 1 read-write use_ratio_no Do not use ratio as the input to ASRC for pair B 0 use_ratio Use ratio as the input to ASRC for pair B 0x1 IDRC IDRC 17 1 read-write idra_measured ASRC internal measured ratio is used 0 idra_ideal Ideal ratio from the interface register ASRIDRHC, ASRIDRLC is used 0x1 USRC USRC 18 1 read-write use_ratio_no Do not use ratio as the input to ASRC for pair C 0 use_ratio Use ratio as the input to ASRC for pair C 0x1 ATSA ATSA 20 1 read-write no_auto_select Pair A does not automatically update its pre-processing and post-processing options 0 auto_select Pair A automatically updates its pre-processing and post-processing options 0x1 ATSB ATSB 21 1 read-write no_auto_select Pair B does not automatically update its pre-processing and post-processing options 0 auto_select Pair B automatically updates its pre-processing and post-processing options 0x1 ATSC ATSC 22 1 read-write no_auto_select Pair C does not automatically update its pre-processing and post-processing options 0 auto_select Pair C automatically updates its pre-processing and post-processing options 0x1 ASRIER ASRC Interrupt Enable Register 0x4 32 read-write 0 0xFFFFFFFF ADIEA ADIEA 0 1 read-write disabled interrupt disabled 0 enabled interrupt enabled 0x1 ADIEB ADIEB 1 1 read-write disabled interrupt disabled 0 enabled interrupt enabled 0x1 ADIEC ADIEC 2 1 read-write disabled interrupt disabled 0 enabled interrupt enabled 0x1 ADOEA ADOEA 3 1 read-write disabled interrupt disabled 0 enabled interrupt enabled 0x1 ADOEB ADOEB 4 1 read-write disabled interrupt disabled 0 enabled interrupt enabled 0x1 ADOEC ADOEC 5 1 read-write disabled interrupt disabled 0 enabled interrupt enabled 0x1 AOLIE AOLIE 6 1 read-write disabled interrupt disabled 0 enabled interrupt enabled 0x1 AFPWE AFPWE 7 1 read-write disabled interrupt disabled 0 enabled interrupt enabled 0x1 ASRCNCR ASRC Channel Number Configuration Register 0xC 32 read-write 0 0xFFFFFFFF ANCA ANCA 0 4 read-write zero_chan 0 channels in A (Pair A is disabled) 0 one_chan 1 channel in A 0x1 two_chan 2 channels in A 0x2 three_chan 3 channels in A 0x3 four_chan 4 channels in A 0x4 five_chan 5 channels in A 0x5 six_chan 6 channels in A 0x6 seven_chan 7 channels in A 0x7 eight_chan 8 channels in A 0x8 nine_chan 9 channels in A 0x9 ten_chan 10 channels in A 0xA not_used Should not be used. 0xB not_used Should not be used. 0xC not_used Should not be used. 0xD not_used Should not be used. 0xE not_used Should not be used. 0xF ANCB ANCB 4 4 read-write zero_chan 0 channels in B (Pair B is disabled) 0 one_chan 1 channel in B 0x1 two_chan 2 channels in B 0x2 three_chan 3 channels in B 0x3 four_chan 4 channels in B 0x4 five_chan 5 channels in B 0x5 six_chan 6 channels in B 0x6 seven_chan 7 channels in B 0x7 eight_chan 8 channels in B 0x8 nine_chan 9 channels in B 0x9 ten_chan 10 channels in B 0xA not_used Should not be used. 0xB not_used Should not be used. 0xC not_used Should not be used. 0xD not_used Should not be used. 0xE not_used Should not be used. 0xF ANCC ANCC 8 4 read-write zero_chan 0 channels in C (Pair C is disabled) 0 one_chan 1 channel in C 0x1 two_chan 2 channels in C 0x2 three_chan 3 channels in C 0x3 four_chan 4 channels in C 0x4 five_chan 5 channels in C 0x5 six_chan 6 channels in C 0x6 seven_chan 7 channels in C 0x7 eight_chan 8 channels in C 0x8 nine_chan 9 channels in C 0x9 ten_chan 10 channels in C 0xA not_used Should not be used. 0xB not_used Should not be used. 0xC not_used Should not be used. 0xD not_used Should not be used. 0xE not_used Should not be used. 0xF ASRCFG ASRC Filter Configuration Status Register 0x10 32 read-write 0 0xFFFFFFFF PREMODA PREMODA 6 2 read-write upsamp_2 Select Upsampling-by-2 0 direct_connect Select Direct-Connection 0x1 downsamp_2 Select Downsampling-by-2 0x2 passthru Select passthrough mode. In this case, POSTMODA[1:0] have no use. 0x3 POSTMODA POSTMODA 8 2 read-write upsamp_2 Select Upsampling-by-2 0 direct_connect Select Direct-Connection 0x1 downsamp_2 Select Downsampling-by-2 0x2 PREMODB PREMODB 10 2 read-write upsamp_2 Select Upsampling-by-2 0 direct_connect Select Direct-Connection 0x1 downsamp_2 Select Downsampling-by-2 0x2 passthru Select passthrough mode. In this case, POSTMODB[1:0] have no use. 0x3 POSTMODB POSTMODB 12 2 read-write upsamp_2 Select Upsampling-by-2 0 direct_connect Select Direct-Connection 0x1 downsamp_2 Select Downsampling-by-2 0x2 PREMODC PREMODC 14 2 read-write upsamp_2 Select Upsampling-by-2 0 direct_connect Select Direct-Connection 0x1 downsamp_2 Select Downsampling-by-2 0x2 passthru Select passthrough mode. In this case, POSTMODC[1:0] have no use. 0x3 POSTMODC POSTMODC 16 2 read-write upsamp_2 Select Upsampling-by-2 as defined in Signal Processing Flow. 0 direct_connect Select Direct-Connection as defined in Signal Processing Flow. 0x1 downsamp_2 Select Downsampling-by-2 as defined in Signal Processing Flow. 0x2 NDPRA NDPRA 18 1 read-write use_default Use default parameters for RAM-stored parameters. Override any parameters already in RAM. 0 not_default Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. 0x1 NDPRB NDPRB 19 1 read-write use_default Use default parameters for RAM-stored parameters. Override any parameters already in RAM. 0 not_default Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM. 0x1 NDPRC NDPRC 20 1 read-write use_default Use default parameters for RAM-stored parameters. Override any parameters already in RAM. 0 not_default Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. 0x1 INIRQA INIRQA 21 1 read-only init_notserved Initialization for Conversion Pair A not served 0 init_served Initialization for Conversion Pair A served 0x1 INIRQB INIRQB 22 1 read-only init_notserved Initialization for Conversion Pair B not served 0 init_served Initialization for Conversion Pair B served 0x1 INIRQC INIRQC 23 1 read-only init_notserved Initialization for Conversion Pair C not served 0 init_served Initialization for Conversion Pair C served 0x1 ASRCSR ASRC Clock Source Register 0x14 32 read-write 0 0xFFFFFFFF AICSA AICSA 0 4 read-write bitclk0 bit clock 0 0 bitclk1 bit clock 1 0x1 bitclk2 bit clock 2 0x2 bitclk3 bit clock 3 0x3 bitclk4 bit clock 4 0x4 bitclk5 bit clock 5 0x5 bitclk6 bit clock 6 0x6 bitclk7 bit clock 7 0x7 bitclk8 bit clock 8 0x8 bitclk9 bit clock 9 0x9 bitclka bit clock A 0xA bitclkb bit clock B 0xB bitclkc bit clock C 0xC bitclkd bit clock D 0xD bitclke bit clock E 0xE clk_disabled clock disabled, connected to zero 0xF AICSB AICSB 4 4 read-write bitclk0 bit clock 0 0 bitclk1 bit clock 1 0x1 bitclk2 bit clock 2 0x2 bitclk3 bit clock 3 0x3 bitclk4 bit clock 4 0x4 bitclk5 bit clock 5 0x5 bitclk6 bit clock 6 0x6 bitclk7 bit clock 7 0x7 bitclk8 bit clock 8 0x8 bitclk9 bit clock 9 0x9 bitclka bit clock A 0xA bitclkb bit clock B 0xB bitclkc bit clock C 0xC bitclkd bit clock D 0xD bitclke bit clock E 0xE clk_disabled clock disabled, connected to zero 0xF AICSC AICSC 8 4 read-write bitclk0 bit clock 0 0 bitclk1 bit clock 1 0x1 bitclk2 bit clock 2 0x2 bitclk3 bit clock 3 0x3 bitclk4 bit clock 4 0x4 bitclk5 bit clock 5 0x5 bitclk6 bit clock 6 0x6 bitclk7 bit clock 7 0x7 bitclk8 bit clock 8 0x8 bitclk9 bit clock 9 0x9 bitclka bit clock A 0xA bitclkb bit clock B 0xB bitclkc bit clock C 0xC bitclkd bit clock D 0xD bitclke bit clock E 0xE clk_disabled clock disabled, connected to zero 0xF AOCSA AOCSA 12 4 read-write bitclk0 bit clock 0 0 bitclk1 bit clock 1 0x1 bitclk2 bit clock 2 0x2 bitclk3 bit clock 3 0x3 bitclk4 bit clock 4 0x4 bitclk5 bit clock 5 0x5 bitclk6 bit clock 6 0x6 bitclk7 bit clock 7 0x7 bitclk8 bit clock 8 0x8 bitclk9 bit clock 9 0x9 bitclka bit clock A 0xA bitclkb bit clock B 0xB bitclkc bit clock C 0xC bitclkd bit clock D 0xD bitclke bit clock E 0xE clk_disabled clock disabled, connected to zero 0xF AOCSB AOCSB 16 4 read-write bitclk0 bit clock 0 0 bitclk1 bit clock 1 0x1 bitclk2 bit clock 2 0x2 bitclk3 bit clock 3 0x3 bitclk4 bit clock 4 0x4 bitclk5 bit clock 5 0x5 bitclk6 bit clock 6 0x6 bitclk7 bit clock 7 0x7 bitclk8 bit clock 8 0x8 bitclk9 bit clock 9 0x9 bitclka bit clock A 0xA bitclkb bit clock B 0xB bitclkc bit clock C 0xC bitclkd bit clock D 0xD bitclke bit clock E 0xE clk_disabled clock disabled, connected to zero 0xF AOCSC AOCSC 20 4 read-write bitclk0 bit clock 0 0 bitclk1 bit clock 1 0x1 bitclk2 bit clock 2 0x2 bitclk3 bit clock 3 0x3 bitclk4 bit clock 4 0x4 bitclk5 bit clock 5 0x5 bitclk6 bit clock 6 0x6 bitclk7 bit clock 7 0x7 bitclk8 bit clock 8 0x8 bitclk9 bit clock 9 0x9 bitclka bit clock A 0xA bitclkb bit clock B 0xB bitclkc bit clock C 0xC bitclkd bit clock D 0xD bitclke bit clock E 0xE clk_disabled clock disabled, connected to zero 0xF ASRCDR1 ASRC Clock Divider Register 1 0x18 32 read-write 0 0xFFFFFFFF AICPA AICPA 0 3 read-write AICDA AICDA 3 3 read-write AICPB AICPB 6 3 read-write AICDB AICDB 9 3 read-write AOCPA AOCPA 12 3 read-write AOCDA AOCDA 15 3 read-write AOCPB AOCPB 18 3 read-write AOCDB AOCDB 21 3 read-write ASRCDR2 ASRC Clock Divider Register 2 0x1C 32 read-write 0 0xFFFFFFFF AICPC AICPC 0 3 read-write AICDC AICDC 3 3 read-write AOCPC AOCPC 6 3 read-write AOCDC AOCDC 9 3 read-write ASRSTR ASRC Status Register 0x20 32 read-only 0 0xFFFFFFFF AIDEA AIDEA 0 1 read-only thresh_met The threshold has been met and no data input A interrupt is generated 0 lessthan_thresh When AIDEA is set, the ASRC generates data input A interrupt request to the processor if ASRIER[AIDEA] = 1 0x1 AIDEB AIDEB 1 1 read-only thresh_met The threshold has been met and no data input B interrupt is generated 0 lessthan_thresh When AIDEB is set, the ASRC generates data input B interrupt request to the processor if ASRIER[AIDEB] = 1 0x1 AIDEC AIDEC 2 1 read-only thresh_met The threshold has been met and no data input C interrupt is generated 0 lessthan_thresh When AIDEC is set, the ASRC generates data input C interrupt request to the processor if ASRIER[AIDEC] = 1 0x1 AODFA AODFA 3 1 read-only thresh_notmet The threshold has not yet been met and no data output A interrupt is generated 0 greaterthan_thresh When AODFA is set, the ASRC generates data output A interrupt request to the processor if ASRIER[ADOEA] = 1 0x1 AODFB AODFB 4 1 read-only thresh_notmet The threshold has not yet been met and no data output B interrupt is generated 0 greaterthan_thresh When AODFB is set, the ASRC generates data output B interrupt request to the processor if ASRIER[ADOEB] = 1 0x1 AODFC AODFC 5 1 read-only thresh_notmet The threshold has not yet been met and no data output C interrupt is generated 0 greaterthan_thresh When AODFC is set, the ASRC generates data output C interrupt request to the processor if ASRIER[ADOEC] = 1 0x1 AOLE AOLE 6 1 read-only task_ok No overload 0 too_high Task rate is too high 0x1 FPWT FPWT 7 1 read-only no_waitstate ASRC is not in wait state 0 waitstate ASRC is in wait state 0x1 AIDUA AIDUA 8 1 read-only no_underflow No Underflow in Input data buffer A 0 underflow Underflow in Input data buffer A 0x1 AIDUB AIDUB 9 1 read-only no_underflow No Underflow in Input data buffer B 0 underflow Underflow in Input data buffer B 0x1 AIDUC AIDUC 10 1 read-only no_underflow No Underflow in Input data buffer C 0 underflow Underflow in Input data buffer C 0x1 AODOA AODOA 11 1 read-only no_overflow No Overflow in Output data buffer A 0 overflow Overflow in Output data buffer A 0x1 AODOB AODOB 12 1 read-only no_overflow No Overflow in Output data buffer B 0 overflow Overflow in Output data buffer B 0x1 AODOC AODOC 13 1 read-only no_overflow No Overflow in Output data buffer C 0 overflow Overflow in Output data buffer C 0x1 AIOLA AIOLA 14 1 read-only no_overload Pair A input task is not oveloaded 0 overload Pair A input task is oveloaded 0x1 AIOLB AIOLB 15 1 read-only no_overload Pair B input task is not oveloaded 0 overload Pair B input task is oveloaded 0x1 AIOLC AIOLC 16 1 read-only no_overload Pair C input task is not oveloaded 0 overload Pair C input task is oveloaded 0x1 AOOLA AOOLA 17 1 read-only no_overload Pair A output task is not oveloaded 0 overload Pair A output task is oveloaded 0x1 AOOLB AOOLB 18 1 read-only no_overload Pair B output task is not oveloaded 0 overload Pair B output task is oveloaded 0x1 AOOLC AOOLC 19 1 read-only no_overload Pair C output task is not oveloaded 0 overload Pair C output task is oveloaded 0x1 ATQOL ATQOL 20 1 read-only no_overload Task queue FIFO logic is not oveloaded 0 overload Task queue FIFO logic is oveloaded 0x1 DSLCNT DSLCNT 21 1 read-only dslcnt_proc New DSL counter information is in the process of storage into the internal ASRC FIFO 0 dslcnt_stored New DSL counter information is stored in the internal ASRC FIFO 0x1 5 0x4 1,2,3,4,5 ASRPM%s ASRC Parameter Register n 0x40 32 read-write 0 0xFFFFFFFF PARAMETER_VALUE PARAMETER_VALUE 0 24 read-write ASRTFR1 ASRC Task Queue FIFO Register 1 0x54 32 read-write 0 0xFFFFFFFF TF_BASE TF_BASE 6 7 read-write TF_FILL TF_FILL 13 7 read-only ASRCCR ASRC Channel Counter Register 0x5C 32 read-write 0 0xFFFFFFFF ACIA ACIA 0 4 read-write ACIB ACIB 4 4 read-write ACIC ACIC 8 4 read-write ACOA ACOA 12 4 read-write ACOB ACOB 16 4 read-write ACOC ACOC 20 4 read-write ASRDIA ASRC Data Input Register for Pair x 0x60 32 write-only 0 0xFFFFFFFF DATA DATA 0 24 write-only ASRDOA ASRC Data Output Register for Pair x 0x64 32 read-only 0 0xFFFFFFFF DATA DATA 0 24 read-only ASRDIB ASRC Data Input Register for Pair x 0x68 32 write-only 0 0xFFFFFFFF DATA DATA 0 24 write-only ASRDOB ASRC Data Output Register for Pair x 0x6C 32 read-only 0 0xFFFFFFFF DATA DATA 0 24 read-only ASRDIC ASRC Data Input Register for Pair x 0x70 32 write-only 0 0xFFFFFFFF DATA DATA 0 24 write-only ASRDOC ASRC Data Output Register for Pair x 0x74 32 read-only 0 0xFFFFFFFF DATA DATA 0 24 read-only ASRIDRHA ASRC Ideal Ratio for Pair A-High Part 0x80 32 read-write 0 0xFFFFFFFF IDRATIOA_H IDRATIOA_H 0 8 read-write ASRIDRLA ASRC Ideal Ratio for Pair A -Low Part 0x84 32 read-write 0 0xFFFFFFFF IDRATIOA_L IDRATIOA_L 0 24 read-write ASRIDRHB ASRC Ideal Ratio for Pair B-High Part 0x88 32 read-write 0 0xFFFFFFFF IDRATIOB_H IDRATIOB_H 0 8 read-write ASRIDRLB ASRC Ideal Ratio for Pair B-Low Part 0x8C 32 read-write 0 0xFFFFFFFF IDRATIOB_L IDRATIOB_L 0 24 read-write ASRIDRHC ASRC Ideal Ratio for Pair C-High Part 0x90 32 read-write 0 0xFFFFFFFF IDRATIOC_H IDRATIOC_H 0 8 read-write ASRIDRLC ASRC Ideal Ratio for Pair C-Low Part 0x94 32 read-write 0 0xFFFFFFFF IDRATIOC_L IDRATIOC_L 0 24 read-write ASR76K ASRC 76 kHz Period in terms of ASRC processing clock 0x98 32 read-write 0xA47 0xFFFFFFFF ASR76K ASR76K 0 17 read-write ASR56K ASRC 56 kHz Period in terms of ASRC processing clock 0x9C 32 read-write 0xDF3 0xFFFFFFFF ASR56K ASR56K 0 17 read-write ASRMCRA ASRC Misc Control Register for Pair A 0xA0 32 read-write 0 0xFFFFFFFF INFIFO_THRESHOLDA INFIFO_THRESHOLDA 0 6 read-write RSYNOFA RSYNOFA 10 1 read-write no_resync Do not touch ASRCCR[ACOA] 0 resync Force ASRCCR[ACOA]=0 0x1 RSYNIFA RSYNIFA 11 1 read-write no_resync Do not touch ASRCCR[ACIA] 0 resync Force ASRCCR[ACIA]=0 0x1 OUTFIFO_THRESHOLDA OUTFIFO_THRESHOLDA 12 6 read-write BYPASSPOLYA BYPASSPOLYA 20 1 read-write no_bypass Don't bypass polyphase filtering. 0 bypass Bypass polyphase filtering. 0x1 BUFSTALLA BUFSTALLA 21 1 read-write no_stall Don't stall Pair A conversion even in case of near empty/full FIFO conditions. 0 stall Stall Pair A conversion in case of near empty/full FIFO conditions. 0x1 EXTTHRSHA EXTTHRSHA 22 1 read-write use_default_thresh Use default thresholds. 0 use_ext_thresh Use external defined thresholds. 0x1 ZEROBUFA ZEROBUFA 23 1 read-write zero_buf Zeroize the buffer 0 do_not_zero_buf Don't zeroize the buffer 0x1 ASRFSTA ASRC FIFO Status Register for Pair A 0xA4 32 read-only 0 0xFFFFFFFF INFIFO_FILLA INFIFO_FILLA 0 7 read-only IAEA IAEA 11 1 read-only not_near_empty Input FIFO is not near empty for Pair A 0 near_empty Input FIFO is near empty for Pair A 0x1 OUTFIFO_FILLA OUTFIFO_FILLA 12 7 read-only OAFA OAFA 23 1 read-only not_near_full Output FIFO is not near full for Pair A 0 near_full Output FIFO is near full for Pair A 0x1 ASRMCRB ASRC Misc Control Register for Pair B 0xA8 32 read-write 0 0xFFFFFFFF INFIFO_THRESHOLDB INFIFO_THRESHOLDB 0 6 read-write RSYNOFB RSYNOFB 10 1 read-write no_resync Do not touch ASRCCR[ACOB] 0 resync Force ASRCCR[ACOB]=0 0x1 RSYNIFB RSYNIFB 11 1 read-write no_resync Do not touch ASRCCR[ACIB] 0 resync Force ASRCCR[ACIB]=0 0x1 OUTFIFO_THRESHOLDB OUTFIFO_THRESHOLDB 12 6 read-write BYPASSPOLYB BYPASSPOLYB 20 1 read-write no_bypass Don't bypass polyphase filtering. 0 bypass Bypass polyphase filtering. 0x1 BUFSTALLB BUFSTALLB 21 1 read-write no_stall Don't stall Pair B conversion even in case of near empty/full FIFO conditions. 0 stall Stall Pair B conversion in case of near empty/full FIFO conditions. 0x1 EXTTHRSHB EXTTHRSHB 22 1 read-write use_default_thresh Use default thresholds. 0 use_ext_thresh Use external defined thresholds. 0x1 ZEROBUFB ZEROBUFB 23 1 read-write zero_buf Zeroize the buffer 0 do_not_zero_buf Don't zeroize the buffer 0x1 ASRFSTB ASRC FIFO Status Register for Pair B 0xAC 32 read-only 0 0xFFFFFFFF INFIFO_FILLB INFIFO_FILLB 0 7 read-only IAEB IAEB 11 1 read-only not_near_empty Input FIFO is not near empty for Pair B 0 near_empty Input FIFO is near empty for Pair B 0x1 OUTFIFO_FILLB OUTFIFO_FILLB 12 7 read-only OAFB OAFB 23 1 read-only not_near_full Output FIFO is not near full for Pair B 0 near_full Output FIFO is near full for Pair B 0x1 ASRMCRC ASRC Misc Control Register for Pair C 0xB0 32 read-write 0 0xFFFFFFFF INFIFO_THRESHOLDC INFIFO_THRESHOLDC 0 6 read-write RSYNOFC RSYNOFC 10 1 read-write no_resync Do not touch ASRCCR[ACOC] 0 resync Force ASRCCR[ACOC]=0 0x1 RSYNIFC RSYNIFC 11 1 read-write no_resync Do not touch ASRCCR[ACIC] 0 resync Force ASRCCR[ACIC]=0 0x1 OUTFIFO_THRESHOLDC OUTFIFO_THRESHOLDC 12 6 read-write BYPASSPOLYC BYPASSPOLYC 20 1 read-write no_bypass Don't bypass polyphase filtering. 0 bypass Bypass polyphase filtering. 0x1 BUFSTALLC BUFSTALLC 21 1 read-write no_stall Don't stall Pair C conversion even in case of near empty/full FIFO conditions. 0 stall Stall Pair C conversion in case of near empty/full FIFO conditions. 0x1 EXTTHRSHC EXTTHRSHC 22 1 read-write use_default_thresh Use default thresholds. 0 use_ext_thresh Use external defined thresholds. 0x1 ZEROBUFC ZEROBUFC 23 1 read-write zero_buf Zeroize the buffer 0 do_not_zero_buf Don't zeroize the buffer 0x1 ASRFSTC ASRC FIFO Status Register for Pair C 0xB4 32 read-only 0 0xFFFFFFFF INFIFO_FILLC INFIFO_FILLC 0 7 read-only IAEC IAEC 11 1 read-only not_near_empty Input FIFO is not near empty for Pair C 0 near_empty Input FIFO is near empty for Pair C 0x1 OUTFIFO_FILLC OUTFIFO_FILLC 12 7 read-only OAFC OAFC 23 1 read-only not_near_full Output FIFO is not near full for Pair C 0 near_full Output FIFO is near full for Pair C 0x1 3 0x4 A,B,C ASRMCR1%s ASRC Misc Control Register 1 for Pair X 0xC0 32 read-write 0 0xFFFFFFFF OW16 OW16 0 1 read-write out_24bit 24-bit output data. 0 out_16bit 16-bit output data 0x1 OSGN OSGN 1 1 read-write no_sign_ext No sign extension. 0 sign_ext Sign extension. 0x1 OMSB OMSB 2 1 read-write lsb_aligned LSB aligned. 0 msb_aligned MSB aligned. 0x1 IMSB IMSB 8 1 read-write lsb_aligned LSB aligned. 0 msb_aligned MSB aligned. 0x1 IWD IWD 9 2 read-write audiodata_24bit 24-bit audio data. 0 audiodata_16bit 16-bit audio data. 0x1 audiodata_8bit 8-bit audio data. 0x2 USDHC1 uSDHC USDHC USDHC 0x40418000 0 0xD0 registers USDHC1 133 DS_ADDR DMA System Address 0 32 read-write 0 0xFFFFFFFF DS_ADDR System address 0 32 read-write BLK_ATT Block Attributes 0x4 32 read-write 0x10000 0xFFFFFFFF BLKSIZE Transfer block size 0 13 read-write BLKSIZE_0 No data transfer 0 BLKSIZE_1 1 byte 0x1 BLKSIZE_2 2 bytes 0x2 BLKSIZE_3 3 bytes 0x3 BLKSIZE_4 4 bytes 0x4 BLKSIZE_511 511 bytes 0x1FF BLKSIZE_512 512 bytes 0x200 BLKSIZE_2048 2048 bytes 0x800 BLKSIZE_4096 4096 bytes 0x1000 BLKCNT Blocks count for current transfer 16 16 read-write BLKCNT_0 Stop count 0 BLKCNT_1 1 block 0x1 BLKCNT_2 2 blocks 0x2 BLKCNT_65535 65535 blocks 0xFFFF CMD_ARG Command Argument 0x8 32 read-write 0 0xFFFFFFFF CMDARG Command argument 0 32 read-write CMD_XFR_TYP Command Transfer Type 0xC 32 read-write 0 0xFFFFFFFF RSPTYP Response type select 16 2 read-write RSPTYP_0 No response 0 RSPTYP_1 Response length 136 0x1 RSPTYP_2 Response length 48 0x2 RSPTYP_3 Response length 48, check busy after response 0x3 CCCEN Command CRC check enable 19 1 read-write CCCEN_0 Disables command CRC check 0 CCCEN_1 Enables command CRC check 0x1 CICEN Command index check enable 20 1 read-write CICEN_0 Disable command index check 0 CICEN_1 Enables command index check 0x1 DPSEL Data present select 21 1 read-write DPSEL_0 No data present 0 DPSEL_1 Data present 0x1 CMDTYP Command type 22 2 read-write CMDTYP_0 Normal other commands 0 CMDTYP_1 Suspend CMD52 for writing bus suspend in CCCR 0x1 CMDTYP_2 Resume CMD52 for writing function select in CCCR 0x2 CMDTYP_3 Abort CMD12, CMD52 for writing I/O Abort in CCCR 0x3 CMDINX Command index 24 6 read-write CMD_RSP0 Command Response0 0x10 32 read-only 0 0xFFFFFFFF CMDRSP0 Command response 0 0 32 read-only CMD_RSP1 Command Response1 0x14 32 read-only 0 0xFFFFFFFF CMDRSP1 Command response 1 0 32 read-only CMD_RSP2 Command Response2 0x18 32 read-only 0 0xFFFFFFFF CMDRSP2 Command response 2 0 32 read-only CMD_RSP3 Command Response3 0x1C 32 read-only 0 0xFFFFFFFF CMDRSP3 Command response 3 0 32 read-only DATA_BUFF_ACC_PORT Data Buffer Access Port 0x20 32 read-write 0 0xFFFFFFFF DATCONT Data content 0 32 read-write PRES_STATE Present State 0x24 32 read-only 0x8080 0x72FFFF CIHB Command inhibit (CMD) 0 1 read-only CIHB_0 Can issue command using only CMD line 0 CIHB_1 Cannot issue command 0x1 CDIHB Command Inhibit Data (DATA) 1 1 read-only CDIHB_0 Can issue command that uses the DATA line 0 CDIHB_1 Cannot issue command that uses the DATA line 0x1 DLA Data line active 2 1 read-only DLA_0 DATA line inactive 0 DLA_1 DATA line active 0x1 SDSTB SD clock stable 3 1 read-only SDSTB_0 Clock is changing frequency and not stable. 0 SDSTB_1 Clock is stable. 0x1 IPGOFF Peripheral clock gated off internally 4 1 read-only IPGOFF_0 Peripheral clock is active. 0 IPGOFF_1 Peripheral clock is gated off. 0x1 HCKOFF HCLK gated off internally 5 1 read-only HCKOFF_0 HCLK is active. 0 HCKOFF_1 HCLK is gated off. 0x1 PEROFF IPG_PERCLK gated off internally 6 1 read-only PEROFF_0 IPG_PERCLK is active. 0 PEROFF_1 IPG_PERCLK is gated off. 0x1 SDOFF SD clock gated off internally 7 1 read-only SDOFF_0 SD clock is active. 0 SDOFF_1 SD clock is gated off. 0x1 WTA Write transfer active 8 1 read-only WTA_0 No valid data 0 WTA_1 Transferring data 0x1 RTA Read transfer active 9 1 read-only RTA_0 No valid data 0 RTA_1 Transferring data 0x1 BWEN Buffer write enable 10 1 read-only BWEN_0 Write disable 0 BWEN_1 Write enable 0x1 BREN Buffer read enable 11 1 read-only BREN_0 Read disable 0 BREN_1 Read enable 0x1 RTR Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode) 12 1 read-only RTR_0 Fixed or well tuned sampling clock 0 RTR_1 Sampling clock needs re-tuning 0x1 TSCD Tap select change done 15 1 read-only TSCD_0 Delay cell select change is not finished. 0 TSCD_1 Delay cell select change is finished. 0x1 CINST Card inserted 16 1 read-only CINST_0 Power on reset or no card 0 CINST_1 Card inserted 0x1 CDPL Card detect pin level 18 1 read-only CDPL_0 No card present (CD_B = 1) 0 CDPL_1 Card present (CD_B = 0) 0x1 WPSPL Write protect switch pin level 19 1 read-only WPSPL_0 Write protected (WP = 1) 0 WPSPL_1 Write enabled (WP = 0) 0x1 CLSL CMD line signal level 23 1 read-only DLSL DATA[7:0] line signal level 24 8 read-only DATA0 Data 0 line signal level 0 DATA1 Data 1 line signal level 0x1 DATA2 Data 2 line signal level 0x2 DATA3 Data 3 line signal level 0x3 DATA4 Data 4 line signal level 0x4 DATA5 Data 5 line signal level 0x5 DATA6 Data 6 line signal level 0x6 DATA7 Data 7 line signal level 0x7 PROT_CTRL Protocol Control 0x28 32 read-write 0x8800020 0xFFFFFFFF DTW Data transfer width 1 2 read-write DTW_0 1-bit mode 0 DTW_1 4-bit mode 0x1 DTW_2 8-bit mode 0x2 D3CD DATA3 as card detection pin 3 1 read-write D3CD_0 DATA3 does not monitor card insertion 0 D3CD_1 DATA3 as card detection pin 0x1 EMODE Endian mode 4 2 read-write EMODE_0 Big endian mode 0 EMODE_1 Half word big endian mode 0x1 EMODE_2 Little endian mode 0x2 CDTL Card detect test level 6 1 read-write CDTL_0 Card detect test level is 0, no card inserted 0 CDTL_1 Card detect test level is 1, card inserted 0x1 CDSS Card detect signal selection 7 1 read-write CDSS_0 Card detection level is selected (for normal purpose). 0 CDSS_1 Card detection test level is selected (for test purpose). 0x1 DMASEL DMA select 8 2 read-write DMASEL_0 No DMA or simple DMA is selected. 0 DMASEL_1 ADMA1 is selected. 0x1 DMASEL_2 ADMA2 is selected. 0x2 SABGREQ Stop at block gap request 16 1 read-write SABGREQ_0 Transfer 0 SABGREQ_1 Stop 0x1 CREQ Continue request 17 1 read-write CREQ_0 No effect 0 CREQ_1 Restart 0x1 RWCTL Read wait control 18 1 read-write RWCTL_0 Disables read wait control and stop SD clock at block gap when SABGREQ field is set 0 RWCTL_1 Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set 0x1 IABG Interrupt at block gap 19 1 read-write IABG_0 Disables interrupt at block gap 0 IABG_1 Enables interrupt at block gap 0x1 RD_DONE_NO_8CLK Read performed number 8 clock 20 1 read-write WECINT Wakeup event enable on card interrupt 24 1 read-write WECINT_0 Disables wakeup event enable on card interrupt 0 WECINT_1 Enables wakeup event enable on card interrupt 0x1 WECINS Wakeup event enable on SD card insertion 25 1 read-write WECINS_0 Disable wakeup event enable on SD card insertion 0 WECINS_1 Enable wakeup event enable on SD card insertion 0x1 WECRM Wakeup event enable on SD card removal 26 1 read-write WECRM_0 Disables wakeup event enable on SD card removal 0 WECRM_1 Enables wakeup event enable on SD card removal 0x1 NON_EXACT_BLK_RD Non-exact block read 30 1 read-write NON_EXACT_BLK_RD_0 The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read. 0 NON_EXACT_BLK_RD_1 The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. 0x1 SYS_CTRL System Control 0x2C 32 read-write 0x80800F 0xFFFFFFFF DVS Divisor 4 4 read-write DVS_0 Divide-by-1 0 DVS_1 Divide-by-2 0x1 DVS_14 Divide-by-15 0xE DVS_15 Divide-by-16 0xF SDCLKFS SDCLK frequency select 8 8 read-write DTOCV Data timeout counter value 16 4 read-write DTOCV_0 SDCLK x 2 14 0 DTOCV_1 SDCLK x 2 15 0x1 DTOCV_2 SDCLK x 2 16 0x2 DTOCV_3 SDCLK x 2 17 0x3 DTOCV_4 SDCLK x 2 18 0x4 DTOCV_5 SDCLK x 2 19 0x5 DTOCV_6 SDCLK x 2 20 0x6 DTOCV_7 SDCLK x 2 21 0x7 DTOCV_8 SDCLK x 2 22 0x8 DTOCV_9 SDCLK x 2 23 0x9 DTOCV_10 SDCLK x 2 24 0xA DTOCV_11 SDCLK x 2 25 0xB DTOCV_12 SDCLK x 2 26 0xC DTOCV_13 SDCLK x 2 27 0xD DTOCV_14 SDCLK x 2 28 0xE DTOCV_15 SDCLK x 2 29 0xF IPP_RST_N Hardware reset 23 1 read-write RSTA Software reset for all 24 1 read-write RSTA_0 No reset 0 RSTA_1 Reset 0x1 RSTC Software reset for CMD line 25 1 read-write RSTC_0 No reset 0 RSTC_1 Reset 0x1 RSTD Software reset for data line 26 1 read-write RSTD_0 No reset 0 RSTD_1 Reset 0x1 INITA Initialization active 27 1 read-write RSTT Reset tuning 28 1 read-write INT_STATUS Interrupt Status 0x30 32 read-write 0 0xFFFFFFFF oneToClear CC Command complete 0 1 read-write oneToClear CC_0 Command not complete 0 CC_1 Command complete 0x1 TC Transfer complete 1 1 read-write oneToClear TC_0 Transfer does not complete 0 TC_1 Transfer complete 0x1 BGE Block gap event 2 1 read-write oneToClear BGE_0 No block gap event 0 BGE_1 Transaction stopped at block gap 0x1 DINT DMA interrupt 3 1 read-write oneToClear DINT_0 No DMA interrupt 0 DINT_1 DMA interrupt is generated. 0x1 BWR Buffer write ready 4 1 read-write oneToClear BWR_0 Not ready to write buffer 0 BWR_1 Ready to write buffer 0x1 BRR Buffer read ready 5 1 read-write oneToClear BRR_0 Not ready to read buffer 0 BRR_1 Ready to read buffer 0x1 CINS Card insertion 6 1 read-write oneToClear CINS_0 Card state unstable or removed 0 CINS_1 Card inserted 0x1 CRM Card removal 7 1 read-write oneToClear CRM_0 Card state unstable or inserted 0 CRM_1 Card removed 0x1 CINT Card interrupt 8 1 read-write oneToClear CINT_0 No card interrupt 0 CINT_1 Generate card interrupt 0x1 RTE Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) 12 1 read-write oneToClear RTE_0 Re-tuning is not required. 0 RTE_1 Re-tuning should be performed. 0x1 TP Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode) 14 1 read-write oneToClear CTOE Command timeout error 16 1 read-write oneToClear CTOE_0 No error 0 CTOE_1 Time out 0x1 CCE Command CRC error 17 1 read-write oneToClear CCE_0 No error 0 CCE_1 CRC error generated 0x1 CEBE Command end bit error 18 1 read-write oneToClear CEBE_0 No error 0 CEBE_1 End bit error generated 0x1 CIE Command index error 19 1 read-write oneToClear CIE_0 No error 0 CIE_1 Error 0x1 DTOE Data timeout error 20 1 read-write oneToClear DTOE_0 No error 0 DTOE_1 Time out 0x1 DCE Data CRC error 21 1 read-write oneToClear DCE_0 No error 0 DCE_1 Error 0x1 DEBE Data end bit error 22 1 read-write oneToClear DEBE_0 No error 0 DEBE_1 Error 0x1 AC12E Auto CMD12 error 24 1 read-write oneToClear AC12E_0 No error 0 AC12E_1 Error 0x1 TNE Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode) 26 1 read-write oneToClear DMAE DMA error 28 1 read-write oneToClear DMAE_0 No error 0 DMAE_1 Error 0x1 INT_STATUS_EN Interrupt Status Enable 0x34 32 read-write 0 0xFFFFFFFF CCSEN Command complete status enable 0 1 read-write CCSEN_0 Masked 0 CCSEN_1 Enabled 0x1 TCSEN Transfer complete status enable 1 1 read-write TCSEN_0 Masked 0 TCSEN_1 Enabled 0x1 BGESEN Block gap event status enable 2 1 read-write BGESEN_0 Masked 0 BGESEN_1 Enabled 0x1 DINTSEN DMA interrupt status enable 3 1 read-write DINTSEN_0 Masked 0 DINTSEN_1 Enabled 0x1 BWRSEN Buffer write ready status enable 4 1 read-write BWRSEN_0 Masked 0 BWRSEN_1 Enabled 0x1 BRRSEN Buffer read ready status enable 5 1 read-write BRRSEN_0 Masked 0 BRRSEN_1 Enabled 0x1 CINSSEN Card insertion status enable 6 1 read-write CINSSEN_0 Masked 0 CINSSEN_1 Enabled 0x1 CRMSEN Card removal status enable 7 1 read-write CRMSEN_0 Masked 0 CRMSEN_1 Enabled 0x1 CINTSEN Card interrupt status enable 8 1 read-write CINTSEN_0 Masked 0 CINTSEN_1 Enabled 0x1 RTESEN Re-tuning event status enable 12 1 read-write RTESEN_0 Masked 0 RTESEN_1 Enabled 0x1 TPSEN Tuning pass status enable 14 1 read-write TPSEN_0 Masked 0 TPSEN_1 Enabled 0x1 CTOESEN Command timeout error status enable 16 1 read-write CTOESEN_0 Masked 0 CTOESEN_1 Enabled 0x1 CCESEN Command CRC error status enable 17 1 read-write CCESEN_0 Masked 0 CCESEN_1 Enabled 0x1 CEBESEN Command end bit error status enable 18 1 read-write CEBESEN_0 Masked 0 CEBESEN_1 Enabled 0x1 CIESEN Command index error status enable 19 1 read-write CIESEN_0 Masked 0 CIESEN_1 Enabled 0x1 DTOESEN Data timeout error status enable 20 1 read-write DTOESEN_0 Masked 0 DTOESEN_1 Enabled 0x1 DCESEN Data CRC error status enable 21 1 read-write DCESEN_0 Masked 0 DCESEN_1 Enabled 0x1 DEBESEN Data end bit error status enable 22 1 read-write DEBESEN_0 Masked 0 DEBESEN_1 Enabled 0x1 AC12ESEN Auto CMD12 error status enable 24 1 read-write AC12ESEN_0 Masked 0 AC12ESEN_1 Enabled 0x1 TNESEN Tuning error status enable 26 1 read-write TNESEN_0 Masked 0 TNESEN_1 Enabled 0x1 DMAESEN DMA error status enable 28 1 read-write DMAESEN_0 Masked 0 DMAESEN_1 Enabled 0x1 INT_SIGNAL_EN Interrupt Signal Enable 0x38 32 read-write 0 0xFFFFFFFF CCIEN Command complete interrupt enable 0 1 read-write CCIEN_0 Masked 0 CCIEN_1 Enabled 0x1 TCIEN Transfer complete interrupt enable 1 1 read-write TCIEN_0 Masked 0 TCIEN_1 Enabled 0x1 BGEIEN Block gap event interrupt enable 2 1 read-write BGEIEN_0 Masked 0 BGEIEN_1 Enabled 0x1 DINTIEN DMA interrupt enable 3 1 read-write DINTIEN_0 Masked 0 DINTIEN_1 Enabled 0x1 BWRIEN Buffer write ready interrupt enable 4 1 read-write BWRIEN_0 Masked 0 BWRIEN_1 Enabled 0x1 BRRIEN Buffer read ready interrupt enable 5 1 read-write BRRIEN_0 Masked 0 BRRIEN_1 Enabled 0x1 CINSIEN Card insertion interrupt enable 6 1 read-write CINSIEN_0 Masked 0 CINSIEN_1 Enabled 0x1 CRMIEN Card removal interrupt enable 7 1 read-write CRMIEN_0 Masked 0 CRMIEN_1 Enabled 0x1 CINTIEN Card interrupt enable 8 1 read-write CINTIEN_0 Masked 0 CINTIEN_1 Enabled 0x1 RTEIEN Re-tuning event interrupt enable 12 1 read-write RTEIEN_0 Masked 0 RTEIEN_1 Enabled 0x1 TPIEN Tuning Pass interrupt enable 14 1 read-write TPIEN_0 Masked 0 TPIEN_1 Enabled 0x1 CTOEIEN Command timeout error interrupt enable 16 1 read-write CTOEIEN_0 Masked 0 CTOEIEN_1 Enabled 0x1 CCEIEN Command CRC error interrupt enable 17 1 read-write CCEIEN_0 Masked 0 CCEIEN_1 Enabled 0x1 CEBEIEN Command end bit error interrupt enable 18 1 read-write CEBEIEN_0 Masked 0 CEBEIEN_1 Enabled 0x1 CIEIEN Command index error interrupt enable 19 1 read-write CIEIEN_0 Masked 0 CIEIEN_1 Enabled 0x1 DTOEIEN Data timeout error interrupt enable 20 1 read-write DTOEIEN_0 Masked 0 DTOEIEN_1 Enabled 0x1 DCEIEN Data CRC error interrupt enable 21 1 read-write DCEIEN_0 Masked 0 DCEIEN_1 Enabled 0x1 DEBEIEN Data end bit error interrupt enable 22 1 read-write DEBEIEN_0 Masked 0 DEBEIEN_1 Enabled 0x1 AC12EIEN Auto CMD12 error interrupt enable 24 1 read-write AC12EIEN_0 Masked 0 AC12EIEN_1 Enabled 0x1 TNEIEN Tuning error interrupt enable 26 1 read-write TNEIEN_0 Masked 0 TNEIEN_1 Enabled 0x1 DMAEIEN DMA error interrupt enable 28 1 read-write DMAEIEN_0 Masked 0 DMAEIEN_1 Enable 0x1 AUTOCMD12_ERR_STATUS Auto CMD12 Error Status 0x3C 32 read-write 0 0xFFFFFFFF AC12NE Auto CMD12 not executed 0 1 read-only AC12NE_0 Executed 0 AC12NE_1 Not executed 0x1 AC12TOE Auto CMD12 / 23 timeout error 1 1 read-only AC12TOE_0 No error 0 AC12TOE_1 Time out 0x1 AC12EBE Auto CMD12 / 23 end bit error 2 1 read-only AC12EBE_0 No error 0 AC12EBE_1 End bit error generated 0x1 AC12CE Auto CMD12 / 23 CRC error 3 1 read-only AC12CE_0 No CRC error 0 AC12CE_1 CRC error met in Auto CMD12/23 response 0x1 AC12IE Auto CMD12 / 23 index error 4 1 read-only AC12IE_0 No error 0 AC12IE_1 Error, the CMD index in response is not CMD12/23 0x1 CNIBAC12E Command not issued by Auto CMD12 error 7 1 read-only CNIBAC12E_0 No error 0 CNIBAC12E_1 Not issued 0x1 EXECUTE_TUNING Execute tuning 22 1 read-write EXECUTE_TUNING_0 Tuning procedure is aborted 0 EXECUTE_TUNING_1 Start tuning procedure 0x1 SMP_CLK_SEL Sample clock select 23 1 read-write SMP_CLK_SEL_0 Fixed clock is used to sample data 0 SMP_CLK_SEL_1 Tuned clock is used to sample data 0x1 HOST_CTRL_CAP Host Controller Capabilities 0x40 32 read-write 0x7F3B407 0xFFFFFFFF SDR50_SUPPORT SDR50 support 0 1 read-only SDR104_SUPPORT SDR104 support 1 1 read-only DDR50_SUPPORT DDR50 support 2 1 read-only USE_TUNING_SDR50 Use Tuning for SDR50 13 1 read-write USE_TUNING_SDR50_0 SDR50 does not support tuning 0 USE_TUNING_SDR50_1 SDR50 supports tuning 0x1 MBL Max block length 16 3 read-only MBL_0 512 bytes 0 MBL_1 1024 bytes 0x1 MBL_2 2048 bytes 0x2 MBL_3 4096 bytes 0x3 ADMAS ADMA support 20 1 read-only ADMAS_0 Advanced DMA not supported 0 ADMAS_1 Advanced DMA supported 0x1 HSS High speed support 21 1 read-only HSS_0 High speed not supported 0 HSS_1 High speed supported 0x1 DMAS DMA support 22 1 read-only DMAS_0 DMA not supported 0 DMAS_1 DMA supported 0x1 SRS Suspend / resume support 23 1 read-only SRS_0 Not supported 0 SRS_1 Supported 0x1 VS33 Voltage support 3.3 V 24 1 read-only VS33_0 3.3 V not supported 0 VS33_1 3.3 V supported 0x1 VS30 Voltage support 3.0 V 25 1 read-only VS30_0 3.0 V not supported 0 VS30_1 3.0 V supported 0x1 VS18 Voltage support 1.8 V 26 1 read-only VS18_0 1.8 V not supported 0 VS18_1 1.8 V supported 0x1 WTMK_LVL Watermark Level 0x44 32 read-write 0x8100810 0xFFFFFFFF RD_WML Read watermark level 0 8 read-write WR_WML Write watermark level 16 8 read-write MIX_CTRL Mixer Control 0x48 32 read-write 0x80000000 0xFFFFFFFF DMAEN DMA enable 0 1 read-write DMAEN_0 Disable 0 DMAEN_1 Enable 0x1 BCEN Block count enable 1 1 read-write BCEN_0 Disable 0 BCEN_1 Enable 0x1 AC12EN Auto CMD12 enable 2 1 read-write AC12EN_0 Disable 0 AC12EN_1 Enable 0x1 DDR_EN Dual data rate mode selection 3 1 read-write DTDSEL Data transfer direction select 4 1 read-write DTDSEL_0 Write (Host to card) 0 DTDSEL_1 Read (Card to host) 0x1 MSBSEL Multi / Single block select 5 1 read-write MSBSEL_0 Single block 0 MSBSEL_1 Multiple blocks 0x1 NIBBLE_POS Nibble position indication 6 1 read-write AC23EN Auto CMD23 enable 7 1 read-write EXE_TUNE Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) 22 1 read-write EXE_TUNE_0 Not tuned or tuning completed 0 EXE_TUNE_1 Execute tuning 0x1 SMP_CLK_SEL Clock selection 23 1 read-write SMP_CLK_SEL_0 Fixed clock is used to sample data / cmd 0 SMP_CLK_SEL_1 Tuned clock is used to sample data / cmd 0x1 AUTO_TUNE_EN Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) 24 1 read-write AUTO_TUNE_EN_0 Disable auto tuning 0 AUTO_TUNE_EN_1 Enable auto tuning 0x1 FBCLK_SEL Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) 25 1 read-write FBCLK_SEL_0 Feedback clock comes from the loopback CLK 0 FBCLK_SEL_1 Feedback clock comes from the ipp_card_clk_out 0x1 HS400_MODE Enable HS400 mode 26 1 read-write FORCE_EVENT Force Event 0x50 32 read-write 0 0xFFFFFFFF FEVTAC12NE Force event auto command 12 not executed 0 1 read-write FEVTAC12TOE Force event auto command 12 time out error 1 1 read-write FEVTAC12CE Force event auto command 12 CRC error 2 1 read-write FEVTAC12EBE Force event Auto Command 12 end bit error 3 1 read-write FEVTAC12IE Force event Auto Command 12 index error 4 1 read-write FEVTCNIBAC12E Force event command not executed by Auto Command 12 error 7 1 read-write FEVTCTOE Force event command time out error 16 1 read-write FEVTCCE Force event command CRC error 17 1 read-write FEVTCEBE Force event command end bit error 18 1 read-write FEVTCIE Force event command index error 19 1 read-write FEVTDTOE Force event data time out error 20 1 read-write FEVTDCE Force event data CRC error 21 1 read-write FEVTDEBE Force event data end bit error 22 1 read-write FEVTAC12E Force event Auto Command 12 error 24 1 read-write FEVTTNE Force tuning error 26 1 read-write FEVTDMAE Force event DMA error 28 1 read-write FEVTCINT Force event card interrupt 31 1 read-write ADMA_ERR_STATUS ADMA Error Status 0x54 32 read-only 0 0xFFFFFFFF ADMAES ADMA error state (when ADMA error is occurred) 0 2 read-only ADMALME ADMA length mismatch error 2 1 read-only ADMALME_0 No error 0 ADMALME_1 Error 0x1 ADMADCE ADMA descriptor error 3 1 read-only ADMADCE_0 No error 0 ADMADCE_1 Error 0x1 ADMA_SYS_ADDR ADMA System Address 0x58 32 read-write 0 0xFFFFFFFF ADS_ADDR ADMA system address 2 30 read-write DLL_CTRL DLL (Delay Line) Control 0x60 32 read-write 0 0xFFFFFFFF DLL_CTRL_ENABLE DLL and delay chain 0 1 read-write DLL_CTRL_RESET DLL reset 1 1 read-write DLL_CTRL_SLV_FORCE_UPD DLL slave delay line 2 1 read-write DLL_CTRL_SLV_DLY_TARGET0 DLL slave delay target0 3 4 read-write DLL_CTRL_GATE_UPDATE DLL gate update 7 1 read-write DLL_CTRL_SLV_OVERRIDE DLL slave override 8 1 read-write DLL_CTRL_SLV_OVERRIDE_VAL DLL slave override val 9 7 read-write DLL_CTRL_SLV_DLY_TARGET1 DLL slave delay target1 16 3 read-write DLL_CTRL_SLV_UPDATE_INT Slave delay line update interval 20 8 read-write DLL_CTRL_REF_UPDATE_INT DLL control loop update interval 28 4 read-write DLL_STATUS DLL Status 0x64 32 read-only 0x200 0xFFFFFFFF DLL_STS_SLV_LOCK Slave delay-line lock status 0 1 read-only DLL_STS_REF_LOCK Reference DLL lock status 1 1 read-only DLL_STS_SLV_SEL Slave delay line select status 2 7 read-only DLL_STS_REF_SEL Reference delay line select taps 9 7 read-only CLK_TUNE_CTRL_STATUS CLK Tuning Control and Status 0x68 32 read-write 0 0xFFFFFFFF DLY_CELL_SET_POST Delay cells on the feedback clock between CLK_OUT and CLK_POST 0 4 read-write DLY_CELL_SET_OUT Delay cells on the feedback clock between CLK_PRE and CLK_OUT 4 4 read-write DLY_CELL_SET_PRE delay cells on the feedback clock between the feedback clock and CLK_PRE 8 7 read-write NXT_ERR NXT error 15 1 read-only TAP_SEL_POST Delay cells added on the feedback clock between CLK_OUT and CLK_POST 16 4 read-only TAP_SEL_OUT Delay cells added on the feedback clock between CLK_PRE and CLK_OUT 20 4 read-only TAP_SEL_PRE TAP_SEL_PRE 24 7 read-only PRE_ERR PRE error 31 1 read-only STROBE_DLL_CTRL Strobe DLL control 0x70 32 read-write 0 0xFFFFFFFF STROBE_DLL_CTRL_ENABLE Strobe DLL control enable 0 1 read-write STROBE_DLL_CTRL_RESET Strobe DLL control reset 1 1 read-write STROBE_DLL_CTRL_SLV_FORCE_UPD Strobe DLL control slave force updated 2 1 read-write STROBE_DLL_CTRL_SLV_DLY_TARGET Strobe DLL Control Slave Delay Target 3 4 read-write STROBE_DLL_CTRL_GATE_UPDATE Strobe DLL control gate update 7 1 read-write STROBE_DLL_CTRL_SLV_OVERRIDE Strobe DLL control slave override 8 1 read-write STROBE_DLL_CTRL_SLV_OVERRIDE_VAL Strobe DLL control slave Override value 9 7 read-write STROBE_DLL_CTRL_SLV_UPDATE_INT Strobe DLL control slave update interval 20 8 read-write STROBE_DLL_CTRL_REF_UPDATE_INT Strobe DLL control reference update interval 28 4 read-write STROBE_DLL_STATUS Strobe DLL status 0x74 32 read-only 0x200 0xFFFFFFFF STROBE_DLL_STS_SLV_LOCK Strobe DLL status slave lock 0 1 read-only STROBE_DLL_STS_REF_LOCK Strobe DLL status reference lock 1 1 read-only STROBE_DLL_STS_SLV_SEL Strobe DLL status slave select 2 7 read-only STROBE_DLL_STS_REF_SEL Strobe DLL status reference select 9 7 read-only VEND_SPEC Vendor Specific Register 0xC0 32 read-write 0x30007809 0xFFFFFFFF VSELECT Voltage selection 1 1 read-write VSELECT_0 Change the voltage to high voltage range, around 3.0 V 0 VSELECT_1 Change the voltage to low voltage range, around 1.8 V 0x1 CONFLICT_CHK_EN Conflict check enable 2 1 read-write CONFLICT_CHK_EN_0 Conflict check disable 0 CONFLICT_CHK_EN_1 Conflict check enable 0x1 AC12_WR_CHKBUSY_EN Check busy enable 3 1 read-write AC12_WR_CHKBUSY_EN_0 Do not check busy after auto CMD12 for write data packet 0 AC12_WR_CHKBUSY_EN_1 Check busy after auto CMD12 for write data packet 0x1 FRC_SDCLK_ON Force CLK 8 1 read-write FRC_SDCLK_ON_0 CLK active or inactive is fully controlled by the hardware. 0 FRC_SDCLK_ON_1 Force CLK active 0x1 CRC_CHK_DIS CRC Check Disable 15 1 read-write CRC_CHK_DIS_0 Check CRC16 for every read data packet and check CRC fields for every write data packet 0 CRC_CHK_DIS_1 Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet 0x1 CMD_BYTE_EN Byte access 31 1 read-write CMD_BYTE_EN_0 Disable 0 CMD_BYTE_EN_1 Enable 0x1 MMC_BOOT MMC Boot 0xC4 32 read-write 0 0xFFFFFFFF DTOCV_ACK Boot ACK time out 0 4 read-write DTOCV_ACK_0 SDCLK x 2^14 0 DTOCV_ACK_1 SDCLK x 2^15 0x1 DTOCV_ACK_2 SDCLK x 2^16 0x2 DTOCV_ACK_3 SDCLK x 2^17 0x3 DTOCV_ACK_4 SDCLK x 2^18 0x4 DTOCV_ACK_5 SDCLK x 2^19 0x5 DTOCV_ACK_6 SDCLK x 2^20 0x6 DTOCV_ACK_7 SDCLK x 2^21 0x7 DTOCV_ACK_14 SDCLK x 2^28 0xE DTOCV_ACK_15 SDCLK x 2^29 0xF BOOT_ACK BOOT ACK 4 1 read-write BOOT_ACK_0 No ack 0 BOOT_ACK_1 Ack 0x1 BOOT_MODE Boot mode 5 1 read-write BOOT_MODE_0 Normal boot 0 BOOT_MODE_1 Alternative boot 0x1 BOOT_EN Boot enable 6 1 read-write BOOT_EN_0 Fast boot disable 0 BOOT_EN_1 Fast boot enable 0x1 AUTO_SABG_EN Auto stop at block gap 7 1 read-write DISABLE_TIME_OUT Time out 8 1 read-write DISABLE_TIME_OUT_0 Enable time out 0 DISABLE_TIME_OUT_1 Disable time out 0x1 BOOT_BLK_CNT Stop At Block Gap value of automatic mode 16 16 read-write VEND_SPEC2 Vendor Specific 2 Register 0xC8 32 read-write 0x19006 0xFFFFFFFF CARD_INT_D3_TEST Card interrupt detection test 3 1 read-write CARD_INT_D3_TEST_0 Check the card interrupt only when DATA3 is high. 0 CARD_INT_D3_TEST_1 Check the card interrupt by ignoring the status of DATA3. 0x1 TUNING_8bit_EN Tuning 8bit enable 4 1 read-write TUNING_1bit_EN Tuning 1bit enable 5 1 read-write TUNING_CMD_EN Tuning command enable 6 1 read-write TUNING_CMD_EN_0 Auto tuning circuit does not check the CMD line. 0 TUNING_CMD_EN_1 Auto tuning circuit checks the CMD line. 0x1 HS400_WR_CLK_STOP_EN HS400 write clock stop enable 10 1 read-write HS400_RD_CLK_STOP_EN HS400 read clock stop enable 11 1 read-write ACMD23_ARGU2_EN Argument2 register enable for ACMD23 12 1 read-write ACMD23_ARGU2_EN_0 Disable 0 ACMD23_ARGU2_EN_1 Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. 0x1 TUNING_CTRL Tuning Control 0xCC 32 read-write 0x212800 0xFFFFFFFF TUNING_START_TAP Tuning start 0 7 read-write DIS_CMD_CHK_FOR_STD_TUNING Disable command check for standard tuning 7 1 read-write TUNING_COUNTER Tuning counter 8 8 read-write TUNING_STEP TUNING_STEP 16 3 read-write TUNING_WINDOW Data window 20 3 read-write STD_TUNING_EN Standard tuning circuit and procedure enable 24 1 read-write USDHC2 uSDHC USDHC 0x4041C000 0 0xD0 registers USDHC2 134 ENET_1G ENET ENET 0x40420000 0 0x628 registers ENET_1G_MAC0_Tx_Rx_1 139 ENET_1G_MAC0_Tx_Rx_2 140 ENET_1G 141 ENET_1G_1588_Timer 142 EIR Interrupt Event Register 0x4 32 read-write 0 0xFFFFFFFF oneToClear RXB1 Receive buffer interrupt, class 1 0 1 read-write oneToClear RXF1 Receive frame interrupt, class 1 1 1 read-write oneToClear TXB1 Transmit buffer interrupt, class 1 2 1 read-write oneToClear TXF1 Transmit frame interrupt, class 1 3 1 read-write oneToClear RXB2 Receive buffer interrupt, class 2 4 1 read-write oneToClear RXF2 Receive frame interrupt, class 2 5 1 read-write oneToClear TXB2 Transmit buffer interrupt, class 2 6 1 read-write oneToClear TXF2 Transmit frame interrupt, class 2 7 1 read-write oneToClear RXFLUSH_0 RX DMA Ring 0 flush indication 12 1 read-write oneToClear RXFLUSH_1 RX DMA Ring 1 flush indication 13 1 read-write oneToClear RXFLUSH_2 RX DMA Ring 2 flush indication 14 1 read-write oneToClear TS_TIMER Timestamp Timer 15 1 read-write oneToClear TS_AVAIL Transmit Timestamp Available 16 1 read-write oneToClear WAKEUP Node Wakeup Request Indication 17 1 read-write oneToClear PLR Payload Receive Error 18 1 read-write oneToClear UN Transmit FIFO Underrun 19 1 read-write oneToClear RL Collision Retry Limit 20 1 read-write oneToClear LC Late Collision 21 1 read-write oneToClear EBERR Ethernet Bus Error 22 1 read-write oneToClear MII MII Interrupt. 23 1 read-write oneToClear RXB Receive Buffer Interrupt 24 1 read-write oneToClear RXF Receive Frame Interrupt 25 1 read-write oneToClear TXB Transmit Buffer Interrupt 26 1 read-write oneToClear TXF Transmit Frame Interrupt 27 1 read-write oneToClear GRA Graceful Stop Complete 28 1 read-write oneToClear BABT Babbling Transmit Error 29 1 read-write oneToClear BABR Babbling Receive Error 30 1 read-write oneToClear EIMR Interrupt Mask Register 0x8 32 read-write 0 0xFFFFFFFF RXB1 Receive buffer interrupt, class 1 0 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RXF1 Receive frame interrupt, class 1 1 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 TXB1 Transmit buffer interrupt, class 1 2 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 TXF1 Transmit frame interrupt, class 1 3 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RXB2 Receive buffer interrupt, class 2 4 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RXF2 Receive frame interrupt, class 2 5 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 TXB2 Transmit buffer interrupt, class 2 6 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 TXF2 Transmit frame interrupt, class 2 7 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RXFLUSH_0 Corresponds to interrupt source EIR[RXFLUSH_0] and determines whether an interrupt condition can generate an interrupt 12 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RXFLUSH_1 Corresponds to interrupt source EIR[RXFLUSH_1] and determines whether an interrupt condition can generate an interrupt 13 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RXFLUSH_2 Corresponds to interrupt source EIR[RXFLUSH_2] and determines whether an interrupt condition can generate an interrupt 14 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 TS_TIMER TS_TIMER Interrupt Mask 15 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 TS_AVAIL TS_AVAIL Interrupt Mask 16 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 WAKEUP WAKEUP Interrupt Mask 17 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 PLR PLR Interrupt Mask 18 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 UN UN Interrupt Mask 19 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RL RL Interrupt Mask 20 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 LC LC Interrupt Mask 21 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 EBERR EBERR Interrupt Mask 22 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 MII MII Interrupt Mask 23 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RXB RXB Interrupt Mask 24 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RXF RXF Interrupt Mask 25 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 TXB TXB Interrupt Mask 26 1 read-write MASKED The corresponding interrupt source is masked. 0 UNMASKED The corresponding interrupt source is not masked. 0x1 TXF TXF Interrupt Mask 27 1 read-write MASKED The corresponding interrupt source is masked. 0 UNMASKED The corresponding interrupt source is not masked. 0x1 GRA GRA Interrupt Mask 28 1 read-write MASKED The corresponding interrupt source is masked. 0 UMASKED The corresponding interrupt source is not masked. 0x1 BABT BABT Interrupt Mask 29 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 BABR BABR Interrupt Mask 30 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RDAR Receive Descriptor Active Register - Ring 0 0x10 32 read-write 0 0xFFFFFFFF RDAR Receive Descriptor Active 24 1 read-write TDAR Transmit Descriptor Active Register - Ring 0 0x14 32 read-write 0 0xFFFFFFFF TDAR Transmit Descriptor Active 24 1 read-write ECR Ethernet Control Register 0x24 32 read-write 0x70000000 0xFFFFFFFF RESET Ethernet MAC Reset 0 1 read-write ETHEREN Ethernet Enable 1 1 read-write ZERO Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0 ONE MAC is enabled, and reception and transmission are possible. 0x1 MAGICEN Magic Packet Detection Enable 2 1 read-write ZERO Magic detection logic disabled. 0 ONE The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. 0x1 SLEEP Sleep Mode Enable 3 1 read-write ZERO Normal operating mode. 0 ONE Sleep mode. 0x1 EN1588 EN1588 Enable 4 1 read-write ZERO Legacy FEC buffer descriptors and functions enabled. 0 ONE Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588. 0x1 SPEED Selects between 10/100-Mbit/s and 1000-Mbit/s modes of operation. 5 1 read-write ZERO 10/100-Mbit/s mode 0 ONE 1000-Mbit/s mode 0x1 DBGEN Debug Enable 6 1 read-write ZERO MAC continues operation in debug mode. 0 ONE MAC enters hardware freeze mode when the processor is in debug mode. 0x1 DBSWP Descriptor Byte Swapping Enable 8 1 read-write ZERO The buffer descriptor bytes are not swapped to support big-endian devices. 0 ONE The buffer descriptor bytes are swapped to support little-endian devices. 0x1 SVLANEN S-VLAN enable 9 1 read-write ZERO Only the EtherType 0x8100 will be considered for VLAN detection. 0 ONE The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the classification match comparators, RCMRn. 0x1 VLANUSE2ND VLAN use second tag 10 1 read-write ZERO Always extract data from the first VLAN tag if it exists. 0 ONE When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The second tag must be a C-VLAN 0x1 SVLANDBL S-VLAN double tag 11 1 read-write ZERO Disable S-VLAN double tag 0 ONE Enable S-VLAN double tag 0x1 TXC_DLY Transmit clock delay 16 1 read-write ZERO RGMII_TXC is not delayed. 0 ONE Generate delayed version of RGMII_TXC. 0x1 MMFR MII Management Frame Register 0x40 32 read-write 0 0xFFFFFFFF DATA Management Frame Data 0 16 read-write TA Turn Around 16 2 read-write RA Register Address 18 5 read-write PA PHY Address 23 5 read-write OP Operation Code 28 2 read-write ST Start Of Frame Delimiter 30 2 read-write MSCR MII Speed Control Register 0x44 32 read-write 0 0xFFFFFFFF MII_SPEED MII Speed 1 6 read-write DIS_PRE Disable Preamble 7 1 read-write ZERO Preamble enabled. 0 ONE Preamble (32 ones) is not prepended to the MII management frame. 0x1 HOLDTIME Hold time On MDIO Output 8 3 read-write VAL_1 1 internal module clock cycle 0 VAL2 2 internal module clock cycles 0x1 VAL3 3 internal module clock cycles 0x2 VAL8 8 internal module clock cycles 0x7 MIBC MIB Control Register 0x64 32 read-write 0xC0000000 0xFFFFFFFF MIB_CLEAR MIB Clear 29 1 read-write ZERO See note above. 0 ONE All statistics counters are reset to 0. 0x1 MIB_IDLE MIB Idle 30 1 read-only ZERO The MIB block is updating MIB counters. 0 ONE The MIB block is not currently updating any MIB counters. 0x1 MIB_DIS Disable MIB Logic 31 1 read-write ZERO MIB logic is enabled. 0 ONE MIB logic is disabled. The MIB logic halts and does not update any MIB counters. 0x1 RCR Receive Control Register 0x84 32 read-write 0x5EE0001 0xFFFFFFFF LOOP Internal Loopback 0 1 read-write ZERO Loopback disabled. 0 ONE Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. 0x1 DRT Disable Receive On Transmit 1 1 read-write ZERO Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0 ONE Disable reception of frames while transmitting. (Normally used for half-duplex mode.) 0x1 MII_MODE Media Independent Interface Mode 2 1 read-write ONE MII or RMII mode, as indicated by the RMII_MODE field. 0x1 PROM Promiscuous Mode 3 1 read-write ZERO Disabled. 0 ONE Enabled. 0x1 BC_REJ Broadcast Frame Reject 4 1 read-write ZERO Will not reject frames as described above 0 ONE Will reject frames as described above 0x1 FCE Flow Control Enable 5 1 read-write ZERO Disable flow control 0 ONE Enable flow control 0x1 RGMII_EN RGMII Mode Enable 6 1 read-write ZERO MAC configured for non-RGMII operation 0 ONE MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode. 0x1 RMII_MODE RMII Mode Enable 8 1 read-write ZERO MAC configured for MII mode. 0 ONE MAC configured for RMII operation. 0x1 RMII_10T Enables 10-Mbit/s mode of the RMII or RGMII . 9 1 read-write ZERO 100-Mbit/s or 1-Gbit/s operation. 0 ONE 10-Mbit/s operation. 0x1 PADEN Enable Frame Padding Remove On Receive 12 1 read-write ZERO No padding is removed on receive by the MAC. 0 ONE Padding is removed from received frames. 0x1 PAUFWD Terminate/Forward Pause Frames 13 1 read-write ZERO Pause frames are terminated and discarded in the MAC. 0 ONE Pause frames are forwarded to the user application. 0x1 CRCFWD Terminate/Forward Received CRC 14 1 read-write ZERO The CRC field of received frames is transmitted to the user application. 0 ONE The CRC field is stripped from the frame. 0x1 CFEN MAC Control Frame Enable 15 1 read-write ZERO MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0 ONE MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. 0x1 MAX_FL Maximum Frame Length 16 14 read-write NLC Payload Length Check Disable 30 1 read-write ZERO The payload length check is disabled. 0 ONE The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. 0x1 GRS Graceful Receive Stopped 31 1 read-only ZERO Receive not stopped 0 ONE Receive stopped 0x1 TCR Transmit Control Register 0xC4 32 read-write 0 0xFFFFFFFF GTS Graceful Transmit Stop 0 1 read-write ZERO Disable graceful transmit stop 0 ONE Enable graceful transmit stop 0x1 FDEN Full-Duplex Enable 2 1 read-write ZERO Disable full-duplex 0 ONE Enable full-duplex 0x1 TFC_PAUSE Transmit Frame Control Pause 3 1 read-write ZERO No PAUSE frame transmitted. 0 ONE The MAC stops transmission of data frames after the current transmission is complete. 0x1 RFC_PAUSE Receive Frame Control Pause 4 1 read-only ADDSEL Source MAC Address Select On Transmit 5 3 read-write VAL_MAC Node MAC address programmed on PADDR1/2 registers. 0 ADDINS Set MAC Address On Transmit 8 1 read-write ZERO The source MAC address is not modified by the MAC. 0 ONE The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. 0x1 CRCFWD Forward Frame From Application With CRC 9 1 read-write ZERO TxBD[TC] controls whether the frame has a CRC from the application. 0 ONE The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. 0x1 PALR Physical Address Lower Register 0xE4 32 read-write 0 0xFFFFFFFF PADDR1 Pause Address 0 32 read-write PAUR Physical Address Upper Register 0xE8 32 read-write 0x8808 0xFFFFFFFF TYPE Type Field In PAUSE Frames 0 16 read-only PADDR2 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames 16 16 read-write OPD Opcode/Pause Duration Register 0xEC 32 read-write 0x10000 0xFFFFFFFF PAUSE_DUR Pause Duration 0 16 read-write OPCODE Opcode Field In PAUSE Frames 16 16 read-only 3 0x4 TXIC[%s] Transmit Interrupt Coalescing Register 0xF0 32 read-write 0 0xFFFFFFFF ICTT Interrupt coalescing timer threshold 0 16 read-write ICFT Interrupt coalescing frame count threshold 20 8 read-write ICCS Interrupt Coalescing Timer Clock Source Select 30 1 read-write ZERO Use MII/GMII TX clocks. 0 ONE Use ENET system clock. 0x1 ICEN Interrupt Coalescing Enable 31 1 read-write ZERO Disable Interrupt coalescing. 0 ONE Enable Interrupt coalescing. 0x1 3 0x4 RXIC[%s] Receive Interrupt Coalescing Register 0x100 32 read-write 0 0xFFFFFFFF ICTT Interrupt coalescing timer threshold 0 16 read-write ICFT Interrupt coalescing frame count threshold 20 8 read-write ICCS Interrupt Coalescing Timer Clock Source Select 30 1 read-write ZERO Use MII/GMII TX clocks. 0 ONE Use ENET system clock. 0x1 ICEN Interrupt Coalescing Enable 31 1 read-write ZERO Disable Interrupt coalescing. 0 ONE Enable Interrupt coalescing. 0x1 IAUR Descriptor Individual Upper Address Register 0x118 32 read-write 0 0xFFFFFFFF IADDR1 Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address 0 32 read-write IALR Descriptor Individual Lower Address Register 0x11C 32 read-write 0 0xFFFFFFFF IADDR2 Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address 0 32 read-write GAUR Descriptor Group Upper Address Register 0x120 32 read-write 0 0xFFFFFFFF GADDR1 Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address 0 32 read-write GALR Descriptor Group Lower Address Register 0x124 32 read-write 0 0xFFFFFFFF GADDR2 Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address 0 32 read-write TFWR Transmit FIFO Watermark Register 0x144 32 read-write 0 0xFFFFFFFF TFWR Transmit FIFO Write 0 6 read-write VAL64_0 64 bytes written. 0 VAL64_1 64 bytes written. 0x1 VAL128 128 bytes written. 0x2 VAL192 192 bytes written. 0x3 VAL4032 4032 bytes written. 0x3F STRFWD Store And Forward Enable 8 1 read-write ZERO Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0 ONE Enabled. 0x1 RDSR1 Receive Descriptor Ring 1 Start Register 0x160 32 read-write 0 0xFFFFFFFF R_DES_START Pointer to the beginning of the receive buffer descriptor queue 1. 3 29 read-write TDSR1 Transmit Buffer Descriptor Ring 1 Start Register 0x164 32 read-write 0 0xFFFFFFFF X_DES_START Pointer to the beginning of transmit buffer descriptor queue 1. 3 29 read-write MRBR1 Maximum Receive Buffer Size Register - Ring 1 0x168 32 read-write 0 0xFFFFFFFF R_BUF_SIZE Receive buffer size (in bytes) 4 7 read-write RDSR2 Receive Descriptor Ring 2 Start Register 0x16C 32 read-write 0 0xFFFFFFFF R_DES_START Pointer to the beginning of receive buffer descriptor queue 2. 3 29 read-write TDSR2 Transmit Buffer Descriptor Ring 2 Start Register 0x170 32 read-write 0 0xFFFFFFFF X_DES_START Pointer to the beginning of transmit buffer descriptor queue 2. 3 29 read-write MRBR2 Maximum Receive Buffer Size Register - Ring 2 0x174 32 read-write 0 0xFFFFFFFF R_BUF_SIZE Receive buffer size (in bytes) 4 7 read-write RDSR Receive Descriptor Ring 0 Start Register 0x180 32 read-write 0 0xFFFFFFFF R_DES_START Pointer to the beginning of the receive buffer descriptor queue. 0 3 29 read-write TDSR Transmit Buffer Descriptor Ring 0 Start Register 0x184 32 read-write 0 0xFFFFFFFF X_DES_START Pointer to the beginning of the transmit buffer descriptor queue. 3 29 read-write MRBR Maximum Receive Buffer Size Register - Ring 0 0x188 32 read-write 0 0xFFFFFFFF R_BUF_SIZE Receive buffer size in bytes 4 7 read-write RSFL Receive FIFO Section Full Threshold 0x190 32 read-write 0 0xFFFFFFFF RX_SECTION_FULL Value Of Receive FIFO Section Full Threshold 0 10 read-write RSEM Receive FIFO Section Empty Threshold 0x194 32 read-write 0 0xFFFFFFFF RX_SECTION_EMPTY Value Of The Receive FIFO Section Empty Threshold 0 10 read-write STAT_SECTION_EMPTY RX Status FIFO Section Empty Threshold 16 5 read-write RAEM Receive FIFO Almost Empty Threshold 0x198 32 read-write 0x4 0xFFFFFFFF RX_ALMOST_EMPTY Value Of The Receive FIFO Almost Empty Threshold 0 10 read-write RAFL Receive FIFO Almost Full Threshold 0x19C 32 read-write 0x4 0xFFFFFFFF RX_ALMOST_FULL Value Of The Receive FIFO Almost Full Threshold 0 10 read-write TSEM Transmit FIFO Section Empty Threshold 0x1A0 32 read-write 0 0xFFFFFFFF TX_SECTION_EMPTY Value Of The Transmit FIFO Section Empty Threshold 0 10 read-write TAEM Transmit FIFO Almost Empty Threshold 0x1A4 32 read-write 0x4 0xFFFFFFFF TX_ALMOST_EMPTY Value of Transmit FIFO Almost Empty Threshold 0 10 read-write TAFL Transmit FIFO Almost Full Threshold 0x1A8 32 read-write 0x8 0xFFFFFFFF TX_ALMOST_FULL Value Of The Transmit FIFO Almost Full Threshold 0 10 read-write TIPG Transmit Inter-Packet Gap 0x1AC 32 read-write 0xC 0xFFFFFFFF IPG Transmit Inter-Packet Gap 0 5 read-write FTRL Frame Truncation Length 0x1B0 32 read-write 0x7FF 0xFFFFFFFF TRUNC_FL Frame Truncation Length 0 14 read-write TACC Transmit Accelerator Function Configuration 0x1C0 32 read-write 0 0xFFFFFFFF SHIFT16 TX FIFO Shift-16 0 1 read-write ZERO Disabled. 0 ONE Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. 0x1 IPCHK Enables insertion of IP header checksum. 3 1 read-write ZERO Checksum is not inserted. 0 ONE If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. 0x1 PROCHK Enables insertion of protocol checksum. 4 1 read-write ZERO Checksum not inserted. 0 ONE If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. 0x1 RACC Receive Accelerator Function Configuration 0x1C4 32 read-write 0 0xFFFFFFFF PADREM Enable Padding Removal For Short IP Frames 0 1 read-write ZERO Padding not removed. 0 ONE Any bytes following the IP payload section of the frame are removed from the frame. 0x1 IPDIS Enable Discard Of Frames With Wrong IPv4 Header Checksum 1 1 read-write ZERO Frames with wrong IPv4 header checksum are not discarded. 0 ONE If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). 0x1 PRODIS Enable Discard Of Frames With Wrong Protocol Checksum 2 1 read-write ZERO Frames with wrong checksum are not discarded. 0 ONE If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). 0x1 LINEDIS Enable Discard Of Frames With MAC Layer Errors 6 1 read-write ZERO Frames with errors are not discarded. 0 ONE Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. 0x1 SHIFT16 RX FIFO Shift-16 7 1 read-write ZERO Disabled. 0 ONE Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. 0x1 2 0x4 1,2 RCMR%s Receive Classification Match Register for Class n 0x1C8 32 read-write 0 0xFFFFFFFF CMP0 Compare 0 0 3 read-write CMP1 Compare 1 4 3 read-write CMP2 Compare 2 8 3 read-write CMP3 Compare 3 12 3 read-write MATCHEN Match Enable 16 1 read-write ZERO Disabled (default): no compares will occur and the classification indicator for this class will never assert. 0 ONE The register contents are valid and a comparison with all compare values is done when a VLAN frame is received. 0x1 2 0x4 1,2 DMACFG%s DMA Class Based Configuration 0x1D8 32 read-write 0 0xFFFFFFFF IDLE_SLOPE Idle slope 0 16 read-write DMA_CLASS_EN DMA class enable 16 1 read-write ZERO The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2 queues are disabled then their frames will be placed in queue 0. 0 ONE Enable the DMA controller to support the corresponding descriptor ring for this class of traffic. 0x1 CALC_NOIPG Calculate no IPG 17 1 read-write ZERO The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations. This is the default. 0 ONE Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping, when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames will become more bandwidth than large frames due to the relation of data to IPG overhead). 0x1 RDAR1 Receive Descriptor Active Register - Ring 1 0x1E0 32 read-write 0 0xFFFFFFFF RDAR Receive Descriptor Active 24 1 read-write TDAR1 Transmit Descriptor Active Register - Ring 1 0x1E4 32 read-write 0 0xFFFFFFFF TDAR Transmit Descriptor Active 24 1 read-write RDAR2 Receive Descriptor Active Register - Ring 2 0x1E8 32 read-write 0 0xFFFFFFFF RDAR Receive Descriptor Active 24 1 read-write TDAR2 Transmit Descriptor Active Register - Ring 2 0x1EC 32 read-write 0 0xFFFFFFFF TDAR Transmit Descriptor Active 24 1 read-write QOS QOS Scheme 0x1F0 32 read-write 0 0xFFFFFFFF TX_SCHEME TX scheme configuration 0 3 read-write CREDIT Credit-based scheme 0 RR Round-robin scheme 0x1 RX_FLUSH0 RX Flush Ring 0 3 1 read-write ZERO Disable 0 ONE Enable 0x1 RX_FLUSH1 RX Flush Ring 1 4 1 read-write ZERO Disable 0 ONE Enable 0x1 RX_FLUSH2 RX Flush Ring 2 5 1 read-write ZERO Disable 0 ONE Enable 0x1 RMON_T_PACKETS Tx Packet Count Statistic Register 0x204 32 read-only 0 0xFFFFFFFF TXPKTS Packet count 0 16 read-only RMON_T_BC_PKT Tx Broadcast Packets Statistic Register 0x208 32 read-only 0 0xFFFFFFFF TXPKTS Broadcast packets 0 16 read-only RMON_T_MC_PKT Tx Multicast Packets Statistic Register 0x20C 32 read-only 0 0xFFFFFFFF TXPKTS Multicast packets 0 16 read-only RMON_T_CRC_ALIGN Tx Packets with CRC/Align Error Statistic Register 0x210 32 read-only 0 0xFFFFFFFF TXPKTS Packets with CRC/align error 0 16 read-only RMON_T_UNDERSIZE Tx Packets Less Than Bytes and Good CRC Statistic Register 0x214 32 read-only 0 0xFFFFFFFF TXPKTS Number of transmit packets less than 64 bytes with good CRC 0 16 read-only RMON_T_OVERSIZE Tx Packets GT MAX_FL bytes and Good CRC Statistic Register 0x218 32 read-only 0 0xFFFFFFFF TXPKTS Number of transmit packets greater than MAX_FL bytes with good CRC 0 16 read-only RMON_T_FRAG Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register 0x21C 32 read-only 0 0xFFFFFFFF TXPKTS Number of packets less than 64 bytes with bad CRC 0 16 read-only RMON_T_JAB Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register 0x220 32 read-only 0 0xFFFFFFFF TXPKTS Number of transmit packets greater than MAX_FL bytes and bad CRC 0 16 read-only RMON_T_COL Tx Collision Count Statistic Register 0x224 32 read-only 0 0xFFFFFFFF TXPKTS Number of transmit collisions 0 16 read-only RMON_T_P64 Tx 64-Byte Packets Statistic Register 0x228 32 read-only 0 0xFFFFFFFF TXPKTS Number of 64-byte transmit packets 0 16 read-only RMON_T_P65TO127 Tx 65- to 127-byte Packets Statistic Register 0x22C 32 read-only 0 0xFFFFFFFF TXPKTS Number of 65- to 127-byte transmit packets 0 16 read-only RMON_T_P128TO255 Tx 128- to 255-byte Packets Statistic Register 0x230 32 read-only 0 0xFFFFFFFF TXPKTS Number of 128- to 255-byte transmit packets 0 16 read-only RMON_T_P256TO511 Tx 256- to 511-byte Packets Statistic Register 0x234 32 read-only 0 0xFFFFFFFF TXPKTS Number of 256- to 511-byte transmit packets 0 16 read-only RMON_T_P512TO1023 Tx 512- to 1023-byte Packets Statistic Register 0x238 32 read-only 0 0xFFFFFFFF TXPKTS Number of 512- to 1023-byte transmit packets 0 16 read-only RMON_T_P1024TO2047 Tx 1024- to 2047-byte Packets Statistic Register 0x23C 32 read-only 0 0xFFFFFFFF TXPKTS Number of 1024- to 2047-byte transmit packets 0 16 read-only RMON_T_P_GTE2048 Tx Packets Greater Than 2048 Bytes Statistic Register 0x240 32 read-only 0 0xFFFFFFFF TXPKTS Number of transmit packets greater than 2048 bytes 0 16 read-only RMON_T_OCTETS Tx Octets Statistic Register 0x244 32 read-only 0 0xFFFFFFFF TXOCTS Number of transmit octets 0 32 read-only IEEE_T_DROP Reserved Statistic Register 0x248 32 read-only 0 0xFFFFFFFF IEEE_T_FRAME_OK Frames Transmitted OK Statistic Register 0x24C 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted OK 0 16 read-only IEEE_T_1COL Frames Transmitted with Single Collision Statistic Register 0x250 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with one collision 0 16 read-only IEEE_T_MCOL Frames Transmitted with Multiple Collisions Statistic Register 0x254 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with multiple collisions 0 16 read-only IEEE_T_DEF Frames Transmitted after Deferral Delay Statistic Register 0x258 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with deferral delay 0 16 read-only IEEE_T_LCOL Frames Transmitted with Late Collision Statistic Register 0x25C 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with late collision 0 16 read-only IEEE_T_EXCOL Frames Transmitted with Excessive Collisions Statistic Register 0x260 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with excessive collisions 0 16 read-only IEEE_T_MACERR Frames Transmitted with Tx FIFO Underrun Statistic Register 0x264 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with transmit FIFO underrun 0 16 read-only IEEE_T_CSERR Frames Transmitted with Carrier Sense Error Statistic Register 0x268 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with carrier sense error 0 16 read-only IEEE_T_SQE Reserved Statistic Register 0x26C 32 read-only 0 0xFFFFFFFF COUNT This read-only field is reserved and always has the value 0 0 16 read-only IEEE_T_FDXFC Flow Control Pause Frames Transmitted Statistic Register 0x270 32 read-only 0 0xFFFFFFFF COUNT Number of flow-control pause frames transmitted 0 16 read-only IEEE_T_OCTETS_OK Octet Count for Frames Transmitted w/o Error Statistic Register 0x274 32 read-only 0 0xFFFFFFFF COUNT Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). 0 32 read-only RMON_R_PACKETS Rx Packet Count Statistic Register 0x284 32 read-only 0 0xFFFFFFFF COUNT Number of packets received 0 16 read-only RMON_R_BC_PKT Rx Broadcast Packets Statistic Register 0x288 32 read-only 0 0xFFFFFFFF COUNT Number of receive broadcast packets 0 16 read-only RMON_R_MC_PKT Rx Multicast Packets Statistic Register 0x28C 32 read-only 0 0xFFFFFFFF COUNT Number of receive multicast packets 0 16 read-only RMON_R_CRC_ALIGN Rx Packets with CRC/Align Error Statistic Register 0x290 32 read-only 0 0xFFFFFFFF COUNT Number of receive packets with CRC or align error 0 16 read-only RMON_R_UNDERSIZE Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register 0x294 32 read-only 0 0xFFFFFFFF COUNT Number of receive packets with less than 64 bytes and good CRC 0 16 read-only RMON_R_OVERSIZE Rx Packets Greater Than MAX_FL and Good CRC Statistic Register 0x298 32 read-only 0 0xFFFFFFFF COUNT Number of receive packets greater than MAX_FL and good CRC 0 16 read-only RMON_R_FRAG Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register 0x29C 32 read-only 0 0xFFFFFFFF COUNT Number of receive packets with less than 64 bytes and bad CRC 0 16 read-only RMON_R_JAB Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register 0x2A0 32 read-only 0 0xFFFFFFFF COUNT Number of receive packets greater than MAX_FL and bad CRC 0 16 read-only RMON_R_P64 Rx 64-Byte Packets Statistic Register 0x2A8 32 read-only 0 0xFFFFFFFF COUNT Number of 64-byte receive packets 0 16 read-only RMON_R_P65TO127 Rx 65- to 127-Byte Packets Statistic Register 0x2AC 32 read-only 0 0xFFFFFFFF COUNT Number of 65- to 127-byte recieve packets 0 16 read-only RMON_R_P128TO255 Rx 128- to 255-Byte Packets Statistic Register 0x2B0 32 read-only 0 0xFFFFFFFF COUNT Number of 128- to 255-byte recieve packets 0 16 read-only RMON_R_P256TO511 Rx 256- to 511-Byte Packets Statistic Register 0x2B4 32 read-only 0 0xFFFFFFFF COUNT Number of 256- to 511-byte recieve packets 0 16 read-only RMON_R_P512TO1023 Rx 512- to 1023-Byte Packets Statistic Register 0x2B8 32 read-only 0 0xFFFFFFFF COUNT Number of 512- to 1023-byte recieve packets 0 16 read-only RMON_R_P1024TO2047 Rx 1024- to 2047-Byte Packets Statistic Register 0x2BC 32 read-only 0 0xFFFFFFFF COUNT Number of 1024- to 2047-byte recieve packets 0 16 read-only RMON_R_P_GTE2048 Rx Packets Greater than 2048 Bytes Statistic Register 0x2C0 32 read-only 0 0xFFFFFFFF COUNT Number of greater-than-2048-byte recieve packets 0 16 read-only RMON_R_OCTETS Rx Octets Statistic Register 0x2C4 32 read-only 0 0xFFFFFFFF COUNT Number of receive octets 0 32 read-only IEEE_R_DROP Frames not Counted Correctly Statistic Register 0x2C8 32 read-only 0 0xFFFFFFFF COUNT Frame count 0 16 read-only IEEE_R_FRAME_OK Frames Received OK Statistic Register 0x2CC 32 read-only 0 0xFFFFFFFF COUNT Number of frames received OK 0 16 read-only IEEE_R_CRC Frames Received with CRC Error Statistic Register 0x2D0 32 read-only 0 0xFFFFFFFF COUNT Number of frames received with CRC error 0 16 read-only IEEE_R_ALIGN Frames Received with Alignment Error Statistic Register 0x2D4 32 read-only 0 0xFFFFFFFF COUNT Number of frames received with alignment error 0 16 read-only IEEE_R_MACERR Receive FIFO Overflow Count Statistic Register 0x2D8 32 read-only 0 0xFFFFFFFF COUNT Receive FIFO overflow count 0 16 read-only IEEE_R_FDXFC Flow Control Pause Frames Received Statistic Register 0x2DC 32 read-only 0 0xFFFFFFFF COUNT Number of flow-control pause frames received 0 16 read-only IEEE_R_OCTETS_OK Octet Count for Frames Received without Error Statistic Register 0x2E0 32 read-only 0 0xFFFFFFFF COUNT Number of octets for frames received without error 0 32 read-only ATCR Adjustable Timer Control Register 0x400 32 read-write 0 0xFFFFFFFF EN Enable Timer 0 1 read-write ZERO The timer stops at the current value. 0 ONE The timer starts incrementing. 0x1 OFFEN Enable One-Shot Offset Event 2 1 read-write ZERO Disable. 0 ONE The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. 0x1 OFFRST Reset Timer On Offset Event 3 1 read-write ZERO The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0 ONE If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. 0x1 PEREN Enable Periodical Event 4 1 read-write ZERO Disable. 0 ONE A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. 0x1 PINPER Enables event signal output external pin frc_evt_period assertion on period event 7 1 read-write ZERO Disable. 0 ONE Enable. 0x1 RESTART Reset Timer 9 1 read-write CAPTURE Capture Timer Value 11 1 read-write ZERO No effect. 0 ONE The current time is captured and can be read from the ATVR register. 0x1 SLAVE Enable Timer Slave Mode 13 1 read-write ZERO The timer is active and all configuration fields in this register are relevant. 0 ONE The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. 0x1 ATVR Timer Value Register 0x404 32 read-write 0 0xFFFFFFFF ATIME A write sets the timer 0 32 read-write ATOFF Timer Offset Register 0x408 32 read-write 0 0xFFFFFFFF OFFSET Offset value for one-shot event generation 0 32 read-write ATPER Timer Period Register 0x40C 32 read-write 0x3B9ACA00 0xFFFFFFFF PERIOD Value for generating periodic events 0 32 read-write ATCOR Timer Correction Register 0x410 32 read-write 0 0xFFFFFFFF COR Correction Counter Wrap-Around Value 0 31 read-write ATINC Time-Stamping Clock Period Register 0x414 32 read-write 0 0xFFFFFFFF INC Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds 0 7 read-write INC_CORR Correction Increment Value 8 7 read-write ATSTMP Timestamp of Last Transmitted Frame 0x418 32 read-only 0 0xFFFFFFFF TIMESTAMP Timestamp of the last frame transmitted by the core that had TxBD[TS] set the ff_tx_ts_frm signal asserted from the user application 0 32 read-only TGSR Timer Global Status Register 0x604 32 read-write 0 0xFFFFFFFF oneToClear TF0 Copy Of Timer Flag For Channel 0 0 1 read-write oneToClear ZERO Timer Flag for Channel 0 is clear 0 ONE Timer Flag for Channel 0 is set 0x1 TF1 Copy Of Timer Flag For Channel 1 1 1 read-write oneToClear ZERO Timer Flag for Channel 1 is clear 0 ONE Timer Flag for Channel 1 is set 0x1 TF2 Copy Of Timer Flag For Channel 2 2 1 read-write oneToClear ZERO Timer Flag for Channel 2 is clear 0 ONE Timer Flag for Channel 2 is set 0x1 TF3 Copy Of Timer Flag For Channel 3 3 1 read-write oneToClear ZERO Timer Flag for Channel 3 is clear 0 ONE Timer Flag for Channel 3 is set 0x1 TCSR0 Timer Control Status Register 0x608 32 read-write 0 0xFFFFFFFF TDRE Timer DMA Request Enable 0 1 read-write ZERO DMA request is disabled 0 ONE DMA request is enabled 0x1 TMODE Timer Mode 2 4 read-write TMR_DIS Timer Channel is disabled. 0 TMR_RE Timer Channel is configured for Input Capture on rising edge. 0x1 TMR_FE Timer Channel is configured for Input Capture on falling edge. 0x2 TMR_BE Timer Channel is configured for Input Capture on both edges. 0x3 TMR_OUT Timer Channel is configured for Output Compare - software only. 0x4 TMR_TOGGLE Timer Channel is configured for Output Compare - toggle output on compare. 0x5 TMR_CLR Timer Channel is configured for Output Compare - clear output on compare. 0x6 TMR_SET_OUT Timer Channel is configured for Output Compare - set output on compare. 0x7 TMR_CLR_SET1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. #10x1 TMR_CLR_SET Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0xA TMR_OUT_CMP_LOW Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0xE TMR_OUT_CMP_HIGH Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle. 0xF TIE Timer Interrupt Enable 6 1 read-write ZERO Interrupt is disabled 0 ONE Interrupt is enabled 0x1 TF Timer Flag 7 1 read-write oneToClear ZERO Input Capture or Output Compare has not occurred. 0 ONE Input Capture or Output Compare has occurred. 0x1 TCCR0 Timer Compare Capture Register 0x60C 32 read-write 0 0xFFFFFFFF TCC Timer Capture Compare 0 32 read-write TCSR1 Timer Control Status Register 0x610 32 read-write 0 0xFFFFFFFF TDRE Timer DMA Request Enable 0 1 read-write ZERO DMA request is disabled 0 ONE DMA request is enabled 0x1 TMODE Timer Mode 2 4 read-write TMR_DIS Timer Channel is disabled. 0 TMR_RE Timer Channel is configured for Input Capture on rising edge. 0x1 TMR_FE Timer Channel is configured for Input Capture on falling edge. 0x2 TMR_BE Timer Channel is configured for Input Capture on both edges. 0x3 TMR_OUT Timer Channel is configured for Output Compare - software only. 0x4 TMR_TOGGLE Timer Channel is configured for Output Compare - toggle output on compare. 0x5 TMR_CLR Timer Channel is configured for Output Compare - clear output on compare. 0x6 TMR_SET_OUT Timer Channel is configured for Output Compare - set output on compare. 0x7 TMR_CLR_SET1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. #10x1 TMR_CLR_SET Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0xA TMR_OUT_CMP_LOW Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0xE TMR_OUT_CMP_HIGH Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle. 0xF TIE Timer Interrupt Enable 6 1 read-write ZERO Interrupt is disabled 0 ONE Interrupt is enabled 0x1 TF Timer Flag 7 1 read-write oneToClear ZERO Input Capture or Output Compare has not occurred. 0 ONE Input Capture or Output Compare has occurred. 0x1 TCCR1 Timer Compare Capture Register 0x614 32 read-write 0 0xFFFFFFFF TCC Timer Capture Compare 0 32 read-write TCSR2 Timer Control Status Register 0x618 32 read-write 0 0xFFFFFFFF TDRE Timer DMA Request Enable 0 1 read-write ZERO DMA request is disabled 0 ONE DMA request is enabled 0x1 TMODE Timer Mode 2 4 read-write TMR_DIS Timer Channel is disabled. 0 TMR_RE Timer Channel is configured for Input Capture on rising edge. 0x1 TMR_FE Timer Channel is configured for Input Capture on falling edge. 0x2 TMR_BE Timer Channel is configured for Input Capture on both edges. 0x3 TMR_OUT Timer Channel is configured for Output Compare - software only. 0x4 TMR_TOGGLE Timer Channel is configured for Output Compare - toggle output on compare. 0x5 TMR_CLR Timer Channel is configured for Output Compare - clear output on compare. 0x6 TMR_SET_OUT Timer Channel is configured for Output Compare - set output on compare. 0x7 TMR_CLR_SET1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. #10x1 TMR_CLR_SET Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0xA TMR_OUT_CMP_LOW Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0xE TMR_OUT_CMP_HIGH Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle. 0xF TIE Timer Interrupt Enable 6 1 read-write ZERO Interrupt is disabled 0 ONE Interrupt is enabled 0x1 TF Timer Flag 7 1 read-write oneToClear ZERO Input Capture or Output Compare has not occurred. 0 ONE Input Capture or Output Compare has occurred. 0x1 TCCR2 Timer Compare Capture Register 0x61C 32 read-write 0 0xFFFFFFFF TCC Timer Capture Compare 0 32 read-write TCSR3 Timer Control Status Register 0x620 32 read-write 0 0xFFFFFFFF TDRE Timer DMA Request Enable 0 1 read-write ZERO DMA request is disabled 0 ONE DMA request is enabled 0x1 TMODE Timer Mode 2 4 read-write TMR_DIS Timer Channel is disabled. 0 TMR_RE Timer Channel is configured for Input Capture on rising edge. 0x1 TMR_FE Timer Channel is configured for Input Capture on falling edge. 0x2 TMR_BE Timer Channel is configured for Input Capture on both edges. 0x3 TMR_OUT Timer Channel is configured for Output Compare - software only. 0x4 TMR_TOGGLE Timer Channel is configured for Output Compare - toggle output on compare. 0x5 TMR_CLR Timer Channel is configured for Output Compare - clear output on compare. 0x6 TMR_SET_OUT Timer Channel is configured for Output Compare - set output on compare. 0x7 TMR_CLR_SET1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. #10x1 TMR_CLR_SET Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0xA TMR_OUT_CMP_LOW Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0xE TMR_OUT_CMP_HIGH Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle. 0xF TIE Timer Interrupt Enable 6 1 read-write ZERO Interrupt is disabled 0 ONE Interrupt is enabled 0x1 TF Timer Flag 7 1 read-write oneToClear ZERO Input Capture or Output Compare has not occurred. 0 ONE Input Capture or Output Compare has occurred. 0x1 TCCR3 Timer Compare Capture Register 0x624 32 read-write 0 0xFFFFFFFF TCC Timer Capture Compare 0 32 read-write ENET ENET ENET 0x40424000 0 0x628 registers ENET 137 ENET_1588_Timer 138 EIR Interrupt Event Register 0x4 32 read-write 0 0xFFFFFFFF oneToClear TS_TIMER Timestamp Timer 15 1 read-write oneToClear TS_AVAIL Transmit Timestamp Available 16 1 read-write oneToClear WAKEUP Node Wakeup Request Indication 17 1 read-write oneToClear PLR Payload Receive Error 18 1 read-write oneToClear UN Transmit FIFO Underrun 19 1 read-write oneToClear RL Collision Retry Limit 20 1 read-write oneToClear LC Late Collision 21 1 read-write oneToClear EBERR Ethernet Bus Error 22 1 read-write oneToClear MII MII Interrupt. 23 1 read-write oneToClear RXB Receive Buffer Interrupt 24 1 read-write oneToClear RXF Receive Frame Interrupt 25 1 read-write oneToClear TXB Transmit Buffer Interrupt 26 1 read-write oneToClear TXF Transmit Frame Interrupt 27 1 read-write oneToClear GRA Graceful Stop Complete 28 1 read-write oneToClear BABT Babbling Transmit Error 29 1 read-write oneToClear BABR Babbling Receive Error 30 1 read-write oneToClear EIMR Interrupt Mask Register 0x8 32 read-write 0 0xFFFFFFFF TS_TIMER TS_TIMER Interrupt Mask 15 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 TS_AVAIL TS_AVAIL Interrupt Mask 16 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 WAKEUP WAKEUP Interrupt Mask 17 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 PLR PLR Interrupt Mask 18 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 UN UN Interrupt Mask 19 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RL RL Interrupt Mask 20 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 LC LC Interrupt Mask 21 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 EBERR EBERR Interrupt Mask 22 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 MII MII Interrupt Mask 23 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RXB RXB Interrupt Mask 24 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RXF RXF Interrupt Mask 25 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 TXB TXB Interrupt Mask 26 1 read-write MASKED The corresponding interrupt source is masked. 0 UNMASKED The corresponding interrupt source is not masked. 0x1 TXF TXF Interrupt Mask 27 1 read-write MASKED The corresponding interrupt source is masked. 0 UNMASKED The corresponding interrupt source is not masked. 0x1 GRA GRA Interrupt Mask 28 1 read-write MASKED The corresponding interrupt source is masked. 0 UMASKED The corresponding interrupt source is not masked. 0x1 BABT BABT Interrupt Mask 29 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 BABR BABR Interrupt Mask 30 1 read-write ZERO The corresponding interrupt source is masked. 0 ONE The corresponding interrupt source is not masked. 0x1 RDAR Receive Descriptor Active Register - Ring 0 0x10 32 read-write 0 0xFFFFFFFF RDAR Receive Descriptor Active 24 1 read-write TDAR Transmit Descriptor Active Register - Ring 0 0x14 32 read-write 0 0xFFFFFFFF TDAR Transmit Descriptor Active 24 1 read-write ECR Ethernet Control Register 0x24 32 read-write 0x70000000 0xFFFFFFFF RESET Ethernet MAC Reset 0 1 read-write ETHEREN Ethernet Enable 1 1 read-write ZERO Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0 ONE MAC is enabled, and reception and transmission are possible. 0x1 MAGICEN Magic Packet Detection Enable 2 1 read-write ZERO Magic detection logic disabled. 0 ONE The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. 0x1 SLEEP Sleep Mode Enable 3 1 read-write ZERO Normal operating mode. 0 ONE Sleep mode. 0x1 EN1588 EN1588 Enable 4 1 read-write ZERO Legacy FEC buffer descriptors and functions enabled. 0 ONE Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588. 0x1 DBGEN Debug Enable 6 1 read-write ZERO MAC continues operation in debug mode. 0 ONE MAC enters hardware freeze mode when the processor is in debug mode. 0x1 DBSWP Descriptor Byte Swapping Enable 8 1 read-write ZERO The buffer descriptor bytes are not swapped to support big-endian devices. 0 ONE The buffer descriptor bytes are swapped to support little-endian devices. 0x1 MMFR MII Management Frame Register 0x40 32 read-write 0 0xFFFFFFFF DATA Management Frame Data 0 16 read-write TA Turn Around 16 2 read-write RA Register Address 18 5 read-write PA PHY Address 23 5 read-write OP Operation Code 28 2 read-write ST Start Of Frame Delimiter 30 2 read-write MSCR MII Speed Control Register 0x44 32 read-write 0 0xFFFFFFFF MII_SPEED MII Speed 1 6 read-write DIS_PRE Disable Preamble 7 1 read-write ZERO Preamble enabled. 0 ONE Preamble (32 ones) is not prepended to the MII management frame. 0x1 HOLDTIME Hold time On MDIO Output 8 3 read-write VAL_1 1 internal module clock cycle 0 VAL2 2 internal module clock cycles 0x1 VAL3 3 internal module clock cycles 0x2 VAL8 8 internal module clock cycles 0x7 MIBC MIB Control Register 0x64 32 read-write 0xC0000000 0xFFFFFFFF MIB_CLEAR MIB Clear 29 1 read-write ZERO See note above. 0 ONE All statistics counters are reset to 0. 0x1 MIB_IDLE MIB Idle 30 1 read-only ZERO The MIB block is updating MIB counters. 0 ONE The MIB block is not currently updating any MIB counters. 0x1 MIB_DIS Disable MIB Logic 31 1 read-write ZERO MIB logic is enabled. 0 ONE MIB logic is disabled. The MIB logic halts and does not update any MIB counters. 0x1 RCR Receive Control Register 0x84 32 read-write 0x5EE0001 0xFFFFFFFF LOOP Internal Loopback 0 1 read-write ZERO Loopback disabled. 0 ONE Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. 0x1 DRT Disable Receive On Transmit 1 1 read-write ZERO Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0 ONE Disable reception of frames while transmitting. (Normally used for half-duplex mode.) 0x1 MII_MODE Media Independent Interface Mode 2 1 read-write ONE MII or RMII mode, as indicated by the RMII_MODE field. 0x1 PROM Promiscuous Mode 3 1 read-write ZERO Disabled. 0 ONE Enabled. 0x1 BC_REJ Broadcast Frame Reject 4 1 read-write ZERO Will not reject frames as described above 0 ONE Will reject frames as described above 0x1 FCE Flow Control Enable 5 1 read-write ZERO Disable flow control 0 ONE Enable flow control 0x1 RMII_MODE RMII Mode Enable 8 1 read-write ZERO MAC configured for MII mode. 0 ONE MAC configured for RMII operation. 0x1 RMII_10T Enables 10-Mbit/s mode of the RMII . 9 1 read-write ZERO 100-Mbit/s operation. 0 ONE 10-Mbit/s operation. 0x1 PADEN Enable Frame Padding Remove On Receive 12 1 read-write ZERO No padding is removed on receive by the MAC. 0 ONE Padding is removed from received frames. 0x1 PAUFWD Terminate/Forward Pause Frames 13 1 read-write ZERO Pause frames are terminated and discarded in the MAC. 0 ONE Pause frames are forwarded to the user application. 0x1 CRCFWD Terminate/Forward Received CRC 14 1 read-write ZERO The CRC field of received frames is transmitted to the user application. 0 ONE The CRC field is stripped from the frame. 0x1 CFEN MAC Control Frame Enable 15 1 read-write ZERO MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0 ONE MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. 0x1 MAX_FL Maximum Frame Length 16 14 read-write NLC Payload Length Check Disable 30 1 read-write ZERO The payload length check is disabled. 0 ONE The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. 0x1 GRS Graceful Receive Stopped 31 1 read-only ZERO Receive not stopped 0 ONE Receive stopped 0x1 TCR Transmit Control Register 0xC4 32 read-write 0 0xFFFFFFFF GTS Graceful Transmit Stop 0 1 read-write ZERO Disable graceful transmit stop 0 ONE Enable graceful transmit stop 0x1 FDEN Full-Duplex Enable 2 1 read-write ZERO Disable full-duplex 0 ONE Enable full-duplex 0x1 TFC_PAUSE Transmit Frame Control Pause 3 1 read-write ZERO No PAUSE frame transmitted. 0 ONE The MAC stops transmission of data frames after the current transmission is complete. 0x1 RFC_PAUSE Receive Frame Control Pause 4 1 read-only ADDSEL Source MAC Address Select On Transmit 5 3 read-write VAL_MAC Node MAC address programmed on PADDR1/2 registers. 0 ADDINS Set MAC Address On Transmit 8 1 read-write ZERO The source MAC address is not modified by the MAC. 0 ONE The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. 0x1 CRCFWD Forward Frame From Application With CRC 9 1 read-write ZERO TxBD[TC] controls whether the frame has a CRC from the application. 0 ONE The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. 0x1 PALR Physical Address Lower Register 0xE4 32 read-write 0 0xFFFFFFFF PADDR1 Pause Address 0 32 read-write PAUR Physical Address Upper Register 0xE8 32 read-write 0x8808 0xFFFFFFFF TYPE Type Field In PAUSE Frames 0 16 read-only PADDR2 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames 16 16 read-write OPD Opcode/Pause Duration Register 0xEC 32 read-write 0x10000 0xFFFFFFFF PAUSE_DUR Pause Duration 0 16 read-write OPCODE Opcode Field In PAUSE Frames 16 16 read-only 3 0x4 TXIC[%s] Transmit Interrupt Coalescing Register 0xF0 32 read-write 0 0xFFFFFFFF ICTT Interrupt coalescing timer threshold 0 16 read-write ICFT Interrupt coalescing frame count threshold 20 8 read-write ICCS Interrupt Coalescing Timer Clock Source Select 30 1 read-write ZERO Use MII/GMII TX clocks. 0 ONE Use ENET system clock. 0x1 ICEN Interrupt Coalescing Enable 31 1 read-write ZERO Disable Interrupt coalescing. 0 ONE Enable Interrupt coalescing. 0x1 3 0x4 RXIC[%s] Receive Interrupt Coalescing Register 0x100 32 read-write 0 0xFFFFFFFF ICTT Interrupt coalescing timer threshold 0 16 read-write ICFT Interrupt coalescing frame count threshold 20 8 read-write ICCS Interrupt Coalescing Timer Clock Source Select 30 1 read-write ZERO Use MII/GMII TX clocks. 0 ONE Use ENET system clock. 0x1 ICEN Interrupt Coalescing Enable 31 1 read-write ZERO Disable Interrupt coalescing. 0 ONE Enable Interrupt coalescing. 0x1 IAUR Descriptor Individual Upper Address Register 0x118 32 read-write 0 0xFFFFFFFF IADDR1 Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address 0 32 read-write IALR Descriptor Individual Lower Address Register 0x11C 32 read-write 0 0xFFFFFFFF IADDR2 Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address 0 32 read-write GAUR Descriptor Group Upper Address Register 0x120 32 read-write 0 0xFFFFFFFF GADDR1 Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address 0 32 read-write GALR Descriptor Group Lower Address Register 0x124 32 read-write 0 0xFFFFFFFF GADDR2 Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address 0 32 read-write TFWR Transmit FIFO Watermark Register 0x144 32 read-write 0 0xFFFFFFFF TFWR Transmit FIFO Write 0 6 read-write VAL64_0 64 bytes written. 0 VAL64_1 64 bytes written. 0x1 VAL128 128 bytes written. 0x2 VAL192 192 bytes written. 0x3 VAL1984 1984 bytes written. 0x1F STRFWD Store And Forward Enable 8 1 read-write ZERO Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0 ONE Enabled. 0x1 RDSR Receive Descriptor Ring 0 Start Register 0x180 32 read-write 0 0xFFFFFFFF R_DES_START Pointer to the beginning of the receive buffer descriptor queue. 3 29 read-write TDSR Transmit Buffer Descriptor Ring 0 Start Register 0x184 32 read-write 0 0xFFFFFFFF X_DES_START Pointer to the beginning of the transmit buffer descriptor queue. 3 29 read-write MRBR Maximum Receive Buffer Size Register - Ring 0 0x188 32 read-write 0 0xFFFFFFFF R_BUF_SIZE Receive buffer size in bytes 4 10 read-write RSFL Receive FIFO Section Full Threshold 0x190 32 read-write 0 0xFFFFFFFF RX_SECTION_FULL Value Of Receive FIFO Section Full Threshold 0 8 read-write RSEM Receive FIFO Section Empty Threshold 0x194 32 read-write 0 0xFFFFFFFF RX_SECTION_EMPTY Value Of The Receive FIFO Section Empty Threshold 0 8 read-write STAT_SECTION_EMPTY RX Status FIFO Section Empty Threshold 16 5 read-write RAEM Receive FIFO Almost Empty Threshold 0x198 32 read-write 0x4 0xFFFFFFFF RX_ALMOST_EMPTY Value Of The Receive FIFO Almost Empty Threshold 0 8 read-write RAFL Receive FIFO Almost Full Threshold 0x19C 32 read-write 0x4 0xFFFFFFFF RX_ALMOST_FULL Value Of The Receive FIFO Almost Full Threshold 0 8 read-write TSEM Transmit FIFO Section Empty Threshold 0x1A0 32 read-write 0 0xFFFFFFFF TX_SECTION_EMPTY Value Of The Transmit FIFO Section Empty Threshold 0 8 read-write TAEM Transmit FIFO Almost Empty Threshold 0x1A4 32 read-write 0x4 0xFFFFFFFF TX_ALMOST_EMPTY Value of Transmit FIFO Almost Empty Threshold 0 8 read-write TAFL Transmit FIFO Almost Full Threshold 0x1A8 32 read-write 0x8 0xFFFFFFFF TX_ALMOST_FULL Value Of The Transmit FIFO Almost Full Threshold 0 8 read-write TIPG Transmit Inter-Packet Gap 0x1AC 32 read-write 0xC 0xFFFFFFFF IPG Transmit Inter-Packet Gap 0 5 read-write FTRL Frame Truncation Length 0x1B0 32 read-write 0x7FF 0xFFFFFFFF TRUNC_FL Frame Truncation Length 0 14 read-write TACC Transmit Accelerator Function Configuration 0x1C0 32 read-write 0 0xFFFFFFFF SHIFT16 TX FIFO Shift-16 0 1 read-write ZERO Disabled. 0 ONE Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. 0x1 IPCHK Enables insertion of IP header checksum. 3 1 read-write ZERO Checksum is not inserted. 0 ONE If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. 0x1 PROCHK Enables insertion of protocol checksum. 4 1 read-write ZERO Checksum not inserted. 0 ONE If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. 0x1 RACC Receive Accelerator Function Configuration 0x1C4 32 read-write 0 0xFFFFFFFF PADREM Enable Padding Removal For Short IP Frames 0 1 read-write ZERO Padding not removed. 0 ONE Any bytes following the IP payload section of the frame are removed from the frame. 0x1 IPDIS Enable Discard Of Frames With Wrong IPv4 Header Checksum 1 1 read-write ZERO Frames with wrong IPv4 header checksum are not discarded. 0 ONE If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). 0x1 PRODIS Enable Discard Of Frames With Wrong Protocol Checksum 2 1 read-write ZERO Frames with wrong checksum are not discarded. 0 ONE If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). 0x1 LINEDIS Enable Discard Of Frames With MAC Layer Errors 6 1 read-write ZERO Frames with errors are not discarded. 0 ONE Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. 0x1 SHIFT16 RX FIFO Shift-16 7 1 read-write ZERO Disabled. 0 ONE Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. 0x1 RMON_T_PACKETS Tx Packet Count Statistic Register 0x204 32 read-only 0 0xFFFFFFFF TXPKTS Packet count 0 16 read-only RMON_T_BC_PKT Tx Broadcast Packets Statistic Register 0x208 32 read-only 0 0xFFFFFFFF TXPKTS Broadcast packets 0 16 read-only RMON_T_MC_PKT Tx Multicast Packets Statistic Register 0x20C 32 read-only 0 0xFFFFFFFF TXPKTS Multicast packets 0 16 read-only RMON_T_CRC_ALIGN Tx Packets with CRC/Align Error Statistic Register 0x210 32 read-only 0 0xFFFFFFFF TXPKTS Packets with CRC/align error 0 16 read-only RMON_T_UNDERSIZE Tx Packets Less Than Bytes and Good CRC Statistic Register 0x214 32 read-only 0 0xFFFFFFFF TXPKTS Number of transmit packets less than 64 bytes with good CRC 0 16 read-only RMON_T_OVERSIZE Tx Packets GT MAX_FL bytes and Good CRC Statistic Register 0x218 32 read-only 0 0xFFFFFFFF TXPKTS Number of transmit packets greater than MAX_FL bytes with good CRC 0 16 read-only RMON_T_FRAG Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register 0x21C 32 read-only 0 0xFFFFFFFF TXPKTS Number of packets less than 64 bytes with bad CRC 0 16 read-only RMON_T_JAB Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register 0x220 32 read-only 0 0xFFFFFFFF TXPKTS Number of transmit packets greater than MAX_FL bytes and bad CRC 0 16 read-only RMON_T_COL Tx Collision Count Statistic Register 0x224 32 read-only 0 0xFFFFFFFF TXPKTS Number of transmit collisions 0 16 read-only RMON_T_P64 Tx 64-Byte Packets Statistic Register 0x228 32 read-only 0 0xFFFFFFFF TXPKTS Number of 64-byte transmit packets 0 16 read-only RMON_T_P65TO127 Tx 65- to 127-byte Packets Statistic Register 0x22C 32 read-only 0 0xFFFFFFFF TXPKTS Number of 65- to 127-byte transmit packets 0 16 read-only RMON_T_P128TO255 Tx 128- to 255-byte Packets Statistic Register 0x230 32 read-only 0 0xFFFFFFFF TXPKTS Number of 128- to 255-byte transmit packets 0 16 read-only RMON_T_P256TO511 Tx 256- to 511-byte Packets Statistic Register 0x234 32 read-only 0 0xFFFFFFFF TXPKTS Number of 256- to 511-byte transmit packets 0 16 read-only RMON_T_P512TO1023 Tx 512- to 1023-byte Packets Statistic Register 0x238 32 read-only 0 0xFFFFFFFF TXPKTS Number of 512- to 1023-byte transmit packets 0 16 read-only RMON_T_P1024TO2047 Tx 1024- to 2047-byte Packets Statistic Register 0x23C 32 read-only 0 0xFFFFFFFF TXPKTS Number of 1024- to 2047-byte transmit packets 0 16 read-only RMON_T_P_GTE2048 Tx Packets Greater Than 2048 Bytes Statistic Register 0x240 32 read-only 0 0xFFFFFFFF TXPKTS Number of transmit packets greater than 2048 bytes 0 16 read-only RMON_T_OCTETS Tx Octets Statistic Register 0x244 32 read-only 0 0xFFFFFFFF TXOCTS Number of transmit octets 0 32 read-only IEEE_T_DROP Reserved Statistic Register 0x248 32 read-only 0 0xFFFFFFFF IEEE_T_FRAME_OK Frames Transmitted OK Statistic Register 0x24C 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted OK 0 16 read-only IEEE_T_1COL Frames Transmitted with Single Collision Statistic Register 0x250 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with one collision 0 16 read-only IEEE_T_MCOL Frames Transmitted with Multiple Collisions Statistic Register 0x254 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with multiple collisions 0 16 read-only IEEE_T_DEF Frames Transmitted after Deferral Delay Statistic Register 0x258 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with deferral delay 0 16 read-only IEEE_T_LCOL Frames Transmitted with Late Collision Statistic Register 0x25C 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with late collision 0 16 read-only IEEE_T_EXCOL Frames Transmitted with Excessive Collisions Statistic Register 0x260 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with excessive collisions 0 16 read-only IEEE_T_MACERR Frames Transmitted with Tx FIFO Underrun Statistic Register 0x264 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with transmit FIFO underrun 0 16 read-only IEEE_T_CSERR Frames Transmitted with Carrier Sense Error Statistic Register 0x268 32 read-only 0 0xFFFFFFFF COUNT Number of frames transmitted with carrier sense error 0 16 read-only IEEE_T_SQE Reserved Statistic Register 0x26C 32 read-only 0 0xFFFFFFFF COUNT This read-only field is reserved and always has the value 0 0 16 read-only IEEE_T_FDXFC Flow Control Pause Frames Transmitted Statistic Register 0x270 32 read-only 0 0xFFFFFFFF COUNT Number of flow-control pause frames transmitted 0 16 read-only IEEE_T_OCTETS_OK Octet Count for Frames Transmitted w/o Error Statistic Register 0x274 32 read-only 0 0xFFFFFFFF COUNT Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). 0 32 read-only RMON_R_PACKETS Rx Packet Count Statistic Register 0x284 32 read-only 0 0xFFFFFFFF COUNT Number of packets received 0 16 read-only RMON_R_BC_PKT Rx Broadcast Packets Statistic Register 0x288 32 read-only 0 0xFFFFFFFF COUNT Number of receive broadcast packets 0 16 read-only RMON_R_MC_PKT Rx Multicast Packets Statistic Register 0x28C 32 read-only 0 0xFFFFFFFF COUNT Number of receive multicast packets 0 16 read-only RMON_R_CRC_ALIGN Rx Packets with CRC/Align Error Statistic Register 0x290 32 read-only 0 0xFFFFFFFF COUNT Number of receive packets with CRC or align error 0 16 read-only RMON_R_UNDERSIZE Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register 0x294 32 read-only 0 0xFFFFFFFF COUNT Number of receive packets with less than 64 bytes and good CRC 0 16 read-only RMON_R_OVERSIZE Rx Packets Greater Than MAX_FL and Good CRC Statistic Register 0x298 32 read-only 0 0xFFFFFFFF COUNT Number of receive packets greater than MAX_FL and good CRC 0 16 read-only RMON_R_FRAG Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register 0x29C 32 read-only 0 0xFFFFFFFF COUNT Number of receive packets with less than 64 bytes and bad CRC 0 16 read-only RMON_R_JAB Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register 0x2A0 32 read-only 0 0xFFFFFFFF COUNT Number of receive packets greater than MAX_FL and bad CRC 0 16 read-only RMON_R_P64 Rx 64-Byte Packets Statistic Register 0x2A8 32 read-only 0 0xFFFFFFFF COUNT Number of 64-byte receive packets 0 16 read-only RMON_R_P65TO127 Rx 65- to 127-Byte Packets Statistic Register 0x2AC 32 read-only 0 0xFFFFFFFF COUNT Number of 65- to 127-byte recieve packets 0 16 read-only RMON_R_P128TO255 Rx 128- to 255-Byte Packets Statistic Register 0x2B0 32 read-only 0 0xFFFFFFFF COUNT Number of 128- to 255-byte recieve packets 0 16 read-only RMON_R_P256TO511 Rx 256- to 511-Byte Packets Statistic Register 0x2B4 32 read-only 0 0xFFFFFFFF COUNT Number of 256- to 511-byte recieve packets 0 16 read-only RMON_R_P512TO1023 Rx 512- to 1023-Byte Packets Statistic Register 0x2B8 32 read-only 0 0xFFFFFFFF COUNT Number of 512- to 1023-byte recieve packets 0 16 read-only RMON_R_P1024TO2047 Rx 1024- to 2047-Byte Packets Statistic Register 0x2BC 32 read-only 0 0xFFFFFFFF COUNT Number of 1024- to 2047-byte recieve packets 0 16 read-only RMON_R_P_GTE2048 Rx Packets Greater than 2048 Bytes Statistic Register 0x2C0 32 read-only 0 0xFFFFFFFF COUNT Number of greater-than-2048-byte recieve packets 0 16 read-only RMON_R_OCTETS Rx Octets Statistic Register 0x2C4 32 read-only 0 0xFFFFFFFF COUNT Number of receive octets 0 32 read-only IEEE_R_DROP Frames not Counted Correctly Statistic Register 0x2C8 32 read-only 0 0xFFFFFFFF COUNT Frame count 0 16 read-only IEEE_R_FRAME_OK Frames Received OK Statistic Register 0x2CC 32 read-only 0 0xFFFFFFFF COUNT Number of frames received OK 0 16 read-only IEEE_R_CRC Frames Received with CRC Error Statistic Register 0x2D0 32 read-only 0 0xFFFFFFFF COUNT Number of frames received with CRC error 0 16 read-only IEEE_R_ALIGN Frames Received with Alignment Error Statistic Register 0x2D4 32 read-only 0 0xFFFFFFFF COUNT Number of frames received with alignment error 0 16 read-only IEEE_R_MACERR Receive FIFO Overflow Count Statistic Register 0x2D8 32 read-only 0 0xFFFFFFFF COUNT Receive FIFO overflow count 0 16 read-only IEEE_R_FDXFC Flow Control Pause Frames Received Statistic Register 0x2DC 32 read-only 0 0xFFFFFFFF COUNT Number of flow-control pause frames received 0 16 read-only IEEE_R_OCTETS_OK Octet Count for Frames Received without Error Statistic Register 0x2E0 32 read-only 0 0xFFFFFFFF COUNT Number of octets for frames received without error 0 32 read-only ATCR Adjustable Timer Control Register 0x400 32 read-write 0 0xFFFFFFFF EN Enable Timer 0 1 read-write ZERO The timer stops at the current value. 0 ONE The timer starts incrementing. 0x1 OFFEN Enable One-Shot Offset Event 2 1 read-write ZERO Disable. 0 ONE The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. 0x1 OFFRST Reset Timer On Offset Event 3 1 read-write ZERO The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0 ONE If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. 0x1 PEREN Enable Periodical Event 4 1 read-write ZERO Disable. 0 ONE A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. 0x1 PINPER Enables event signal output external pin frc_evt_period assertion on period event 7 1 read-write ZERO Disable. 0 ONE Enable. 0x1 RESTART Reset Timer 9 1 read-write CAPTURE Capture Timer Value 11 1 read-write ZERO No effect. 0 ONE The current time is captured and can be read from the ATVR register. 0x1 SLAVE Enable Timer Slave Mode 13 1 read-write ZERO The timer is active and all configuration fields in this register are relevant. 0 ONE The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. 0x1 ATVR Timer Value Register 0x404 32 read-write 0 0xFFFFFFFF ATIME A write sets the timer 0 32 read-write ATOFF Timer Offset Register 0x408 32 read-write 0 0xFFFFFFFF OFFSET Offset value for one-shot event generation 0 32 read-write ATPER Timer Period Register 0x40C 32 read-write 0x3B9ACA00 0xFFFFFFFF PERIOD Value for generating periodic events 0 32 read-write ATCOR Timer Correction Register 0x410 32 read-write 0 0xFFFFFFFF COR Correction Counter Wrap-Around Value 0 31 read-write ATINC Time-Stamping Clock Period Register 0x414 32 read-write 0 0xFFFFFFFF INC Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds 0 7 read-write INC_CORR Correction Increment Value 8 7 read-write ATSTMP Timestamp of Last Transmitted Frame 0x418 32 read-only 0 0xFFFFFFFF TIMESTAMP Timestamp of the last frame transmitted by the core that had TxBD[TS] set the ff_tx_ts_frm signal asserted from the user application 0 32 read-only TGSR Timer Global Status Register 0x604 32 read-write 0 0xFFFFFFFF oneToClear TF0 Copy Of Timer Flag For Channel 0 0 1 read-write oneToClear ZERO Timer Flag for Channel 0 is clear 0 ONE Timer Flag for Channel 0 is set 0x1 TF1 Copy Of Timer Flag For Channel 1 1 1 read-write oneToClear ZERO Timer Flag for Channel 1 is clear 0 ONE Timer Flag for Channel 1 is set 0x1 TF2 Copy Of Timer Flag For Channel 2 2 1 read-write oneToClear ZERO Timer Flag for Channel 2 is clear 0 ONE Timer Flag for Channel 2 is set 0x1 TF3 Copy Of Timer Flag For Channel 3 3 1 read-write oneToClear ZERO Timer Flag for Channel 3 is clear 0 ONE Timer Flag for Channel 3 is set 0x1 TCSR0 Timer Control Status Register 0x608 32 read-write 0 0xFFFFFFFF TDRE Timer DMA Request Enable 0 1 read-write ZERO DMA request is disabled 0 ONE DMA request is enabled 0x1 TMODE Timer Mode 2 4 read-write TMR_DIS Timer Channel is disabled. 0 TMR_RE Timer Channel is configured for Input Capture on rising edge. 0x1 TMR_FE Timer Channel is configured for Input Capture on falling edge. 0x2 TMR_BE Timer Channel is configured for Input Capture on both edges. 0x3 TMR_OUT Timer Channel is configured for Output Compare - software only. 0x4 TMR_TOGGLE Timer Channel is configured for Output Compare - toggle output on compare. 0x5 TMR_CLR Timer Channel is configured for Output Compare - clear output on compare. 0x6 TMR_SET_OUT Timer Channel is configured for Output Compare - set output on compare. 0x7 TMR_CLR_SET1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. #10x1 TMR_CLR_SET Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0xA TMR_OUT_CMP_LOW Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0xE TMR_OUT_CMP_HIGH Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0xF TIE Timer Interrupt Enable 6 1 read-write ZERO Interrupt is disabled 0 ONE Interrupt is enabled 0x1 TF Timer Flag 7 1 read-write oneToClear ZERO Input Capture or Output Compare has not occurred. 0 ONE Input Capture or Output Compare has occurred. 0x1 TPWC Timer PulseWidth Control 11 5 read-write VALW1 Pulse width is one 1588-clock cycle. 0 VALW2 Pulse width is two 1588-clock cycles. 0x1 VALW3 Pulse width is three 1588-clock cycles. 0x2 VALW4 Pulse width is four 1588-clock cycles. 0x3 VALW32 Pulse width is 32 1588-clock cycles. 0x1F TCCR0 Timer Compare Capture Register 0x60C 32 read-write 0 0xFFFFFFFF TCC Timer Capture Compare 0 32 read-write TCSR1 Timer Control Status Register 0x610 32 read-write 0 0xFFFFFFFF TDRE Timer DMA Request Enable 0 1 read-write ZERO DMA request is disabled 0 ONE DMA request is enabled 0x1 TMODE Timer Mode 2 4 read-write TMR_DIS Timer Channel is disabled. 0 TMR_RE Timer Channel is configured for Input Capture on rising edge. 0x1 TMR_FE Timer Channel is configured for Input Capture on falling edge. 0x2 TMR_BE Timer Channel is configured for Input Capture on both edges. 0x3 TMR_OUT Timer Channel is configured for Output Compare - software only. 0x4 TMR_TOGGLE Timer Channel is configured for Output Compare - toggle output on compare. 0x5 TMR_CLR Timer Channel is configured for Output Compare - clear output on compare. 0x6 TMR_SET_OUT Timer Channel is configured for Output Compare - set output on compare. 0x7 TMR_CLR_SET1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. #10x1 TMR_CLR_SET Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0xA TMR_OUT_CMP_LOW Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0xE TMR_OUT_CMP_HIGH Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0xF TIE Timer Interrupt Enable 6 1 read-write ZERO Interrupt is disabled 0 ONE Interrupt is enabled 0x1 TF Timer Flag 7 1 read-write oneToClear ZERO Input Capture or Output Compare has not occurred. 0 ONE Input Capture or Output Compare has occurred. 0x1 TPWC Timer PulseWidth Control 11 5 read-write VALW1 Pulse width is one 1588-clock cycle. 0 VALW2 Pulse width is two 1588-clock cycles. 0x1 VALW3 Pulse width is three 1588-clock cycles. 0x2 VALW4 Pulse width is four 1588-clock cycles. 0x3 VALW32 Pulse width is 32 1588-clock cycles. 0x1F TCCR1 Timer Compare Capture Register 0x614 32 read-write 0 0xFFFFFFFF TCC Timer Capture Compare 0 32 read-write TCSR2 Timer Control Status Register 0x618 32 read-write 0 0xFFFFFFFF TDRE Timer DMA Request Enable 0 1 read-write ZERO DMA request is disabled 0 ONE DMA request is enabled 0x1 TMODE Timer Mode 2 4 read-write TMR_DIS Timer Channel is disabled. 0 TMR_RE Timer Channel is configured for Input Capture on rising edge. 0x1 TMR_FE Timer Channel is configured for Input Capture on falling edge. 0x2 TMR_BE Timer Channel is configured for Input Capture on both edges. 0x3 TMR_OUT Timer Channel is configured for Output Compare - software only. 0x4 TMR_TOGGLE Timer Channel is configured for Output Compare - toggle output on compare. 0x5 TMR_CLR Timer Channel is configured for Output Compare - clear output on compare. 0x6 TMR_SET_OUT Timer Channel is configured for Output Compare - set output on compare. 0x7 TMR_CLR_SET1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. #10x1 TMR_CLR_SET Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0xA TMR_OUT_CMP_LOW Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0xE TMR_OUT_CMP_HIGH Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0xF TIE Timer Interrupt Enable 6 1 read-write ZERO Interrupt is disabled 0 ONE Interrupt is enabled 0x1 TF Timer Flag 7 1 read-write oneToClear ZERO Input Capture or Output Compare has not occurred. 0 ONE Input Capture or Output Compare has occurred. 0x1 TPWC Timer PulseWidth Control 11 5 read-write VALW1 Pulse width is one 1588-clock cycle. 0 VALW2 Pulse width is two 1588-clock cycles. 0x1 VALW3 Pulse width is three 1588-clock cycles. 0x2 VALW4 Pulse width is four 1588-clock cycles. 0x3 VALW32 Pulse width is 32 1588-clock cycles. 0x1F TCCR2 Timer Compare Capture Register 0x61C 32 read-write 0 0xFFFFFFFF TCC Timer Capture Compare 0 32 read-write TCSR3 Timer Control Status Register 0x620 32 read-write 0 0xFFFFFFFF TDRE Timer DMA Request Enable 0 1 read-write ZERO DMA request is disabled 0 ONE DMA request is enabled 0x1 TMODE Timer Mode 2 4 read-write TMR_DIS Timer Channel is disabled. 0 TMR_RE Timer Channel is configured for Input Capture on rising edge. 0x1 TMR_FE Timer Channel is configured for Input Capture on falling edge. 0x2 TMR_BE Timer Channel is configured for Input Capture on both edges. 0x3 TMR_OUT Timer Channel is configured for Output Compare - software only. 0x4 TMR_TOGGLE Timer Channel is configured for Output Compare - toggle output on compare. 0x5 TMR_CLR Timer Channel is configured for Output Compare - clear output on compare. 0x6 TMR_SET_OUT Timer Channel is configured for Output Compare - set output on compare. 0x7 TMR_CLR_SET1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. #10x1 TMR_CLR_SET Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0xA TMR_OUT_CMP_LOW Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0xE TMR_OUT_CMP_HIGH Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0xF TIE Timer Interrupt Enable 6 1 read-write ZERO Interrupt is disabled 0 ONE Interrupt is enabled 0x1 TF Timer Flag 7 1 read-write oneToClear ZERO Input Capture or Output Compare has not occurred. 0 ONE Input Capture or Output Compare has occurred. 0x1 TPWC Timer PulseWidth Control 11 5 read-write VALW1 Pulse width is one 1588-clock cycle. 0 VALW2 Pulse width is two 1588-clock cycles. 0x1 VALW3 Pulse width is three 1588-clock cycles. 0x2 VALW4 Pulse width is four 1588-clock cycles. 0x3 VALW32 Pulse width is 32 1588-clock cycles. 0x1F TCCR3 Timer Compare Capture Register 0x624 32 read-write 0 0xFFFFFFFF TCC Timer Capture Compare 0 32 read-write USB_OTG1 USB USB USB 0x40430000 0 0x1E0 registers USB_OTG1 136 ID Identification register 0 32 read-only 0xE4A1FA05 0xFFFFFFFF ID ID 0 6 read-only NID NID 8 6 read-only REVISION REVISION 16 8 read-only HWGENERAL Hardware General 0x4 32 read-only 0x15 0xFFFFFFFF PHYW PHYW 4 2 read-only DATA_BUS_8 8 bit wide data bus (Software non-programmable) 0 DATA_BUS_16 16 bit wide data bus (Software non-programmable) 0x1 SW_RST_8 Reset to 8 bit wide data bus (Software programmable) 0x2 SW_RST_16 Reset to 16 bit wide data bus (Software programmable) 0x3 PHYM PHYM 6 3 read-only UTMI UTMI/UMTI+ 0 ULPI_DDR ULPI DDR 0x1 ULPI ULPI 0x2 SERIAL Serial Only 0x3 SW_RST_UTMI Software programmable - reset to UTMI/UTMI+ 0x4 SW_RST_ULPI_DDR Software programmable - reset to ULPI DDR 0x5 SW_RST_ULPI Software programmable - reset to ULPI 0x6 SW_RST_SERIAL Software programmable - reset to Serial 0x7 SM SM 9 2 read-only SERIAL_ENGINE_NO No Serial Engine, always use parallel signalling. 0 SERIAL_ENGINE_EN Serial Engine present, always use serial signalling for FS/LS. 0x1 SW_RST_PARALLEL Software programmable - Reset to use parallel signalling for FS/LS 0x2 SW_RST_SERIAL_ENG Software programmable - Reset to use serial signalling for FS/LS 0x3 HWHOST Host Hardware Parameters 0x8 32 read-only 0x10020001 0xFFFFFFFF HC HC 0 1 read-only HOST_OP_DIS Not supported 0 HOST_OP_EN Supported 0x1 NPORT NPORT 1 3 read-only HWDEVICE Device Hardware Parameters 0xC 32 read-only 0x11 0xFFFFFFFF DC DC 0 1 read-only DEVICE_OP_DIS Not supported 0 DEVICE_OP_EN Supported 0x1 DEVEP DEVEP 1 5 read-only HWTXBUF TX Buffer Hardware Parameters 0x10 32 read-only 0x80080B08 0xFFFFFFFF TXBURST TXBURST 0 8 read-only TXCHANADD TXCHANADD 16 8 read-only HWRXBUF RX Buffer Hardware Parameters 0x14 32 read-only 0x808 0xFFFFFFFF RXBURST RXBURST 0 8 read-only RXADD RXADD 8 8 read-only GPTIMER0LD General Purpose Timer #0 Load 0x80 32 read-write 0 0xFFFFFFFF GPTLD GPTLD 0 24 read-write GPTIMER0CTRL General Purpose Timer #0 Controller 0x84 32 read-write 0 0xFFFFFFFF GPTCNT GPTCNT 0 24 read-write GPTMODE GPTMODE 24 1 read-write ONE_SHOT One Shot Mode 0 REPEAT Repeat Mode 0x1 GPTRST GPTRST 30 1 read-write NO_ACTION No action 0 LOAD_CNTR Load counter value from GPTLD bits in n_GPTIMER0LD 0x1 GPTRUN GPTRUN 31 1 read-write STOP_CNTR Stop counting 0 RUN Run 0x1 GPTIMER1LD General Purpose Timer #1 Load 0x88 32 read-write 0 0xFFFFFFFF GPTLD GPTLD 0 24 read-write GPTIMER1CTRL General Purpose Timer #1 Controller 0x8C 32 read-write 0 0xFFFFFFFF GPTCNT GPTCNT 0 24 read-write GPTMODE GPTMODE 24 1 read-write ONE_SHOT One Shot Mode 0 REPEAT Repeat Mode 0x1 GPTRST GPTRST 30 1 read-write NO_ACTION No action 0 LOAD_CNTR Load counter value from GPTLD bits in USB_n_GPTIMER0LD 0x1 GPTRUN GPTRUN 31 1 read-write STOP_CNTR Stop counting 0 RUN Run 0x1 SBUSCFG System Bus Config 0x90 32 read-write 0x2 0xFFFFFFFF AHBBRST AHBBRST 0 3 read-write INCR_BURST Incremental burst of unspecified length only 0 INCR4_BURST INCR4 burst, then single transfer 0x1 INCR8_BURST INCR8 burst, INCR4 burst, then single transfer 0x2 INCR16_BURST INCR16 burst, INCR8 burst, INCR4 burst, then single transfer 0x3 INCR4_UNSPEC INCR4 burst, then incremental burst of unspecified length 0x5 INCR8_4_UNSPEC INCR8 burst, INCR4 burst, then incremental burst of unspecified length 0x6 INCR16_8_4_UNSPEC INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length 0x7 CAPLENGTH Capability Registers Length 0x100 8 read-only 0x40 0xFF CAPLENGTH CAPLENGTH 0 8 read-only HCIVERSION Host Controller Interface Version 0x102 16 read-only 0x100 0xFFFF HCIVERSION HCIVERSION 0 16 read-only HCSPARAMS Host Controller Structural Parameters 0x104 32 read-only 0x10011 0xFFFFFFFF N_PORTS N_PORTS 0 4 read-only PPC PPC 4 1 read-only N_PCC N_PCC 8 4 read-only N_CC N_CC 12 4 read-only NO_COMP_CONTROLLER There is no internal Companion Controller and port-ownership hand-off is not supported. 0 COMP_CONTROLLER There are internal companion controller(s) and port-ownership hand-offs is supported. 0x1 PI PI 16 1 read-only N_PTT N_PTT 20 4 read-only N_TT N_TT 24 4 read-only HCCPARAMS Host Controller Capability Parameters 0x108 32 read-only 0x6 0xFFFFFFFF ADC ADC 0 1 read-only PFL PFL 1 1 read-only ASP ASP 2 1 read-only IST IST 4 4 read-only EECP EECP 8 8 read-only DCIVERSION Device Controller Interface Version 0x120 16 read-only 0x1 0xFFFF DCIVERSION DCIVERSION 0 16 read-only DCCPARAMS Device Controller Capability Parameters 0x124 32 read-only 0x188 0xFFFFFFFF DEN DEN 0 5 read-only DC DC 7 1 read-only HC HC 8 1 read-only USBCMD USB Command Register 0x140 32 read-write 0x80000 0xFFFFFFFF RS RS 0 1 read-write RST RST 1 1 read-write FS_1 FS_1 2 2 read-write PSE PSE 4 1 read-write DONT_PROCESS_PT Do not process the Periodic Schedule 0 PROCESS_PT_PERIODICLISTBASE Use the PERIODICLISTBASE register to access the Periodic Schedule. 0x1 ASE ASE 5 1 read-write DONT_PROCESS_ASYNC Do not process the Asynchronous Schedule. 0 ACCESS_ASYNC Use the ASYNCLISTADDR register to access the Asynchronous Schedule. 0x1 IAA IAA 6 1 read-write ASP ASP 8 2 read-write ASPE ASPE 11 1 read-write SUTW SUTW 13 1 read-write ATDTW ATDTW 14 1 read-write FS_2 FS_2 15 1 read-write ITC ITC 16 8 read-write IMMEDIATE Immediate (no threshold) 0 MICROFRAME_1 1 micro-frame 0x1 MICROFRAME_2 2 micro-frames 0x2 MICROFRAME_4 4 micro-frames 0x4 MICROFRAME_8 8 micro-frames 0x8 MICROFRAME_16 16 micro-frames 0x10 MICROFRAME_32 32 micro-frames 0x20 MICROFRAME_64 64 micro-frames 0x40 USBSTS USB Status Register 0x144 32 read-write 0x80 0xFFFFFFFF UI UI 0 1 read-write UEI UEI 1 1 read-write PCI PCI 2 1 read-write FRI FRI 3 1 read-write SEI SEI 4 1 read-write AAI AAI 5 1 read-write URI URI 6 1 read-write SRI SRI 7 1 read-write SLI SLI 8 1 read-write ULPII ULPII 10 1 read-write HCH HCH 12 1 read-write RCL RCL 13 1 read-write PS PS 14 1 read-write AS AS 15 1 read-write NAKI NAKI 16 1 read-only TI0 TI0 24 1 read-write TI1 TI1 25 1 read-write USBINTR Interrupt Enable Register 0x148 32 read-write 0 0xFFFFFFFF UE UE 0 1 read-write UEE UEE 1 1 read-write PCE PCE 2 1 read-write FRE FRE 3 1 read-write SEE SEE 4 1 read-write AAE AAE 5 1 read-write URE URE 6 1 read-write SRE SRE 7 1 read-write SLE SLE 8 1 read-write ULPIE ULPIE 10 1 read-write NAKE NAKE 16 1 read-write UAIE UAIE 18 1 read-write UPIE UPIE 19 1 read-write TIE0 TIE0 24 1 read-write TIE1 TIE1 25 1 read-write FRINDEX USB Frame Index 0x14C 32 read-write 0 0xFFFFFFFF FRINDEX FRINDEX 0 14 read-write FRINDEX_1024 (1024) 12 0 FRINDEX_512 (512) 11 0x1 FRINDEX_256 (256) 10 0x2 FRINDEX_128 (128) 9 0x3 FRINDEX_64 (64) 8 0x4 FRINDEX_32 (32) 7 0x5 FRINDEX_16 (16) 6 0x6 FRINDEX_8 (8) 5 0x7 DEVICEADDR Device Address ADDRESS_MODES 0x154 32 read-write 0 0xFFFFFFFF USBADRA USBADRA 24 1 read-write USBADR USBADR 25 7 read-write PERIODICLISTBASE Frame List Base Address ADDRESS_MODES 0x154 32 read-write 0 0xFFFFFFFF BASEADR BASEADR 12 20 read-write ASYNCLISTADDR Next Asynch. Address ADDRESS_MODES 0x158 32 read-write 0 0xFFFFFFFF ASYBASE ASYBASE 5 27 read-write ENDPTLISTADDR Endpoint List Address ADDRESS_MODES 0x158 32 read-write 0 0xFFFFFFFF EPBASE EPBASE 11 21 read-write BURSTSIZE Programmable Burst Size 0x160 32 read-write 0x808 0xFFFFFFFF RXPBURST RXPBURST 0 8 read-write TXPBURST TXPBURST 8 9 read-write TXFILLTUNING TX FIFO Fill Tuning 0x164 32 read-write 0 0xFFFFFFFF TXSCHOH TXSCHOH 0 8 read-write TXSCHHEALTH TXSCHHEALTH 8 5 read-write TXFIFOTHRES TXFIFOTHRES 16 6 read-write ENDPTNAK Endpoint NAK 0x178 32 read-write 0 0xFFFFFFFF EPRN EPRN 0 8 read-write EPTN EPTN 16 8 read-write ENDPTNAKEN Endpoint NAK Enable 0x17C 32 read-write 0 0xFFFFFFFF EPRNE EPRNE 0 8 read-write EPTNE EPTNE 16 8 read-write CONFIGFLAG Configure Flag Register 0x180 32 read-only 0x1 0xFFFFFFFF CF CF 0 1 read-only PORT_ROUTING_CLASSIC_HOST Port routing control logic default-routes each port to an implementation dependent classic host controller. 0 PORT_ROUTING_HOST Port routing control logic default-routes all ports to this host controller. 0x1 PORTSC1 Port Status & Control 0x184 32 read-write 0x1C000004 0xFFFFFFFF CCS CCS 0 1 read-only CSC CSC 1 1 read-write PE PE 2 1 read-write PEC PEC 3 1 read-write OCA OCA 4 1 read-only NO_OVERCURRENT This port does not have an over-current condition. 0 OVERCURRENT This port currently has an over-current condition 0x1 OCC OCC 5 1 read-write FPR FPR 6 1 read-write SUSP SUSP 7 1 read-write PR PR 8 1 read-write HSP HSP 9 1 read-only LS LS 10 2 read-write SE0 SE0 0 K_STATE K-state 0x1 J_STATE J-state 0x2 UNDEFINED Undefined 0x3 PP PP 12 1 read-write PO PO 13 1 read-write PIC PIC 14 2 read-write PORT_INDICATOR_OFF Port indicators are off 0 PORT_IND_AMBER Amber 0x1 PORT_IND_GREEN Green 0x2 UNDEFINED Undefined 0x3 PTC PTC 16 4 read-write TST_MODE_DIS TEST_MODE_DISABLE 0 J_STATE J_STATE 0x1 K_STATE K_STATE 0x2 SE0 SE0 (host) / NAK (device) 0x3 PCKT Packet 0x4 HS FORCE_ENABLE_HS 0x5 FS FORCE_ENABLE_FS 0x6 LS FORCE_ENABLE_LS 0x7 WKCN WKCN 20 1 read-write WKDC WKDC 21 1 read-write WKOC WKOC 22 1 read-write PHCD PHCD 23 1 read-write PHY_CLK_EN Enable PHY clock 0 PHY_CLK_DIS Disable PHY clock 0x1 PFSC PFSC 24 1 read-write NORMAL Normal operation 0 FULL_SPEED Forced to full speed 0x1 PTS_2 PTS_2 25 1 read-write PSPD PSPD 26 2 read-write FS Full Speed 0 LS Low Speed 0x1 HS High Speed 0x2 UNDEFINED Undefined 0x3 PTW PTW 28 1 read-write UTMI_8 Select the 8-bit UTMI interface [60MHz] 0 UTMI_16 Select the 16-bit UTMI interface [30MHz] 0x1 STS STS 29 1 read-write PTS_1 PTS_1 30 2 read-write OTGSC On-The-Go Status & control 0x1A4 32 read-write 0x202F20 0xFFFFFFFF VD VD 0 1 read-write VC VC 1 1 read-write OT OT 3 1 read-write DP DP 4 1 read-write IDPU IDPU 5 1 read-write ID ID 8 1 read-only AVV AVV 9 1 read-only ASV ASV 10 1 read-only BSV BSV 11 1 read-only BSE BSE 12 1 read-only TOG_1MS TOG_1MS 13 1 read-only DPS DPS 14 1 read-only IDIS IDIS 16 1 read-write AVVIS AVVIS 17 1 read-write ASVIS ASVIS 18 1 read-write BSVIS BSVIS 19 1 read-write BSEIS BSEIS 20 1 read-write STATUS_1MS STATUS_1MS 21 1 read-write DPIS DPIS 22 1 read-write IDIE IDIE 24 1 read-write AVVIE AVVIE 25 1 read-write ASVIE ASVIE 26 1 read-write BSVIE BSVIE 27 1 read-write BSEIE BSEIE 28 1 read-write EN_1MS EN_1MS 29 1 read-write DPIE DPIE 30 1 read-write USBMODE USB Device Mode 0x1A8 32 read-write 0x5000 0xFFFFFFFF CM CM 0 2 read-write IDL Idle [Default for combination host/device] 0 DEVICE_CONTR Device Controller [Default for device only controller] 0x2 HOST_CONTR Host Controller [Default for host only controller] 0x3 ES ES 2 1 read-write LITTLE_ENDIAN Little Endian [Default] 0 BIG_ENDIAN Big Endian 0x1 SLOM SLOM 3 1 read-write LOCKOUT_ON Setup Lockouts On (default); 0 LOCKOUT_OFF Setup Lockouts Off 0x1 SDIS SDIS 4 1 read-write ENDPTSETUPSTAT Endpoint Setup Status 0x1AC 32 read-write 0 0xFFFFFFFF ENDPTSETUPSTAT ENDPTSETUPSTAT 0 16 read-write ENDPTPRIME Endpoint Prime 0x1B0 32 read-write 0 0xFFFFFFFF PERB PERB 0 8 read-write PETB PETB 16 8 read-write ENDPTFLUSH Endpoint Flush 0x1B4 32 read-write 0 0xFFFFFFFF FERB FERB 0 8 read-write FETB FETB 16 8 read-write ENDPTSTAT Endpoint Status 0x1B8 32 read-only 0 0xFFFFFFFF ERBR ERBR 0 8 read-only ETBR ETBR 16 8 read-only ENDPTCOMPLETE Endpoint Complete 0x1BC 32 read-write 0 0xFFFFFFFF ERCE ERCE 0 8 read-write ETCE ETCE 16 8 read-write ENDPTCTRL0 Endpoint Control0 0x1C0 32 read-write 0x800080 0xFFFFFFFF RXS RXS 0 1 read-write RXT RXT 2 2 read-write RXE RXE 7 1 read-write TXS TXS 16 1 read-write TXT TXT 18 2 read-write TXE TXE 23 1 read-write ENDPTCTRL1 Endpoint Control 1 0x1C4 32 read-write 0 0xFFFFFFFF RXS RXS 0 1 read-write RXD RXD 1 1 read-write RXT RXT 2 2 read-write RXI RXI 5 1 read-write RXR RXR 6 1 read-write RXE RXE 7 1 read-write TXS TXS 16 1 read-write TXD TXD 17 1 read-write TXT TXT 18 2 read-write TXI TXI 21 1 read-write TXR TXR 22 1 read-write TXE TXE 23 1 read-write ENDPTCTRL2 Endpoint Control 2 0x1C8 32 read-write 0 0xFFFFFFFF RXS RXS 0 1 read-write RXD RXD 1 1 read-write RXT RXT 2 2 read-write RXI RXI 5 1 read-write RXR RXR 6 1 read-write RXE RXE 7 1 read-write TXS TXS 16 1 read-write TXD TXD 17 1 read-write TXT TXT 18 2 read-write TXI TXI 21 1 read-write TXR TXR 22 1 read-write TXE TXE 23 1 read-write ENDPTCTRL3 Endpoint Control 3 0x1CC 32 read-write 0 0xFFFFFFFF RXS RXS 0 1 read-write RXD RXD 1 1 read-write RXT RXT 2 2 read-write RXI RXI 5 1 read-write RXR RXR 6 1 read-write RXE RXE 7 1 read-write TXS TXS 16 1 read-write TXD TXD 17 1 read-write TXT TXT 18 2 read-write TXI TXI 21 1 read-write TXR TXR 22 1 read-write TXE TXE 23 1 read-write ENDPTCTRL4 Endpoint Control 4 0x1D0 32 read-write 0 0xFFFFFFFF RXS RXS 0 1 read-write RXD RXD 1 1 read-write RXT RXT 2 2 read-write RXI RXI 5 1 read-write RXR RXR 6 1 read-write RXE RXE 7 1 read-write TXS TXS 16 1 read-write TXD TXD 17 1 read-write TXT TXT 18 2 read-write TXI TXI 21 1 read-write TXR TXR 22 1 read-write TXE TXE 23 1 read-write ENDPTCTRL5 Endpoint Control 5 0x1D4 32 read-write 0 0xFFFFFFFF RXS RXS 0 1 read-write RXD RXD 1 1 read-write RXT RXT 2 2 read-write RXI RXI 5 1 read-write RXR RXR 6 1 read-write RXE RXE 7 1 read-write TXS TXS 16 1 read-write TXD TXD 17 1 read-write TXT TXT 18 2 read-write TXI TXI 21 1 read-write TXR TXR 22 1 read-write TXE TXE 23 1 read-write ENDPTCTRL6 Endpoint Control 6 0x1D8 32 read-write 0 0xFFFFFFFF RXS RXS 0 1 read-write RXD RXD 1 1 read-write RXT RXT 2 2 read-write RXI RXI 5 1 read-write RXR RXR 6 1 read-write RXE RXE 7 1 read-write TXS TXS 16 1 read-write TXD TXD 17 1 read-write TXT TXT 18 2 read-write TXI TXI 21 1 read-write TXR TXR 22 1 read-write TXE TXE 23 1 read-write ENDPTCTRL7 Endpoint Control 7 0x1DC 32 read-write 0 0xFFFFFFFF RXS RXS 0 1 read-write RXD RXD 1 1 read-write RXT RXT 2 2 read-write RXI RXI 5 1 read-write RXR RXR 6 1 read-write RXE RXE 7 1 read-write TXS TXS 16 1 read-write TXD TXD 17 1 read-write TXT TXT 18 2 read-write TXI TXI 21 1 read-write TXR TXR 22 1 read-write TXE TXE 23 1 read-write USB_OTG2 USB USB 0x4042C000 0 0x1E0 registers USB_OTG2 135 USBNC_OTG1 USBNC USBNC USBNC 0x40430200 0 0x14 registers CTRL1 USB OTG Control 1 Register 0 32 read-write 0x30001000 0xFFFFFFFF OVER_CUR_DIS OVER_CUR_DIS 7 1 read-write OVRCRNT_DETCT_EN Enables overcurrent detection 0 OVRCRNT_DETCT_DIS Disables overcurrent detection 0x1 OVER_CUR_POL OVER_CUR_POL 8 1 read-write ACTIVE_HI_OVRCRNT High active (high on this signal represents an overcurrent condition) 0 ACTIVE_LOW_OVRCRNT Low active (low on this signal represents an overcurrent condition) 0x1 PWR_POL PWR_POL 9 1 read-write ACTIVE_LO_PMIC PMIC Power Pin is Low active. 0 ACTIVE_HI_PMIC PMIC Power Pin is High active. 0x1 WIE WIE 10 1 read-write INT_DIS Interrupt Disabled 0 INT_EN Interrupt Enabled 0x1 WKUP_SW_EN WKUP_SW_EN 14 1 read-write SW_WKUP_DIS Disable 0 SW_WKUP_EN Enable 0x1 WKUP_SW WKUP_SW 15 1 read-write INACTIVE Inactive 0 FORCE_WKUP Force wake-up 0x1 WKUP_ID_EN WKUP_ID_EN 16 1 read-write WKUP_ID_DIS Disable 0 WKUP_ID_EN Enable 0x1 WKUP_VBUS_EN WKUP_VBUS_EN 17 1 read-write WKUP_VBUS_DIS Disable 0 WKUP_VBUS_EN Enable 0x1 WKUP_DPDM_EN Wake-up on DPDM change enable 29 1 read-write DPDM_WKUP_DIS DPDM changes wake-up to be disabled only when VBUS is 0. 0 DPDM_WKUP_EN (Default) DPDM changes wake-up to be enabled, it is for device only. 0x1 WIR WIR 31 1 read-only NO_WKUP_REQ No wake-up interrupt request received 0 WKUP_REQ Wake-up Interrupt Request received 0x1 CTRL2 USB OTG Control 2 Register 0x4 32 read-write 0x5F000000 0xFFFFFFFF VBUS_SOURCE_SEL VBUS_SOURCE_SEL 0 2 read-write VBUS_VALID vbus_valid 0 SESS_VALID_1 sess_valid 0x1 SESS_VALID_2 sess_valid 0x2 SESS_VALID_3 sess_valid 0x3 AUTURESUME_EN Auto Resume Enable 2 1 read-write DEFAULT Default 0 LOWSPEED_EN LOWSPEED_EN 3 1 read-write DEFAULT Default 0 UTMI_CLK_VLD UTMI_CLK_VLD 31 1 read-write oneToClear DEFAULT Default 0 HSIC_CTRL USB Host HSIC Control Register 0x10 32 read-write 0x10004084 0xFFFFFFFF HSIC_CLK_ON HSIC_CLK_ON 11 1 read-write INACTIVE Inactive 0 ACTIVE Active 0x1 HSIC_EN HSIC_EN 12 1 read-write DISABLE Disabled 0 ENABLE Enabled 0x1 CLK_VLD CLK_VLD 31 1 read-only INVALID Invalid 0 VALID Valid 0x1 USBNC_OTG2 USBNC USBNC 0x4042C200 0 0x14 registers USBPHY1 USBPHY USBPHY USBPHY 0x40434000 0 0x140 registers USBPHY1 90 PWD USB PHY Power-Down Register 0 32 read-write 0x1E1C00 0xFFFFFFFF TXPWDFS TXPWDFS 10 1 read-write NORMAL Normal operation. 0 PWR_DOWN Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output 0x1 TXPWDIBIAS TXPWDIBIAS 11 1 read-write NORMAL Normal operation 0 PWR_DOWN Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path 0x1 TXPWDV2I TXPWDV2I 12 1 read-write NORMAL Normal operation. 0 PWR_DOWN Power-down the USB PHY transmit V-to-I converter and the current mirror 0x1 RXPWDENV RXPWDENV 17 1 read-write NORMAL Normal operation. 0 PWR_DOWN Power-down the USB high-speed receiver envelope detector (squelch signal) 0x1 RXPWD1PT1 RXPWD1PT1 18 1 read-write NORMAL Normal operation 0 PWR_DOWN Power-down the USB full-speed differential receiver. 0x1 RXPWDDIFF RXPWDDIFF 19 1 read-write NORMAL Normal operation. 0 PWR_DOWN Power-down the USB high-speed differential receiver 0x1 RXPWDRX RXPWDRX 20 1 read-write NORMAL Normal operation 0 PWR_DOWN Power-down the entire USB PHY receiver block except for the full-speed differential receiver 0x1 PWD_SET USB PHY Power-Down Register 0x4 32 read-write 0x1E1C00 0xFFFFFFFF oneToSet TXPWDFS TXPWDFS 10 1 read-write oneToSet TXPWDIBIAS TXPWDIBIAS 11 1 read-write oneToSet TXPWDV2I TXPWDV2I 12 1 read-write oneToSet RXPWDENV RXPWDENV 17 1 read-write oneToSet RXPWD1PT1 RXPWD1PT1 18 1 read-write oneToSet RXPWDDIFF RXPWDDIFF 19 1 read-write oneToSet RXPWDRX RXPWDRX 20 1 read-write oneToSet PWD_CLR USB PHY Power-Down Register 0x8 32 read-write 0x1E1C00 0xFFFFFFFF oneToClear TXPWDFS TXPWDFS 10 1 read-write oneToClear TXPWDIBIAS TXPWDIBIAS 11 1 read-write oneToClear TXPWDV2I TXPWDV2I 12 1 read-write oneToClear RXPWDENV RXPWDENV 17 1 read-write oneToClear RXPWD1PT1 RXPWD1PT1 18 1 read-write oneToClear RXPWDDIFF RXPWDDIFF 19 1 read-write oneToClear RXPWDRX RXPWDRX 20 1 read-write oneToClear PWD_TOG USB PHY Power-Down Register 0xC 32 read-write 0x1E1C00 0xFFFFFFFF oneToToggle TXPWDFS TXPWDFS 10 1 read-write oneToToggle TXPWDIBIAS TXPWDIBIAS 11 1 read-write oneToToggle TXPWDV2I TXPWDV2I 12 1 read-write oneToToggle RXPWDENV RXPWDENV 17 1 read-write oneToToggle RXPWD1PT1 RXPWD1PT1 18 1 read-write oneToToggle RXPWDDIFF RXPWDDIFF 19 1 read-write oneToToggle RXPWDRX RXPWDRX 20 1 read-write oneToToggle TX USB PHY Transmitter Control Register 0x10 32 read-write 0x10060607 0xFFFFFFFF D_CAL D_CAL 0 4 read-write MAX Maximum current, approximately 19% above nominal. 0 NOMINAL Nominal 0x7 MIN Minimum current, approximately 19% below nominal. 0xF TXCAL45DN TXCAL45DN 8 4 read-write TXCAL45DP TXCAL45DP 16 4 read-write TX_SET USB PHY Transmitter Control Register 0x14 32 read-write 0x10060607 0xFFFFFFFF oneToSet D_CAL D_CAL 0 4 read-write oneToSet TXCAL45DN TXCAL45DN 8 4 read-write oneToSet TXCAL45DP TXCAL45DP 16 4 read-write oneToSet TX_CLR USB PHY Transmitter Control Register 0x18 32 read-write 0x10060607 0xFFFFFFFF oneToClear D_CAL D_CAL 0 4 read-write oneToClear TXCAL45DN TXCAL45DN 8 4 read-write oneToClear TXCAL45DP TXCAL45DP 16 4 read-write oneToClear TX_TOG USB PHY Transmitter Control Register 0x1C 32 read-write 0x10060607 0xFFFFFFFF oneToToggle D_CAL D_CAL 0 4 read-write oneToToggle TXCAL45DN TXCAL45DN 8 4 read-write oneToToggle TXCAL45DP TXCAL45DP 16 4 read-write oneToToggle RX USB PHY Receiver Control Register 0x20 32 read-write 0 0xFFFFFFFF ENVADJ ENVADJ 0 3 read-write LVL_P1 Trip-Level Voltage is 0.1000 V 0 LVL_P1125 Trip-Level Voltage is 0.1125 V 0x1 LVL_P1250 Trip-Level Voltage is 0.1250 V 0x2 LVL_P0875 Trip-Level Voltage is 0.0875 V 0x3 DISCONADJ DISCONADJ 4 3 read-write LVL_P56875 Trip-Level Voltage is 0.56875 V 0 LVL_P55 Trip-Level Voltage is 0.55000 V 0x1 LVL_P58125 Trip-Level Voltage is 0.58125 V 0x2 LVL_P6 Trip-Level Voltage is 0.60000 V 0x3 RXDBYPASS RXDBYPASS 22 1 read-write NORMAL Normal operation. 0 OUT_SINGLE_END Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver 0x1 RX_SET USB PHY Receiver Control Register 0x24 32 read-write 0 0xFFFFFFFF oneToSet ENVADJ ENVADJ 0 3 read-write oneToSet DISCONADJ DISCONADJ 4 3 read-write oneToSet RXDBYPASS RXDBYPASS 22 1 read-write oneToSet RX_CLR USB PHY Receiver Control Register 0x28 32 read-write 0 0xFFFFFFFF oneToClear ENVADJ ENVADJ 0 3 read-write oneToClear DISCONADJ DISCONADJ 4 3 read-write oneToClear RXDBYPASS RXDBYPASS 22 1 read-write oneToClear RX_TOG USB PHY Receiver Control Register 0x2C 32 read-write 0 0xFFFFFFFF oneToToggle ENVADJ ENVADJ 0 3 read-write oneToToggle DISCONADJ DISCONADJ 4 3 read-write oneToToggle RXDBYPASS RXDBYPASS 22 1 read-write oneToToggle CTRL USB PHY General Control Register 0x30 32 read-write 0x88000000 0xFFFFFFFF ENOTG_ID_CHG_IRQ ENOTG_ID_CHG_IRQ 0 1 read-write ENHOSTDISCONDETECT ENHOSTDISCONDETECT 1 1 read-write ENIRQHOSTDISCON ENIRQHOSTDISCON 2 1 read-write HOSTDISCONDETECT_IRQ HOSTDISCONDETECT_IRQ 3 1 read-write ENDEVPLUGINDETECT Enables non-standard resistive plugged-in detection 4 1 read-write DISABLE Disables 200kohm pullup resistors on DP and DN pins 0 ENABLE Enables 200kohm pullup resistors on DP and DN pins 0x1 DEVPLUGIN_POLARITY DEVPLUGIN_POLARITY 5 1 read-write OTG_ID_CHG_IRQ OTG_ID_CHG_IRQ 6 1 read-write ENOTGIDDETECT ENOTGIDDETECT 7 1 read-write RESUMEIRQSTICKY RESUMEIRQSTICKY 8 1 read-write ENIRQRESUMEDETECT ENIRQRESUMEDETECT 9 1 read-write RESUME_IRQ RESUME_IRQ 10 1 read-write ENIRQDEVPLUGIN ENIRQDEVPLUGIN 11 1 read-write DEVPLUGIN_IRQ DEVPLUGIN_IRQ 12 1 read-write ENUTMILEVEL2 ENUTMILEVEL2 14 1 read-write ENUTMILEVEL3 ENUTMILEVEL3 15 1 read-write ENIRQWAKEUP ENIRQWAKEUP 16 1 read-write WAKEUP_IRQ WAKEUP_IRQ 17 1 read-write AUTORESUME_EN AUTORESUME_EN 18 1 read-write ENAUTOCLR_CLKGATE ENAUTOCLR_CLKGATE 19 1 read-write ENAUTOCLR_PHY_PWD ENAUTOCLR_PHY_PWD 20 1 read-write ENDPDMCHG_WKUP ENDPDMCHG_WKUP 21 1 read-write ENIDCHG_WKUP ENIDCHG_WKUP 22 1 read-write ENVBUSCHG_WKUP ENVBUSCHG_WKUP 23 1 read-write FSDLL_RST_EN FSDLL_RST_EN 24 1 read-write OTG_ID_VALUE OTG_ID_VALUE 27 1 read-only HOST_FORCE_LS_SE0 HOST_FORCE_LS_SE0 28 1 read-write UTMI_SUSPENDM UTMI_SUSPENDM 29 1 read-only CLKGATE CLKGATE 30 1 read-write SFTRST SFTRST 31 1 read-write CTRL_SET USB PHY General Control Register 0x34 32 read-write 0x88000000 0xFFFFFFFF oneToSet ENOTG_ID_CHG_IRQ ENOTG_ID_CHG_IRQ 0 1 read-write oneToSet ENHOSTDISCONDETECT ENHOSTDISCONDETECT 1 1 read-write oneToSet ENIRQHOSTDISCON ENIRQHOSTDISCON 2 1 read-write oneToSet HOSTDISCONDETECT_IRQ HOSTDISCONDETECT_IRQ 3 1 read-write oneToSet ENDEVPLUGINDETECT Enables non-standard resistive plugged-in detection 4 1 read-write oneToSet DEVPLUGIN_POLARITY DEVPLUGIN_POLARITY 5 1 read-write oneToSet OTG_ID_CHG_IRQ OTG_ID_CHG_IRQ 6 1 read-write oneToSet ENOTGIDDETECT ENOTGIDDETECT 7 1 read-write oneToSet RESUMEIRQSTICKY RESUMEIRQSTICKY 8 1 read-write oneToSet ENIRQRESUMEDETECT ENIRQRESUMEDETECT 9 1 read-write oneToSet RESUME_IRQ RESUME_IRQ 10 1 read-write oneToSet ENIRQDEVPLUGIN ENIRQDEVPLUGIN 11 1 read-write oneToSet DEVPLUGIN_IRQ DEVPLUGIN_IRQ 12 1 read-write oneToSet ENUTMILEVEL2 ENUTMILEVEL2 14 1 read-write oneToSet ENUTMILEVEL3 ENUTMILEVEL3 15 1 read-write oneToSet ENIRQWAKEUP ENIRQWAKEUP 16 1 read-write oneToSet WAKEUP_IRQ WAKEUP_IRQ 17 1 read-write oneToSet AUTORESUME_EN AUTORESUME_EN 18 1 read-write oneToSet ENAUTOCLR_CLKGATE ENAUTOCLR_CLKGATE 19 1 read-write oneToSet ENAUTOCLR_PHY_PWD ENAUTOCLR_PHY_PWD 20 1 read-write oneToSet ENDPDMCHG_WKUP ENDPDMCHG_WKUP 21 1 read-write oneToSet ENIDCHG_WKUP ENIDCHG_WKUP 22 1 read-write oneToSet ENVBUSCHG_WKUP ENVBUSCHG_WKUP 23 1 read-write oneToSet FSDLL_RST_EN FSDLL_RST_EN 24 1 read-write oneToSet OTG_ID_VALUE OTG_ID_VALUE 27 1 read-only oneToSet HOST_FORCE_LS_SE0 HOST_FORCE_LS_SE0 28 1 read-write oneToSet UTMI_SUSPENDM UTMI_SUSPENDM 29 1 read-only oneToSet CLKGATE CLKGATE 30 1 read-write oneToSet SFTRST SFTRST 31 1 read-write oneToSet CTRL_CLR USB PHY General Control Register 0x38 32 read-write 0x88000000 0xFFFFFFFF oneToClear ENOTG_ID_CHG_IRQ ENOTG_ID_CHG_IRQ 0 1 read-write oneToClear ENHOSTDISCONDETECT ENHOSTDISCONDETECT 1 1 read-write oneToClear ENIRQHOSTDISCON ENIRQHOSTDISCON 2 1 read-write oneToClear HOSTDISCONDETECT_IRQ HOSTDISCONDETECT_IRQ 3 1 read-write oneToClear ENDEVPLUGINDETECT Enables non-standard resistive plugged-in detection 4 1 read-write oneToClear DEVPLUGIN_POLARITY DEVPLUGIN_POLARITY 5 1 read-write oneToClear OTG_ID_CHG_IRQ OTG_ID_CHG_IRQ 6 1 read-write oneToClear ENOTGIDDETECT ENOTGIDDETECT 7 1 read-write oneToClear RESUMEIRQSTICKY RESUMEIRQSTICKY 8 1 read-write oneToClear ENIRQRESUMEDETECT ENIRQRESUMEDETECT 9 1 read-write oneToClear RESUME_IRQ RESUME_IRQ 10 1 read-write oneToClear ENIRQDEVPLUGIN ENIRQDEVPLUGIN 11 1 read-write oneToClear DEVPLUGIN_IRQ DEVPLUGIN_IRQ 12 1 read-write oneToClear ENUTMILEVEL2 ENUTMILEVEL2 14 1 read-write oneToClear ENUTMILEVEL3 ENUTMILEVEL3 15 1 read-write oneToClear ENIRQWAKEUP ENIRQWAKEUP 16 1 read-write oneToClear WAKEUP_IRQ WAKEUP_IRQ 17 1 read-write oneToClear AUTORESUME_EN AUTORESUME_EN 18 1 read-write oneToClear ENAUTOCLR_CLKGATE ENAUTOCLR_CLKGATE 19 1 read-write oneToClear ENAUTOCLR_PHY_PWD ENAUTOCLR_PHY_PWD 20 1 read-write oneToClear ENDPDMCHG_WKUP ENDPDMCHG_WKUP 21 1 read-write oneToClear ENIDCHG_WKUP ENIDCHG_WKUP 22 1 read-write oneToClear ENVBUSCHG_WKUP ENVBUSCHG_WKUP 23 1 read-write oneToClear FSDLL_RST_EN FSDLL_RST_EN 24 1 read-write oneToClear OTG_ID_VALUE OTG_ID_VALUE 27 1 read-only oneToClear HOST_FORCE_LS_SE0 HOST_FORCE_LS_SE0 28 1 read-write oneToClear UTMI_SUSPENDM UTMI_SUSPENDM 29 1 read-only oneToClear CLKGATE CLKGATE 30 1 read-write oneToClear SFTRST SFTRST 31 1 read-write oneToClear CTRL_TOG USB PHY General Control Register 0x3C 32 read-write 0x88000000 0xFFFFFFFF oneToToggle ENOTG_ID_CHG_IRQ ENOTG_ID_CHG_IRQ 0 1 read-write oneToToggle ENHOSTDISCONDETECT ENHOSTDISCONDETECT 1 1 read-write oneToToggle ENIRQHOSTDISCON ENIRQHOSTDISCON 2 1 read-write oneToToggle HOSTDISCONDETECT_IRQ HOSTDISCONDETECT_IRQ 3 1 read-write oneToToggle ENDEVPLUGINDETECT Enables non-standard resistive plugged-in detection 4 1 read-write oneToToggle DEVPLUGIN_POLARITY DEVPLUGIN_POLARITY 5 1 read-write oneToToggle OTG_ID_CHG_IRQ OTG_ID_CHG_IRQ 6 1 read-write oneToToggle ENOTGIDDETECT ENOTGIDDETECT 7 1 read-write oneToToggle RESUMEIRQSTICKY RESUMEIRQSTICKY 8 1 read-write oneToToggle ENIRQRESUMEDETECT ENIRQRESUMEDETECT 9 1 read-write oneToToggle RESUME_IRQ RESUME_IRQ 10 1 read-write oneToToggle ENIRQDEVPLUGIN ENIRQDEVPLUGIN 11 1 read-write oneToToggle DEVPLUGIN_IRQ DEVPLUGIN_IRQ 12 1 read-write oneToToggle ENUTMILEVEL2 ENUTMILEVEL2 14 1 read-write oneToToggle ENUTMILEVEL3 ENUTMILEVEL3 15 1 read-write oneToToggle ENIRQWAKEUP ENIRQWAKEUP 16 1 read-write oneToToggle WAKEUP_IRQ WAKEUP_IRQ 17 1 read-write oneToToggle AUTORESUME_EN AUTORESUME_EN 18 1 read-write oneToToggle ENAUTOCLR_CLKGATE ENAUTOCLR_CLKGATE 19 1 read-write oneToToggle ENAUTOCLR_PHY_PWD ENAUTOCLR_PHY_PWD 20 1 read-write oneToToggle ENDPDMCHG_WKUP ENDPDMCHG_WKUP 21 1 read-write oneToToggle ENIDCHG_WKUP ENIDCHG_WKUP 22 1 read-write oneToToggle ENVBUSCHG_WKUP ENVBUSCHG_WKUP 23 1 read-write oneToToggle FSDLL_RST_EN FSDLL_RST_EN 24 1 read-write oneToToggle OTG_ID_VALUE OTG_ID_VALUE 27 1 read-only oneToToggle HOST_FORCE_LS_SE0 HOST_FORCE_LS_SE0 28 1 read-write oneToToggle UTMI_SUSPENDM UTMI_SUSPENDM 29 1 read-only oneToToggle CLKGATE CLKGATE 30 1 read-write oneToToggle SFTRST SFTRST 31 1 read-write oneToToggle STATUS USB PHY Status Register 0x40 32 read-write 0 0xFFFFFFFF HOSTDISCONDETECT_STATUS HOSTDISCONDETECT_STATUS 3 1 read-only NOT_DET USB cable disconnect has not been detected at the local host 0 DET USB cable disconnect has been detected at the local host 0x1 DEVPLUGIN_STATUS Status indicator for non-standard resistive plugged-in detection 6 1 read-only NO_ATTACH No attachment to a USB host is detected 0 ATTACH Cable attachment to a USB host is detected 0x1 OTGID_STATUS OTGID_STATUS 8 1 read-write RESUME_STATUS RESUME_STATUS 10 1 read-only DEBUG USB PHY Debug Register 0x50 32 read-write 0x7F180000 0xFFFFFFFF OTGIDPIOLOCK OTGIDPIOLOCK 0 1 read-write DEBUG_INTERFACE_HOLD DEBUG_INTERFACE_HOLD 1 1 read-write HSTPULLDOWN HSTPULLDOWN 2 2 read-write ENHSTPULLDOWN ENHSTPULLDOWN 4 2 read-write TX2RXCOUNT TX2RXCOUNT 8 4 read-write ENTX2RXCOUNT ENTX2RXCOUNT 12 1 read-write SQUELCHRESETCOUNT SQUELCHRESETCOUNT 16 5 read-write ENSQUELCHRESET ENSQUELCHRESET 24 1 read-write SQUELCHRESETLENGTH SQUELCHRESETLENGTH 25 4 read-write HOST_RESUME_DEBUG HOST_RESUME_DEBUG 29 1 read-write CLKGATE CLKGATE 30 1 read-write DEBUG_SET USB PHY Debug Register 0x54 32 read-write 0x7F180000 0xFFFFFFFF oneToSet OTGIDPIOLOCK OTGIDPIOLOCK 0 1 read-write oneToSet DEBUG_INTERFACE_HOLD DEBUG_INTERFACE_HOLD 1 1 read-write oneToSet HSTPULLDOWN HSTPULLDOWN 2 2 read-write oneToSet ENHSTPULLDOWN ENHSTPULLDOWN 4 2 read-write oneToSet TX2RXCOUNT TX2RXCOUNT 8 4 read-write oneToSet ENTX2RXCOUNT ENTX2RXCOUNT 12 1 read-write oneToSet SQUELCHRESETCOUNT SQUELCHRESETCOUNT 16 5 read-write oneToSet ENSQUELCHRESET ENSQUELCHRESET 24 1 read-write oneToSet SQUELCHRESETLENGTH SQUELCHRESETLENGTH 25 4 read-write oneToSet HOST_RESUME_DEBUG HOST_RESUME_DEBUG 29 1 read-write oneToSet CLKGATE CLKGATE 30 1 read-write oneToSet DEBUG_CLR USB PHY Debug Register 0x58 32 read-write 0x7F180000 0xFFFFFFFF oneToClear OTGIDPIOLOCK OTGIDPIOLOCK 0 1 read-write oneToClear DEBUG_INTERFACE_HOLD DEBUG_INTERFACE_HOLD 1 1 read-write oneToClear HSTPULLDOWN HSTPULLDOWN 2 2 read-write oneToClear ENHSTPULLDOWN ENHSTPULLDOWN 4 2 read-write oneToClear TX2RXCOUNT TX2RXCOUNT 8 4 read-write oneToClear ENTX2RXCOUNT ENTX2RXCOUNT 12 1 read-write oneToClear SQUELCHRESETCOUNT SQUELCHRESETCOUNT 16 5 read-write oneToClear ENSQUELCHRESET ENSQUELCHRESET 24 1 read-write oneToClear SQUELCHRESETLENGTH SQUELCHRESETLENGTH 25 4 read-write oneToClear HOST_RESUME_DEBUG HOST_RESUME_DEBUG 29 1 read-write oneToClear CLKGATE CLKGATE 30 1 read-write oneToClear DEBUG_TOG USB PHY Debug Register 0x5C 32 read-write 0x7F180000 0xFFFFFFFF oneToToggle OTGIDPIOLOCK OTGIDPIOLOCK 0 1 read-write oneToToggle DEBUG_INTERFACE_HOLD DEBUG_INTERFACE_HOLD 1 1 read-write oneToToggle HSTPULLDOWN HSTPULLDOWN 2 2 read-write oneToToggle ENHSTPULLDOWN ENHSTPULLDOWN 4 2 read-write oneToToggle TX2RXCOUNT TX2RXCOUNT 8 4 read-write oneToToggle ENTX2RXCOUNT ENTX2RXCOUNT 12 1 read-write oneToToggle SQUELCHRESETCOUNT SQUELCHRESETCOUNT 16 5 read-write oneToToggle ENSQUELCHRESET ENSQUELCHRESET 24 1 read-write oneToToggle SQUELCHRESETLENGTH SQUELCHRESETLENGTH 25 4 read-write oneToToggle HOST_RESUME_DEBUG HOST_RESUME_DEBUG 29 1 read-write oneToToggle CLKGATE CLKGATE 30 1 read-write oneToToggle DEBUG0_STATUS UTMI Debug Status Register 0 0x60 32 read-only 0 0xFFFFFFFF LOOP_BACK_FAIL_COUNT LOOP_BACK_FAIL_COUNT 0 16 read-only UTMI_RXERROR_FAIL_COUNT UTMI_RXERROR_FAIL_COUNT 16 10 read-only SQUELCH_COUNT SQUELCH_COUNT 26 6 read-only DEBUG1 UTMI Debug Status Register 1 0x70 32 read-write 0x1000 0xFFFFFFFF ENTAILADJVD ENTAILADJVD 13 2 read-write NOM_DELAY Delay is nominal 0 DELAY_20_P Delay is +20% 0x1 DELAY_20_N Delay is -20% 0x2 DELAY_40_N Delay is -40% 0x3 USB2_REFBIAS_SELFBIASOFF Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. 15 1 read-write USB2_REFBIAS_PWDVBGUP Powers down the bandgap detect logic, will affect vbgup on misc1 register. 16 1 read-write USB2_REFBIAS_LOWPWR to be added 17 1 read-write USB2_REFBIAS_VBGADJ Adjustment bits on bandgap 18 3 read-write USB2_REFBIAS_TST Bias current control for usb2_phy 21 2 read-write DEBUG1_SET UTMI Debug Status Register 1 0x74 32 read-write 0x1000 0xFFFFFFFF oneToSet ENTAILADJVD ENTAILADJVD 13 2 read-write oneToSet USB2_REFBIAS_SELFBIASOFF Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. 15 1 read-write oneToSet USB2_REFBIAS_PWDVBGUP Powers down the bandgap detect logic, will affect vbgup on misc1 register. 16 1 read-write oneToSet USB2_REFBIAS_LOWPWR to be added 17 1 read-write oneToSet USB2_REFBIAS_VBGADJ Adjustment bits on bandgap 18 3 read-write oneToSet USB2_REFBIAS_TST Bias current control for usb2_phy 21 2 read-write oneToSet DEBUG1_CLR UTMI Debug Status Register 1 0x78 32 read-write 0x1000 0xFFFFFFFF oneToClear ENTAILADJVD ENTAILADJVD 13 2 read-write oneToClear USB2_REFBIAS_SELFBIASOFF Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. 15 1 read-write oneToClear USB2_REFBIAS_PWDVBGUP Powers down the bandgap detect logic, will affect vbgup on misc1 register. 16 1 read-write oneToClear USB2_REFBIAS_LOWPWR to be added 17 1 read-write oneToClear USB2_REFBIAS_VBGADJ Adjustment bits on bandgap 18 3 read-write oneToClear USB2_REFBIAS_TST Bias current control for usb2_phy 21 2 read-write oneToClear DEBUG1_TOG UTMI Debug Status Register 1 0x7C 32 read-write 0x1000 0xFFFFFFFF oneToToggle ENTAILADJVD ENTAILADJVD 13 2 read-write oneToToggle USB2_REFBIAS_SELFBIASOFF Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. 15 1 read-write oneToToggle USB2_REFBIAS_PWDVBGUP Powers down the bandgap detect logic, will affect vbgup on misc1 register. 16 1 read-write oneToToggle USB2_REFBIAS_LOWPWR to be added 17 1 read-write oneToToggle USB2_REFBIAS_VBGADJ Adjustment bits on bandgap 18 3 read-write oneToToggle USB2_REFBIAS_TST Bias current control for usb2_phy 21 2 read-write oneToToggle VERSION UTMI RTL Version 0x80 32 read-only 0x4030000 0xFFFFFFFF STEP STEP 0 16 read-only MINOR MINOR 16 8 read-only MAJOR MAJOR 24 8 read-only PLL_SIC USB PHY PLL Control/Status Register 0xA0 32 read-write 0xD12000 0xFFFFFFFF PLL_POSTDIV PLL_POSTDIV 2 3 read-write PLL_EN_USB_CLKS PLL_EN_USB_CLKS 6 1 read-write PLL_POWER PLL_POWER 12 1 read-write PLL_ENABLE PLL_ENABLE 13 1 read-write PLL_BYPASS PLL_BYPASS 16 1 read-write REFBIAS_PWD_SEL REFBIAS_PWD_SEL 19 1 read-write PLL_PWR Selects PLL_POWER to control the reference bias 0 REFBIAS_PWD Selects REFBIAS_PWD to control the reference bias. 0x1 REFBIAS_PWD Power down the reference bias 20 1 read-write PLL_REG_ENABLE PLL_REG_ENABLE 21 1 read-write PLL_DIV_SEL PLL_DIV_SEL 22 3 read-write DIV_BY_13 Divide by 13 0 DIV_BY_15 Divide by 15 0x1 DIV_BY_16 Divide by 16 0x2 DIV_BY_20 Divide by 20 0x3 DIV_BY_22 Divide by 22 0x4 DIV_BY_25 Divide by 25 0x5 DIV_BY_30 Divide by 30 0x6 DIV_BY_240 Divide by 240 0x7 PLL_LOCK PLL_LOCK 31 1 read-only NOT_LOCKED PLL is not currently locked 0 LOCKED PLL is currently locked 0x1 PLL_SIC_SET USB PHY PLL Control/Status Register 0xA4 32 read-write 0xD12000 0xFFFFFFFF oneToSet PLL_POSTDIV PLL_POSTDIV 2 3 read-write oneToSet PLL_EN_USB_CLKS PLL_EN_USB_CLKS 6 1 read-write oneToSet PLL_POWER PLL_POWER 12 1 read-write oneToSet PLL_ENABLE PLL_ENABLE 13 1 read-write oneToSet PLL_BYPASS PLL_BYPASS 16 1 read-write oneToSet REFBIAS_PWD_SEL REFBIAS_PWD_SEL 19 1 read-write oneToSet REFBIAS_PWD Power down the reference bias 20 1 read-write oneToSet PLL_REG_ENABLE PLL_REG_ENABLE 21 1 read-write oneToSet PLL_DIV_SEL PLL_DIV_SEL 22 3 read-write oneToSet PLL_LOCK PLL_LOCK 31 1 read-only oneToSet PLL_SIC_CLR USB PHY PLL Control/Status Register 0xA8 32 read-write 0xD12000 0xFFFFFFFF oneToClear PLL_POSTDIV PLL_POSTDIV 2 3 read-write oneToClear PLL_EN_USB_CLKS PLL_EN_USB_CLKS 6 1 read-write oneToClear PLL_POWER PLL_POWER 12 1 read-write oneToClear PLL_ENABLE PLL_ENABLE 13 1 read-write oneToClear PLL_BYPASS PLL_BYPASS 16 1 read-write oneToClear REFBIAS_PWD_SEL REFBIAS_PWD_SEL 19 1 read-write oneToClear REFBIAS_PWD Power down the reference bias 20 1 read-write oneToClear PLL_REG_ENABLE PLL_REG_ENABLE 21 1 read-write oneToClear PLL_DIV_SEL PLL_DIV_SEL 22 3 read-write oneToClear PLL_LOCK PLL_LOCK 31 1 read-only oneToClear PLL_SIC_TOG USB PHY PLL Control/Status Register 0xAC 32 read-write 0xD12000 0xFFFFFFFF oneToToggle PLL_POSTDIV PLL_POSTDIV 2 3 read-write oneToToggle PLL_EN_USB_CLKS PLL_EN_USB_CLKS 6 1 read-write oneToToggle PLL_POWER PLL_POWER 12 1 read-write oneToToggle PLL_ENABLE PLL_ENABLE 13 1 read-write oneToToggle PLL_BYPASS PLL_BYPASS 16 1 read-write oneToToggle REFBIAS_PWD_SEL REFBIAS_PWD_SEL 19 1 read-write oneToToggle REFBIAS_PWD Power down the reference bias 20 1 read-write oneToToggle PLL_REG_ENABLE PLL_REG_ENABLE 21 1 read-write oneToToggle PLL_DIV_SEL PLL_DIV_SEL 22 3 read-write oneToToggle PLL_LOCK PLL_LOCK 31 1 read-only oneToToggle USB1_VBUS_DETECT USB PHY VBUS Detect Control Register 0xC0 32 read-write 0x700004 0xFFFFFFFF VBUSVALID_THRESH VBUSVALID_THRESH 0 3 read-write VOLT_4 4.0 V 0 VOLT_4P1 4.1 V 0x1 VOLT_4P2 4.2 V 0x2 VOLT_4P3 4.3 V 0x3 VOLT_4P4 4.4 V (Default) 0x4 VOLT_4P5 4.5 V 0x5 VOLT_4P6 4.6 V 0x6 VOLT_4P7 4.7 V 0x7 VBUS_OVERRIDE_EN VBUS detect signal override enable 3 1 read-write INTERNAL Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) 0 OVERRIDE Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND 0x1 SESSEND_OVERRIDE Override value for SESSEND 4 1 read-write BVALID_OVERRIDE Override value for B-Device Session Valid 5 1 read-write AVALID_OVERRIDE Override value for A-Device Session Valid 6 1 read-write VBUSVALID_OVERRIDE Override value for VBUS_VALID signal sent to USB controller 7 1 read-write VBUSVALID_SEL Selects the source of the VBUS_VALID signal reported to the USB controller 8 1 read-write COMP Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) 0 DET_3V Use the VBUS_VALID_3V detector results for signal reported to the USB controller 0x1 VBUS_SOURCE_SEL Selects the source of the VBUS_VALID signal reported to the USB controller 9 2 read-write VBUS_VALID_COMP Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) 0 SESSION_VALID_COMP Use the Session Valid comparator results for signal reported to the USB controller 0x1 SESSION_VALID_COMP_1 Use the Session Valid comparator results for signal reported to the USB controller 0x2 ID_OVERRIDE_EN TBA 11 1 read-write ID_OVERRIDE TBA 12 1 read-write VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID 18 1 read-write VBUS_VALID Use the VBUS_VALID comparator for VBUS_VALID results 0 SESSION_VALID Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. 0x1 PWRUP_CMPS Enables the VBUS_VALID comparator 20 3 read-write DISABLE Powers down the VBUS_VALID comparator 0 ENABLE Enables the SESS_VALID comparator (default) 0x1 VDETECT Enables the 3Vdetect (default) 0x2 DISCHARGE_VBUS Controls VBUS discharge resistor 26 1 read-write DISABLE VBUS discharge resistor is disabled (Default) 0 ENABLE VBUS discharge resistor is enabled 0x1 EN_CHARGER_RESISTOR Enables resistors used for an older method of resistive battery charger detection 31 1 read-write DISABLE Disable resistive charger detection resistors on DP and DP 0 ENABLE Enable resistive charger detection resistors on DP and DP 0x1 USB1_VBUS_DETECT_SET USB PHY VBUS Detect Control Register 0xC4 32 read-write 0x700004 0xFFFFFFFF oneToSet VBUSVALID_THRESH VBUSVALID_THRESH 0 3 read-write oneToSet VBUS_OVERRIDE_EN VBUS detect signal override enable 3 1 read-write oneToSet SESSEND_OVERRIDE Override value for SESSEND 4 1 read-write oneToSet BVALID_OVERRIDE Override value for B-Device Session Valid 5 1 read-write oneToSet AVALID_OVERRIDE Override value for A-Device Session Valid 6 1 read-write oneToSet VBUSVALID_OVERRIDE Override value for VBUS_VALID signal sent to USB controller 7 1 read-write oneToSet VBUSVALID_SEL Selects the source of the VBUS_VALID signal reported to the USB controller 8 1 read-write oneToSet VBUS_SOURCE_SEL Selects the source of the VBUS_VALID signal reported to the USB controller 9 2 read-write oneToSet ID_OVERRIDE_EN TBA 11 1 read-write oneToSet ID_OVERRIDE TBA 12 1 read-write oneToSet VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID 18 1 read-write oneToSet PWRUP_CMPS Enables the VBUS_VALID comparator 20 3 read-write oneToSet DISCHARGE_VBUS Controls VBUS discharge resistor 26 1 read-write oneToSet EN_CHARGER_RESISTOR Enables resistors used for an older method of resistive battery charger detection 31 1 read-write oneToSet USB1_VBUS_DETECT_CLR USB PHY VBUS Detect Control Register 0xC8 32 read-write 0x700004 0xFFFFFFFF oneToClear VBUSVALID_THRESH VBUSVALID_THRESH 0 3 read-write oneToClear VBUS_OVERRIDE_EN VBUS detect signal override enable 3 1 read-write oneToClear SESSEND_OVERRIDE Override value for SESSEND 4 1 read-write oneToClear BVALID_OVERRIDE Override value for B-Device Session Valid 5 1 read-write oneToClear AVALID_OVERRIDE Override value for A-Device Session Valid 6 1 read-write oneToClear VBUSVALID_OVERRIDE Override value for VBUS_VALID signal sent to USB controller 7 1 read-write oneToClear VBUSVALID_SEL Selects the source of the VBUS_VALID signal reported to the USB controller 8 1 read-write oneToClear VBUS_SOURCE_SEL Selects the source of the VBUS_VALID signal reported to the USB controller 9 2 read-write oneToClear ID_OVERRIDE_EN TBA 11 1 read-write oneToClear ID_OVERRIDE TBA 12 1 read-write oneToClear VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID 18 1 read-write oneToClear PWRUP_CMPS Enables the VBUS_VALID comparator 20 3 read-write oneToClear DISCHARGE_VBUS Controls VBUS discharge resistor 26 1 read-write oneToClear EN_CHARGER_RESISTOR Enables resistors used for an older method of resistive battery charger detection 31 1 read-write oneToClear USB1_VBUS_DETECT_TOG USB PHY VBUS Detect Control Register 0xCC 32 read-write 0x700004 0xFFFFFFFF oneToToggle VBUSVALID_THRESH VBUSVALID_THRESH 0 3 read-write oneToToggle VBUS_OVERRIDE_EN VBUS detect signal override enable 3 1 read-write oneToToggle SESSEND_OVERRIDE Override value for SESSEND 4 1 read-write oneToToggle BVALID_OVERRIDE Override value for B-Device Session Valid 5 1 read-write oneToToggle AVALID_OVERRIDE Override value for A-Device Session Valid 6 1 read-write oneToToggle VBUSVALID_OVERRIDE Override value for VBUS_VALID signal sent to USB controller 7 1 read-write oneToToggle VBUSVALID_SEL Selects the source of the VBUS_VALID signal reported to the USB controller 8 1 read-write oneToToggle VBUS_SOURCE_SEL Selects the source of the VBUS_VALID signal reported to the USB controller 9 2 read-write oneToToggle ID_OVERRIDE_EN TBA 11 1 read-write oneToToggle ID_OVERRIDE TBA 12 1 read-write oneToToggle VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID 18 1 read-write oneToToggle PWRUP_CMPS Enables the VBUS_VALID comparator 20 3 read-write oneToToggle DISCHARGE_VBUS Controls VBUS discharge resistor 26 1 read-write oneToToggle EN_CHARGER_RESISTOR Enables resistors used for an older method of resistive battery charger detection 31 1 read-write oneToToggle USB1_VBUS_DET_STAT USB PHY VBUS Detector Status Register 0xD0 32 read-only 0 0xFFFFFFFF SESSEND Session End indicator 0 1 read-only ABOVE The VBUS voltage is above the Session Valid threshold 0 BELOW The VBUS voltage is below the Session Valid threshold 0x1 BVALID B-Device Session Valid status 1 1 read-only BELOW The VBUS voltage is below the Session Valid threshold 0 ABOVE The VBUS voltage is above the Session Valid threshold 0x1 AVALID A-Device Session Valid status 2 1 read-only BELOW The VBUS voltage is below the Session Valid threshold 0 ABOVE The VBUS voltage is above the Session Valid threshold 0x1 VBUS_VALID VBUS voltage status 3 1 read-only BELOW VBUS is below the comparator threshold 0 ABOVE VBUS is above the comparator threshold 0x1 VBUS_VALID_3V VBUS_VALID_3V detector status 4 1 read-only BELOW VBUS voltage is below VBUS_VALID_3V threshold 0 ABOVE VBUS voltage is above VBUS_VALID_3V threshold 0x1 USB1_CHRG_DETECT USB PHY Charger Detect Control Register 0xE0 32 read-write 0x80180000 0xFFFFFFFF PULLUP_DP PULLUP_DP 2 1 read-write BGR_BIAS BGR_BIAS 23 1 read-write LOCAL_BIAS Use local bias powered from USB1_VBUS for 10uA reference (Default) 0 BANDGAP Use bandgap bias powered from VREGIN0/VREGIN1 for 10uA reference 0x1 USB1_CHRG_DETECT_SET USB PHY Charger Detect Control Register 0xE4 32 read-write 0x80180000 0xFFFFFFFF oneToSet PULLUP_DP PULLUP_DP 2 1 read-write oneToSet BGR_BIAS BGR_BIAS 23 1 read-write oneToSet USB1_CHRG_DETECT_CLR USB PHY Charger Detect Control Register 0xE8 32 read-write 0x80180000 0xFFFFFFFF oneToClear PULLUP_DP PULLUP_DP 2 1 read-write oneToClear BGR_BIAS BGR_BIAS 23 1 read-write oneToClear USB1_CHRG_DETECT_TOG USB PHY Charger Detect Control Register 0xEC 32 read-write 0x80180000 0xFFFFFFFF oneToToggle PULLUP_DP PULLUP_DP 2 1 read-write oneToToggle BGR_BIAS BGR_BIAS 23 1 read-write oneToToggle USB1_CHRG_DET_STAT USB PHY Charger Detect Status Register 0xF0 32 read-only 0 0xFFFFFFFF PLUG_CONTACT Battery Charging Data Contact Detection phase output 0 1 read-only NO_ATTACH No USB cable attachment has been detected 0 ATTACH A USB cable attachment between the device and host has been detected 0x1 CHRG_DETECTED Battery Charging Primary Detection phase output 1 1 read-only SDP Standard Downstream Port (SDP) has been detected 0 CHRG_PORT Charging Port has been detected 0x1 DN_STATE DN_STATE 2 1 read-only BELOW_P8 DN pin voltage is < 0.8V 0 ABOVE_2 DN pin voltage is > 2.0V 0x1 DP_STATE DP_STATE 3 1 read-only BELOW_P8 DP pin voltage is < 0.8V 0 ABOVE_2 DP pin voltage is > 2.0V 0x1 SECDET_DCP Battery Charging Secondary Detection phase output 4 1 read-only CDP Charging Downstream Port (CDP) has been detected 0 DCP Downstream Charging Port (DCP) has been detected 0x1 ANACTRL USB PHY Analog Control Register 0x100 32 read-write 0x402 0xFFFFFFFF DEV_PULLDOWN DEV_PULLDOWN 10 1 read-write DISABLE The 15kohm nominal pulldowns on the DP and DN pinsare disabled in device mode. 0 ENABLE The 15kohm nominal pulldowns on the DP and DN pinsare enabled in device mode. 0x1 ANACTRL_SET USB PHY Analog Control Register 0x104 32 read-write 0x402 0xFFFFFFFF oneToSet DEV_PULLDOWN DEV_PULLDOWN 10 1 read-write oneToSet ANACTRL_CLR USB PHY Analog Control Register 0x108 32 read-write 0x402 0xFFFFFFFF oneToClear DEV_PULLDOWN DEV_PULLDOWN 10 1 read-write oneToClear ANACTRL_TOG USB PHY Analog Control Register 0x10C 32 read-write 0x402 0xFFFFFFFF oneToToggle DEV_PULLDOWN DEV_PULLDOWN 10 1 read-write oneToToggle USB1_LOOPBACK USB PHY Loopback Control/Status Register 0x110 32 read-write 0x550000 0xFFFFFFFF UTMI_TESTSTART UTMI_TESTSTART 0 1 read-write UTMI_DIG_TST0 UTMI_DIG_TST0 1 1 read-write UTMI_DIG_TST1 UTMI_DIG_TST1 2 1 read-write TSTI_TX_HS_MODE TSTI_TX_HS_MODE 3 1 read-write TSTI_TX_LS_MODE TSTI_TX_LS_MODE 4 1 read-write TSTI_TX_EN TSTI_TX_EN 5 1 read-write TSTI_TX_HIZ TSTI_TX_HIZ 6 1 read-write UTMO_DIG_TST0 UTMO_DIG_TST0 7 1 read-only UTMO_DIG_TST1 UTMO_DIG_TST1 8 1 read-only TSTI_HSFS_MODE_EN TSTI_HSFS_MODE_EN 15 1 read-write TSTPKT TSTPKT 16 8 read-write USB1_LOOPBACK_SET USB PHY Loopback Control/Status Register 0x114 32 read-write 0x550000 0xFFFFFFFF oneToSet UTMI_TESTSTART UTMI_TESTSTART 0 1 read-write oneToSet UTMI_DIG_TST0 UTMI_DIG_TST0 1 1 read-write oneToSet UTMI_DIG_TST1 UTMI_DIG_TST1 2 1 read-write oneToSet TSTI_TX_HS_MODE TSTI_TX_HS_MODE 3 1 read-write oneToSet TSTI_TX_LS_MODE TSTI_TX_LS_MODE 4 1 read-write oneToSet TSTI_TX_EN TSTI_TX_EN 5 1 read-write oneToSet TSTI_TX_HIZ TSTI_TX_HIZ 6 1 read-write oneToSet UTMO_DIG_TST0 UTMO_DIG_TST0 7 1 read-only oneToSet UTMO_DIG_TST1 UTMO_DIG_TST1 8 1 read-only oneToSet TSTI_HSFS_MODE_EN TSTI_HSFS_MODE_EN 15 1 read-write oneToSet TSTPKT TSTPKT 16 8 read-write oneToSet USB1_LOOPBACK_CLR USB PHY Loopback Control/Status Register 0x118 32 read-write 0x550000 0xFFFFFFFF oneToClear UTMI_TESTSTART UTMI_TESTSTART 0 1 read-write oneToClear UTMI_DIG_TST0 UTMI_DIG_TST0 1 1 read-write oneToClear UTMI_DIG_TST1 UTMI_DIG_TST1 2 1 read-write oneToClear TSTI_TX_HS_MODE TSTI_TX_HS_MODE 3 1 read-write oneToClear TSTI_TX_LS_MODE TSTI_TX_LS_MODE 4 1 read-write oneToClear TSTI_TX_EN TSTI_TX_EN 5 1 read-write oneToClear TSTI_TX_HIZ TSTI_TX_HIZ 6 1 read-write oneToClear UTMO_DIG_TST0 UTMO_DIG_TST0 7 1 read-only oneToClear UTMO_DIG_TST1 UTMO_DIG_TST1 8 1 read-only oneToClear TSTI_HSFS_MODE_EN TSTI_HSFS_MODE_EN 15 1 read-write oneToClear TSTPKT TSTPKT 16 8 read-write oneToClear USB1_LOOPBACK_TOG USB PHY Loopback Control/Status Register 0x11C 32 read-write 0x550000 0xFFFFFFFF oneToToggle UTMI_TESTSTART UTMI_TESTSTART 0 1 read-write oneToToggle UTMI_DIG_TST0 UTMI_DIG_TST0 1 1 read-write oneToToggle UTMI_DIG_TST1 UTMI_DIG_TST1 2 1 read-write oneToToggle TSTI_TX_HS_MODE TSTI_TX_HS_MODE 3 1 read-write oneToToggle TSTI_TX_LS_MODE TSTI_TX_LS_MODE 4 1 read-write oneToToggle TSTI_TX_EN TSTI_TX_EN 5 1 read-write oneToToggle TSTI_TX_HIZ TSTI_TX_HIZ 6 1 read-write oneToToggle UTMO_DIG_TST0 UTMO_DIG_TST0 7 1 read-only oneToToggle UTMO_DIG_TST1 UTMO_DIG_TST1 8 1 read-only oneToToggle TSTI_HSFS_MODE_EN TSTI_HSFS_MODE_EN 15 1 read-write oneToToggle TSTPKT TSTPKT 16 8 read-write oneToToggle USB1_LOOPBACK_HSFSCNT USB PHY Loopback Packet Number Select Register 0x120 32 read-write 0x40010 0xFFFFFFFF TSTI_HS_NUMBER TSTI_HS_NUMBER 0 16 read-write TSTI_FS_NUMBER TSTI_FS_NUMBER 16 16 read-write USB1_LOOPBACK_HSFSCNT_SET USB PHY Loopback Packet Number Select Register 0x124 32 read-write 0x40010 0xFFFFFFFF oneToSet TSTI_HS_NUMBER TSTI_HS_NUMBER 0 16 read-write oneToSet TSTI_FS_NUMBER TSTI_FS_NUMBER 16 16 read-write oneToSet USB1_LOOPBACK_HSFSCNT_CLR USB PHY Loopback Packet Number Select Register 0x128 32 read-write 0x40010 0xFFFFFFFF oneToClear TSTI_HS_NUMBER TSTI_HS_NUMBER 0 16 read-write oneToClear TSTI_FS_NUMBER TSTI_FS_NUMBER 16 16 read-write oneToClear USB1_LOOPBACK_HSFSCNT_TOG USB PHY Loopback Packet Number Select Register 0x12C 32 read-write 0x40010 0xFFFFFFFF oneToToggle TSTI_HS_NUMBER TSTI_HS_NUMBER 0 16 read-write oneToToggle TSTI_FS_NUMBER TSTI_FS_NUMBER 16 16 read-write oneToToggle TRIM_OVERRIDE_EN USB PHY Trim Override Enable Register 0x130 32 read-write 0x7F 0xFFFFFFFF TRIM_DIV_SEL_OVERRIDE TRIM_DIV_SEL_OVERRIDE 0 1 read-write TRIM_ENV_TAIL_ADJ_VD_OVERRIDE TRIM_ENV_TAIL_ADJ_VD_OVERRIDE 1 1 read-write TRIM_TX_D_CAL_OVERRIDE TRIM_TX_D_CAL_OVERRIDE 2 1 read-write TRIM_TX_CAL45DP_OVERRIDE TRIM_TX_CAL45DP_OVERRIDE 3 1 read-write TRIM_TX_CAL45DN_OVERRIDE TRIM_TX_CAL45DN_OVERRIDE 4 1 read-write TRIM_REFBIAS_VBGADJ_OVERRIDE Override enable for bandgap adjustment. 5 1 read-write TRIM_REFBIAS_TST_OVERRIDE Override enable for bias current control 6 1 read-write TRIM_USB2_REFBIAS_VBGADJ TRIM_USB2_REFBIAS_VBGADJ 10 3 read-only TRIM_USB2_REFBIAS_TST TRIM_USB2_REFBIAS_TST 13 2 read-only TRIM_PLL_CTRL0_DIV_SEL TRIM_PLL_CTRL0_DIV_SEL 15 3 read-only TRIM_USB_REG_ENV_TAIL_ADJ_VD TRIM_USB_REG_ENV_TAIL_ADJ_VD 18 2 read-only TRIM_USBPHY_TX_D_CAL TRIM_USBPHY_TX_D_CAL 20 4 read-only TRIM_USBPHY_TX_CAL45DP TRIM_USBPHY_TX_CAL45DP 24 4 read-only TRIM_USBPHY_TX_CAL45DN TRIM_USBPHY_TX_CAL45DN 28 4 read-only TRIM_OVERRIDE_EN_SET USB PHY Trim Override Enable Register 0x134 32 read-write 0x7F 0xFFFFFFFF oneToSet TRIM_DIV_SEL_OVERRIDE TRIM_DIV_SEL_OVERRIDE 0 1 read-write oneToSet TRIM_ENV_TAIL_ADJ_VD_OVERRIDE TRIM_ENV_TAIL_ADJ_VD_OVERRIDE 1 1 read-write oneToSet TRIM_TX_D_CAL_OVERRIDE TRIM_TX_D_CAL_OVERRIDE 2 1 read-write oneToSet TRIM_TX_CAL45DP_OVERRIDE TRIM_TX_CAL45DP_OVERRIDE 3 1 read-write oneToSet TRIM_TX_CAL45DN_OVERRIDE TRIM_TX_CAL45DN_OVERRIDE 4 1 read-write oneToSet TRIM_REFBIAS_VBGADJ_OVERRIDE Override enable for bandgap adjustment. 5 1 read-write oneToSet TRIM_REFBIAS_TST_OVERRIDE Override enable for bias current control 6 1 read-write oneToSet TRIM_USB2_REFBIAS_VBGADJ TRIM_USB2_REFBIAS_VBGADJ 10 3 read-only oneToSet TRIM_USB2_REFBIAS_TST TRIM_USB2_REFBIAS_TST 13 2 read-only oneToSet TRIM_PLL_CTRL0_DIV_SEL TRIM_PLL_CTRL0_DIV_SEL 15 3 read-only oneToSet TRIM_USB_REG_ENV_TAIL_ADJ_VD TRIM_USB_REG_ENV_TAIL_ADJ_VD 18 2 read-only oneToSet TRIM_USBPHY_TX_D_CAL TRIM_USBPHY_TX_D_CAL 20 4 read-only oneToSet TRIM_USBPHY_TX_CAL45DP TRIM_USBPHY_TX_CAL45DP 24 4 read-only oneToSet TRIM_USBPHY_TX_CAL45DN TRIM_USBPHY_TX_CAL45DN 28 4 read-only oneToSet TRIM_OVERRIDE_EN_CLR USB PHY Trim Override Enable Register 0x138 32 read-write 0x7F 0xFFFFFFFF oneToClear TRIM_DIV_SEL_OVERRIDE TRIM_DIV_SEL_OVERRIDE 0 1 read-write oneToClear TRIM_ENV_TAIL_ADJ_VD_OVERRIDE TRIM_ENV_TAIL_ADJ_VD_OVERRIDE 1 1 read-write oneToClear TRIM_TX_D_CAL_OVERRIDE TRIM_TX_D_CAL_OVERRIDE 2 1 read-write oneToClear TRIM_TX_CAL45DP_OVERRIDE TRIM_TX_CAL45DP_OVERRIDE 3 1 read-write oneToClear TRIM_TX_CAL45DN_OVERRIDE TRIM_TX_CAL45DN_OVERRIDE 4 1 read-write oneToClear TRIM_REFBIAS_VBGADJ_OVERRIDE Override enable for bandgap adjustment. 5 1 read-write oneToClear TRIM_REFBIAS_TST_OVERRIDE Override enable for bias current control 6 1 read-write oneToClear TRIM_USB2_REFBIAS_VBGADJ TRIM_USB2_REFBIAS_VBGADJ 10 3 read-only oneToClear TRIM_USB2_REFBIAS_TST TRIM_USB2_REFBIAS_TST 13 2 read-only oneToClear TRIM_PLL_CTRL0_DIV_SEL TRIM_PLL_CTRL0_DIV_SEL 15 3 read-only oneToClear TRIM_USB_REG_ENV_TAIL_ADJ_VD TRIM_USB_REG_ENV_TAIL_ADJ_VD 18 2 read-only oneToClear TRIM_USBPHY_TX_D_CAL TRIM_USBPHY_TX_D_CAL 20 4 read-only oneToClear TRIM_USBPHY_TX_CAL45DP TRIM_USBPHY_TX_CAL45DP 24 4 read-only oneToClear TRIM_USBPHY_TX_CAL45DN TRIM_USBPHY_TX_CAL45DN 28 4 read-only oneToClear TRIM_OVERRIDE_EN_TOG USB PHY Trim Override Enable Register 0x13C 32 read-write 0x7F 0xFFFFFFFF oneToToggle TRIM_DIV_SEL_OVERRIDE TRIM_DIV_SEL_OVERRIDE 0 1 read-write oneToToggle TRIM_ENV_TAIL_ADJ_VD_OVERRIDE TRIM_ENV_TAIL_ADJ_VD_OVERRIDE 1 1 read-write oneToToggle TRIM_TX_D_CAL_OVERRIDE TRIM_TX_D_CAL_OVERRIDE 2 1 read-write oneToToggle TRIM_TX_CAL45DP_OVERRIDE TRIM_TX_CAL45DP_OVERRIDE 3 1 read-write oneToToggle TRIM_TX_CAL45DN_OVERRIDE TRIM_TX_CAL45DN_OVERRIDE 4 1 read-write oneToToggle TRIM_REFBIAS_VBGADJ_OVERRIDE Override enable for bandgap adjustment. 5 1 read-write oneToToggle TRIM_REFBIAS_TST_OVERRIDE Override enable for bias current control 6 1 read-write oneToToggle TRIM_USB2_REFBIAS_VBGADJ TRIM_USB2_REFBIAS_VBGADJ 10 3 read-only oneToToggle TRIM_USB2_REFBIAS_TST TRIM_USB2_REFBIAS_TST 13 2 read-only oneToToggle TRIM_PLL_CTRL0_DIV_SEL TRIM_PLL_CTRL0_DIV_SEL 15 3 read-only oneToToggle TRIM_USB_REG_ENV_TAIL_ADJ_VD TRIM_USB_REG_ENV_TAIL_ADJ_VD 18 2 read-only oneToToggle TRIM_USBPHY_TX_D_CAL TRIM_USBPHY_TX_D_CAL 20 4 read-only oneToToggle TRIM_USBPHY_TX_CAL45DP TRIM_USBPHY_TX_CAL45DP 24 4 read-only oneToToggle TRIM_USBPHY_TX_CAL45DN TRIM_USBPHY_TX_CAL45DN 28 4 read-only oneToToggle USBPHY2 USBPHY USBPHY 0x40438000 0 0x140 registers USBPHY2 91 USBHSDCD1 USBDCD USBHSDCD USBHSDCD 0x40434800 0 0x1C registers CONTROL Control register 0 32 read-write 0x10000 0xFFFFFFFF IACK Interrupt Acknowledge 0 1 read-write INT_NOCLEAR Do not clear the interrupt. 0 INT_CLEAR Clear the IF bit (interrupt flag). 0x1 IF Interrupt Flag 8 1 read-only INT_PEND No interrupt is pending. 0 INT_NOPEND An interrupt is pending. 0x1 IE Interrupt Enable 16 1 read-write DIS_INT Disable interrupts to the system. 0 EN_INT Enable interrupts to the system. 0x1 BC12 BC12 17 1 read-write BC11 Compatible with BC1.1 (default) 0 BC12 Compatible with BC1.2 0x1 START Start Change Detection Sequence 24 1 read-write NO_START Do not start the sequence. Writes of this value have no effect. 0 START Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. 0x1 SR Software Reset 25 1 read-write NO_RESET Do not perform a software reset. 0 SW_RESET Perform a software reset. 0x1 CLOCK Clock register 0x4 32 read-write 0xC1 0xFFFFFFFF CLOCK_UNIT Unit of Measurement Encoding for Clock Speed 0 1 read-write KHZ_CLK kHz Speed (between 1 kHz and 1023 kHz) 0 MHZ_CLK MHz Speed (between 1 MHz and 1023 MHz) 0x1 CLOCK_SPEED Numerical Value of Clock Speed in Binary 2 10 read-write STATUS Status register 0x8 32 read-only 0 0xFFFFFFFF SEQ_RES Charger Detection Sequence Results 16 2 read-only NO_RESULT No results to report. 0 CONN_SDP Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. 0x1 CONN_CP Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type detection has completed.) 0x2 CONN_DCP Attached to a DCP. 0x3 SEQ_STAT Charger Detection Sequence Status 18 2 read-only NO_DATA_PIN_CONN The module is either not enabled, or the module is enabled but the data pins have not yet been detected. 0 DATA_PIN_CONN Data pin contact detection is complete. 0x1 CP_DET_DONE Charging port detection is complete. 0x2 CT_DET_DONE Charger type detection is complete. 0x3 ERR Error Flag 20 1 read-only NO_SEQ_ERR No sequence errors. 0 SEQ_ERR Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred. 0x1 TO Timeout Flag 21 1 read-only NO_TIMEOUT The detection sequence has not been running for over 1s. 0 TIMEOUT It has been over 1 s since the data pin contact was detected and debounced. 0x1 ACTIVE Active Status Indicator 22 1 read-only SEQ_NOT_RUNNING The sequence is not running. 0 SEQ_RUNNING The sequence is running. 0x1 SIGNAL_OVERRIDE Signal Override Register 0xC 32 read-write 0 0xFFFFFFFF PS Phase Selection 0 2 read-write NO_OVERRIDE No overrides. Bit field must remain at this value during normal USB data communication to prevent unexpected conditions on USB_DP and USB_DM pins. (Default) 0 PRI_DET_OVERRIDE Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin. 0x2 TIMER0 TIMER0 register 0x10 32 read-write 0x100000 0xFFFFFFFF TUNITCON Unit Connection Timer Elapse (in ms) 0 12 read-only TSEQ_INIT Sequence Initiation Time 16 10 read-write MS 0ms - 1023ms 0 MS 0ms - 1023ms 0x1 MS 0ms - 1023ms 0x2 MS 0ms - 1023ms 0x3 MS 0ms - 1023ms 0x4 MS 0ms - 1023ms 0x5 MS 0ms - 1023ms 0x6 MS 0ms - 1023ms 0x7 MS 0ms - 1023ms 0x8 MS 0ms - 1023ms 0x9 TIMER1 TIMER1 register 0x14 32 read-write 0xA0028 0xFFFFFFFF TVDPSRC_ON Time Period Comparator Enabled 0 10 read-write MS 1ms - 1023ms 0x1 MS 1ms - 1023ms 0x2 MS 1ms - 1023ms 0x3 MS 1ms - 1023ms 0x4 MS 1ms - 1023ms 0x5 MS 1ms - 1023ms 0x6 MS 1ms - 1023ms 0x7 MS 1ms - 1023ms 0x8 MS 1ms - 1023ms 0x9 MS 1ms - 1023ms 0xA TDCD_DBNC Time Period to Debounce D+ Signal 16 10 read-write MS 1ms - 1023ms 0x1 MS 1ms - 1023ms 0x2 MS 1ms - 1023ms 0x3 MS 1ms - 1023ms 0x4 MS 1ms - 1023ms 0x5 MS 1ms - 1023ms 0x6 MS 1ms - 1023ms 0x7 MS 1ms - 1023ms 0x8 MS 1ms - 1023ms 0x9 MS 1ms - 1023ms 0xA TIMER2_BC11 TIMER2_BC11 register TIMER2 0x18 32 read-write 0x280001 0xFFFFFFFF CHECK_DM Time Before Check of D- Line 0 4 read-write MS 1ms - 15ms 0x1 MS 1ms - 15ms 0x2 MS 1ms - 15ms 0x3 MS 1ms - 15ms 0x4 MS 1ms - 15ms 0x5 MS 1ms - 15ms 0x6 MS 1ms - 15ms 0x7 MS 1ms - 15ms 0x8 MS 1ms - 15ms 0x9 MS 1ms - 15ms 0xA TVDPSRC_CON Time Period Before Enabling D+ Pullup 16 10 read-write MS 1ms - 1023ms 0x1 MS 1ms - 1023ms 0x2 MS 1ms - 1023ms 0x3 MS 1ms - 1023ms 0x4 MS 1ms - 1023ms 0x5 MS 1ms - 1023ms 0x6 MS 1ms - 1023ms 0x7 MS 1ms - 1023ms 0x8 MS 1ms - 1023ms 0x9 MS 1ms - 1023ms 0xA TIMER2_BC12 TIMER2_BC12 register TIMER2 0x18 32 read-write 0x10028 0xFFFFFFFF TVDMSRC_ON TVDMSRC_ON 0 10 read-write MS 0ms - 40ms 0 MS 0ms - 40ms 0x1 MS 0ms - 40ms 0x2 MS 0ms - 40ms 0x3 MS 0ms - 40ms 0x4 MS 0ms - 40ms 0x5 MS 0ms - 40ms 0x6 MS 0ms - 40ms 0x7 MS 0ms - 40ms 0x8 MS 0ms - 40ms 0x9 TWAIT_AFTER_PRD TWAIT_AFTER_PRD 16 10 read-write MS 1ms - 1023ms 0x1 MS 1ms - 1023ms 0x2 MS 1ms - 1023ms 0x3 MS 1ms - 1023ms 0x4 MS 1ms - 1023ms 0x5 MS 1ms - 1023ms 0x6 MS 1ms - 1023ms 0x7 MS 1ms - 1023ms 0x8 MS 1ms - 1023ms 0x9 MS 1ms - 1023ms 0xA USBHSDCD2 USBDCD USBHSDCD 0x40438800 0 0x1C registers ENET_QOS ENET_QOS ENET_QOS 0x4043C000 0 0x1370 registers ENET_QOS 216 ENET_QOS_PMT 217 MAC_CONFIGURATION MAC Configuration Register 0 32 read-write 0 0xFFFFFFFF RE Receiver Enable 0 1 read-write DISABLE Receiver is disabled 0 ENABLE Receiver is enabled 0x1 TE Transmitter Enable 1 1 read-write DISABLE Transmitter is disabled 0 ENABLE Transmitter is enabled 0x1 PRELEN Preamble Length for Transmit packets 2 2 read-write BYTES_7 7 bytes of preamble 0 BYTES_5 5 bytes of preamble 0x1 BYTES_3 3 bytes of preamble 0x2 DC Deferral Check 4 1 read-write DISABLE Deferral check function is disabled 0 ENABLE Deferral check function is enabled 0x1 BL Back-Off Limit 5 2 read-write MIN_N_10 k = min(n,10) 0 MIN_N_8 k = min(n,8) 0x1 MIN_N_4 k = min(n,4) 0x2 MIN_N_1 k = min(n,1) 0x3 DR Disable Retry 8 1 read-write ENABLE Enable Retry 0 DISABLE Disable Retry 0x1 DCRS Disable Carrier Sense During Transmission 9 1 read-write ENABLE Enable Carrier Sense During Transmission 0 DISABLE Disable Carrier Sense During Transmission 0x1 DO Disable Receive Own 10 1 read-write ENABLE Enable Receive Own 0 DISABLE Disable Receive Own 0x1 ECRSFD Enable Carrier Sense Before Transmission in Full-Duplex Mode 11 1 read-write DISABLE ECRSFD is disabled 0 ENABLE ECRSFD is enabled 0x1 LM Loopback Mode 12 1 read-write DISABLE Loopback is disabled 0 ENABLE Loopback is enabled 0x1 DM Duplex Mode 13 1 read-write HDUPLX Half-duplex mode 0 FDUPLX Full-duplex mode 0x1 FES Speed 14 1 read-write Mbps_10_1000M 10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0 0 Mbps_100_2500M 100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0 0x1 PS Port Select 15 1 read-write bf_1000_2500M For 1000 or 2500 Mbps operations 0 bf_10_100M For 10 or 100 Mbps operations 0x1 JE Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status. 16 1 read-write DISABLE Jumbo packet is disabled 0 ENABLE Jumbo packet is enabled 0x1 JD Jabber Disable 17 1 read-write ENABLE Jabber is enabled 0 DISABLE Jabber is disabled 0x1 BE Packet Burst Enable When this bit is set, the MAC allows packet bursting during transmission in the GMII half-duplex mode. 18 1 read-write DISABLE Packet Burst is disabled 0 ENABLE Packet Burst is enabled 0x1 WD Watchdog Disable 19 1 read-write ENABLE Watchdog is enabled 0 DISABLE Watchdog is disabled 0x1 ACS Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1,536 bytes. 20 1 read-write DISABLE Automatic Pad or CRC Stripping is disabled 0 ENABLE Automatic Pad or CRC Stripping is enabled 0x1 CST CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding the packet to the application. 21 1 read-write DISABLE CRC stripping for Type packets is disabled 0 ENABLE CRC stripping for Type packets is enabled 0x1 S2KP IEEE 802. 22 1 read-write DISABLE Support upto 2K packet is disabled 0 ENABLE Support upto 2K packet is Enabled 0x1 GPSLCE Giant Packet Size Limit Control Enable 23 1 read-write DISABLE Giant Packet Size Limit Control is disabled 0 ENABLE Giant Packet Size Limit Control is enabled 0x1 IPG Inter-Packet Gap These bits control the minimum IPG between packets during transmission. 24 3 read-write IPG96 96 bit times IPG 0 IPG88 88 bit times IPG 0x1 IPG80 80 bit times IPG 0x2 IPG72 72 bit times IPG 0x3 IPG64 64 bit times IPG 0x4 IPG56 56 bit times IPG 0x5 IPG48 48 bit times IPG 0x6 IPG40 40 bit times IPG 0x7 IPC Checksum Offload 27 1 read-write DISABLE IP header/payload checksum checking is disabled 0 ENABLE IP header/payload checksum checking is enabled 0x1 SARC Source Address Insertion or Replacement Control 28 3 read-write SA_CTRL_IN mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation 0 MAC0_INS_SA Contents of MAC Addr-0 inserted in SA field 0x2 MAC0_REP_SA Contents of MAC Addr-0 replaces SA field 0x3 MAC1_INS_SA Contents of MAC Addr-1 inserted in SA field 0x6 MAC1_REP_SA Contents of MAC Addr-1 replaces SA field 0x7 MAC_EXT_CONFIGURATION MAC Extended Configuration Register 0x4 32 read-write 0 0xFFFFFFFF GPSL Giant Packet Size Limit 0 14 read-write DCRCC Disable CRC Checking for Received Packets 16 1 read-write ENABLE CRC Checking is enabled 0 DISABLE CRC Checking is disabled 0x1 SPEN Slow Protocol Detection Enable 17 1 read-write DISABLE Slow Protocol Detection is disabled 0 ENABLE Slow Protocol Detection is enabled 0x1 USP Unicast Slow Protocol Packet Detect 18 1 read-write DISABLE Unicast Slow Protocol Packet Detection is disabled 0 ENABLE Unicast Slow Protocol Packet Detection is enabled 0x1 PDC Packet Duplication Control 19 1 read-write DISABLE Packet Duplication Control is disabled 0 ENABLE Packet Duplication Control is enabled 0x1 EIPGEN Extended Inter-Packet Gap Enable 24 1 read-write DISABLE Extended Inter-Packet Gap is disabled 0 ENABLE Extended Inter-Packet Gap is enabled 0x1 EIPG Extended Inter-Packet Gap 25 5 read-write MAC_PACKET_FILTER MAC Packet Filter 0x8 32 read-write 0 0xFFFFFFFF PR Promiscuous Mode 0 1 read-write DISABLE Promiscuous Mode is disabled 0 ENABLE Promiscuous Mode is enabled 0x1 HUC Hash Unicast 1 1 read-write DISABLE Hash Unicast is disabled 0 ENABLE Hash Unicast is enabled 0x1 HMC Hash Multicast 2 1 read-write DISABLE Hash Multicast is disabled 0 ENABLE Hash Multicast is enabled 0x1 DAIF DA Inverse Filtering 3 1 read-write DISABLE DA Inverse Filtering is disabled 0 ENABLE DA Inverse Filtering is enabled 0x1 PM Pass All Multicast 4 1 read-write DISABLE Pass All Multicast is disabled 0 ENABLE Pass All Multicast is enabled 0x1 DBF Disable Broadcast Packets 5 1 read-write ENABLE Enable Broadcast Packets 0 DISABLE Disable Broadcast Packets 0x1 PCF Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets). 6 2 read-write FLTR_ALL MAC filters all control packets from reaching the application 0 FW_XCPT_PAU MAC forwards all control packets except Pause packets to the application even if they fail the Address filter 0x1 FW_ALL MAC forwards all control packets to the application even if they fail the Address filter 0x2 FW_PASS MAC forwards the control packets that pass the Address filter 0x3 SAIF SA Inverse Filtering 8 1 read-write DISABLE SA Inverse Filtering is disabled 0 ENABLE SA Inverse Filtering is enabled 0x1 SAF Source Address Filter Enable 9 1 read-write DISABLE SA Filtering is disabled 0 ENABLE SA Filtering is enabled 0x1 HPF Hash or Perfect Filter 10 1 read-write DISABLE Hash or Perfect Filter is disabled 0 ENABLE Hash or Perfect Filter is enabled 0x1 VTFE VLAN Tag Filter Enable 16 1 read-write DISABLE VLAN Tag Filter is disabled 0 ENABLE VLAN Tag Filter is enabled 0x1 IPFE Layer 3 and Layer 4 Filter Enable 20 1 read-write DISABLE Layer 3 and Layer 4 Filters are disabled 0 ENABLE Layer 3 and Layer 4 Filters are enabled 0x1 DNTU Drop Non-TCP/UDP over IP Packets 21 1 read-write FWD Forward Non-TCP/UDP over IP Packets 0 DROP Drop Non-TCP/UDP over IP Packets 0x1 RA Receive All 31 1 read-write DISABLE Receive All is disabled 0 ENABLE Receive All is enabled 0x1 MAC_WATCHDOG_TIMEOUT Watchdog Timeout 0xC 32 read-write 0 0xFFFFFFFF WTO Watchdog Timeout 0 4 read-write bf_2KBYTES 2 KB 0 bf_3KBYTES 3 KB 0x1 bf_4KBYTES 4 KB 0x2 bf_5KBYTES 5 KB 0x3 bf_6KBYTES 6 KB 0x4 bf_7KBYTES 7 KB 0x5 bf_8KBYTES 8 KB 0x6 bf_9KBYTES 9 KB 0x7 bf_10KBYTES 10 KB 0x8 bf_11KBYTES 11 KB 0x9 bf_12KBYTES 12 KB 0xA bf_13KBYTES 13 KB 0xB bf_14KBYTES 14 KB 0xC bf_15KBYTES 15 KB 0xD bf_16383BYTES 16383 Bytes 0xE PWE Programmable Watchdog Enable 8 1 read-write DISABLE Programmable Watchdog is disabled 0 ENABLE Programmable Watchdog is enabled 0x1 MAC_HASH_TABLE_REG0 MAC Hash Table Register 0 0x10 32 read-write 0 0xFFFFFFFF HT31T0 MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table. 0 32 read-write MAC_HASH_TABLE_REG1 MAC Hash Table Register 1 0x14 32 read-write 0 0xFFFFFFFF HT63T32 MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table. 0 32 read-write MAC_VLAN_TAG_CTRL MAC VLAN Tag Control 0x50 32 read-write 0 0xFFFFFFFF OB Operation Busy 0 1 read-write DISABLE Operation Busy is disabled 0 ENABLE Operation Busy is enabled 0x1 CT Command Type 1 1 read-write WRITE Write operation 0 READ Read operation 0x1 OFS Offset 2 5 read-write VTIM VLAN Tag Inverse Match Enable 17 1 read-write DISABLE VLAN Tag Inverse Match is disabled 0 ENABLE VLAN Tag Inverse Match is enabled 0x1 ESVL Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets. 18 1 read-write DISABLE S-VLAN is disabled 0 ENABLE S-VLAN is enabled 0x1 EVLS Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet. 21 2 read-write DONOT Do not strip 0 IFPASS Strip if VLAN filter passes 0x1 IFFAIL Strip if VLAN filter fails 0x2 ALWAYS Always strip 0x3 EVLRXS Enable VLAN Tag in Rx status 24 1 read-write DISABLE VLAN Tag in Rx status is disabled 0 ENABLE VLAN Tag in Rx status is enabled 0x1 VTHM VLAN Tag Hash Table Match Enable 25 1 read-write DISABLE VLAN Tag Hash Table Match is disabled 0 ENABLE VLAN Tag Hash Table Match is enabled 0x1 EDVLP Enable Double VLAN Processing 26 1 read-write DISABLE Double VLAN Processing is disabled 0 ENABLE Double VLAN Processing is enabled 0x1 ERIVLT ERIVLT 27 1 read-write DISABLE Inner VLAN tag is disabled 0 ENABLE Inner VLAN tag is enabled 0x1 EIVLS Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet. 28 2 read-write DONOT Do not strip 0 IFPASS Strip if VLAN filter passes 0x1 IFFAIL Strip if VLAN filter fails 0x2 ALWAYS Always strip 0x3 EIVLRXS Enable Inner VLAN Tag in Rx Status 31 1 read-write DISABLE Inner VLAN Tag in Rx status is disabled 0 ENABLE Inner VLAN Tag in Rx status is enabled 0x1 MAC_VLAN_TAG_DATA MAC VLAN Tag Data 0x54 32 read-write 0 0xFFFFFFFF VID VLAN Tag ID 0 16 read-write VEN VLAN Tag Enable 16 1 read-write DISABLE VLAN Tag is disabled 0 ENABLE VLAN Tag is enabled 0x1 ETV 12bits or 16bits VLAN comparison 17 1 read-write bf_16BIT 16 bit VLAN comparison 0 bf_12BIT 12 bit VLAN comparison 0x1 DOVLTC Disable VLAN Type Comparison 18 1 read-write ENABLE VLAN type comparison is enabled 0 DISABLE VLAN type comparison is disabled 0x1 ERSVLM Enable S-VLAN Match for received Frames 19 1 read-write DISABLE Receive S-VLAN Match is disabled 0 ENABLE Receive S-VLAN Match is enabled 0x1 ERIVLT Enable Inner VLAN Tag Comparison 20 1 read-write DISABLE Inner VLAN tag comparison is disabled 0 ENABLE Inner VLAN tag comparison is enabled 0x1 DMACHEN DMA Channel Number Enable 24 1 read-write DISABLE DMA Channel Number is disabled 0 ENABLE DMA Channel Number is enabled 0x1 DMACHN DMA Channel Number 25 3 read-write MAC_VLAN_HASH_TABLE MAC VLAN Hash Table 0x58 32 read-write 0 0xFFFFFFFF VLHT VLAN Hash Table This field contains the 16-bit VLAN Hash Table. 0 16 read-write MAC_VLAN_INCL VLAN Tag Inclusion or Replacement 0x60 32 read-write 0 0xFFFFFFFF VLT VLAN Tag for Transmit Packets 0 16 read-write VLC VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags. 16 2 read-write NONE No VLAN tag deletion, insertion, or replacement 0 DELETE VLAN tag deletion 0x1 INSERT VLAN tag insertion 0x2 REPLACE VLAN tag replacement 0x3 VLP VLAN Priority Control 18 1 read-write DISABLE VLAN Priority Control is disabled 0 ENABLE VLAN Priority Control is enabled 0x1 CSVL C-VLAN or S-VLAN 19 1 read-write C_VLAN C-VLAN type (0x8100) is inserted or replaced 0 S_VLAN S-VLAN type (0x88A8) is inserted or replaced 0x1 VLTI VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor 20 1 read-write DISABLE VLAN Tag Input is disabled 0 ENABLE VLAN Tag Input is enabled 0x1 CBTI Channel based tag insertion 21 1 read-write DISABLE Channel based tag insertion is disabled 0 ENABLE Channel based tag insertion is enabled 0x1 ADDR Address 24 3 read-write RDWR Read write control 30 1 read-write READ Read operation of indirect access 0 WRITE Write operation of indirect access 0x1 BUSY Busy 31 1 read-only INACTIVE Busy status not detected 0 ACTIVE Busy status detected 0x1 MAC_INNER_VLAN_INCL MAC Inner VLAN Tag Inclusion or Replacement 0x64 32 read-write 0 0xFFFFFFFF VLT VLAN Tag for Transmit Packets 0 16 read-write VLC VLAN Tag Control in Transmit Packets 16 2 read-write NONE No VLAN tag deletion, insertion, or replacement 0 DELETE VLAN tag deletion 0x1 INSERT VLAN tag insertion 0x2 REPLACE VLAN tag replacement 0x3 VLP VLAN Priority Control 18 1 read-write DISABLE VLAN Priority Control is disabled 0 ENABLE VLAN Priority Control is enabled 0x1 CSVL C-VLAN or S-VLAN 19 1 read-write C_VLAN C-VLAN type (0x8100) is inserted 0 S_VLAN S-VLAN type (0x88A8) is inserted 0x1 VLTI VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor 20 1 read-write DISABLE VLAN Tag Input is disabled 0 ENABLE VLAN Tag Input is enabled 0x1 MAC_Q0_TX_FLOW_CTRL MAC Q0 Tx Flow Control 0x70 32 read-write 0 0xFFFFFFFF FCB_BPA Flow Control Busy or Backpressure Activate 0 1 read-write DISABLE Flow Control Busy or Backpressure Activate is disabled 0 ENABLE Flow Control Busy or Backpressure Activate is enabled 0x1 TFE Transmit Flow Control Enable 1 1 read-write DISABLE Transmit Flow Control is disabled 0 ENABLE Transmit Flow Control is enabled 0x1 PLT Pause Low Threshold 4 3 read-write PT4 Pause Time minus 4 Slot Times (PT -4 slot times) 0 PT28 Pause Time minus 28 Slot Times (PT -28 slot times) 0x1 PT36 Pause Time minus 36 Slot Times (PT -36 slot times) 0x2 PT144 Pause Time minus 144 Slot Times (PT -144 slot times) 0x3 PT256 Pause Time minus 256 Slot Times (PT -256 slot times) 0x4 PT512 Pause Time minus 512 Slot Times (PT -512 slot times) 0x5 DZPQ Disable Zero-Quanta Pause 7 1 read-write ENABLE Zero-Quanta Pause packet generation is enabled 0 DISABLE Zero-Quanta Pause packet generation is disabled 0x1 PT Pause Time 16 16 read-write MAC_Q1_TX_FLOW_CTRL MAC Q1 Tx Flow Control 0x74 32 read-write 0 0xFFFFFFFF FCB_BPA Flow Control Busy 0 1 read-write DISABLE Flow Control Busy or Backpressure Activate is disabled 0 ENABLE Flow Control Busy or Backpressure Activate is enabled 0x1 TFE Transmit Flow Control Enable 1 1 read-write DISABLE Transmit Flow Control is disabled 0 ENABLE Transmit Flow Control is enabled 0x1 PLT Pause Low Threshold 4 3 read-write PT4 Pause Time minus 4 Slot Times (PT -4 slot times) 0 PT28 Pause Time minus 28 Slot Times (PT -28 slot times) 0x1 PT36 Pause Time minus 36 Slot Times (PT -36 slot times) 0x2 PT144 Pause Time minus 144 Slot Times (PT -144 slot times) 0x3 PT256 Pause Time minus 256 Slot Times (PT -256 slot times) 0x4 PT512 Pause Time minus 512 Slot Times (PT -512 slot times) 0x5 DZPQ Disable Zero-Quanta Pause 7 1 read-write ENABLE Zero-Quanta Pause packet generation is enabled 0 DISABLE Zero-Quanta Pause packet generation is disabled 0x1 PT Pause Time 16 16 read-write MAC_Q2_TX_FLOW_CTRL MAC Q2 Tx Flow Control 0x78 32 read-write 0 0xFFFFFFFF FCB_BPA Flow Control Busy 0 1 read-write DISABLE Flow Control Busy or Backpressure Activate is disabled 0 ENABLE Flow Control Busy or Backpressure Activate is enabled 0x1 TFE Transmit Flow Control Enable 1 1 read-write DISABLE Transmit Flow Control is disabled 0 ENABLE Transmit Flow Control is enabled 0x1 PLT Pause Low Threshold 4 3 read-write PT4 Pause Time minus 4 Slot Times (PT -4 slot times) 0 PT28 Pause Time minus 28 Slot Times (PT -28 slot times) 0x1 PT36 Pause Time minus 36 Slot Times (PT -36 slot times) 0x2 PT144 Pause Time minus 144 Slot Times (PT -144 slot times) 0x3 PT256 Pause Time minus 256 Slot Times (PT -256 slot times) 0x4 PT512 Pause Time minus 512 Slot Times (PT -512 slot times) 0x5 DZPQ Disable Zero-Quanta Pause 7 1 read-write ENABLE Zero-Quanta Pause packet generation is enabled 0 DISABLE Zero-Quanta Pause packet generation is disabled 0x1 PT Pause Time 16 16 read-write MAC_Q3_TX_FLOW_CTRL MAC Q3 Tx Flow Control 0x7C 32 read-write 0 0xFFFFFFFF FCB_BPA Flow Control Busy 0 1 read-write DISABLE Flow Control Busy or Backpressure Activate is disabled 0 ENABLE Flow Control Busy or Backpressure Activate is enabled 0x1 TFE Transmit Flow Control Enable 1 1 read-write DISABLE Transmit Flow Control is disabled 0 ENABLE Transmit Flow Control is enabled 0x1 PLT Pause Low Threshold 4 3 read-write PT4 Pause Time minus 4 Slot Times (PT -4 slot times) 0 PT28 Pause Time minus 28 Slot Times (PT -28 slot times) 0x1 PT36 Pause Time minus 36 Slot Times (PT -36 slot times) 0x2 PT144 Pause Time minus 144 Slot Times (PT -144 slot times) 0x3 PT256 Pause Time minus 256 Slot Times (PT -256 slot times) 0x4 PT512 Pause Time minus 512 Slot Times (PT -512 slot times) 0x5 DZPQ Disable Zero-Quanta Pause 7 1 read-write ENABLE Zero-Quanta Pause packet generation is enabled 0 DISABLE Zero-Quanta Pause packet generation is disabled 0x1 PT Pause Time 16 16 read-write MAC_Q4_TX_FLOW_CTRL MAC Q4 Tx Flow Control 0x80 32 read-write 0 0xFFFFFFFF FCB_BPA Flow Control Busy 0 1 read-write DISABLE Flow Control Busy or Backpressure Activate is disabled 0 ENABLE Flow Control Busy or Backpressure Activate is enabled 0x1 TFE Transmit Flow Control Enable 1 1 read-write DISABLE Transmit Flow Control is disabled 0 ENABLE Transmit Flow Control is enabled 0x1 PLT Pause Low Threshold 4 3 read-write PT4 Pause Time minus 4 Slot Times (PT -4 slot times) 0 PT28 Pause Time minus 28 Slot Times (PT -28 slot times) 0x1 PT36 Pause Time minus 36 Slot Times (PT -36 slot times) 0x2 PT144 Pause Time minus 144 Slot Times (PT -144 slot times) 0x3 PT256 Pause Time minus 256 Slot Times (PT -256 slot times) 0x4 PT512 Pause Time minus 512 Slot Times (PT -512 slot times) 0x5 DZPQ Disable Zero-Quanta Pause 7 1 read-write ENABLE Zero-Quanta Pause packet generation is enabled 0 DISABLE Zero-Quanta Pause packet generation is disabled 0x1 PT Pause Time 16 16 read-write MAC_RX_FLOW_CTRL MAC Rx Flow Control 0x90 32 read-write 0 0xFFFFFFFF RFE Receive Flow Control Enable 0 1 read-write DISABLE Receive Flow Control is disabled 0 ENABLE Receive Flow Control is enabled 0x1 UP Unicast Pause Packet Detect 1 1 read-write DISABLE Unicast Pause Packet Detect disabled 0 ENABLE Unicast Pause Packet Detect enabled 0x1 PFCE Priority Based Flow Control Enable 8 1 read-write DISABLE Priority Based Flow Control is disabled 0 ENABLE Priority Based Flow Control is enabled 0x1 MAC_RXQ_CTRL4 Receive Queue Control 4 0x94 32 read-write 0 0xFFFFFFFF UFFQE Unicast Address Filter Fail Packets Queuing Enable. 0 1 read-write DISABLE Unicast Address Filter Fail Packets Queuing is disabled 0 ENABLE Unicast Address Filter Fail Packets Queuing is enabled 0x1 UFFQ Unicast Address Filter Fail Packets Queue. 1 3 read-write MFFQE Multicast Address Filter Fail Packets Queuing Enable. 8 1 read-write DISABLE Multicast Address Filter Fail Packets Queuing is disabled 0 ENABLE Multicast Address Filter Fail Packets Queuing is enabled 0x1 MFFQ Multicast Address Filter Fail Packets Queue. 9 3 read-write VFFQE VLAN Tag Filter Fail Packets Queuing Enable 16 1 read-write DISABLE VLAN tag Filter Fail Packets Queuing is disabled 0 ENABLE VLAN tag Filter Fail Packets Queuing is enabled 0x1 VFFQ VLAN Tag Filter Fail Packets Queue 17 3 read-write MAC_TXQ_PRTY_MAP0 Transmit Queue Priority Mapping 0 0x98 32 read-write 0 0xFFFFFFFF PSTQ0 Priorities Selected in Transmit Queue 0 0 8 read-write PSTQ1 Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit. 8 8 read-write PSTQ2 Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit. 16 8 read-write PSTQ3 Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit. 24 8 read-write MAC_TXQ_PRTY_MAP1 Transmit Queue Priority Mapping 1 0x9C 32 read-write 0 0xFFFFFFFF PSTQ4 Priorities Selected in Transmit Queue 4 0 8 read-write MAC_RXQ_CTRL0 Receive Queue Control 0 0xA0 32 read-write 0 0xFFFFFFFF RXQ0EN Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB. 0 2 read-write DISABLE Queue not enabled 0 EN_AV Queue enabled for AV 0x1 EN_DCB_GEN Queue enabled for DCB/Generic 0x2 RXQ1EN Receive Queue 1 Enable This field is similar to the RXQ0EN field. 2 2 read-write DISABLE Queue not enabled 0 EN_AV Queue enabled for AV 0x1 EN_DCB_GEN Queue enabled for DCB/Generic 0x2 RXQ2EN Receive Queue 2 Enable This field is similar to the RXQ0EN field. 4 2 read-write DISABLE Queue not enabled 0 EN_AV Queue enabled for AV 0x1 EN_DCB_GEN Queue enabled for DCB/Generic 0x2 RXQ3EN Receive Queue 3 Enable This field is similar to the RXQ0EN field. 6 2 read-write DISABLE Queue not enabled 0 EN_AV Queue enabled for AV 0x1 EN_DCB_GEN Queue enabled for DCB/Generic 0x2 RXQ4EN Receive Queue 4 Enable This field is similar to the RXQ0EN field. 8 2 read-write DISABLE Queue not enabled 0 EN_AV Queue enabled for AV 0x1 EN_DCB_GEN Queue enabled for DCB/Generic 0x2 MAC_RXQ_CTRL1 Receive Queue Control 1 0xA4 32 read-write 0 0xFFFFFFFF AVCPQ AV Untagged Control Packets Queue 0 3 read-write QUEUE0 Receive Queue 0 0 QUEUE1 Receive Queue 1 0x1 QUEUE2 Receive Queue 2 0x2 QUEUE3 Receive Queue 3 0x3 QUEUE4 Receive Queue 4 0x4 PTPQ PTP Packets Queue 4 3 read-write QUEUE0 Receive Queue 0 0 QUEUE1 Receive Queue 1 0x1 QUEUE2 Receive Queue 2 0x2 QUEUE3 Receive Queue 3 0x3 QUEUE4 Receive Queue 4 0x4 DCBCPQ DCB Control Packets Queue 8 3 read-write QUEUE0 Receive Queue 0 0 QUEUE1 Receive Queue 1 0x1 QUEUE2 Receive Queue 2 0x2 QUEUE3 Receive Queue 3 0x3 QUEUE4 Receive Queue 4 0x4 UPQ Untagged Packet Queue 12 3 read-write QUEUE0 Receive Queue 0 0 QUEUE1 Receive Queue 1 0x1 QUEUE2 Receive Queue 2 0x2 QUEUE3 Receive Queue 3 0x3 QUEUE4 Receive Queue 4 0x4 MCBCQ Multicast and Broadcast Queue 16 3 read-write QUEUE0 Receive Queue 0 0 QUEUE1 Receive Queue 1 0x1 QUEUE2 Receive Queue 2 0x2 QUEUE3 Receive Queue 3 0x3 QUEUE4 Receive Queue 4 0x4 MCBCQEN Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field. 20 1 read-write DISABLE Multicast and Broadcast Queue is disabled 0 ENABLE Multicast and Broadcast Queue is enabled 0x1 TACPQE Tagged AV Control Packets Queuing Enable. 21 1 read-write DISABLE Tagged AV Control Packets Queuing is disabled 0 ENABLE Tagged AV Control Packets Queuing is enabled 0x1 TPQC Tagged PTP over Ethernet Packets Queuing Control. 22 2 read-write FPRQ Frame Preemption Residue Queue 24 3 read-write MAC_RXQ_CTRL2 Receive Queue Control 2 0xA8 32 read-write 0 0xFFFFFFFF PSRQ0 Priorities Selected in the Receive Queue 0 0 8 read-write PSRQ1 Priorities Selected in the Receive Queue 1 8 8 read-write PSRQ2 Priorities Selected in the Receive Queue 2 16 8 read-write PSRQ3 Priorities Selected in the Receive Queue 3 24 8 read-write MAC_RXQ_CTRL3 Receive Queue Control 3 0xAC 32 read-write 0 0xFFFFFFFF PSRQ4 Priorities Selected in the Receive Queue 4 0 8 read-write MAC_INTERRUPT_STATUS Interrupt Status 0xB0 32 read-only 0 0xFFFFFFFF RGSMIIIS RGMII or SMII Interrupt Status 0 1 read-only INACTIVE RGMII or SMII Interrupt Status is not active 0 ACTIVE RGMII or SMII Interrupt Status is active 0x1 PHYIS PHY Interrupt 3 1 read-only INACTIVE PHY Interrupt not detected 0 ACTIVE PHY Interrupt detected 0x1 PMTIS PMT Interrupt Status 4 1 read-only INACTIVE PMT Interrupt status not active 0 ACTIVE PMT Interrupt status active 0x1 LPIIS LPI Interrupt Status 5 1 read-only INACTIVE LPI Interrupt status not active 0 ACTIVE LPI Interrupt status active 0x1 MMCIS MMC Interrupt Status 8 1 read-only INACTIVE MMC Interrupt status not active 0 ACTIVE MMC Interrupt status active 0x1 MMCRXIS MMC Receive Interrupt Status 9 1 read-only INACTIVE MMC Receive Interrupt status not active 0 ACTIVE MMC Receive Interrupt status active 0x1 MMCTXIS MMC Transmit Interrupt Status 10 1 read-only INACTIVE MMC Transmit Interrupt status not active 0 ACTIVE MMC Transmit Interrupt status active 0x1 MMCRXIPIS MMC Receive Checksum Offload Interrupt Status 11 1 read-only INACTIVE MMC Receive Checksum Offload Interrupt status not active 0 ACTIVE MMC Receive Checksum Offload Interrupt status active 0x1 TSIS Timestamp Interrupt Status 12 1 read-only INACTIVE Timestamp Interrupt status not active 0 ACTIVE Timestamp Interrupt status active 0x1 TXSTSIS Transmit Status Interrupt 13 1 read-only INACTIVE Transmit Interrupt status not active 0 ACTIVE Transmit Interrupt status active 0x1 RXSTSIS Receive Status Interrupt 14 1 read-only INACTIVE Receive Interrupt status not active 0 ACTIVE Receive Interrupt status active 0x1 FPEIS Frame Preemption Interrupt Status 17 1 read-only INACTIVE Frame Preemption Interrupt status not active 0 ACTIVE Frame Preemption Interrupt status active 0x1 MDIOIS MDIO Interrupt Status 18 1 read-only INACTIVE MDIO Interrupt status not active 0 ACTIVE MDIO Interrupt status active 0x1 MFTIS MMC FPE Transmit Interrupt Status 19 1 read-only INACTIVE MMC FPE Transmit Interrupt status not active 0 ACTIVE MMC FPE Transmit Interrupt status active 0x1 MFRIS MMC FPE Receive Interrupt Status 20 1 read-only INACTIVE MMC FPE Receive Interrupt status not active 0 ACTIVE MMC FPE Receive Interrupt status active 0x1 MAC_INTERRUPT_ENABLE Interrupt Enable 0xB4 32 read-write 0 0xFFFFFFFF RGSMIIIE RGMII or SMII Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in MAC_INTERRUPT_STATUS register. 0 1 read-write DISABLE RGMII or SMII Interrupt is disabled 0 ENABLE RGMII or SMII Interrupt is enabled 0x1 PHYIE PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[PHYIS]. 3 1 read-write DISABLE PHY Interrupt is disabled 0 ENABLE PHY Interrupt is enabled 0x1 PMTIE PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[PMTIS]. 4 1 read-write DISABLE PMT Interrupt is disabled 0 ENABLE PMT Interrupt is enabled 0x1 LPIIE LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[LPIIS]. 5 1 read-write DISABLE LPI Interrupt is disabled 0 ENABLE LPI Interrupt is enabled 0x1 TSIE Timestamp Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TSIS]. 12 1 read-write DISABLE Timestamp Interrupt is disabled 0 ENABLE Timestamp Interrupt is enabled 0x1 TXSTSIE Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TXSTSIS]. 13 1 read-write DISABLE Timestamp Status Interrupt is disabled 0 ENABLE Timestamp Status Interrupt is enabled 0x1 RXSTSIE Receive Status Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[RXSTSIS]. 14 1 read-write DISABLE Receive Status Interrupt is disabled 0 ENABLE Receive Status Interrupt is enabled 0x1 FPEIE Frame Preemption Interrupt Enable When this bit is set, it enables the assertion of the interrupt when FPEIS field is set in the MAC_INTERRUPT_STATUS. 17 1 read-write DISABLE Frame Preemption Interrupt is disabled 0 ENABLE Frame Preemption Interrupt is enabled 0x1 MDIOIE MDIO Interrupt Enable When this bit is set, it enables the assertion of the interrupt when MDIOIS field is set in the MAC_INTERRUPT_STATUS register. 18 1 read-write DISABLE MDIO Interrupt is disabled 0 ENABLE MDIO Interrupt is enabled 0x1 MAC_RX_TX_STATUS Receive Transmit Status 0xB8 32 read-only 0 0xFFFFFFFF TJT Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_CONFIGURATION register. 0 1 read-only INACTIVE No Transmit Jabber Timeout 0 ACTIVE Transmit Jabber Timeout occurred 0x1 NCARR No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission. 1 1 read-only INACTIVE Carrier is present 0 ACTIVE No carrier 0x1 LCARR Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i signal was inactive for one or more transmission clock periods during packet transmission. 2 1 read-only INACTIVE Carrier is present 0 ACTIVE Loss of carrier 0x1 EXDEF Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the DC bit is set in the MAC_CONFIGURATION register, this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or when Jumbo packet is enabled). 3 1 read-only INACTIVE No Excessive deferral 0 ACTIVE Excessive deferral 0x1 LCOL Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode; 512 bytes including Preamble and Carrier Extension in GMII mode). 4 1 read-only INACTIVE No collision 0 ACTIVE Late collision is sensed 0x1 EXCOL Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. 5 1 read-only INACTIVE No collision 0 ACTIVE Excessive collision is sensed 0x1 RWT Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_CONFIGURATION register. 8 1 read-only INACTIVE No receive watchdog timeout 0 ACTIVE Receive watchdog timed out 0x1 MAC_PMT_CONTROL_STATUS PMT Control and Status 0xC0 32 read-write 0 0xFFFFFFFF PWRDWN Power Down When this bit is set, the MAC receiver drops all received packets until it receives the expected magic packet or remote wake-up packet. 0 1 read-write DISABLE Power down is disabled 0 ENABLE Power down is enabled 0x1 MGKPKTEN Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet. 1 1 read-write DISABLE Magic Packet is disabled 0 ENABLE Magic Packet is enabled 0x1 RWKPKTEN Remote Wake-Up Packet Enable When this bit is set, a power management event is generated when the MAC receives a remote wake-up packet. 2 1 read-write DISABLE Remote wake-up packet is disabled 0 ENABLE Remote wake-up packet is enabled 0x1 MGKPRCVD Magic Packet Received When this bit is set, it indicates that the power management event is generated because of the reception of a magic packet. 5 1 read-only INACTIVE No Magic packet is received 0 ACTIVE Magic packet is received 0x1 RWKPRCVD Remote Wake-Up Packet Received When this bit is set, it indicates that the power management event is generated because of the reception of a remote wake-up packet. 6 1 read-only INACTIVE Remote wake-up packet is received 0 ACTIVE Remote wake-up packet is received 0x1 GLBLUCAST Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet. 9 1 read-write DISABLE Global unicast is disabled 0 ENABLE Global unicast is enabled 0x1 RWKPFE Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the MAC receiver drops all received frames until it receives the expected Wake-up frame. 10 1 read-write DISABLE Remote Wake-up Packet Forwarding is disabled 0 ENABLE Remote Wake-up Packet Forwarding is enabled 0x1 RWKPTR Remote Wake-up FIFO Pointer This field gives the current value (0 to 7, 15, or 31 when 4, 8, or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter register pointer. 24 5 read-only RWKFILTRST Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the remote wake-up packet filter register pointer is reset to 3'b000. 31 1 read-write DISABLE Remote Wake-Up Packet Filter Register Pointer is not Reset 0 ENABLE Remote Wake-Up Packet Filter Register Pointer is Reset 0x1 MAC_RWK_PACKET_FILTER Remote Wakeup Filter 0xC4 32 read-write 0 0xFFFFFFFF WKUPFRMFTR RWK Packet Filter This field contains the various controls of RWK Packet filter. 0 32 read-write MAC_LPI_CONTROL_STATUS LPI Control and Status 0xD0 32 read-write 0 0xFFFFFFFF TLPIEN Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. 0 1 read-only INACTIVE Transmit LPI entry not detected 0 ACTIVE Transmit LPI entry detected 0x1 TLPIEX Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. 1 1 read-only INACTIVE Transmit LPI exit not detected 0 ACTIVE Transmit LPI exit detected 0x1 RLPIEN Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. 2 1 read-only INACTIVE Receive LPI entry not detected 0 ACTIVE Receive LPI entry detected 0x1 RLPIEX Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. 3 1 read-only INACTIVE Receive LPI exit not detected 0 ACTIVE Receive LPI exit detected 0x1 TLPIST Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. 8 1 read-only INACTIVE Transmit LPI state not detected 0 ACTIVE Transmit LPI state detected 0x1 RLPIST Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. 9 1 read-only INACTIVE Receive LPI state not detected 0 ACTIVE Receive LPI state detected 0x1 LPIEN LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state. 16 1 read-write DISABLE LPI state is disabled 0 ENABLE LPI state is enabled 0x1 PLS PHY Link Status This bit indicates the link status of the PHY. 17 1 read-write DISABLE link is down 0 ENABLE link is okay (UP) 0x1 PLSEN PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or SMII Receive paths to be used for activating the LPI LS TIMER. 18 1 read-write DISABLE PHY Link Status is disabled 0 ENABLE PHY Link Status is enabled 0x1 LPITXA LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side. 19 1 read-write DISABLE LPI Tx Automate is disabled 0 ENABLE LPI Tx Automate is enabled 0x1 LPIATE LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. 20 1 read-write DISABLE LPI Timer is disabled 0 ENABLE LPI Timer is enabled 0x1 LPITCSE LPI Tx Clock Stop Enable When this bit is set, the MAC asserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped. 21 1 read-write DISABLE LPI Tx Clock Stop is disabled 0 ENABLE LPI Tx Clock Stop is enabled 0x1 MAC_LPI_TIMERS_CONTROL LPI Timers Control 0xD4 32 read-write 0x3E80000 0xFFFFFFFF TWT LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. 0 16 read-write LST LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. 16 10 read-write MAC_LPI_ENTRY_TIMER Tx LPI Entry Timer Control 0xD8 32 read-write 0 0xFFFFFFFF LPIET LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI mode, after it has transmitted all the frames. 3 17 read-write MAC_ONEUS_TIC_COUNTER One-microsecond Reference Timer 0xDC 32 read-write 0x63 0xFFFFFFFF TIC_1US_CNTR 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us. 0 12 read-write MAC_PHYIF_CONTROL_STATUS PHY Interface Control and Status 0xF8 32 read-write 0 0xFFFFFFFF TC Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. 0 1 read-write DISABLE Disable Transmit Configuration in RGMII, SGMII, or SMII 0 ENABLE Enable Transmit Configuration in RGMII, SGMII, or SMII 0x1 LUD Link Up or Down This bit indicates whether the link is up or down during transmission of configuration in the RGMII, SGMII, or SMII interface. 1 1 read-write LINKDOWN Link down 0 LINKUP Link up 0x1 LNKMOD Link Mode This bit indicates the current mode of operation of the link. 16 1 read-only HDUPLX Half-duplex mode 0 FDUPLX Full-duplex mode 0x1 LNKSPEED Link Speed This bit indicates the current speed of the link. 17 2 read-only bf_2500K 2.5 MHz 0 bf_25M 25 MHz 0x1 bf_125M 125 MHz 0x2 LNKSTS Link Status This bit indicates whether the link is up (1'b1) or down (1'b0). 19 1 read-only INACTIVE Link down 0 ACTIVE Link up 0x1 MAC_VERSION MAC Version 0x110 32 read-only 0x1051 0xFFFFFFFF SNPSVER Synopsys-defined Version 0 8 read-only USERVER User-defined Version (8'h10) 8 8 read-only MAC_DEBUG MAC Debug 0x114 32 read-only 0 0xFFFFFFFF RPESTS MAC GMII or MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC GMII or MII receive protocol engine is actively receiving data, and it is not in the Idle state. 0 1 read-only INACTIVE MAC GMII or MII Receive Protocol Engine Status not detected 0 ACTIVE MAC GMII or MII Receive Protocol Engine Status detected 0x1 RFCFCSTS MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module. 1 2 read-only TPESTS MAC GMII or MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in the Idle state. 16 1 read-only INACTIVE MAC GMII or MII Transmit Protocol Engine Status not detected 0 ACTIVE MAC GMII or MII Transmit Protocol Engine Status detected 0x1 TFCSTS MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module. 17 2 read-only IDLE Idle state 0 WAITING Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over 0x1 GEN_TX_PAU Generating and transmitting a Pause control packet (in full-duplex mode) 0x2 TRNSFR Transferring input packet for transmission 0x3 MAC_HW_FEATURE0 Optional Features or Functions 0 0x11C 32 read-only 0xEFD71F7 0xFFFFFFFF MIISEL 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation 0 1 read-only INACTIVE No 10 or 100 Mbps support 0 ACTIVE 10 or 100 Mbps support 0x1 GMIISEL 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation 1 1 read-only INACTIVE No 1000 Mbps support 0 ACTIVE 1000 Mbps support 0x1 HDSEL Half-duplex Support This bit is set to 1 when the half-duplex mode is selected 2 1 read-only INACTIVE No Half-duplex support 0 ACTIVE Half-duplex support 0x1 PCSSEL PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI, SGMII, or RTBI PHY interface option is selected 3 1 read-only INACTIVE No PCS Registers (TBI, SGMII, or RTBI PHY interface) 0 ACTIVE PCS Registers (TBI, SGMII, or RTBI PHY interface) 0x1 VLHASH VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected 4 1 read-only INACTIVE VLAN Hash Filter not selected 0 ACTIVE VLAN Hash Filter selected 0x1 SMASEL SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected 5 1 read-only INACTIVE SMA (MDIO) Interface not selected 0 ACTIVE SMA (MDIO) Interface selected 0x1 RWKSEL PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected 6 1 read-only INACTIVE PMT Remote Wake-up Packet Enable option is not selected 0 ACTIVE PMT Remote Wake-up Packet Enable option is selected 0x1 MGKSEL PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected 7 1 read-only INACTIVE PMT Magic Packet Enable option is not selected 0 ACTIVE PMT Magic Packet Enable option is selected 0x1 MMCSEL RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected 8 1 read-only INACTIVE RMON Module Enable option is not selected 0 ACTIVE RMON Module Enable option is selected 0x1 ARPOFFSEL ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected 9 1 read-only INACTIVE ARP Offload Enable option is not selected 0 ACTIVE ARP Offload Enable option is selected 0x1 TSSEL IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected 12 1 read-only INACTIVE IEEE 1588-2008 Timestamp Enable option is not selected 0 ACTIVE IEEE 1588-2008 Timestamp Enable option is selected 0x1 EEESEL Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected 13 1 read-only INACTIVE Energy Efficient Ethernet Enable option is not selected 0 ACTIVE Energy Efficient Ethernet Enable option is selected 0x1 TXCOESEL Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected 14 1 read-only INACTIVE Transmit Checksum Offload Enable option is not selected 0 ACTIVE Transmit Checksum Offload Enable option is selected 0x1 RXCOESEL Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected 16 1 read-only INACTIVE Receive Checksum Offload Enable option is not selected 0 ACTIVE Receive Checksum Offload Enable option is selected 0x1 ADDMACADRSEL MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is selected for Enable Additional 1-31 MAC Address Registers option 18 5 read-only MACADR32SEL MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected 23 1 read-only INACTIVE MAC Addresses 32-63 Select option is not selected 0 ACTIVE MAC Addresses 32-63 Select option is selected 0x1 MACADR64SEL MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected 24 1 read-only INACTIVE MAC Addresses 64-127 Select option is not selected 0 ACTIVE MAC Addresses 64-127 Select option is selected 0x1 TSSTSSEL Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected 25 2 read-only INTRNL Internal 0 EXTRNL External 0x1 BOTH Both 0x2 SAVLANINS Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected 27 1 read-only INACTIVE Source Address or VLAN Insertion Enable option is not selected 0 ACTIVE Source Address or VLAN Insertion Enable option is selected 0x1 ACTPHYSEL Active PHY Selected When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. 28 3 read-only GMII_MII GMII or MII 0 RGMII RGMII 0x1 SGMII SGMII 0x2 TBI TBI 0x3 RMII RMII 0x4 RTBI RTBI 0x5 SMII SMII 0x6 REVMIII RevMII 0x7 MAC_HW_FEATURE1 Optional Features or Functions 1 0x120 32 read-only 0x419939A6 0xFFFFFFFF RXFIFOSIZE MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7: 0 5 read-only bf_128B 128 bytes 0 bf_256B 256 bytes 0x1 bf_512B 512 bytes 0x2 bf_1024B 1024 bytes 0x3 bf_2048B 2048 bytes 0x4 bf_4096B 4096 bytes 0x5 bf_8192B 8192 bytes 0x6 bf_16384B 16384 bytes 0x7 bf_32KB 32 KB 0x8 bf_64KB 64 KB 0x9 bf_128KB 128 KB 0xA bf_256KB 256 KB 0xB SPRAM Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected. 5 1 read-only INACTIVE Single Port RAM feature is not selected 0 ACTIVE Single Port RAM feature is selected 0x1 TXFIFOSIZE MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7: 6 5 read-only bf_128B 128 bytes 0 bf_256B 256 bytes 0x1 bf_512B 512 bytes 0x2 bf_1024B 1024 bytes 0x3 bf_2048B 2048 bytes 0x4 bf_4096B 4096 bytes 0x5 bf_8192B 8192 bytes 0x6 bf_16384B 16384 bytes 0x7 bf_32KB 32 KB 0x8 bf_64KB 64 KB 0x9 bf_128KB 128 KB 0xA OSTEN One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected. 11 1 read-only INACTIVE One-Step Timestamping feature is not selected 0 ACTIVE One-Step Timestamping feature is selected 0x1 PTOEN PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected. 12 1 read-only INACTIVE PTP Offload feature is not selected 0 ACTIVE PTP Offload feature is selected 0x1 ADVTHWORD IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected 13 1 read-only INACTIVE IEEE 1588 High Word Register option is not selected 0 ACTIVE IEEE 1588 High Word Register option is selected 0x1 ADDR64 Address Width. 14 2 read-only bf_32 32 0 bf_40 40 0x1 bf_48 48 0x2 DCBEN DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected 16 1 read-only INACTIVE DCB Feature is not selected 0 ACTIVE DCB Feature is selected 0x1 SPHEN Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected 17 1 read-only INACTIVE Split Header Feature is not selected 0 ACTIVE Split Header Feature is selected 0x1 TSOEN TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected 18 1 read-only INACTIVE TCP Segmentation Offload Feature is not selected 0 ACTIVE TCP Segmentation Offload Feature is selected 0x1 DBGMEMA DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected 19 1 read-only INACTIVE DMA Debug Registers option is not selected 0 ACTIVE DMA Debug Registers option is selected 0x1 AVSEL AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected. 20 1 read-only INACTIVE AV Feature is not selected 0 ACTIVE AV Feature is selected 0x1 RAVSEL Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected. 21 1 read-only INACTIVE Rx Side Only AV Feature is not selected 0 ACTIVE Rx Side Only AV Feature is selected 0x1 POUOST One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One step timestamp for PTP over UDP/IP feature is selected. 23 1 read-only INACTIVE One Step for PTP over UDP/IP Feature is not selected 0 ACTIVE One Step for PTP over UDP/IP Feature is selected 0x1 HASHTBLSZ Hash Table Size This field indicates the size of the hash table: 24 2 read-only NO_HT No hash table 0 bf_64 64 0x1 bf_128 128 0x2 bf_256 256 0x3 L3L4FNUM Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters: 27 4 read-only NOFILT No L3 or L4 Filter 0 bf_1FILT 1 L3 or L4 Filter 0x1 bf_2FILT 2 L3 or L4 Filters 0x2 bf_3FILT 3 L3 or L4 Filters 0x3 bf_4FILT 4 L3 or L4 Filters 0x4 bf_5FILT 5 L3 or L4 Filters 0x5 bf_6FILT 6 L3 or L4 Filters 0x6 bf_7FILT 7 L3 or L4 Filters 0x7 bf_8FILT 8 L3 or L4 Filters 0x8 MAC_HW_FEATURE2 Optional Features or Functions 2 0x124 32 read-only 0x44104104 0xFFFFFFFF RXQCNT Number of MTL Receive Queues This field indicates the number of MTL Receive queues: 0 4 read-only bf_1RXQ 1 MTL Rx Queue 0 bf_2RXQ 2 MTL Rx Queues 0x1 bf_3RXQ 3 MTL Rx Queues 0x2 bf_4RXQ 4 MTL Rx Queues 0x3 bf_5RXQ 5 MTL Rx Queues 0x4 TXQCNT Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues: 6 4 read-only bf_1TXQ 1 MTL Tx Queue 0 bf_2TXQ 2 MTL Tx Queues 0x1 bf_3TXQ 3 MTL Tx Queues 0x2 bf_4TXQ 4 MTL Tx Queues 0x3 bf_5TXQ 5 MTL Tx Queues 0x4 RXCHCNT Number of DMA Receive Channels This field indicates the number of DMA Receive channels: 12 4 read-only bf_1RXCH 1 MTL Rx Channel 0 bf_2RXCH 2 MTL Rx Channels 0x1 bf_3RXCH 3 MTL Rx Channels 0x2 bf_4RXCH 4 MTL Rx Channels 0x3 bf_5RXCH 5 MTL Rx Channels 0x4 TXCHCNT Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels: 18 4 read-only bf_1TXCH 1 MTL Tx Channel 0 bf_2TXCH 2 MTL Tx Channels 0x1 bf_3TXCH 3 MTL Tx Channels 0x2 bf_4TXCH 4 MTL Tx Channels 0x3 bf_5TXCH 5 MTL Tx Channels 0x4 PPSOUTNUM Number of PPS Outputs This field indicates the number of PPS outputs: 24 3 read-only NO_PPSO No PPS output 0 bf_1_PPSO 1 PPS output 0x1 bf_2_PPSO 2 PPS output 0x2 bf_3_PPSO 3 PPS output 0x3 bf_4_PPSO 4 PPS output 0x4 AUXSNAPNUM Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs: 28 3 read-only NO_AUXI No auxiliary input 0 bf_1_AUXI 1 auxiliary input 0x1 bf_2_AUXI 2 auxiliary input 0x2 bf_3_AUXI 3 auxiliary input 0x3 bf_4_AUXI 4 auxiliary input 0x4 MAC_HW_FEATURE3 Optional Features or Functions 3 0x128 32 read-only 0xC395632 0xFFFFFFFF NRVF Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected: 0 3 read-only NO_ERVLAN No Extended Rx VLAN Filters 0 bf_4_ERVLAN 4 Extended Rx VLAN Filters 0x1 bf_8_ERVLAN 8 Extended Rx VLAN Filters 0x2 bf_16_ERVLAN 16 Extended Rx VLAN Filters 0x3 bf_24_ERVLAN 24 Extended Rx VLAN Filters 0x4 bf_32_ERVLAN 32 Extended Rx VLAN Filters 0x5 CBTISEL Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected. 4 1 read-only INACTIVE Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected 0 ACTIVE Enable Queue/Channel based VLAN tag insertion on Tx feature is selected 0x1 DVLAN Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected. 5 1 read-only INACTIVE Double VLAN option is not selected 0 ACTIVE Double VLAN option is selected 0x1 PDUPSEL Broadcast/Multicast Packet Duplication This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected. 9 1 read-only INACTIVE Broadcast/Multicast Packet Duplication feature is not selected 0 ACTIVE Broadcast/Multicast Packet Duplication feature is selected 0x1 FRPSEL Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible Programmable Receive Parser option is selected. 10 1 read-only INACTIVE Flexible Receive Parser feature is not selected 0 ACTIVE Flexible Receive Parser feature is selected 0x1 FRPBS Flexible Receive Parser Buffer size This field indicates the supported Max Number of bytes of the packet data to be Parsed by Flexible Receive Parser. 11 2 read-only bf_64BYTES 64 Bytes 0 bf_128BYTES 128 Bytes 0x1 bf_256BYTES 256 Bytes 0x2 FRPES Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser Entries supported by Flexible Receive Parser. 13 2 read-only bf_64ENTR 64 Entries 0 bf_128ENTR 128 Entries 0x1 bf_256ENTR 256 Entries 0x2 ESTSEL Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected. 16 1 read-only INACTIVE Enable Enhancements to Scheduling Traffic feature is not selected 0 ACTIVE Enable Enhancements to Scheduling Traffic feature is selected 0x1 ESTDEP Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5 17 3 read-only NODEPTH No Depth configured 0 DEPTH64 64 0x1 DEPTH128 128 0x2 DEPTH256 256 0x3 DEPTH512 512 0x4 DEPTH1024 1024 0x5 ESTWID Width of the Time Interval field in the Gate Control List This field indicates the width of the Configured Time Interval Field 20 2 read-only NOWIDTH Width not configured 0 WIDTH16 16 0x1 WIDTH20 20 0x2 WIDTH24 24 0x3 FPESEL Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected. 26 1 read-only INACTIVE Frame Preemption Enable feature is not selected 0 ACTIVE Frame Preemption Enable feature is selected 0x1 TBSSEL Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected. 27 1 read-only INACTIVE Time Based Scheduling Enable feature is not selected 0 ACTIVE Time Based Scheduling Enable feature is selected 0x1 ASP Automotive Safety Package Following are the encoding for the different Safety features 28 2 read-only NONE No Safety features selected 0 ECC_ONLY Only "ECC protection for external memory" feature is selected 0x1 AS_NPPE All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature 0x2 AS_PPE All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature 0x3 MAC_MDIO_ADDRESS MDIO Address 0x200 32 read-write 0 0xFFFFFFFF GB GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave. 0 1 read-write DISABLE GMII Busy is disabled 0 ENABLE GMII Busy is enabled 0x1 C45E Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO. 1 1 read-write DISABLE Clause 45 PHY is disabled 0 ENABLE Clause 45 PHY is enabled 0x1 GOC_0 GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII. 2 1 read-write DISABLE GMII Operation Command 0 is disabled 0 ENABLE GMII Operation Command 0 is enabled 0x1 GOC_1 GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or RevMII, GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or RevMII is enabled, only Write and Read commands are valid. 3 1 read-write DISABLE GMII Operation Command 1 is disabled 0 ENABLE GMII Operation Command 1 is enabled 0x1 SKAP Skip Address Packet When this bit is set, the SMA does not send the address packets before read, write, or post-read increment address packets. 4 1 read-write DISABLE Skip Address Packet is disabled 0 ENABLE Skip Address Packet is enabled 0x1 CR CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 - 0010: CSR clock = 20-35 MHz; MDC clock = CSR clock/16 - 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26 - 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 - 0101: CSR clock = 250-300 MHz; MDC clock = CSR clock/124 - 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204 - 0111: CSR clock = 500-800 MHz; MDC clock = CSR clock/324 The suggested range of CSR clock frequency applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1. 8 4 read-write NTC Number of Trailing Clocks This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame. 12 3 read-write RDA Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. 16 5 read-write PA Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. 21 5 read-write BTB Back to Back transactions When this bit is set and the NTC has value greater than 0, then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted). 26 1 read-write DISABLE Back to Back transactions disabled 0 ENABLE Back to Back transactions enabled 0x1 PSE Preamble Suppression Enable When this bit is set, the SMA suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit. 27 1 read-write DISABLE Preamble Suppression disabled 0 ENABLE Preamble Suppression enabled 0x1 MAC_MDIO_DATA MAC MDIO Data 0x204 32 read-write 0 0xFFFFFFFF GD GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. 0 16 read-write RA Register Address This field is valid only when C45E is set. 16 16 read-write MAC_CSR_SW_CTRL CSR Software Control 0x230 32 read-write 0 0xFFFFFFFF RCWE Register Clear on Write 1 Enable When this bit is set, the access mode of some register fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to clear it. 0 1 read-write DISABLE Register Clear on Write 1 is disabled 0 ENABLE Register Clear on Write 1 is enabled 0x1 MAC_FPE_CTRL_STS Frame Preemption Control 0x234 32 read-write 0 0xFFFFFFFF EFPE Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled. 0 1 read-write DISABLE Tx Frame Preemption is disabled 0 ENABLE Tx Frame Preemption is enabled 0x1 SVER Send Verify mPacket When set indicates hardware to send a verify mPacket. 1 1 read-write DISABLE Send Verify mPacket is disabled 0 ENABLE Send Verify mPacket is enabled 0x1 SRSP Send Respond mPacket When set indicates hardware to send a Respond mPacket. 2 1 read-write DISABLE Send Respond mPacket is disabled 0 ENABLE Send Respond mPacket is enabled 0x1 S1_SET_0 Synopsys Reserved, Must be set to "0". 3 1 read-write RVER Received Verify Frame Set when a Verify mPacket is received. 16 1 read-write INACTIVE Not received Verify Frame 0 ACTIVE Received Verify Frame 0x1 RRSP Received Respond Frame Set when a Respond mPacket is received. 17 1 read-write INACTIVE Not received Respond Frame 0 ACTIVE Received Respond Frame 0x1 TVER Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field). 18 1 read-write INACTIVE Not transmitted Verify Frame 0 ACTIVE transmitted Verify Frame 0x1 TRSP Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field). 19 1 read-write INACTIVE Not transmitted Respond Frame 0 ACTIVE transmitted Respond Frame 0x1 MAC_PRESN_TIME_NS 32-bit Binary Rollover Equivalent Time 0x240 32 read-only 0 0xFFFFFFFF MPTN MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary rollover equivalent time of the PTP System Time in ns 0 32 read-only MAC_PRESN_TIME_UPDT MAC 1722 Presentation Time 0x244 32 read-write 0 0xFFFFFFFF MPTU MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time. 0 32 read-write MAC_ADDRESS0_HIGH MAC Address0 High 0x300 32 read-write 0x8000FFFF 0xFFFFFFFF ADDRHI MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address0 content is routed. 16 5 read-write AE Address Enable This bit is always set to 1. 31 1 read-only DISABLE INVALID : This bit must be always set to 1 0 ENABLE This bit is always set to 1 0x1 MAC_ADDRESS0_LOW MAC Address0 Low 0x304 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address0[31:0] This field contains the lower 32 bits of the first 6-byte MAC address. 0 32 read-write MAC_ADDRESS1_HIGH MAC Address1 High 0x308 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS1_LOW MAC Address1 Low 0x30C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS2_HIGH MAC Address2 High 0x310 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS2_LOW MAC Address2 Low 0x314 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS3_HIGH MAC Address3 High 0x318 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS3_LOW MAC Address3 Low 0x31C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS4_HIGH MAC Address4 High 0x320 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS4_LOW MAC Address4 Low 0x324 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS5_HIGH MAC Address5 High 0x328 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS5_LOW MAC Address5 Low 0x32C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS6_HIGH MAC Address6 High 0x330 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS6_LOW MAC Address6 Low 0x334 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS7_HIGH MAC Address7 High 0x338 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS7_LOW MAC Address7 Low 0x33C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS8_HIGH MAC Address8 High 0x340 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS8_LOW MAC Address8 Low 0x344 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS9_HIGH MAC Address9 High 0x348 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS9_LOW MAC Address9 Low 0x34C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS10_HIGH MAC Address10 High 0x350 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS10_LOW MAC Address10 Low 0x354 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS11_HIGH MAC Address11 High 0x358 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS11_LOW MAC Address11 Low 0x35C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS12_HIGH MAC Address12 High 0x360 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS12_LOW MAC Address12 Low 0x364 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS13_HIGH MAC Address13 High 0x368 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS13_LOW MAC Address13 Low 0x36C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS14_HIGH MAC Address14 High 0x370 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS14_LOW MAC Address14 Low 0x374 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS15_HIGH MAC Address15 High 0x378 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS15_LOW MAC Address15 Low 0x37C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS16_HIGH MAC Address16 High 0x380 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS16_LOW MAC Address16 Low 0x384 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS17_HIGH MAC Address17 High 0x388 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS17_LOW MAC Address17 Low 0x38C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS18_HIGH MAC Address18 High 0x390 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS18_LOW MAC Address18 Low 0x394 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS19_HIGH MAC Address19 High 0x398 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS19_LOW MAC Address19 Low 0x39C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS20_HIGH MAC Address20 High 0x3A0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS20_LOW MAC Address20 Low 0x3A4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS21_HIGH MAC Address21 High 0x3A8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS21_LOW MAC Address21 Low 0x3AC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS22_HIGH MAC Address22 High 0x3B0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS22_LOW MAC Address22 Low 0x3B4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS23_HIGH MAC Address23 High 0x3B8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS23_LOW MAC Address23 Low 0x3BC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS24_HIGH MAC Address24 High 0x3C0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS24_LOW MAC Address24 Low 0x3C4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS25_HIGH MAC Address25 High 0x3C8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS25_LOW MAC Address25 Low 0x3CC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS26_HIGH MAC Address26 High 0x3D0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS26_LOW MAC Address26 Low 0x3D4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS27_HIGH MAC Address27 High 0x3D8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS27_LOW MAC Address27 Low 0x3DC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS28_HIGH MAC Address28 High 0x3E0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS28_LOW MAC Address28 Low 0x3E4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS29_HIGH MAC Address29 High 0x3E8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS29_LOW MAC Address29 Low 0x3EC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS30_HIGH MAC Address30 High 0x3F0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS30_LOW MAC Address30 Low 0x3F4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS31_HIGH MAC Address31 High 0x3F8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write DCS DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. 16 5 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. 24 6 read-write SA Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet. 30 1 read-write DA Compare with Destination Address 0 SA Compare with Source Address 0x1 AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS31_LOW MAC Address31 Low 0x3FC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. 0 32 read-write MAC_ADDRESS32_HIGH MAC Address32 High 0x400 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS32_LOW MAC Address32 Low 0x404 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS33_HIGH MAC Address33 High 0x408 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS33_LOW MAC Address33 Low 0x40C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS34_HIGH MAC Address34 High 0x410 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS34_LOW MAC Address34 Low 0x414 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS35_HIGH MAC Address35 High 0x418 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS35_LOW MAC Address35 Low 0x41C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS36_HIGH MAC Address36 High 0x420 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS36_LOW MAC Address36 Low 0x424 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS37_HIGH MAC Address37 High 0x428 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS37_LOW MAC Address37 Low 0x42C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS38_HIGH MAC Address38 High 0x430 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS38_LOW MAC Address38 Low 0x434 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS39_HIGH MAC Address39 High 0x438 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS39_LOW MAC Address39 Low 0x43C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS40_HIGH MAC Address40 High 0x440 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS40_LOW MAC Address40 Low 0x444 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS41_HIGH MAC Address41 High 0x448 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS41_LOW MAC Address41 Low 0x44C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS42_HIGH MAC Address42 High 0x450 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS42_LOW MAC Address42 Low 0x454 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS43_HIGH MAC Address43 High 0x458 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS43_LOW MAC Address43 Low 0x45C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS44_HIGH MAC Address44 High 0x460 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS44_LOW MAC Address44 Low 0x464 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS45_HIGH MAC Address45 High 0x468 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS45_LOW MAC Address45 Low 0x46C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS46_HIGH MAC Address46 High 0x470 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS46_LOW MAC Address46 Low 0x474 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS47_HIGH MAC Address47 High 0x478 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS47_LOW MAC Address47 Low 0x47C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS48_HIGH MAC Address48 High 0x480 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS48_LOW MAC Address48 Low 0x484 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS49_HIGH MAC Address49 High 0x488 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS49_LOW MAC Address49 Low 0x48C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS50_HIGH MAC Address50 High 0x490 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS50_LOW MAC Address50 Low 0x494 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS51_HIGH MAC Address51 High 0x498 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS51_LOW MAC Address51 Low 0x49C 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS52_HIGH MAC Address52 High 0x4A0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS52_LOW MAC Address52 Low 0x4A4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS53_HIGH MAC Address53 High 0x4A8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS53_LOW MAC Address53 Low 0x4AC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS54_HIGH MAC Address54 High 0x4B0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS54_LOW MAC Address54 Low 0x4B4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS55_HIGH MAC Address55 High 0x4B8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS55_LOW MAC Address55 Low 0x4BC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS56_HIGH MAC Address56 High 0x4C0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS56_LOW MAC Address56 Low 0x4C4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS57_HIGH MAC Address57 High 0x4C8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS57_LOW MAC Address57 Low 0x4CC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS58_HIGH MAC Address58 High 0x4D0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS58_LOW MAC Address58 Low 0x4D4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS59_HIGH MAC Address59 High 0x4D8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS59_LOW MAC Address59 Low 0x4DC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS60_HIGH MAC Address60 High 0x4E0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS60_LOW MAC Address60 Low 0x4E4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS61_HIGH MAC Address61 High 0x4E8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS61_LOW MAC Address61 Low 0x4EC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS62_HIGH MAC Address62 High 0x4F0 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS62_LOW MAC Address62 Low 0x4F4 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_ADDRESS63_HIGH MAC Address63 High 0x4F8 32 read-write 0xFFFF 0xFFFFFFFF ADDRHI MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed. 16 3 read-write AE Address Enable When this bit is set, the Address filter module uses the 33rd MAC address for perfect filtering. 31 1 read-write DISABLE Address is ignored 0 ENABLE Address is enabled 0x1 MAC_ADDRESS63_LOW MAC Address63 Low 0x4FC 32 read-write 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. 0 32 read-write MAC_MMC_CONTROL MMC Control 0x700 32 read-write 0 0xFFFFFFFF CNTRST Counters Reset When this bit is set, all counters are reset. 0 1 read-write DISABLE Counters are not reset 0 ENABLE All counters are reset 0x1 CNTSTOPRO Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value. 1 1 read-write DISABLE Counter Stop Rollover is disabled 0 ENABLE Counter Stop Rollover is enabled 0x1 RSTONRD Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). 2 1 read-write DISABLE Reset on Read is disabled 0 ENABLE Reset on Read is enabled 0x1 CNTFREEZ MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value. 3 1 read-write DISABLE MMC Counter Freeze is disabled 0 ENABLE MMC Counter Freeze is enabled 0x1 CNTPRST Counters Preset When this bit is set, all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit. 4 1 read-write DISABLE Counters Preset is disabled 0 ENABLE Counters Preset is enabled 0x1 CNTPRSTLVL Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value. 5 1 read-write DISABLE Full-Half Preset is disabled 0 ENABLE Full-Half Preset is enabled 0x1 UCDBC Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit. 8 1 read-write DISABLE Update MMC Counters for Dropped Broadcast Packets is disabled 0 ENABLE Update MMC Counters for Dropped Broadcast Packets is enabled 0x1 MAC_MMC_RX_INTERRUPT MMC Rx Interrupt 0x704 32 read-only 0 0xFFFFFFFF RXGBPKTIS MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value. 0 1 read-only INACTIVE MMC Receive Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Good Bad Packet Counter Interrupt Status detected 0x1 RXGBOCTIS MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. 1 1 read-only INACTIVE MMC Receive Good Bad Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Good Bad Octet Counter Interrupt Status detected 0x1 RXGOCTIS MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. 2 1 read-only INACTIVE MMC Receive Good Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Good Octet Counter Interrupt Status detected 0x1 RXBCGPIS MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value. 3 1 read-only INACTIVE MMC Receive Broadcast Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Broadcast Good Packet Counter Interrupt Status detected 0x1 RXMCGPIS MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value. 4 1 read-only INACTIVE MMC Receive Multicast Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Multicast Good Packet Counter Interrupt Status detected 0x1 RXCRCERPIS MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. 5 1 read-only INACTIVE MMC Receive CRC Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive CRC Error Packet Counter Interrupt Status detected 0x1 RXALGNERPIS MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. 6 1 read-only INACTIVE MMC Receive Alignment Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Alignment Error Packet Counter Interrupt Status detected 0x1 RXRUNTPIS MMC Receive Runt Packet Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. 7 1 read-only INACTIVE MMC Receive Runt Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Runt Packet Counter Interrupt Status detected 0x1 RXJABERPIS MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. 8 1 read-only INACTIVE MMC Receive Jabber Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Jabber Error Packet Counter Interrupt Status detected 0x1 RXUSIZEGPIS MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. 9 1 read-only INACTIVE MMC Receive Undersize Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Undersize Good Packet Counter Interrupt Status detected 0x1 RXOSIZEGPIS MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. 10 1 read-only INACTIVE MMC Receive Oversize Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Oversize Good Packet Counter Interrupt Status detected 0x1 RX64OCTGBPIS MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. 11 1 read-only INACTIVE MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected 0x1 RX65T127OCTGBPIS MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. 12 1 read-only INACTIVE MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected 0x1 RX128T255OCTGBPIS MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. 13 1 read-only INACTIVE MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected 0x1 RX256T511OCTGBPIS MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. 14 1 read-only INACTIVE MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected 0x1 RX512T1023OCTGBPIS MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 15 1 read-only INACTIVE MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected 0x1 RX1024TMAXOCTGBPIS MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. 16 1 read-only INACTIVE MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected 0x1 RXUCGPIS MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value. 17 1 read-only INACTIVE MMC Receive Unicast Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Unicast Good Packet Counter Interrupt Status detected 0x1 RXLENERPIS MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. 18 1 read-only INACTIVE MMC Receive Length Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Length Error Packet Counter Interrupt Status detected 0x1 RXORANGEPIS MMC Receive Out Of Range Error Packet Counter Interrupt Status. 19 1 read-only INACTIVE MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Out Of Range Error Packet Counter Interrupt Status detected 0x1 RXPAUSPIS MMC Receive Pause Packet Counter Interrupt Status This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value. 20 1 read-only INACTIVE MMC Receive Pause Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Pause Packet Counter Interrupt Status detected 0x1 RXFOVPIS MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. 21 1 read-only INACTIVE MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive FIFO Overflow Packet Counter Interrupt Status detected 0x1 RXVLANGBPIS MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value. 22 1 read-only INACTIVE MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected 0x1 RXWDOGPIS MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. 23 1 read-only INACTIVE MMC Receive Watchdog Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Watchdog Error Packet Counter Interrupt Status detected 0x1 RXRCVERRPIS MMC Receive Error Packet Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. 24 1 read-only INACTIVE MMC Receive Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Error Packet Counter Interrupt Status detected 0x1 RXCTRLPIS MMC Receive Control Packet Counter Interrupt Status This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value. 25 1 read-only INACTIVE MMC Receive Control Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive Control Packet Counter Interrupt Status detected 0x1 RXLPIUSCIS MMC Receive LPI microsecond counter interrupt status This bit is set when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. 26 1 read-only INACTIVE MMC Receive LPI microsecond Counter Interrupt Status not detected 0 ACTIVE MMC Receive LPI microsecond Counter Interrupt Status detected 0x1 RXLPITRCIS MMC Receive LPI transition counter interrupt status This bit is set when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. 27 1 read-only INACTIVE MMC Receive LPI transition Counter Interrupt Status not detected 0 ACTIVE MMC Receive LPI transition Counter Interrupt Status detected 0x1 MAC_MMC_TX_INTERRUPT MMC Tx Interrupt 0x708 32 read-only 0 0xFFFFFFFF TXGBOCTIS MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. 0 1 read-only INACTIVE MMC Transmit Good Bad Octet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Good Bad Octet Counter Interrupt Status detected 0x1 TXGBPKTIS MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value. 1 1 read-only INACTIVE MMC Transmit Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Good Bad Packet Counter Interrupt Status detected 0x1 TXBCGPIS MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value. 2 1 read-only INACTIVE MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Broadcast Good Packet Counter Interrupt Status detected 0x1 TXMCGPIS MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value. 3 1 read-only INACTIVE MMC Transmit Multicast Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Multicast Good Packet Counter Interrupt Status detected 0x1 TX64OCTGBPIS MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. 4 1 read-only INACTIVE MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected 0x1 TX65T127OCTGBPIS MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. 5 1 read-only INACTIVE MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected 0x1 TX128T255OCTGBPIS MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. 6 1 read-only INACTIVE MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected 0x1 TX256T511OCTGBPIS MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. 7 1 read-only INACTIVE MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected 0x1 TX512T1023OCTGBPIS MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 8 1 read-only INACTIVE MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected 0x1 TX1024TMAXOCTGBPIS MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. 9 1 read-only INACTIVE MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected 0x1 TXUCGBPIS MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value. 10 1 read-only INACTIVE MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected 0x1 TXMCGBPIS MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value. 11 1 read-only INACTIVE MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected 0x1 TXBCGBPIS MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value. 12 1 read-only INACTIVE MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected 0x1 TXUFLOWERPIS MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. 13 1 read-only INACTIVE MMC Transmit Underflow Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Underflow Error Packet Counter Interrupt Status detected 0x1 TXSCOLGPIS MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. 14 1 read-only INACTIVE MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Single Collision Good Packet Counter Interrupt Status detected 0x1 TXMCOLGPIS MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. 15 1 read-only INACTIVE MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected 0x1 TXDEFPIS MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. 16 1 read-only INACTIVE MMC Transmit Deferred Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Deferred Packet Counter Interrupt Status detected 0x1 TXLATCOLPIS MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. 17 1 read-only INACTIVE MMC Transmit Late Collision Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Late Collision Packet Counter Interrupt Status detected 0x1 TXEXCOLPIS MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. 18 1 read-only INACTIVE MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Excessive Collision Packet Counter Interrupt Status detected 0x1 TXCARERPIS MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. 19 1 read-only INACTIVE MMC Transmit Carrier Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Carrier Error Packet Counter Interrupt Status detected 0x1 TXGOCTIS MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. 20 1 read-only INACTIVE MMC Transmit Good Octet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Good Octet Counter Interrupt Status detected 0x1 TXGPKTIS MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value. 21 1 read-only INACTIVE MMC Transmit Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Good Packet Counter Interrupt Status detected 0x1 TXEXDEFPIS MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. 22 1 read-only INACTIVE MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected 0x1 TXPAUSPIS MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value. 23 1 read-only INACTIVE MMC Transmit Pause Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Pause Packet Counter Interrupt Status detected 0x1 TXVLANGPIS MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value. 24 1 read-only INACTIVE MMC Transmit VLAN Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit VLAN Good Packet Counter Interrupt Status detected 0x1 TXOSIZEGPIS MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. 25 1 read-only INACTIVE MMC Transmit Oversize Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Transmit Oversize Good Packet Counter Interrupt Status detected 0x1 TXLPIUSCIS MMC Transmit LPI microsecond counter interrupt status This bit is set when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. 26 1 read-only INACTIVE MMC Transmit LPI microsecond Counter Interrupt Status not detected 0 ACTIVE MMC Transmit LPI microsecond Counter Interrupt Status detected 0x1 TXLPITRCIS MMC Transmit LPI transition counter interrupt status This bit is set when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. 27 1 read-only INACTIVE MMC Transmit LPI transition Counter Interrupt Status not detected 0 ACTIVE MMC Transmit LPI transition Counter Interrupt Status detected 0x1 MAC_MMC_RX_INTERRUPT_MASK MMC Rx Interrupt Mask 0x70C 32 read-write 0 0xFFFFFFFF RXGBPKTIM MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value. 0 1 read-write DISABLE MMC Receive Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Good Bad Packet Counter Interrupt Mask is enabled 0x1 RXGBOCTIM MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. 1 1 read-write DISABLE MMC Receive Good Bad Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Good Bad Octet Counter Interrupt Mask is enabled 0x1 RXGOCTIM MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. 2 1 read-write DISABLE MMC Receive Good Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Good Octet Counter Interrupt Mask is enabled 0x1 RXBCGPIM MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value. 3 1 read-write DISABLE MMC Receive Broadcast Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled 0x1 RXMCGPIM MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value. 4 1 read-write DISABLE MMC Receive Multicast Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled 0x1 RXCRCERPIM MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. 5 1 read-write DISABLE MMC Receive CRC Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive CRC Error Packet Counter Interrupt Mask is enabled 0x1 RXALGNERPIM MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. 6 1 read-write DISABLE MMC Receive Alignment Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled 0x1 RXRUNTPIM MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. 7 1 read-write DISABLE MMC Receive Runt Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Runt Packet Counter Interrupt Mask is enabled 0x1 RXJABERPIM MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. 8 1 read-write DISABLE MMC Receive Jabber Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled 0x1 RXUSIZEGPIM MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. 9 1 read-write DISABLE MMC Receive Undersize Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled 0x1 RXOSIZEGPIM MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. 10 1 read-write DISABLE MMC Receive Oversize Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled 0x1 RX64OCTGBPIM MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. 11 1 read-write DISABLE MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 RX65T127OCTGBPIM MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. 12 1 read-write DISABLE MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 RX128T255OCTGBPIM MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. 13 1 read-write DISABLE MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 RX256T511OCTGBPIM MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. 14 1 read-write DISABLE MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 RX512T1023OCTGBPIM MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 15 1 read-write DISABLE MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 RX1024TMAXOCTGBPIM MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask. 16 1 read-write DISABLE MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 RXUCGPIM MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value. 17 1 read-write DISABLE MMC Receive Unicast Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled 0x1 RXLENERPIM MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. 18 1 read-write DISABLE MMC Receive Length Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Length Error Packet Counter Interrupt Mask is enabled 0x1 RXORANGEPIM MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. 19 1 read-write DISABLE MMC Receive Out Of Range Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled 0x1 RXPAUSPIM MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value. 20 1 read-write DISABLE MMC Receive Pause Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Pause Packet Counter Interrupt Mask is enabled 0x1 RXFOVPIM MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. 21 1 read-write DISABLE MMC Receive FIFO Overflow Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled 0x1 RXVLANGBPIM MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value. 22 1 read-write DISABLE MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled 0x1 RXWDOGPIM MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. 23 1 read-write DISABLE MMC Receive Watchdog Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled 0x1 RXRCVERRPIM MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. 24 1 read-write DISABLE MMC Receive Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Error Packet Counter Interrupt Mask is enabled 0x1 RXCTRLPIM MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value. 25 1 read-write DISABLE MMC Receive Control Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive Control Packet Counter Interrupt Mask is enabled 0x1 RXLPIUSCIM MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. 26 1 read-write DISABLE MMC Receive LPI microsecond counter interrupt Mask is disabled 0 ENABLE MMC Receive LPI microsecond counter interrupt Mask is enabled 0x1 RXLPITRCIM MMC Receive LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. 27 1 read-write DISABLE MMC Receive LPI transition counter interrupt Mask is disabled 0 ENABLE MMC Receive LPI transition counter interrupt Mask is enabled 0x1 MAC_MMC_TX_INTERRUPT_MASK MMC Tx Interrupt Mask 0x710 32 read-write 0 0xFFFFFFFF TXGBOCTIM MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. 0 1 read-write DISABLE MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Good Bad Octet Counter Interrupt Mask is enabled 0x1 TXGBPKTIM MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value. 1 1 read-write DISABLE MMC Transmit Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Good Bad Packet Counter Interrupt Mask is enabled 0x1 TXBCGPIM MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value. 2 1 read-write DISABLE MMC Transmit Broadcast Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Broadcast Good Packet Counter Interrupt Mask is enabled 0x1 TXMCGPIM MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value. 3 1 read-write DISABLE MMC Transmit Multicast Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Multicast Good Packet Counter Interrupt Mask is enabled 0x1 TX64OCTGBPIM MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. 4 1 read-write DISABLE MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 TX65T127OCTGBPIM MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. 5 1 read-write DISABLE MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 TX128T255OCTGBPIM MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. 6 1 read-write DISABLE MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 TX256T511OCTGBPIM MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. 7 1 read-write DISABLE MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 TX512T1023OCTGBPIM MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 8 1 read-write DISABLE MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 TX1024TMAXOCTGBPIM MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. 9 1 read-write DISABLE MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled 0x1 TXUCGBPIM MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value. 10 1 read-write DISABLE MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is enabled 0x1 TXMCGBPIM MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value. 11 1 read-write DISABLE MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is enabled 0x1 TXBCGBPIM MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value. 12 1 read-write DISABLE MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is enabled 0x1 TXUFLOWERPIM MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. 13 1 read-write DISABLE MMC Transmit Underflow Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Underflow Error Packet Counter Interrupt Mask is enabled 0x1 TXSCOLGPIM MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. 14 1 read-write DISABLE MMC Transmit Single Collision Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Single Collision Good Packet Counter Interrupt Mask is enabled 0x1 TXMCOLGPIM MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. 15 1 read-write DISABLE MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is enabled 0x1 TXDEFPIM MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. 16 1 read-write DISABLE MMC Transmit Deferred Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Deferred Packet Counter Interrupt Mask is enabled 0x1 TXLATCOLPIM MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. 17 1 read-write DISABLE MMC Transmit Late Collision Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Late Collision Packet Counter Interrupt Mask is enabled 0x1 TXEXCOLPIM MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. 18 1 read-write DISABLE MMC Transmit Excessive Collision Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Excessive Collision Packet Counter Interrupt Mask is enabled 0x1 TXCARERPIM MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. 19 1 read-write DISABLE MMC Transmit Carrier Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Carrier Error Packet Counter Interrupt Mask is enabled 0x1 TXGOCTIM MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. 20 1 read-write DISABLE MMC Transmit Good Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Good Octet Counter Interrupt Mask is enabled 0x1 TXGPKTIM MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value. 21 1 read-write DISABLE MMC Transmit Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Good Packet Counter Interrupt Mask is enabled 0x1 TXEXDEFPIM MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. 22 1 read-write DISABLE MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled 0x1 TXPAUSPIM MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value. 23 1 read-write DISABLE MMC Transmit Pause Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Pause Packet Counter Interrupt Mask is enabled 0x1 TXVLANGPIM MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value. 24 1 read-write DISABLE MMC Transmit VLAN Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled 0x1 TXOSIZEGPIM MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. 25 1 read-write DISABLE MMC Transmit Oversize Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled 0x1 TXLPIUSCIM MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. 26 1 read-write DISABLE MMC Transmit LPI microsecond counter interrupt Mask is disabled 0 ENABLE MMC Transmit LPI microsecond counter interrupt Mask is enabled 0x1 TXLPITRCIM MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. 27 1 read-write DISABLE MMC Transmit LPI transition counter interrupt Mask is disabled 0 ENABLE MMC Transmit LPI transition counter interrupt Mask is enabled 0x1 MAC_TX_OCTET_COUNT_GOOD_BAD Tx Octet Count Good and Bad 0x714 32 read-only 0 0xFFFFFFFF TXOCTGB Tx Octet Count Good Bad This field indicates the number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad packets. 0 32 read-only MAC_TX_PACKET_COUNT_GOOD_BAD Tx Packet Count Good and Bad 0x718 32 read-only 0 0xFFFFFFFF TXPKTGB Tx Packet Count Good Bad This field indicates the number of good and bad packets transmitted, exclusive of retried packets. 0 32 read-only MAC_TX_BROADCAST_PACKETS_GOOD Tx Broadcast Packets Good 0x71C 32 read-only 0 0xFFFFFFFF TXBCASTG Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted. 0 32 read-only MAC_TX_MULTICAST_PACKETS_GOOD Tx Multicast Packets Good 0x720 32 read-only 0 0xFFFFFFFF TXMCASTG Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted. 0 32 read-only MAC_TX_64OCTETS_PACKETS_GOOD_BAD Tx Good and Bad 64-Byte Packets 0x724 32 read-only 0 0xFFFFFFFF TX64OCTGB Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets transmitted with length 64 bytes, exclusive of preamble and retried packets. 0 32 read-only MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD Tx Good and Bad 65 to 127-Byte Packets 0x728 32 read-only 0 0xFFFFFFFF TX65_127OCTGB Tx 65To127Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried packets. 0 32 read-only MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD Tx Good and Bad 128 to 255-Byte Packets 0x72C 32 read-only 0 0xFFFFFFFF TX128_255OCTGB Tx 128To255Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried packets. 0 32 read-only MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD Tx Good and Bad 256 to 511-Byte Packets 0x730 32 read-only 0 0xFFFFFFFF TX256_511OCTGB Tx 256To511Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried packets. 0 32 read-only MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD Tx Good and Bad 512 to 1023-Byte Packets 0x734 32 read-only 0 0xFFFFFFFF TX512_1023OCTGB Tx 512To1023Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of preamble and retried packets. 0 32 read-only MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD Tx Good and Bad 1024 to Max-Byte Packets 0x738 32 read-only 0 0xFFFFFFFF TX1024_MAXOCTGB Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes, exclusive of preamble and retried packets. 0 32 read-only MAC_TX_UNICAST_PACKETS_GOOD_BAD Good and Bad Unicast Packets Transmitted 0x73C 32 read-only 0 0xFFFFFFFF TXUCASTGB Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted. 0 32 read-only MAC_TX_MULTICAST_PACKETS_GOOD_BAD Good and Bad Multicast Packets Transmitted 0x740 32 read-only 0 0xFFFFFFFF TXMCASTGB Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted. 0 32 read-only MAC_TX_BROADCAST_PACKETS_GOOD_BAD Good and Bad Broadcast Packets Transmitted 0x744 32 read-only 0 0xFFFFFFFF TXBCASTGB Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted. 0 32 read-only MAC_TX_UNDERFLOW_ERROR_PACKETS Tx Packets Aborted By Underflow Error 0x748 32 read-only 0 0xFFFFFFFF TXUNDRFLW Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error. 0 32 read-only MAC_TX_SINGLE_COLLISION_GOOD_PACKETS Single Collision Good Packets Transmitted 0x74C 32 read-only 0 0xFFFFFFFF TXSNGLCOLG Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode. 0 32 read-only MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS Multiple Collision Good Packets Transmitted 0x750 32 read-only 0 0xFFFFFFFF TXMULTCOLG Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode. 0 32 read-only MAC_TX_DEFERRED_PACKETS Deferred Packets Transmitted 0x754 32 read-only 0 0xFFFFFFFF TXDEFRD Tx Deferred Packets This field indicates the number of successfully transmitted after a deferral in the half-duplex mode. 0 32 read-only MAC_TX_LATE_COLLISION_PACKETS Late Collision Packets Transmitted 0x758 32 read-only 0 0xFFFFFFFF TXLATECOL Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error. 0 32 read-only MAC_TX_EXCESSIVE_COLLISION_PACKETS Excessive Collision Packets Transmitted 0x75C 32 read-only 0 0xFFFFFFFF TXEXSCOL Tx Excessive Collision Packets This field indicates the number of packets aborted because of excessive (16) collision errors. 0 32 read-only MAC_TX_CARRIER_ERROR_PACKETS Carrier Error Packets Transmitted 0x760 32 read-only 0 0xFFFFFFFF TXCARR Tx Carrier Error Packets This field indicates the number of packets aborted because of carrier sense error (no carrier or loss of carrier). 0 32 read-only MAC_TX_OCTET_COUNT_GOOD Bytes Transmitted in Good Packets 0x764 32 read-only 0 0xFFFFFFFF TXOCTG Tx Octet Count Good This field indicates the number of bytes transmitted, exclusive of preamble, only in good packets. 0 32 read-only MAC_TX_PACKET_COUNT_GOOD Good Packets Transmitted 0x768 32 read-only 0 0xFFFFFFFF TXPKTG Tx Packet Count Good This field indicates the number of good packets transmitted. 0 32 read-only MAC_TX_EXCESSIVE_DEFERRAL_ERROR Packets Aborted By Excessive Deferral Error 0x76C 32 read-only 0 0xFFFFFFFF TXEXSDEF Tx Excessive Deferral Error This field indicates the number of packets aborted because of excessive deferral error (deferred for more than two max-sized packet times). 0 32 read-only MAC_TX_PAUSE_PACKETS Pause Packets Transmitted 0x770 32 read-only 0 0xFFFFFFFF TXPAUSE Tx Pause Packets This field indicates the number of good Pause packets transmitted. 0 32 read-only MAC_TX_VLAN_PACKETS_GOOD Good VLAN Packets Transmitted 0x774 32 read-only 0 0xFFFFFFFF TXVLANG Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted. 0 32 read-only MAC_TX_OSIZE_PACKETS_GOOD Good Oversize Packets Transmitted 0x778 32 read-only 0 0xFFFFFFFF TXOSIZG Tx OSize Packets Good This field indicates the number of packets transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the CONFIGURATION register). 0 32 read-only MAC_RX_PACKETS_COUNT_GOOD_BAD Good and Bad Packets Received 0x780 32 read-only 0 0xFFFFFFFF RXPKTGB Rx Packets Count Good Bad This field indicates the number of good and bad packets received. 0 32 read-only MAC_RX_OCTET_COUNT_GOOD_BAD Bytes in Good and Bad Packets Received 0x784 32 read-only 0 0xFFFFFFFF RXOCTGB Rx Octet Count Good Bad This field indicates the number of bytes received, exclusive of preamble, in good and bad packets. 0 32 read-only MAC_RX_OCTET_COUNT_GOOD Bytes in Good Packets Received 0x788 32 read-only 0 0xFFFFFFFF RXOCTG Rx Octet Count Good This field indicates the number of bytes received, exclusive of preamble, only in good packets. 0 32 read-only MAC_RX_BROADCAST_PACKETS_GOOD Good Broadcast Packets Received 0x78C 32 read-only 0 0xFFFFFFFF RXBCASTG Rx Broadcast Packets Good This field indicates the number of good broadcast packets received. 0 32 read-only MAC_RX_MULTICAST_PACKETS_GOOD Good Multicast Packets Received 0x790 32 read-only 0 0xFFFFFFFF RXMCASTG Rx Multicast Packets Good This field indicates the number of good multicast packets received. 0 32 read-only MAC_RX_CRC_ERROR_PACKETS CRC Error Packets Received 0x794 32 read-only 0 0xFFFFFFFF RXCRCERR Rx CRC Error Packets This field indicates the number of packets received with CRC error. 0 32 read-only MAC_RX_ALIGNMENT_ERROR_PACKETS Alignment Error Packets Received 0x798 32 read-only 0 0xFFFFFFFF RXALGNERR Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error. 0 32 read-only MAC_RX_RUNT_ERROR_PACKETS Runt Error Packets Received 0x79C 32 read-only 0 0xFFFFFFFF RXRUNTERR Rx Runt Error Packets This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error. 0 32 read-only MAC_RX_JABBER_ERROR_PACKETS Jabber Error Packets Received 0x7A0 32 read-only 0 0xFFFFFFFF RXJABERR Rx Jabber Error Packets This field indicates the number of giant packets received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. 0 32 read-only MAC_RX_UNDERSIZE_PACKETS_GOOD Good Undersize Packets Received 0x7A4 32 read-only 0 0xFFFFFFFF RXUNDERSZG Rx Undersize Packets Good This field indicates the number of packets received with length less than 64 bytes, without any errors. 0 32 read-only MAC_RX_OVERSIZE_PACKETS_GOOD Good Oversize Packets Received 0x7A8 32 read-only 0 0xFFFFFFFF RXOVERSZG Rx Oversize Packets Good This field indicates the number of packets received without errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION register). 0 32 read-only MAC_RX_64OCTETS_PACKETS_GOOD_BAD Good and Bad 64-Byte Packets Received 0x7AC 32 read-only 0 0xFFFFFFFF RX64OCTGB Rx 64 Octets Packets Good Bad This field indicates the number of good and bad packets received with length 64 bytes, exclusive of the preamble. 0 32 read-only MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD Good and Bad 64-to-127 Byte Packets Received 0x7B0 32 read-only 0 0xFFFFFFFF RX65_127OCTGB Rx 65-127 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes, exclusive of the preamble. 0 32 read-only MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD Good and Bad 128-to-255 Byte Packets Received 0x7B4 32 read-only 0 0xFFFFFFFF RX128_255OCTGB Rx 128-255 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes, exclusive of the preamble. 0 32 read-only MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD Good and Bad 256-to-511 Byte Packets Received 0x7B8 32 read-only 0 0xFFFFFFFF RX256_511OCTGB Rx 256-511 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes, exclusive of the preamble. 0 32 read-only MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD Good and Bad 512-to-1023 Byte Packets Received 0x7BC 32 read-only 0 0xFFFFFFFF RX512_1023OCTGB RX 512-1023 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes, exclusive of the preamble. 0 32 read-only MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD Good and Bad 1024-to-Max Byte Packets Received 0x7C0 32 read-only 0 0xFFFFFFFF RX1024_MAXOCTGB Rx 1024-Max Octets Good Bad This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes, exclusive of the preamble. 0 32 read-only MAC_RX_UNICAST_PACKETS_GOOD Good Unicast Packets Received 0x7C4 32 read-only 0 0xFFFFFFFF RXUCASTG Rx Unicast Packets Good This field indicates the number of good unicast packets received. 0 32 read-only MAC_RX_LENGTH_ERROR_PACKETS Length Error Packets Received 0x7C8 32 read-only 0 0xFFFFFFFF RXLENERR Rx Length Error Packets This field indicates the number of packets received with length error (Length Type field not equal to packet size), for all packets with valid length field. 0 32 read-only MAC_RX_OUT_OF_RANGE_TYPE_PACKETS Out-of-range Type Packets Received 0x7CC 32 read-only 0 0xFFFFFFFF RXOUTOFRNG Rx Out of Range Type Packet This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1,500 but less than 1,536). 0 32 read-only MAC_RX_PAUSE_PACKETS Pause Packets Received 0x7D0 32 read-only 0 0xFFFFFFFF RXPAUSEPKT Rx Pause Packets This field indicates the number of good and valid Pause packets received. 0 32 read-only MAC_RX_FIFO_OVERFLOW_PACKETS Missed Packets Due to FIFO Overflow 0x7D4 32 read-only 0 0xFFFFFFFF RXFIFOOVFL Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow. 0 32 read-only MAC_RX_VLAN_PACKETS_GOOD_BAD Good and Bad VLAN Packets Received 0x7D8 32 read-only 0 0xFFFFFFFF RXVLANPKTGB Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received. 0 32 read-only MAC_RX_WATCHDOG_ERROR_PACKETS Watchdog Error Packets Received 0x7DC 32 read-only 0 0xFFFFFFFF RXWDGERR Rx Watchdog Error Packets This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when JE and WD bits are reset in MAC_CONFIGURATION register), 10,240 bytes (when JE bit is set and WD bit is reset in MAC_CONFIGURATION register), 16,384 bytes (when WD bit is set in MAC_CONFIGURATION register) or the value programmed in the MAC_WATCHDOG_TIMEOUT register). 0 32 read-only MAC_RX_RECEIVE_ERROR_PACKETS Receive Error Packets Received 0x7E0 32 read-only 0 0xFFFFFFFF RXRCVERR Rx Receive Error Packets This field indicates the number of packets received with Receive error or Packet Extension error on the GMII or MII interface. 0 32 read-only MAC_RX_CONTROL_PACKETS_GOOD Good Control Packets Received 0x7E4 32 read-only 0 0xFFFFFFFF RXCTRLG Rx Control Packets Good This field indicates the number of good control packets received. 0 32 read-only MAC_TX_LPI_USEC_CNTR Microseconds Tx LPI Asserted 0x7EC 32 read-only 0 0xFFFFFFFF TXLPIUSC Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted. 0 32 read-only MAC_TX_LPI_TRAN_CNTR Number of Times Tx LPI Asserted 0x7F0 32 read-only 0 0xFFFFFFFF TXLPITRC Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred. 0 32 read-only MAC_RX_LPI_USEC_CNTR Microseconds Rx LPI Sampled 0x7F4 32 read-only 0 0xFFFFFFFF RXLPIUSC Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted. 0 32 read-only MAC_RX_LPI_TRAN_CNTR Number of Times Rx LPI Entered 0x7F8 32 read-only 0 0xFFFFFFFF RXLPITRC Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred. 0 32 read-only MAC_MMC_IPC_RX_INTERRUPT_MASK MMC IPC Receive Interrupt Mask 0x800 32 read-write 0 0xFFFFFFFF RXIPV4GPIM MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value. 0 1 read-write DISABLE MMC Receive IPV4 Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV4 Good Packet Counter Interrupt Mask is enabled 0x1 RXIPV4HERPIM MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value. 1 1 read-write DISABLE MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is enabled 0x1 RXIPV4NOPAYPIM MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value. 2 1 read-write DISABLE MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is enabled 0x1 RXIPV4FRAGPIM MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value. 3 1 read-write DISABLE MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is enabled 0x1 RXIPV4UDSBLPIM MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value. 4 1 read-write DISABLE MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is enabled 0x1 RXIPV6GPIM MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value. 5 1 read-write DISABLE MMC Receive IPV6 Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV6 Good Packet Counter Interrupt Mask is enabled 0x1 RXIPV6HERPIM MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value. 6 1 read-write DISABLE MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is enabled 0x1 RXIPV6NOPAYPIM MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value. 7 1 read-write DISABLE MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is enabled 0x1 RXUDPGPIM MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value. 8 1 read-write DISABLE MMC Receive UDP Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive UDP Good Packet Counter Interrupt Mask is enabled 0x1 RXUDPERPIM MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value. 9 1 read-write DISABLE MMC Receive UDP Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive UDP Error Packet Counter Interrupt Mask is enabled 0x1 RXTCPGPIM MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value. 10 1 read-write DISABLE MMC Receive TCP Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive TCP Good Packet Counter Interrupt Mask is enabled 0x1 RXTCPERPIM MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value. 11 1 read-write DISABLE MMC Receive TCP Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive TCP Error Packet Counter Interrupt Mask is enabled 0x1 RXICMPGPIM MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value. 12 1 read-write DISABLE MMC Receive ICMP Good Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive ICMP Good Packet Counter Interrupt Mask is enabled 0x1 RXICMPERPIM MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value. 13 1 read-write DISABLE MMC Receive ICMP Error Packet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive ICMP Error Packet Counter Interrupt Mask is enabled 0x1 RXIPV4GOIM MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. 16 1 read-write DISABLE MMC Receive IPV4 Good Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV4 Good Octet Counter Interrupt Mask is enabled 0x1 RXIPV4HEROIM MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. 17 1 read-write DISABLE MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is enabled 0x1 RXIPV4NOPAYOIM MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. 18 1 read-write DISABLE MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is enabled 0x1 RXIPV4FRAGOIM MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. 19 1 read-write DISABLE MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is enabled 0x1 RXIPV4UDSBLOIM MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. 20 1 read-write DISABLE MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is enabled 0x1 RXIPV6GOIM MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. 21 1 read-write DISABLE MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled 0x1 RXIPV6HEROIM MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. 22 1 read-write DISABLE MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled 0x1 RXIPV6NOPAYOIM MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. 23 1 read-write DISABLE MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is enabled 0x1 RXUDPGOIM MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. 24 1 read-write DISABLE MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is enabled 0x1 RXUDPEROIM MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. 25 1 read-write DISABLE MMC Receive UDP Good Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive UDP Good Octet Counter Interrupt Mask is enabled 0x1 RXTCPGOIM MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. 26 1 read-write DISABLE MMC Receive TCP Good Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive TCP Good Octet Counter Interrupt Mask is enabled 0x1 RXTCPEROIM MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. 27 1 read-write DISABLE MMC Receive TCP Error Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive TCP Error Octet Counter Interrupt Mask is enabled 0x1 RXICMPGOIM MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. 28 1 read-write DISABLE MMC Receive ICMP Good Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive ICMP Good Octet Counter Interrupt Mask is enabled 0x1 RXICMPEROIM MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. 29 1 read-write DISABLE MMC Receive ICMP Error Octet Counter Interrupt Mask is disabled 0 ENABLE MMC Receive ICMP Error Octet Counter Interrupt Mask is enabled 0x1 MAC_MMC_IPC_RX_INTERRUPT MMC IPC Receive Interrupt 0x808 32 read-only 0 0xFFFFFFFF RXIPV4GPIS MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value. 0 1 read-only INACTIVE MMC Receive IPV4 Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV4 Good Packet Counter Interrupt Status detected 0x1 RXIPV4HERPIS MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value. 1 1 read-only INACTIVE MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected 0x1 RXIPV4NOPAYPIS MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value. 2 1 read-only INACTIVE MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected 0x1 RXIPV4FRAGPIS MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value. 3 1 read-only INACTIVE MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected 0x1 RXIPV4UDSBLPIS MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value. 4 1 read-only INACTIVE MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected 0x1 RXIPV6GPIS MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value. 5 1 read-only INACTIVE MMC Receive IPV6 Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV6 Good Packet Counter Interrupt Status detected 0x1 RXIPV6HERPIS MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value. 6 1 read-only INACTIVE MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected 0x1 RXIPV6NOPAYPIS MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value. 7 1 read-only INACTIVE MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected 0x1 RXUDPGPIS MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value. 8 1 read-only INACTIVE MMC Receive UDP Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive UDP Good Packet Counter Interrupt Status detected 0x1 RXUDPERPIS MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value. 9 1 read-only INACTIVE MMC Receive UDP Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive UDP Error Packet Counter Interrupt Status detected 0x1 RXTCPGPIS MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value. 10 1 read-only INACTIVE MMC Receive TCP Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive TCP Good Packet Counter Interrupt Status detected 0x1 RXTCPERPIS MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value. 11 1 read-only INACTIVE MMC Receive TCP Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive TCP Error Packet Counter Interrupt Status detected 0x1 RXICMPGPIS MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value. 12 1 read-only INACTIVE MMC Receive ICMP Good Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive ICMP Good Packet Counter Interrupt Status detected 0x1 RXICMPERPIS MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value. 13 1 read-only INACTIVE MMC Receive ICMP Error Packet Counter Interrupt Status not detected 0 ACTIVE MMC Receive ICMP Error Packet Counter Interrupt Status detected 0x1 RXIPV4GOIS MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. 16 1 read-only INACTIVE MMC Receive IPV4 Good Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV4 Good Octet Counter Interrupt Status detected 0x1 RXIPV4HEROIS MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. 17 1 read-only INACTIVE MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected 0x1 RXIPV4NOPAYOIS MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. 18 1 read-only INACTIVE MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected 0x1 RXIPV4FRAGOIS MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. 19 1 read-only INACTIVE MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected 0x1 RXIPV4UDSBLOIS MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. 20 1 read-only INACTIVE MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected 0x1 RXIPV6GOIS MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. 21 1 read-only INACTIVE MMC Receive IPV6 Good Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV6 Good Octet Counter Interrupt Status detected 0x1 RXIPV6HEROIS MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. 22 1 read-only INACTIVE MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected 0x1 RXIPV6NOPAYOIS MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. 23 1 read-only INACTIVE MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected 0x1 RXUDPGOIS MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. 24 1 read-only INACTIVE MMC Receive UDP Good Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive UDP Good Octet Counter Interrupt Status detected 0x1 RXUDPEROIS MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. 25 1 read-only INACTIVE MMC Receive UDP Error Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive UDP Error Octet Counter Interrupt Status detected 0x1 RXTCPGOIS MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. 26 1 read-only INACTIVE MMC Receive TCP Good Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive TCP Good Octet Counter Interrupt Status detected 0x1 RXTCPEROIS MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. 27 1 read-only INACTIVE MMC Receive TCP Error Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive TCP Error Octet Counter Interrupt Status detected 0x1 RXICMPGOIS MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. 28 1 read-only INACTIVE MMC Receive ICMP Good Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive ICMP Good Octet Counter Interrupt Status detected 0x1 RXICMPEROIS MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. 29 1 read-only INACTIVE MMC Receive ICMP Error Octet Counter Interrupt Status not detected 0 ACTIVE MMC Receive ICMP Error Octet Counter Interrupt Status detected 0x1 MAC_RXIPV4_GOOD_PACKETS Good IPv4 Datagrams Received 0x810 32 read-only 0 0xFFFFFFFF RXIPV4GDPKT RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload. 0 32 read-only MAC_RXIPV4_HEADER_ERROR_PACKETS IPv4 Datagrams Received with Header Errors 0x814 32 read-only 0 0xFFFFFFFF RXIPV4HDRERRPKT RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors. 0 32 read-only MAC_RXIPV4_NO_PAYLOAD_PACKETS IPv4 Datagrams Received with No Payload 0x818 32 read-only 0 0xFFFFFFFF RXIPV4NOPAYPKT RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets received that did not have a TCP, UDP, or ICMP payload. 0 32 read-only MAC_RXIPV4_FRAGMENTED_PACKETS IPv4 Datagrams Received with Fragmentation 0x81C 32 read-only 0 0xFFFFFFFF RXIPV4FRAGPKT RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation. 0 32 read-only MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS IPv4 Datagrams Received with UDP Checksum Disabled 0x820 32 read-only 0 0xFFFFFFFF RXIPV4UDSBLPKT RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good IPv4 datagrams received that had a UDP payload with checksum disabled. 0 32 read-only MAC_RXIPV6_GOOD_PACKETS Good IPv6 Datagrams Received 0x824 32 read-only 0 0xFFFFFFFF RXIPV6GDPKT RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP, UDP, or ICMP payload. 0 32 read-only MAC_RXIPV6_HEADER_ERROR_PACKETS IPv6 Datagrams Received with Header Errors 0x828 32 read-only 0 0xFFFFFFFF RXIPV6HDRERRPKT RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams received with header (length or version mismatch) errors. 0 32 read-only MAC_RXIPV6_NO_PAYLOAD_PACKETS IPv6 Datagrams Received with No Payload 0x82C 32 read-only 0 0xFFFFFFFF RXIPV6NOPAYPKT RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets received that did not have a TCP, UDP, or ICMP payload. 0 32 read-only MAC_RXUDP_GOOD_PACKETS IPv6 Datagrams Received with Good UDP 0x830 32 read-only 0 0xFFFFFFFF RXUDPGDPKT RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload. 0 32 read-only MAC_RXUDP_ERROR_PACKETS IPv6 Datagrams Received with UDP Checksum Error 0x834 32 read-only 0 0xFFFFFFFF RXUDPERRPKT RxUDP Error Packets This field indicates the number of good IP datagrams received whose UDP payload has a checksum error. 0 32 read-only MAC_RXTCP_GOOD_PACKETS IPv6 Datagrams Received with Good TCP Payload 0x838 32 read-only 0 0xFFFFFFFF RXTCPGDPKT RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload. 0 32 read-only MAC_RXTCP_ERROR_PACKETS IPv6 Datagrams Received with TCP Checksum Error 0x83C 32 read-only 0 0xFFFFFFFF RXTCPERRPKT RxTCP Error Packets This field indicates the number of good IP datagrams received whose TCP payload has a checksum error. 0 32 read-only MAC_RXICMP_GOOD_PACKETS IPv6 Datagrams Received with Good ICMP Payload 0x840 32 read-only 0 0xFFFFFFFF RXICMPGDPKT RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload. 0 32 read-only MAC_RXICMP_ERROR_PACKETS IPv6 Datagrams Received with ICMP Checksum Error 0x844 32 read-only 0 0xFFFFFFFF RXICMPERRPKT RxICMP Error Packets This field indicates the number of good IP datagrams received whose ICMP payload has a checksum error. 0 32 read-only MAC_RXIPV4_GOOD_OCTETS Good Bytes Received in IPv4 Datagrams 0x850 32 read-only 0 0xFFFFFFFF RXIPV4GDOCT RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. 0 32 read-only MAC_RXIPV4_HEADER_ERROR_OCTETS Bytes Received in IPv4 Datagrams with Header Errors 0x854 32 read-only 0 0xFFFFFFFF RXIPV4HDRERROCT RxIPv4 Header Error Octets This field indicates the number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). 0 32 read-only MAC_RXIPV4_NO_PAYLOAD_OCTETS Bytes Received in IPv4 Datagrams with No Payload 0x858 32 read-only 0 0xFFFFFFFF RXIPV4NOPAYOCT RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. 0 32 read-only MAC_RXIPV4_FRAGMENTED_OCTETS Bytes Received in Fragmented IPv4 Datagrams 0x85C 32 read-only 0 0xFFFFFFFF RXIPV4FRAGOCT RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams. 0 32 read-only MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS Bytes Received with UDP Checksum Disabled 0x860 32 read-only 0 0xFFFFFFFF RXIPV4UDSBLOCT RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled. 0 32 read-only MAC_RXIPV6_GOOD_OCTETS Bytes Received in Good IPv6 Datagrams 0x864 32 read-only 0 0xFFFFFFFF RXIPV6GDOCT RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP, UDP, or ICMP data. 0 32 read-only MAC_RXIPV6_HEADER_ERROR_OCTETS Bytes Received in IPv6 Datagrams with Data Errors 0x868 32 read-only 0 0xFFFFFFFF RXIPV6HDRERROCT RxIPv6 Header Error Octets This field indicates the number of bytes received in IPv6 datagrams with header errors (length, version mismatch). 0 32 read-only MAC_RXIPV6_NO_PAYLOAD_OCTETS Bytes Received in IPv6 Datagrams with No Payload 0x86C 32 read-only 0 0xFFFFFFFF RXIPV6NOPAYOCT RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. 0 32 read-only MAC_RXUDP_GOOD_OCTETS Bytes Received in Good UDP Segment 0x870 32 read-only 0 0xFFFFFFFF RXUDPGDOCT RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment. 0 32 read-only MAC_RXUDP_ERROR_OCTETS Bytes Received in UDP Segment with Checksum Errors 0x874 32 read-only 0 0xFFFFFFFF RXUDPERROCT RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors. 0 32 read-only MAC_RXTCP_GOOD_OCTETS Bytes Received in Good TCP Segment 0x878 32 read-only 0 0xFFFFFFFF RXTCPGDOCT RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment. 0 32 read-only MAC_RXTCP_ERROR_OCTETS Bytes Received in TCP Segment with Checksum Errors 0x87C 32 read-only 0 0xFFFFFFFF RXTCPERROCT RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors. 0 32 read-only MAC_RXICMP_GOOD_OCTETS Bytes Received in Good ICMP Segment 0x880 32 read-only 0 0xFFFFFFFF RXICMPGDOCT RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment. 0 32 read-only MAC_RXICMP_ERROR_OCTETS Bytes Received in ICMP Segment with Checksum Errors 0x884 32 read-only 0 0xFFFFFFFF RXICMPERROCT RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors. 0 32 read-only MAC_MMC_FPE_TX_INTERRUPT MMC FPE Transmit Interrupt 0x8A0 32 read-only 0 0xFFFFFFFF FCIS MMC Tx FPE Fragment Counter Interrupt status This bit is set when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. 0 1 read-only INACTIVE MMC Tx FPE Fragment Counter Interrupt status not detected 0 ACTIVE MMC Tx FPE Fragment Counter Interrupt status detected 0x1 HRCIS MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value. 1 1 read-only INACTIVE MMC Tx Hold Request Counter Interrupt Status not detected 0 ACTIVE MMC Tx Hold Request Counter Interrupt Status detected 0x1 MAC_MMC_FPE_TX_INTERRUPT_MASK MMC FPE Transmit Mask Interrupt 0x8A4 32 read-write 0 0xFFFFFFFF FCIM MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. 0 1 read-write DISABLE MMC Transmit Fragment Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Fragment Counter Interrupt Mask is enabled 0x1 HRCIM MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value. 1 1 read-write DISABLE MMC Transmit Hold Request Counter Interrupt Mask is disabled 0 ENABLE MMC Transmit Hold Request Counter Interrupt Mask is enabled 0x1 MAC_MMC_TX_FPE_FRAGMENT_CNTR MMC FPE Transmitted Fragment Counter 0x8A8 32 read-only 0 0xFFFFFFFF TXFFC Tx FPE Fragment counter This field indicates the number of additional mPackets that has been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled configuration. 0 32 read-only MAC_MMC_TX_HOLD_REQ_CNTR MMC FPE Transmitted Hold Request Counter 0x8AC 32 read-only 0 0xFFFFFFFF TXHRC Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC. 0 32 read-only MAC_MMC_FPE_RX_INTERRUPT MMC FPE Receive Interrupt 0x8C0 32 read-only 0 0xFFFFFFFF PAECIS MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value. 0 1 read-only INACTIVE MMC Rx Packet Assembly Error Counter Interrupt Status not detected 0 ACTIVE MMC Rx Packet Assembly Error Counter Interrupt Status detected 0x1 PSECIS MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value. 1 1 read-only INACTIVE MMC Rx Packet SMD Error Counter Interrupt Status not detected 0 ACTIVE MMC Rx Packet SMD Error Counter Interrupt Status detected 0x1 PAOCIS MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value. 2 1 read-only INACTIVE MMC Rx Packet Assembly OK Counter Interrupt Status not detected 0 ACTIVE MMC Rx Packet Assembly OK Counter Interrupt Status detected 0x1 FCIS MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. 3 1 read-only INACTIVE MMC Rx FPE Fragment Counter Interrupt Status not detected 0 ACTIVE MMC Rx FPE Fragment Counter Interrupt Status detected 0x1 MAC_MMC_FPE_RX_INTERRUPT_MASK MMC FPE Receive Interrupt Mask 0x8C4 32 read-write 0 0xFFFFFFFF PAECIM MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value. 0 1 read-write DISABLE MMC Rx Packet Assembly Error Counter Interrupt Mask is disabled 0 ENABLE MMC Rx Packet Assembly Error Counter Interrupt Mask is enabled 0x1 PSECIM MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value. 1 1 read-write DISABLE MMC Rx Packet SMD Error Counter Interrupt Mask is disabled 0 ENABLE MMC Rx Packet SMD Error Counter Interrupt Mask is enabled 0x1 PAOCIM MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value. 2 1 read-write DISABLE MMC Rx Packet Assembly OK Counter Interrupt Mask is disabled 0 ENABLE MMC Rx Packet Assembly OK Counter Interrupt Mask is enabled 0x1 FCIM MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. 3 1 read-write DISABLE MMC Rx FPE Fragment Counter Interrupt Mask is disabled 0 ENABLE MMC Rx FPE Fragment Counter Interrupt Mask is enabled 0x1 MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR MMC Receive Packet Reassembly Error Counter 0x8C8 32 read-only 0 0xFFFFFFFF PAEC Rx Packet Assembly Error Counter This field indicates the number of MAC frames with reassembly errors on the Receiver, due to mismatch in the Fragment Count value. 0 32 read-only MAC_MMC_RX_PACKET_SMD_ERR_CNTR MMC Receive Packet SMD Error Counter 0x8CC 32 read-only 0 0xFFFFFFFF PSEC Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame. 0 32 read-only MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR MMC Receive Packet Successful Reassembly Counter 0x8D0 32 read-only 0 0xFFFFFFFF PAOC Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were successfully reassembled and delivered to MAC. 0 32 read-only MAC_MMC_RX_FPE_FRAGMENT_CNTR MMC FPE Received Fragment Counter 0x8D4 32 read-only 0 0xFFFFFFFF FFC Rx FPE Fragment Counter This field indicates the number of additional mPackets received due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration. 0 32 read-only MAC_L3_L4_CONTROL0 Layer 3 and Layer 4 Control of Filter 0 0x900 32 read-write 0 0xFFFFFFFF L3PEN0 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. 0 1 read-write DISABLE Layer 3 Protocol is disabled 0 ENABLE Layer 3 Protocol is enabled 0x1 L3SAM0 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. 2 1 read-write DISABLE Layer 3 IP SA Match is disabled 0 ENABLE Layer 3 IP SA Match is enabled 0x1 L3SAIM0 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. 3 1 read-write DISABLE Layer 3 IP SA Inverse Match is disabled 0 ENABLE Layer 3 IP SA Inverse Match is enabled 0x1 L3DAM0 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. 4 1 read-write DISABLE Layer 3 IP DA Match is disabled 0 ENABLE Layer 3 IP DA Match is enabled 0x1 L3DAIM0 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. 5 1 read-write DISABLE Layer 3 IP DA Inverse Match is disabled 0 ENABLE Layer 3 IP DA Inverse Match is enabled 0x1 L3HSBM0 Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. 6 5 read-write L3HDBM0 Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. 11 5 read-write L4PEN0 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. 16 1 read-write DISABLE Layer 4 Protocol is disabled 0 ENABLE Layer 4 Protocol is enabled 0x1 L4SPM0 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. 18 1 read-write DISABLE Layer 4 Source Port Match is disabled 0 ENABLE Layer 4 Source Port Match is enabled 0x1 L4SPIM0 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. 19 1 read-write DISABLE Layer 4 Source Port Inverse Match is disabled 0 ENABLE Layer 4 Source Port Inverse Match is enabled 0x1 L4DPM0 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. 20 1 read-write DISABLE Layer 4 Destination Port Match is disabled 0 ENABLE Layer 4 Destination Port Match is enabled 0x1 L4DPIM0 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. 21 1 read-write DISABLE Layer 4 Destination Port Inverse Match is disabled 0 ENABLE Layer 4 Destination Port Inverse Match is enabled 0x1 DMCHN0 DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. 24 3 read-write DMCHEN0 DMA Channel Select Enable When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. 28 1 read-write DISABLE DMA Channel Select is disabled 0 ENABLE DMA Channel Select is enabled 0x1 MAC_LAYER4_ADDRESS0 Layer 4 Address 0 0x904 32 read-write 0 0xFFFFFFFF L4SP0 Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP0 Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MAC_LAYER3_ADDR0_REG0 Layer 3 Address 0 Register 0 0x910 32 read-write 0 0xFFFFFFFF L3A00 Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR1_REG0 Layer 3 Address 1 Register 0 0x914 32 read-write 0 0xFFFFFFFF L3A10 Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR2_REG0 Layer 3 Address 2 Register 0 0x918 32 read-write 0 0xFFFFFFFF L3A20 Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR3_REG0 Layer 3 Address 3 Register 0 0x91C 32 read-write 0 0xFFFFFFFF L3A30 Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_L3_L4_CONTROL1 Layer 3 and Layer 4 Control of Filter 1 0x930 32 read-write 0 0xFFFFFFFF L3PEN1 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. 0 1 read-write DISABLE Layer 3 Protocol is disabled 0 ENABLE Layer 3 Protocol is enabled 0x1 L3SAM1 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. 2 1 read-write DISABLE Layer 3 IP SA Match is disabled 0 ENABLE Layer 3 IP SA Match is enabled 0x1 L3SAIM1 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. 3 1 read-write DISABLE Layer 3 IP SA Inverse Match is disabled 0 ENABLE Layer 3 IP SA Inverse Match is enabled 0x1 L3DAM1 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. 4 1 read-write DISABLE Layer 3 IP DA Match is disabled 0 ENABLE Layer 3 IP DA Match is enabled 0x1 L3DAIM1 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. 5 1 read-write DISABLE Layer 3 IP DA Inverse Match is disabled 0 ENABLE Layer 3 IP DA Inverse Match is enabled 0x1 L3HSBM1 Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. 6 5 read-write L3HDBM1 Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. 11 5 read-write L4PEN1 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. 16 1 read-write DISABLE Layer 4 Protocol is disabled 0 ENABLE Layer 4 Protocol is enabled 0x1 L4SPM1 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. 18 1 read-write DISABLE Layer 4 Source Port Match is disabled 0 ENABLE Layer 4 Source Port Match is enabled 0x1 L4SPIM1 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. 19 1 read-write DISABLE Layer 4 Source Port Inverse Match is disabled 0 ENABLE Layer 4 Source Port Inverse Match is enabled 0x1 L4DPM1 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. 20 1 read-write DISABLE Layer 4 Destination Port Match is disabled 0 ENABLE Layer 4 Destination Port Match is enabled 0x1 L4DPIM1 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. 21 1 read-write DISABLE Layer 4 Destination Port Inverse Match is disabled 0 ENABLE Layer 4 Destination Port Inverse Match is enabled 0x1 DMCHN1 DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. 24 3 read-write DMCHEN1 DMA Channel Select Enable When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. 28 1 read-write DISABLE DMA Channel Select is disabled 0 ENABLE DMA Channel Select is enabled 0x1 MAC_LAYER4_ADDRESS1 Layer 4 Address 0 0x934 32 read-write 0 0xFFFFFFFF L4SP1 Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP1 Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MAC_LAYER3_ADDR0_REG1 Layer 3 Address 0 Register 1 0x940 32 read-write 0 0xFFFFFFFF L3A01 Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR1_REG1 Layer 3 Address 1 Register 1 0x944 32 read-write 0 0xFFFFFFFF L3A11 Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR2_REG1 Layer 3 Address 2 Register 1 0x948 32 read-write 0 0xFFFFFFFF L3A21 Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR3_REG1 Layer 3 Address 3 Register 1 0x94C 32 read-write 0 0xFFFFFFFF L3A31 Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_L3_L4_CONTROL2 Layer 3 and Layer 4 Control of Filter 2 0x960 32 read-write 0 0xFFFFFFFF L3PEN2 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. 0 1 read-write DISABLE Layer 3 Protocol is disabled 0 ENABLE Layer 3 Protocol is enabled 0x1 L3SAM2 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. 2 1 read-write DISABLE Layer 3 IP SA Match is disabled 0 ENABLE Layer 3 IP SA Match is enabled 0x1 L3SAIM2 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. 3 1 read-write DISABLE Layer 3 IP SA Inverse Match is disabled 0 ENABLE Layer 3 IP SA Inverse Match is enabled 0x1 L3DAM2 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. 4 1 read-write DISABLE Layer 3 IP DA Match is disabled 0 ENABLE Layer 3 IP DA Match is enabled 0x1 L3DAIM2 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. 5 1 read-write DISABLE Layer 3 IP DA Inverse Match is disabled 0 ENABLE Layer 3 IP DA Inverse Match is enabled 0x1 L3HSBM2 Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. 6 5 read-write L3HDBM2 Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. 11 5 read-write L4PEN2 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. 16 1 read-write DISABLE Layer 4 Protocol is disabled 0 ENABLE Layer 4 Protocol is enabled 0x1 L4SPM2 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. 18 1 read-write DISABLE Layer 4 Source Port Match is disabled 0 ENABLE Layer 4 Source Port Match is enabled 0x1 L4SPIM2 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. 19 1 read-write DISABLE Layer 4 Source Port Inverse Match is disabled 0 ENABLE Layer 4 Source Port Inverse Match is enabled 0x1 L4DPM2 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. 20 1 read-write DISABLE Layer 4 Destination Port Match is disabled 0 ENABLE Layer 4 Destination Port Match is enabled 0x1 L4DPIM2 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. 21 1 read-write DISABLE Layer 4 Destination Port Inverse Match is disabled 0 ENABLE Layer 4 Destination Port Inverse Match is enabled 0x1 DMCHN2 DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. 24 3 read-write DMCHEN2 DMA Channel Select Enable When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. 28 1 read-write DISABLE DMA Channel Select is disabled 0 ENABLE DMA Channel Select is enabled 0x1 MAC_LAYER4_ADDRESS2 Layer 4 Address 2 0x964 32 read-write 0 0xFFFFFFFF L4SP2 Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP2 Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MAC_LAYER3_ADDR0_REG2 Layer 3 Address 0 Register 2 0x970 32 read-write 0 0xFFFFFFFF L3A02 Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR1_REG2 Layer 3 Address 0 Register 2 0x974 32 read-write 0 0xFFFFFFFF L3A12 Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR2_REG2 Layer 3 Address 2 Register 2 0x978 32 read-write 0 0xFFFFFFFF L3A22 Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR3_REG2 Layer 3 Address 3 Register 2 0x97C 32 read-write 0 0xFFFFFFFF L3A32 Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_L3_L4_CONTROL3 Layer 3 and Layer 4 Control of Filter 3 0x990 32 read-write 0 0xFFFFFFFF L3PEN3 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. 0 1 read-write DISABLE Layer 3 Protocol is disabled 0 ENABLE Layer 3 Protocol is enabled 0x1 L3SAM3 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. 2 1 read-write DISABLE Layer 3 IP SA Match is disabled 0 ENABLE Layer 3 IP SA Match is enabled 0x1 L3SAIM3 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. 3 1 read-write DISABLE Layer 3 IP SA Inverse Match is disabled 0 ENABLE Layer 3 IP SA Inverse Match is enabled 0x1 L3DAM3 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. 4 1 read-write DISABLE Layer 3 IP DA Match is disabled 0 ENABLE Layer 3 IP DA Match is enabled 0x1 L3DAIM3 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. 5 1 read-write DISABLE Layer 3 IP DA Inverse Match is disabled 0 ENABLE Layer 3 IP DA Inverse Match is enabled 0x1 L3HSBM3 Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. 6 5 read-write L3HDBM3 Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. 11 5 read-write L4PEN3 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. 16 1 read-write DISABLE Layer 4 Protocol is disabled 0 ENABLE Layer 4 Protocol is enabled 0x1 L4SPM3 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. 18 1 read-write DISABLE Layer 4 Source Port Match is disabled 0 ENABLE Layer 4 Source Port Match is enabled 0x1 L4SPIM3 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. 19 1 read-write DISABLE Layer 4 Source Port Inverse Match is disabled 0 ENABLE Layer 4 Source Port Inverse Match is enabled 0x1 L4DPM3 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. 20 1 read-write DISABLE Layer 4 Destination Port Match is disabled 0 ENABLE Layer 4 Destination Port Match is enabled 0x1 L4DPIM3 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. 21 1 read-write DISABLE Layer 4 Destination Port Inverse Match is disabled 0 ENABLE Layer 4 Destination Port Inverse Match is enabled 0x1 DMCHN3 DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. 24 3 read-write DMCHEN3 DMA Channel Select Enable When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. 28 1 read-write DISABLE DMA Channel Select is disabled 0 ENABLE DMA Channel Select is enabled 0x1 MAC_LAYER4_ADDRESS3 Layer 4 Address 3 0x994 32 read-write 0 0xFFFFFFFF L4SP3 Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP3 Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MAC_LAYER3_ADDR0_REG3 Layer 3 Address 0 Register 3 0x9A0 32 read-write 0 0xFFFFFFFF L3A03 Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR1_REG3 Layer 3 Address 1 Register 3 0x9A4 32 read-write 0 0xFFFFFFFF L3A13 Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR2_REG3 Layer 3 Address 2 Register 3 0x9A8 32 read-write 0 0xFFFFFFFF L3A23 Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR3_REG3 Layer 3 Address 3 Register 3 0x9AC 32 read-write 0 0xFFFFFFFF L3A33 Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_L3_L4_CONTROL4 Layer 3 and Layer 4 Control of Filter 4 0x9C0 32 read-write 0 0xFFFFFFFF L3PEN4 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. 0 1 read-write DISABLE Layer 3 Protocol is disabled 0 ENABLE Layer 3 Protocol is enabled 0x1 L3SAM4 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. 2 1 read-write DISABLE Layer 3 IP SA Match is disabled 0 ENABLE Layer 3 IP SA Match is enabled 0x1 L3SAIM4 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. 3 1 read-write DISABLE Layer 3 IP SA Inverse Match is disabled 0 ENABLE Layer 3 IP SA Inverse Match is enabled 0x1 L3DAM4 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. 4 1 read-write DISABLE Layer 3 IP DA Match is disabled 0 ENABLE Layer 3 IP DA Match is enabled 0x1 L3DAIM4 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. 5 1 read-write DISABLE Layer 3 IP DA Inverse Match is disabled 0 ENABLE Layer 3 IP DA Inverse Match is enabled 0x1 L3HSBM4 Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. 6 5 read-write L3HDBM4 Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. 11 5 read-write L4PEN4 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. 16 1 read-write DISABLE Layer 4 Protocol is disabled 0 ENABLE Layer 4 Protocol is enabled 0x1 L4SPM4 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. 18 1 read-write DISABLE Layer 4 Source Port Match is disabled 0 ENABLE Layer 4 Source Port Match is enabled 0x1 L4SPIM4 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. 19 1 read-write DISABLE Layer 4 Source Port Inverse Match is disabled 0 ENABLE Layer 4 Source Port Inverse Match is enabled 0x1 L4DPM4 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. 20 1 read-write DISABLE Layer 4 Destination Port Match is disabled 0 ENABLE Layer 4 Destination Port Match is enabled 0x1 L4DPIM4 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. 21 1 read-write DISABLE Layer 4 Destination Port Inverse Match is disabled 0 ENABLE Layer 4 Destination Port Inverse Match is enabled 0x1 DMCHN4 DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. 24 3 read-write DMCHEN4 DMA Channel Select Enable When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. 28 1 read-write DISABLE DMA Channel Select is disabled 0 ENABLE DMA Channel Select is enabled 0x1 MAC_LAYER4_ADDRESS4 Layer 4 Address 4 0x9C4 32 read-write 0 0xFFFFFFFF L4SP4 Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP4 Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MAC_LAYER3_ADDR0_REG4 Layer 3 Address 0 Register 4 0x9D0 32 read-write 0 0xFFFFFFFF L3A04 Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR1_REG4 Layer 3 Address 1 Register 4 0x9D4 32 read-write 0 0xFFFFFFFF L3A14 Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR2_REG4 Layer 3 Address 2 Register 4 0x9D8 32 read-write 0 0xFFFFFFFF L3A24 Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR3_REG4 Layer 3 Address 3 Register 4 0x9DC 32 read-write 0 0xFFFFFFFF L3A34 Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_L3_L4_CONTROL5 Layer 3 and Layer 4 Control of Filter 5 0x9F0 32 read-write 0 0xFFFFFFFF L3PEN5 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. 0 1 read-write DISABLE Layer 3 Protocol is disabled 0 ENABLE Layer 3 Protocol is enabled 0x1 L3SAM5 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. 2 1 read-write DISABLE Layer 3 IP SA Match is disabled 0 ENABLE Layer 3 IP SA Match is enabled 0x1 L3SAIM5 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. 3 1 read-write DISABLE Layer 3 IP SA Inverse Match is disabled 0 ENABLE Layer 3 IP SA Inverse Match is enabled 0x1 L3DAM5 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. 4 1 read-write DISABLE Layer 3 IP DA Match is disabled 0 ENABLE Layer 3 IP DA Match is enabled 0x1 L3DAIM5 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. 5 1 read-write DISABLE Layer 3 IP DA Inverse Match is disabled 0 ENABLE Layer 3 IP DA Inverse Match is enabled 0x1 L3HSBM5 Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. 6 5 read-write L3HDBM5 Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. 11 5 read-write L4PEN5 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. 16 1 read-write DISABLE Layer 4 Protocol is disabled 0 ENABLE Layer 4 Protocol is enabled 0x1 L4SPM5 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. 18 1 read-write DISABLE Layer 4 Source Port Match is disabled 0 ENABLE Layer 4 Source Port Match is enabled 0x1 L4SPIM5 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. 19 1 read-write DISABLE Layer 4 Source Port Inverse Match is disabled 0 ENABLE Layer 4 Source Port Inverse Match is enabled 0x1 L4DPM5 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. 20 1 read-write DISABLE Layer 4 Destination Port Match is disabled 0 ENABLE Layer 4 Destination Port Match is enabled 0x1 L4DPIM5 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. 21 1 read-write DISABLE Layer 4 Destination Port Inverse Match is disabled 0 ENABLE Layer 4 Destination Port Inverse Match is enabled 0x1 DMCHN5 DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. 24 3 read-write DMCHEN5 DMA Channel Select Enable When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. 28 1 read-write DISABLE DMA Channel Select is disabled 0 ENABLE DMA Channel Select is enabled 0x1 MAC_LAYER4_ADDRESS5 Layer 4 Address 5 0x9F4 32 read-write 0 0xFFFFFFFF L4SP5 Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP5 Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MAC_LAYER3_ADDR0_REG5 Layer 3 Address 0 Register 5 0xA00 32 read-write 0 0xFFFFFFFF L3A05 Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR1_REG5 Layer 3 Address 1 Register 5 0xA04 32 read-write 0 0xFFFFFFFF L3A15 Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR2_REG5 Layer 3 Address 2 Register 5 0xA08 32 read-write 0 0xFFFFFFFF L3A25 Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR3_REG5 Layer 3 Address 3 Register 5 0xA0C 32 read-write 0 0xFFFFFFFF L3A35 Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_L3_L4_CONTROL6 Layer 3 and Layer 4 Control of Filter 6 0xA20 32 read-write 0 0xFFFFFFFF L3PEN6 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. 0 1 read-write DISABLE Layer 3 Protocol is disabled 0 ENABLE Layer 3 Protocol is enabled 0x1 L3SAM6 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. 2 1 read-write DISABLE Layer 3 IP SA Match is disabled 0 ENABLE Layer 3 IP SA Match is enabled 0x1 L3SAIM6 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. 3 1 read-write DISABLE Layer 3 IP SA Inverse Match is disabled 0 ENABLE Layer 3 IP SA Inverse Match is enabled 0x1 L3DAM6 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. 4 1 read-write DISABLE Layer 3 IP DA Match is disabled 0 ENABLE Layer 3 IP DA Match is enabled 0x1 L3DAIM6 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. 5 1 read-write DISABLE Layer 3 IP DA Inverse Match is disabled 0 ENABLE Layer 3 IP DA Inverse Match is enabled 0x1 L3HSBM6 Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. 6 5 read-write L3HDBM6 Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. 11 5 read-write L4PEN6 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. 16 1 read-write DISABLE Layer 4 Protocol is disabled 0 ENABLE Layer 4 Protocol is enabled 0x1 L4SPM6 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. 18 1 read-write DISABLE Layer 4 Source Port Match is disabled 0 ENABLE Layer 4 Source Port Match is enabled 0x1 L4SPIM6 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. 19 1 read-write DISABLE Layer 4 Source Port Inverse Match is disabled 0 ENABLE Layer 4 Source Port Inverse Match is enabled 0x1 L4DPM6 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. 20 1 read-write DISABLE Layer 4 Destination Port Match is disabled 0 ENABLE Layer 4 Destination Port Match is enabled 0x1 L4DPIM6 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. 21 1 read-write DISABLE Layer 4 Destination Port Inverse Match is disabled 0 ENABLE Layer 4 Destination Port Inverse Match is enabled 0x1 DMCHN6 DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. 24 3 read-write DMCHEN6 DMA Channel Select Enable When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. 28 1 read-write DISABLE DMA Channel Select is disabled 0 ENABLE DMA Channel Select is enabled 0x1 MAC_LAYER4_ADDRESS6 Layer 4 Address 6 0xA24 32 read-write 0 0xFFFFFFFF L4SP6 Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP6 Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MAC_LAYER3_ADDR0_REG6 Layer 3 Address 0 Register 6 0xA30 32 read-write 0 0xFFFFFFFF L3A06 Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR1_REG6 Layer 3 Address 1 Register 6 0xA34 32 read-write 0 0xFFFFFFFF L3A16 Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR2_REG6 Layer 3 Address 2 Register 6 0xA38 32 read-write 0 0xFFFFFFFF L3A26 Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR3_REG6 Layer 3 Address 3 Register 6 0xA3C 32 read-write 0 0xFFFFFFFF L3A36 Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_L3_L4_CONTROL7 Layer 3 and Layer 4 Control of Filter 0 0xA50 32 read-write 0 0xFFFFFFFF L3PEN7 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. 0 1 read-write DISABLE Layer 3 Protocol is disabled 0 ENABLE Layer 3 Protocol is enabled 0x1 L3SAM7 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. 2 1 read-write DISABLE Layer 3 IP SA Match is disabled 0 ENABLE Layer 3 IP SA Match is enabled 0x1 L3SAIM7 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. 3 1 read-write DISABLE Layer 3 IP SA Inverse Match is disabled 0 ENABLE Layer 3 IP SA Inverse Match is enabled 0x1 L3DAM7 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. 4 1 read-write DISABLE Layer 3 IP DA Match is disabled 0 ENABLE Layer 3 IP DA Match is enabled 0x1 L3DAIM7 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. 5 1 read-write DISABLE Layer 3 IP DA Inverse Match is disabled 0 ENABLE Layer 3 IP DA Inverse Match is enabled 0x1 L3HSBM7 Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. 6 5 read-write L3HDBM7 Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. 11 5 read-write L4PEN7 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. 16 1 read-write DISABLE Layer 4 Protocol is disabled 0 ENABLE Layer 4 Protocol is enabled 0x1 L4SPM7 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. 18 1 read-write DISABLE Layer 4 Source Port Match is disabled 0 ENABLE Layer 4 Source Port Match is enabled 0x1 L4SPIM7 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. 19 1 read-write DISABLE Layer 4 Source Port Inverse Match is disabled 0 ENABLE Layer 4 Source Port Inverse Match is enabled 0x1 L4DPM7 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. 20 1 read-write DISABLE Layer 4 Destination Port Match is disabled 0 ENABLE Layer 4 Destination Port Match is enabled 0x1 L4DPIM7 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. 21 1 read-write DISABLE Layer 4 Destination Port Inverse Match is disabled 0 ENABLE Layer 4 Destination Port Inverse Match is enabled 0x1 DMCHN7 DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. 24 3 read-write DMCHEN7 DMA Channel Select Enable When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. 28 1 read-write DISABLE DMA Channel Select is disabled 0 ENABLE DMA Channel Select is enabled 0x1 MAC_LAYER4_ADDRESS7 Layer 4 Address 7 0xA54 32 read-write 0 0xFFFFFFFF L4SP7 Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP7 Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MAC_LAYER3_ADDR0_REG7 Layer 3 Address 0 Register 7 0xA60 32 read-write 0 0xFFFFFFFF L3A07 Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR1_REG7 Layer 3 Address 1 Register 7 0xA64 32 read-write 0 0xFFFFFFFF L3A17 Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR2_REG7 Layer 3 Address 2 Register 7 0xA68 32 read-write 0 0xFFFFFFFF L3A27 Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_LAYER3_ADDR3_REG7 Layer 3 Address 3 Register 7 0xA6C 32 read-write 0 0xFFFFFFFF L3A37 Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. 0 32 read-write MAC_TIMESTAMP_CONTROL Timestamp Control 0xB00 32 read-write 0x2000 0xFFFFFFFF TSENA Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets. 0 1 read-write DISABLE Timestamp is disabled 0 ENABLE Timestamp is enabled 0x1 TSCFUPDT Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp. 1 1 read-write COARSE Coarse method is used to update system timestamp 0 FINE Fine method is used to update system timestamp 0x1 TSINIT Initialize Timestamp When this bit is set, the system time is initialized (overwritten) with the value specified in the MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers. 2 1 read-write DISABLE Timestamp is not initialized 0 ENABLE Timestamp is initialized 0x1 TSUPDT Update Timestamp When this bit is set, the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers. 3 1 read-write DISABLE Timestamp is not updated 0 ENABLE Timestamp is updated 0x1 TSADDREG Update Addend Register When this bit is set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. 5 1 read-write DISABLE Addend Register is not updated 0 ENABLE Addend Register is updated 0x1 PTGE Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled. 6 1 read-write DISABLE Presentation Time Generation is disabled 0 ENABLE Presentation Time Generation is enabled 0x1 TSENALL Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is enabled for all packets received by the MAC. 8 1 read-write DISABLE Timestamp for All Packets disabled 0 ENABLE Timestamp for All Packets enabled 0x1 TSCTRLSSR Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. 9 1 read-write DISABLE Timestamp Digital or Binary Rollover Control is disabled 0 ENABLE Timestamp Digital or Binary Rollover Control is enabled 0x1 TSVER2ENA Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE 1588 version 2 format is used to process the PTP packets. 10 1 read-write DISABLE PTP Packet Processing for Version 2 Format is disabled 0 ENABLE PTP Packet Processing for Version 2 Format is enabled 0x1 TSIPENA Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets. 11 1 read-write DISABLE Processing of PTP over Ethernet Packets is disabled 0 ENABLE Processing of PTP over Ethernet Packets is enabled 0x1 TSIPV6ENA Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets. 12 1 read-write DISABLE Processing of PTP Packets Sent over IPv6-UDP is disabled 0 ENABLE Processing of PTP Packets Sent over IPv6-UDP is enabled 0x1 TSIPV4ENA Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets. 13 1 read-write DISABLE Processing of PTP Packets Sent over IPv4-UDP is disabled 0 ENABLE Processing of PTP Packets Sent over IPv4-UDP is enabled 0x1 TSEVNTENA Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). 14 1 read-write DISABLE Timestamp Snapshot for Event Messages is disabled 0 ENABLE Timestamp Snapshot for Event Messages is enabled 0x1 TSMSTRENA Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot is taken only for the messages that are relevant to the master node. 15 1 read-write DISABLE Snapshot for Messages Relevant to Master is disabled 0 ENABLE Snapshot for Messages Relevant to Master is enabled 0x1 SNAPTYPSEL Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14, decide the set of PTP packet types for which snapshot needs to be taken. 16 2 read-write TSENMACADDR Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet. 18 1 read-write DISABLE MAC Address for PTP Packet Filtering is disabled 0 ENABLE MAC Address for PTP Packet Filtering is enabled 0x1 CSC Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set, the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum correct, for changes made to origin timestamp and/or correction field as part of one step timestamp operation. 19 1 read-write DISABLE checksum correction during OST for PTP over UDP/IPv4 packets is disabled 0 ENABLE checksum correction during OST for PTP over UDP/IPv4 packets is enabled 0x1 ESTI External System Time Input When this bit is set, the MAC uses the external 64-bit reference System Time input for the following: - To take the timestamp provided as status - To insert the timestamp in transmit PTP packets when One-step Timestamp or Timestamp Offload feature is enabled. 20 1 read-write DISABLE External System Time Input is disabled 0 ENABLE External System Time Input is enabled 0x1 TXTSSTSM Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier transmit timestamp status even if it is not read by the software. 24 1 read-write DISABLE Transmit Timestamp Status Mode is disabled 0 ENABLE Transmit Timestamp Status Mode is enabled 0x1 AV8021ASMEN AV 802. 28 1 read-write DISABLE AV 802.1AS Mode is disabled 0 ENABLE AV 802.1AS Mode is enabled 0x1 MAC_SUB_SECOND_INCREMENT Subsecond Increment 0xB04 32 read-write 0 0xFFFFFFFF SNSINC Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value, represented in nanoseconds multiplied by 2^8. 8 8 read-write SSINC Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. 16 8 read-write MAC_SYSTEM_TIME_SECONDS System Time Seconds 0xB08 32 read-only 0 0xFFFFFFFF TSS Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC. 0 32 read-only MAC_SYSTEM_TIME_NANOSECONDS System Time Nanoseconds 0xB0C 32 read-only 0 0xFFFFFFFF TSSS Timestamp Sub Seconds The value in this field has the sub-second representation of time, with an accuracy of 0. 0 31 read-only MAC_SYSTEM_TIME_SECONDS_UPDATE System Time Seconds Update 0xB10 32 read-write 0 0xFFFFFFFF TSS Timestamp Seconds The value in this field is the seconds part of the update. 0 32 read-write MAC_SYSTEM_TIME_NANOSECONDS_UPDATE System Time Nanoseconds Update 0xB14 32 read-write 0 0xFFFFFFFF TSSS Timestamp Sub Seconds The value in this field is the sub-seconds part of the update. 0 31 read-write ADDSUB Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register. 31 1 read-write ADD Add time 0 SUB Subtract time 0x1 MAC_TIMESTAMP_ADDEND Timestamp Addend 0xB18 32 read-write 0 0xFFFFFFFF TSAR Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. 0 32 read-write MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS System Time - Higher Word Seconds 0xB1C 32 read-write 0 0xFFFFFFFF TSHWR Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value. 0 16 read-write MAC_TIMESTAMP_STATUS Timestamp Status 0xB20 32 read-only 0 0xFFFFFFFF TSSOVF Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. 0 1 read-only INACTIVE Timestamp Seconds Overflow status not detected 0 ACTIVE Timestamp Seconds Overflow status detected 0x1 TSTARGT0 Timestamp Target Time Reached When set, this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers. 1 1 read-only INACTIVE Timestamp Target Time Reached status not detected 0 ACTIVE Timestamp Target Time Reached status detected 0x1 AUXTSTRIG Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO. 2 1 read-only INACTIVE Auxiliary Timestamp Trigger Snapshot status not detected 0 ACTIVE Auxiliary Timestamp Trigger Snapshot status detected 0x1 TSTRGTERR0 Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses. 3 1 read-only INACTIVE Timestamp Target Time Error status not detected 0 ACTIVE Timestamp Target Time Error status detected 0x1 TSTARGT1 Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers. 4 1 read-only INACTIVE Timestamp Target Time Reached for Target Time PPS1 status not detected 0 ACTIVE Timestamp Target Time Reached for Target Time PPS1 status detected 0x1 TSTRGTERR1 Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses. 5 1 read-only INACTIVE Timestamp Target Time Error status not detected 0 ACTIVE Timestamp Target Time Error status detected 0x1 TSTARGT2 Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers. 6 1 read-only INACTIVE Timestamp Target Time Reached for Target Time PPS2 status not detected 0 ACTIVE Timestamp Target Time Reached for Target Time PPS2 status detected 0x1 TSTRGTERR2 Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses. 7 1 read-only INACTIVE Timestamp Target Time Error status not detected 0 ACTIVE Timestamp Target Time Error status detected 0x1 TSTARGT3 Timestamp Target Time Reached for Target Time PPS3 When this bit is set, it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers. 8 1 read-only INACTIVE Timestamp Target Time Reached for Target Time PPS3 status not detected 0 ACTIVE Timestamp Target Time Reached for Target Time PPS3 status detected 0x1 TSTRGTERR3 Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses. 9 1 read-only INACTIVE Timestamp Target Time Error status not detected 0 ACTIVE Timestamp Target Time Error status detected 0x1 TXTSSIS Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and MAC_TX_TIMESTAMP_STATUS_SECONDS registers. 15 1 read-only INACTIVE Tx Timestamp Status Interrupt status not detected 0 ACTIVE Tx Timestamp Status Interrupt status detected 0x1 ATSSTN Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. 16 4 read-only ATSSTM Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. 24 1 read-only INACTIVE Auxiliary Timestamp Snapshot Trigger Missed status not detected 0 ACTIVE Auxiliary Timestamp Snapshot Trigger Missed status detected 0x1 ATSNS Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. 25 5 read-only MAC_TX_TIMESTAMP_STATUS_NANOSECONDS Transmit Timestamp Status Nanoseconds 0xB30 32 read-only 0 0xFFFFFFFF TXTSSLO Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp. 0 31 read-only TXTSSMIS Transmit Timestamp Status Missed When this bit is set, it indicates one of the following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the TIMESTAMP_CONTROL register is reset - The timestamp of the previous packet is overwritten with timestamp of the current packet if TXTSSTSM bit of the MAC_TIMESTAMP_CONTROL register is set. 31 1 read-only INACTIVE Transmit Timestamp Status Missed status not detected 0 ACTIVE Transmit Timestamp Status Missed status detected 0x1 MAC_TX_TIMESTAMP_STATUS_SECONDS Transmit Timestamp Status Seconds 0xB34 32 read-only 0 0xFFFFFFFF TXTSSHI Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp. 0 32 read-only MAC_AUXILIARY_CONTROL Auxiliary Timestamp Control 0xB40 32 read-write 0 0xFFFFFFFF ATSFC Auxiliary Snapshot FIFO Clear When set, this bit resets the pointers of the Auxiliary Snapshot FIFO. 0 1 read-write DISABLE Auxiliary Snapshot FIFO Clear is disabled 0 ENABLE Auxiliary Snapshot FIFO Clear is enabled 0x1 ATSEN0 Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0. 4 1 read-write DISABLE Auxiliary Snapshot $i is disabled 0 ENABLE Auxiliary Snapshot $i is enabled 0x1 ATSEN1 Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1. 5 1 read-write DISABLE Auxiliary Snapshot $i is disabled 0 ENABLE Auxiliary Snapshot $i is enabled 0x1 ATSEN2 Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2. 6 1 read-write DISABLE Auxiliary Snapshot $i is disabled 0 ENABLE Auxiliary Snapshot $i is enabled 0x1 ATSEN3 Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3. 7 1 read-write DISABLE Auxiliary Snapshot $i is disabled 0 ENABLE Auxiliary Snapshot $i is enabled 0x1 MAC_AUXILIARY_TIMESTAMP_NANOSECONDS Auxiliary Timestamp Nanoseconds 0xB48 32 read-only 0 0xFFFFFFFF AUXTSLO Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp. 0 31 read-only MAC_AUXILIARY_TIMESTAMP_SECONDS Auxiliary Timestamp Seconds 0xB4C 32 read-only 0 0xFFFFFFFF AUXTSHI Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. 0 32 read-only MAC_TIMESTAMP_INGRESS_ASYM_CORR Timestamp Ingress Asymmetry Correction 0xB50 32 read-write 0 0xFFFFFFFF OSTIAC One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet. 0 32 read-write MAC_TIMESTAMP_EGRESS_ASYM_CORR imestamp Egress Asymmetry Correction 0xB54 32 read-write 0 0xFFFFFFFF OSTEAC One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet. 0 32 read-write MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND Timestamp Ingress Correction Nanosecond 0xB58 32 read-write 0 0xFFFFFFFF TSIC Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression. 0 32 read-write MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND Timestamp Egress Correction Nanosecond 0xB5C 32 read-write 0 0xFFFFFFFF TSEC Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression. 0 32 read-write MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC Timestamp Ingress Correction Subnanosecond 0xB60 32 read-write 0 0xFFFFFFFF TSICSNS Timestamp Ingress Correction, sub-nanoseconds This field contains the sub-nanoseconds part of the ingress path correction value as defined by the "Ingress Correction" expression. 8 8 read-write MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC Timestamp Egress Correction Subnanosecond 0xB64 32 read-write 0 0xFFFFFFFF TSECSNS Timestamp Egress Correction, sub-nanoseconds This field contains the sub-nanoseconds part of the egress path correction value as defined by the "Egress Correction" expression. 8 8 read-write MAC_TIMESTAMP_INGRESS_LATENCY Timestamp Ingress Latency 0xB68 32 read-only 0 0xFFFFFFFF ITLSNS Ingress Timestamp Latency, in nanoseconds This register holds the average latency in nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken. 8 8 read-only ITLNS Ingress Timestamp Latency, in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken. 16 12 read-only MAC_TIMESTAMP_EGRESS_LATENCY Timestamp Egress Latency 0xB6C 32 read-only 0 0xFFFFFFFF ETLSNS Egress Timestamp Latency, in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC. 8 8 read-only ETLNS Egress Timestamp Latency, in nanoseconds This register holds the average latency in nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC. 16 12 read-only MAC_PPS_CONTROL PPS Control 0xB70 32 read-write 0 0xFFFFFFFF PPSCTRL_PPSCMD PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. 0 4 read-write PPSEN0 Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD. 4 1 read-write DISABLE Flexible PPS Output Mode is disabled 0 ENABLE Flexible PPS Output Mode is enabled 0x1 TRGTMODSEL0 Target Time Register Mode for PPS0 Output This field indicates the Target Time registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0 output signal: 5 2 read-write ONLY_INT Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding ptp_pps_o output port 0 INT_ST Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation 0x2 ONLY_ST Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted 0x3 MCGREN0 MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode. 7 1 read-write PPS 0th PPS instance is enabled to operate in PPS mode 0 MCGR 0th PPS instance is enabled to operate in MCGR mode 0x1 PPSCMD1 Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. 8 4 read-write TRGTMODSEL1 Target Time Register Mode for PPS1 Output This field indicates the Target Time registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1 output signal. 13 2 read-write ONLY_INT Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding ptp_pps_o output port 0 INT_ST Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation 0x2 ONLY_ST Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted 0x3 MCGREN1 MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode. 15 1 read-write DISABLE 1st PPS instance is disabled to operate in PPS or MCGR mode 0 ENABLE 1st PPS instance is enabled to operate in PPS or MCGR mode 0x1 PPSCMD2 Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. 16 4 read-write TRGTMODSEL2 Target Time Register Mode for PPS2 Output This field indicates the Target Time registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2 output signal. 21 2 read-write ONLY_INT Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding ptp_pps_o output port 0 INT_ST Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation 0x2 ONLY_ST Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted 0x3 MCGREN2 MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode. 23 1 read-write DISABLE 2nd PPS instance is disabled to operate in PPS or MCGR mode 0 ENABLE 2nd PPS instance is enabled to operate in PPS or MCGR mode 0x1 PPSCMD3 Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. 24 4 read-write TRGTMODSEL3 Target Time Register Mode for PPS3 Output This field indicates the Target Time registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3 output signal. 29 2 read-write ONLY_INT Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding ptp_pps_o output port 0 INT_ST Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation 0x2 ONLY_ST Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted 0x3 MCGREN3 MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode. 31 1 read-write MAC_PPS0_TARGET_TIME_SECONDS PPS0 Target Time Seconds 0xB80 32 read-write 0 0xFFFFFFFF TSTRH0 PPS Target Time Seconds Register This field stores the time in seconds. 0 32 read-write MAC_PPS0_TARGET_TIME_NANOSECONDS PPS0 Target Time Nanoseconds 0xB84 32 read-write 0 0xFFFFFFFF TTSL0 Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. 0 31 read-write TRGTBUSY0 PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011. 31 1 read-write INACTIVE PPS Target Time Register Busy status is not detected 0 ACTIVE PPS Target Time Register Busy is detected 0x1 MAC_PPS0_INTERVAL PPS0 Interval 0xB88 32 read-write 0 0xFFFFFFFF PPSINT0 PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. 0 32 read-write MAC_PPS0_WIDTH PPS0 Width 0xB8C 32 read-write 0 0xFFFFFFFF PPSWIDTH0 PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. 0 32 read-write MAC_PPS1_TARGET_TIME_SECONDS PPS1 Target Time Seconds 0xB90 32 read-write 0 0xFFFFFFFF TSTRH1 PPS Target Time Seconds Register This field stores the time in seconds. 0 32 read-write MAC_PPS1_TARGET_TIME_NANOSECONDS PPS1 Target Time Nanoseconds 0xB94 32 read-write 0 0xFFFFFFFF TTSL1 Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. 0 31 read-write TRGTBUSY1 PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011. 31 1 read-write INACTIVE PPS Target Time Register Busy status is not detected 0 ACTIVE PPS Target Time Register Busy is detected 0x1 MAC_PPS1_INTERVAL PPS1 Interval 0xB98 32 read-write 0 0xFFFFFFFF PPSINT1 PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. 0 32 read-write MAC_PPS1_WIDTH PPS1 Width 0xB9C 32 read-write 0 0xFFFFFFFF PPSWIDTH1 PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. 0 32 read-write MAC_PPS2_TARGET_TIME_SECONDS PPS2 Target Time Seconds 0xBA0 32 read-write 0 0xFFFFFFFF TSTRH2 PPS Target Time Seconds Register This field stores the time in seconds. 0 32 read-write MAC_PPS2_TARGET_TIME_NANOSECONDS PPS2 Target Time Nanoseconds 0xBA4 32 read-write 0 0xFFFFFFFF TTSL2 Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. 0 31 read-write TRGTBUSY2 PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011. 31 1 read-write INACTIVE PPS Target Time Register Busy status is not detected 0 ACTIVE PPS Target Time Register Busy is detected 0x1 MAC_PPS2_INTERVAL PPS2 Interval 0xBA8 32 read-write 0 0xFFFFFFFF PPSINT2 PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. 0 32 read-write MAC_PPS2_WIDTH PPS2 Width 0xBAC 32 read-write 0 0xFFFFFFFF PPSWIDTH2 PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. 0 32 read-write MAC_PPS3_TARGET_TIME_SECONDS PPS3 Target Time Seconds 0xBB0 32 read-write 0 0xFFFFFFFF TSTRH3 PPS Target Time Seconds Register This field stores the time in seconds. 0 32 read-write MAC_PPS3_TARGET_TIME_NANOSECONDS PPS3 Target Time Nanoseconds 0xBB4 32 read-write 0 0xFFFFFFFF TTSL3 Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. 0 31 read-write TRGTBUSY3 PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011. 31 1 read-write INACTIVE PPS Target Time Register Busy status is not detected 0 ACTIVE PPS Target Time Register Busy is detected 0x1 MAC_PPS3_INTERVAL PPS3 Interval 0xBB8 32 read-write 0 0xFFFFFFFF PPSINT3 PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. 0 32 read-write MAC_PPS3_WIDTH PPS3 Width 0xBBC 32 read-write 0 0xFFFFFFFF PPSWIDTH3 PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. 0 32 read-write MAC_PTO_CONTROL PTP Offload Engine Control 0xBC0 32 read-write 0 0xFFFFFFFF PTOEN PTP Offload Enable When this bit is set, the PTP Offload feature is enabled. 0 1 read-write DISABLE PTP Offload feature is disabled 0 ENABLE PTP Offload feature is enabled 0x1 ASYNCEN Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Clock Master mode. 1 1 read-write DISABLE Automatic PTP SYNC message is disabled 0 ENABLE Automatic PTP SYNC message is enabled 0x1 APDREQEN Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Peer-to-Peer Transparent mode. 2 1 read-write DISABLE Automatic PTP Pdelay_Req message is disabled 0 ENABLE Automatic PTP Pdelay_Req message is enabled 0x1 ASYNCTRIG Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted. 4 1 read-write DISABLE Automatic PTP SYNC message Trigger is disabled 0 ENABLE Automatic PTP SYNC message Trigger is enabled 0x1 APDREQTRIG Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted. 5 1 read-write DISABLE Automatic PTP Pdelay_Req message Trigger is disabled 0 ENABLE Automatic PTP Pdelay_Req message Trigger is enabled 0x1 DRRDIS Disable PTO Delay Request/Response response generation When this bit is set, the Delay Request and Delay response is not generated for received SYNC and Delay request packet respectively, as required by the programmed mode. 6 1 read-write ENABLE PTO Delay Request/Response response generation is enabled 0 DISABLE PTO Delay Request/Response response generation is disabled 0x1 PDRDIS Disable Peer Delay Response response generation When this bit is set, the Peer Delay Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req) request packet, as required by the programmed mode. 7 1 read-write ENABLE Peer Delay Response response generation is enabled 0 DISABLE Peer Delay Response response generation is disabled 0x1 DN Domain Number This field indicates the domain Number in which the PTP node is operating. 8 8 read-write MAC_SOURCE_PORT_IDENTITY0 Source Port Identity 0 0xBC4 32 read-write 0 0xFFFFFFFF SPI0 Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node. 0 32 read-write MAC_SOURCE_PORT_IDENTITY1 Source Port Identity 1 0xBC8 32 read-write 0 0xFFFFFFFF SPI1 Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node. 0 32 read-write MAC_SOURCE_PORT_IDENTITY2 Source Port Identity 2 0xBCC 32 read-write 0 0xFFFFFFFF SPI2 Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node. 0 16 read-write MAC_LOG_MESSAGE_INTERVAL Log Message Interval 0xBD0 32 read-write 0 0xFFFFFFFF LSI Log Sync Interval This field indicates the periodicity of the automatically generated SYNC message when the PTP node is Master. 0 8 read-write DRSYNCR Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted. 8 3 read-write SYNC1 DelayReq generated for every received SYNC 0 SYNC2 DelayReq generated every alternate reception of SYNC 0x1 SYNC4 for every 4 SYNC messages 0x2 SYNC8 for every 8 SYNC messages 0x3 SYNC16 for every 16 SYNC messages 0x4 SYNC32 for every 32 SYNC messages 0x5 LMPDRI Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node. 24 8 read-write MTL_OPERATION_MODE MTL Operation Mode 0xC00 32 read-write 0 0xFFFFFFFF DTXSTS Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. 1 1 read-write DISABLE Drop Transmit Status is disabled 0 ENABLE Drop Transmit Status is enabled 0x1 RAA Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side. 2 1 read-write SP Strict priority (SP) 0 WSP Weighted Strict Priority (WSP) 0x1 SCHALG Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 5 2 read-write WRR WRR algorithm 0 WFQ WFQ algorithm when DCB feature is selected.Otherwise, Reserved 0x1 DWRR DWRR algorithm when DCB feature is selected.Otherwise, Reserved 0x2 SP Strict priority algorithm 0x3 CNTPRST Counters Preset When this bit is set, - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0. 8 1 read-write DISABLE Counters Preset is disabled 0 ENABLE Counters Preset is enabled 0x1 CNTCLR Counters Reset When this bit is set, all counters are reset. 9 1 read-write DISABLE Counters are not reset 0 ENABLE All counters are reset 0x1 FRPE Flexible Rx parser Enable When this bit is set to 1, the Programmable Rx Parser functionality is enabled. 15 1 read-write DISABLE Flexible Rx parser is disabled 0 ENABLE Flexible Rx parser is enabled 0x1 MTL_DBG_CTL FIFO Debug Access Control and Status 0xC08 32 read-write 0 0xFFFFFFFF FDBGEN FIFO Debug Access Enable When this bit is set, it indicates that the debug mode access to the FIFO is enabled. 0 1 read-write DISABLE FIFO Debug Access is disabled 0 ENABLE FIFO Debug Access is enabled 0x1 DBGMOD Debug Mode Access to FIFO When this bit is set, it indicates that the current access to the FIFO is read, write, and debug access. 1 1 read-write DISABLE Debug Mode Access to FIFO is disabled 0 ENABLE Debug Mode Access to FIFO is enabled 0x1 BYTEEN Byte Enables This field indicates the number of data bytes valid in the data register during Write operation. 2 2 read-write B0_VAL Byte 0 valid 0 B01_VAL Byte 0 and Byte 1 are valid 0x1 B012_VAL Byte 0, Byte 1, and Byte 2 are valid 0x2 B0123_VAL All four bytes are valid 0x3 PKTSTATE Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO. 5 2 read-write PKT_DATA Packet Data 0 CW_NS Control Word/Normal Status 0x1 SOP_LS SOP Data/Last Status 0x2 EOP EOP Data/EOP 0x3 RSTALL Reset All Pointers When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled. 8 1 read-write DISABLE Reset All Pointers is disabled 0 ENABLE Reset All Pointers is enabled 0x1 RSTSEL Reset Pointers of Selected FIFO When this bit is set, the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled. 9 1 read-write DISABLE Reset Pointers of Selected FIFO is disabled 0 ENABLE Reset Pointers of Selected FIFO is enabled 0x1 FIFORDEN FIFO Read Enable When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled. 10 1 read-write DISABLE FIFO Read is disabled 0 ENABLE FIFO Read is enabled 0x1 FIFOWREN FIFO Write Enable When this bit is set, it enables the Write operation on selected FIFO when FIFO Debug Access is enabled. 11 1 read-write DISABLE FIFO Write is disabled 0 ENABLE FIFO Write is enabled 0x1 FIFOSEL FIFO Selected for Access This field indicates the FIFO selected for debug access: 12 2 read-write TXFIFO Tx FIFO 0 TXSTSFIFO Tx Status FIFO (only read access when SLVMOD is set) 0x1 TSOFIFO TSO FIFO (cannot be accessed when SLVMOD is set) 0x2 RXFIFO Rx FIFO 0x3 PKTIE Receive Packet Available Interrupt Status Enable When this bit is set, an interrupt is generated when EOP of received packet is written to the Rx FIFO. 14 1 read-write DISABLE Receive Packet Available Interrupt Status is disabled 0 ENABLE Receive Packet Available Interrupt Status is enabled 0x1 STSIE Transmit Status Available Interrupt Status Enable When this bit is set, an interrupt is generated when Transmit status is available in slave mode. 15 1 read-write DISABLE Transmit Packet Available Interrupt Status is disabled 0 ENABLE Transmit Packet Available Interrupt Status is enabled 0x1 MTL_DBG_STS FIFO Debug Status 0xC0C 32 read-write 0x18 0xFFFFFFFF FIFOBUSY FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid: - All other fields of this register - All fields of the MTL_FIFO_DEBUG_DATA register 0 1 read-only INACTIVE FIFO Busy not detected 0 ACTIVE FIFO Busy detected 0x1 PKTSTATE Encoded Packet State This field is used to get the control or status information of the selected FIFO. 1 2 read-only PKT_DATA Packet Data 0 CW_NS Control Word/Normal Status 0x1 SOP_LS SOP Data/Last Status 0x2 EOP EOP Data/EOP 0x3 BYTEEN Byte Enables This field indicates the number of data bytes valid in the data register during Read operation. 3 2 read-only B0_VAL Byte 0 valid 0 B01_VAL Byte 0 and Byte 1 are valid 0x1 B012_VAL Byte 0, Byte 1, and Byte 2 are valid 0x2 B0123_VAL All four bytes are valid 0x3 PKTI Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO. 8 1 read-write INACTIVE Receive Packet Available Interrupt Status not detected 0 ACTIVE Receive Packet Available Interrupt Status detected 0x1 STSI Transmit Status Available Interrupt Status When set, this bit indicates that the Slave mode Tx packet is transmitted, and the status is available in Tx Status FIFO. 9 1 read-write INACTIVE Transmit Status Available Interrupt Status not detected 0 ACTIVE Transmit Status Available Interrupt Status detected 0x1 LOCR Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO. 15 17 read-only MTL_FIFO_DEBUG_DATA FIFO Debug Data 0xC10 32 read-write 0 0xFFFFFFFF FDBGDATA FIFO Debug Data During debug or slave access write operation, this field contains the data to be written to the Tx FIFO, Rx FIFO, or TSO FIFO. 0 32 read-write MTL_INTERRUPT_STATUS MTL Interrupt Status 0xC20 32 read-only 0 0xFFFFFFFF Q0IS Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0. 0 1 read-only INACTIVE Queue 0 Interrupt status not detected 0 ACTIVE Queue 0 Interrupt status detected 0x1 Q1IS Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1. 1 1 read-only INACTIVE Queue 1 Interrupt status not detected 0 ACTIVE Queue 1 Interrupt status detected 0x1 Q2IS Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2. 2 1 read-only INACTIVE Queue 2 Interrupt status not detected 0 ACTIVE Queue 2 Interrupt status detected 0x1 Q3IS Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3. 3 1 read-only INACTIVE Queue 3 Interrupt status not detected 0 ACTIVE Queue 3 Interrupt status detected 0x1 Q4IS Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4. 4 1 read-only INACTIVE Queue 4 Interrupt status not detected 0 ACTIVE Queue 4 Interrupt status detected 0x1 DBGIS Debug Interrupt status This bit indicates an interrupt event during the slave access. 17 1 read-only INACTIVE Debug Interrupt status not detected 0 ACTIVE Debug Interrupt status detected 0x1 ESTIS EST (TAS- 802. 18 1 read-only INACTIVE EST (TAS- 802.1Qbv) Interrupt status not detected 0 ACTIVE EST (TAS- 802.1Qbv) Interrupt status detected 0x1 MTLPIS MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block. 23 1 read-only INACTIVE MTL Rx Parser Interrupt status not detected 0 ACTIVE MTL Rx Parser Interrupt status detected 0x1 MTL_RXQ_DMA_MAP0 Receive Queue and DMA Channel Mapping 0 0xC30 32 read-write 0 0xFFFFFFFF Q0MDMACH Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This field is valid when the Q0DDMACH field is reset. 0 3 read-write Q0DDMACH Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address. 4 1 read-write DISABLE Queue 0 disabled for DA-based DMA Channel Selection 0 ENABLE Queue 0 enabled for DA-based DMA Channel Selection 0x1 Q1MDMACH Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This field is valid when the Q1DDMACH field is reset. 8 3 read-write Q1DDMACH Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address. 12 1 read-write DISABLE Queue 1 disabled for DA-based DMA Channel Selection 0 ENABLE Queue 1 enabled for DA-based DMA Channel Selection 0x1 Q2MDMACH Queue 2 Mapped to DMA Channel This field controls the routing of the received packet in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This field is valid when the Q2DDMACH field is reset. 16 3 read-write Q2DDMACH Queue 2 Enabled for DA-based DMA Channel Selection When set, this bit indicates that the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address. 20 1 read-write DISABLE Queue 2 disabled for DA-based DMA Channel Selection 0 ENABLE Queue 2 enabled for DA-based DMA Channel Selection 0x1 Q3MDMACH Queue 3 Mapped to DMA Channel This field controls the routing of the received packet in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This field is valid when the Q3DDMACH field is reset. 24 3 read-write Q3DDMACH Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set, this bit indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address. 28 1 read-write DISABLE Queue 3 disabled for DA-based DMA Channel Selection 0 ENABLE Queue 3 enabled for DA-based DMA Channel Selection 0x1 MTL_RXQ_DMA_MAP1 Receive Queue and DMA Channel Mapping 1 0xC34 32 read-write 0 0xFFFFFFFF Q4MDMACH Queue 4 Mapped to DMA Channel This field controls the routing of the packet received in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This field is valid when the Q4DDMACH field is reset. 0 3 read-write Q4DDMACH Queue 4 Enabled for DA-based DMA Channel Selection When set, this bit indicates that the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address. 4 1 read-write DISABLE Queue 4 disabled for DA-based DMA Channel Selection 0 ENABLE Queue 4 enabled for DA-based DMA Channel Selection 0x1 MTL_TBS_CTRL Time Based Scheduling Control 0xC40 32 read-write 0 0xFFFFFFFF ESTM EST offset Mode When this bit is set, the Launch Time value used in Time Based Scheduling is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the current list. 0 1 read-write DISABLE EST offset Mode is disabled 0 ENABLE EST offset Mode is enabled 0x1 LEOV Launch Expiry Offset Valid When set indicates the LEOS field is valid. 1 1 read-write INVALID LEOS field is invalid 0 VALID LEOS field is valid 0x1 LEGOS Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time. 4 3 read-write LEOS Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the Launch time to compute the Launch Expiry time. 8 24 read-write MTL_EST_CONTROL Enhancements to Scheduled Transmission Control 0xC50 32 read-write 0 0xFFFFFFFF EEST Enable EST When reset, the gate control list processing is halted and all gates are assumed to be in Open state. 0 1 read-write DISABLE EST is disabled 0 ENABLE EST is enabled 0x1 SSWL Switch to S/W owned list When set indicates that the software has programmed that list that it currently owns (SWOL) and the hardware should switch to the new list based on the new BTR. 1 1 read-write DISABLE Switch to S/W owned list is disabled 0 ENABLE Switch to S/W owned list is enabled 0x1 DDBF Do not Drop frames during Frame Size Error When set, frames are not be dropped during Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register). 4 1 read-write DROP Drop frames during Frame Size Error 0 DONT_DROP Do not Drop frames during Frame Size Error 0x1 DFBS Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due to not getting scheduled (HLBS field of EST_STATUS register) after 4,8,16,32 (based on LCSE field of this register) GCL iterations are dropped. 5 1 read-write DONT_DROP Do not Drop Frames causing Scheduling Error 0 DROP Drop Frames causing Scheduling Error 0x1 LCSE Loop Count to report Scheduling Error Programmable number of GCL list iterations before reporting an HLBS error defined in EST_STATUS register. 6 2 read-write bf_4_ITERNS 4 iterations 0 bf_8_ITERNS 8 iterations 0x1 bf_16_ITERNS 16 iterations 0x2 bf_32_ITERNS 32 iterations 0x3 TILS Time Interval Left Shift Amount This field provides the left shift amount for the programmed Time Interval values used in the Gate Control Lists. 8 3 read-write CTOV Current Time Offset Value Provides a 12 bit time offset value in nano second that is added to the current time to compensate for all the implementation pipeline delays such as the CDC sync delay, buffering delays, data path delays etc. 12 12 read-write PTOV PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds. 24 8 read-write MTL_EST_STATUS Enhancements to Scheduled Transmission Status 0xC58 32 read-write 0 0xFFFFFFFF SWLC Switch to S/W owned list Complete When "1" indicates the hardware has successfully switched to the SWOL, and the SWOL bit has been updated to that effect. 0 1 read-write INACTIVE Switch to S/W owned list Complete not detected 0 ACTIVE Switch to S/W owned list Complete detected 0x1 BTRE BTR Error When "1" indicates a programming error in the BTR of SWOL where the programmed value is less than current time. 1 1 read-write INACTIVE BTR Error not detected 0 ACTIVE BTR Error detected 0x1 HLBF Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or equal to the duration needed for frame size (or frame fragment size when preemption is enabled) transmission. 2 1 read-only INACTIVE Head-Of-Line Blocking due to Frame Size not detected 0 ACTIVE Head-Of-Line Blocking due to Frame Size detected 0x1 HLBS Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL. 3 1 read-only INACTIVE Head-Of-Line Blocking due to Scheduling not detected 0 ACTIVE Head-Of-Line Blocking due to Scheduling detected 0x1 CGCE Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the Cycle Time (CTR). 4 1 read-write INACTIVE Constant Gate Control Error not detected 0 ACTIVE Constant Gate Control Error detected 0x1 SWOL S/W owned list When '0' indicates Gate control list number "0" is owned by software and when "1" indicates the Gate Control list "1" is owned by the software. 7 1 read-only INACTIVE Gate control list number "0" is owned by software 0 ACTIVE Gate control list number "1" is owned by software 0x1 BTRL BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true. 8 4 read-only CGSN Current GCL Slot Number Indicates the slot number of the GCL list. 16 4 read-only MTL_EST_SCH_ERROR EST Scheduling Error 0xC60 32 read-write 0 0xFFFFFFFF SEQN Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced error/timeout described in HLBS field of status register. 0 5 read-write MTL_EST_FRM_SIZE_ERROR EST Frame Size Error 0xC64 32 read-write 0 0xFFFFFFFF FEQN Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced error described in HLBF field of status register. 0 5 read-write MTL_EST_FRM_SIZE_CAPTURE EST Frame Size Capture 0xC68 32 read-only 0 0xFFFFFFFF HBFS Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number indicated in HBFQ field of this register. 0 15 read-only HBFQ Queue Number of HLBF Captures the binary value of the of the first Queue (number) experiencing HLBF error (see HLBF field of status register). 16 3 read-only MTL_EST_INTR_ENABLE EST Interrupt Enable 0xC70 32 read-write 0 0xFFFFFFFF IECC Interrupt Enable for Switch List When set, generates interrupt when the configuration change is successful and the hardware has switched to the new list. 0 1 read-write DISABLE Interrupt for Switch List is disabled 0 ENABLE Interrupt for Switch List is enabled 0x1 IEBE Interrupt Enable for BTR Error When set, generates interrupt when the BTR Error occurs and is indicated in the status. 1 1 read-write DISABLE Interrupt for BTR Error is disabled 0 ENABLE Interrupt for BTR Error is enabled 0x1 IEHF Interrupt Enable for HLBF When set, generates interrupt when the Head-of-Line Blocking due to Frame Size error occurs and is indicated in the status. 2 1 read-write DISABLE Interrupt for HLBF is disabled 0 ENABLE Interrupt for HLBF is enabled 0x1 IEHS Interrupt Enable for HLBS When set, generates interrupt when the Head-of-Line Blocking due to Scheduling issue and is indicated in the status. 3 1 read-write DISABLE Interrupt for HLBS is disabled 0 ENABLE Interrupt for HLBS is enabled 0x1 CGCE Interrupt Enable for CGCE When set, generates interrupt when the Constant Gate Control Error occurs and is indicated in the status. 4 1 read-write DISABLE Interrupt for CGCE is disabled 0 ENABLE Interrupt for CGCE is enabled 0x1 MTL_EST_GCL_CONTROL EST GCL Control 0xC80 32 read-write 0 0xFFFFFFFF SRWO Start Read/Write Op When set indicates a Read/Write Op has started and is in progress. 0 1 read-write DISABLE Start Read/Write Op disabled 0 ENABLE Start Read/Write Op enabled 0x1 R1W0 Read '1', Write '0': When set to '1': Read Operation When set to '0': Write Operation. 1 1 read-write WRITE Write Operation 0 READ Read Operation 0x1 GCRR Gate Control Related Registers When set to "1" indicates the R/W access is for the GCL related registers (BTR, CTR, TER, LLR) whose address is provided by GCRA. 2 1 read-write DISABLE Gate Control Related Registers are disabled 0 ENABLE Gate Control Related Registers are enabled 0x1 DBGM Debug Mode When set to "1" indicates R/W in debug mode where the memory bank (for GCL and Time related registers) is explicitly provided by DBGB value, when set to "0" SWOL bit is used to determine which bank to use. 4 1 read-write DISABLE Debug Mode is disabled 0 ENABLE Debug Mode is enabled 0x1 DBGB Debug Mode Bank Select When set to "0" indicates R/W in debug mode should be directed to Bank 0 (GCL0 and corresponding Time related registers). 5 1 read-write BANK0 R/W in debug mode should be directed to Bank 0 0 BANK1 R/W in debug mode should be directed to Bank 1 0x1 ADDR Gate Control List Address: (GCLA when GCRR is "0"). 8 9 read-write ERR0 When set indicates the last write operation was aborted as software writes to GCL and GCL registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set. 20 1 read-write DISABLE ERR0 is disabled 0 ENABLE ERR1 is enabled 0x1 ESTEIEE EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register, enables the ECC error injection feature. 21 1 read-only DISABLE EST ECC Inject Error is disabled 0 ENABLE EST ECC Inject Error is enabled 0x1 ESTEIEC ECC Inject Error Control for EST Memory When EIEE bit of this register is set, following are the errors inserted based on the value encoded in this field. 22 2 read-only bf_1BIT Insert 1 bit error 0 bf_2BIT Insert 2 bit errors 0x1 bf_3BIT Insert 3 bit errors 0x2 bf_1BIT_ADDR Insert 1 bit error in address field 0x3 MTL_EST_GCL_DATA EST GCL Data 0xC84 32 read-write 0 0xFFFFFFFF GCD Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register. 0 32 read-write MTL_FPE_CTRL_STS Frame Preemption Control and Status 0xC90 32 read-write 0 0xFFFFFFFF AFSZ Additional Fragment Size used to indicate, in units of 64 bytes, the minimum number of bytes over 64 bytes required in non-final fragments of preempted frames. 0 2 read-write PEC Preemption Classification When set indicates the corresponding Queue must be classified as preemptable, when '0' Queue is classified as express. 8 5 read-write HRS Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State. 28 1 read-only SET_REL Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State 0 SET_HOLD Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State 0x1 MTL_FPE_ADVANCE Frame Preemption Hold and Release Advance 0xC94 32 read-write 0 0xFFFFFFFF HADV Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of transmission or any preemptable frames that are queued for transmission. 0 16 read-write RADV Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC and the MAC being ready to resume transmission of preemptable frames, in the absence of there being any express frames available for transmission. 16 16 read-write MTL_RXP_CONTROL_STATUS RXP Control Status 0xCA0 32 read-write 0x80FF00FF 0xFFFFFFFF NVE Number of valid entries in the Instruction table This control indicates the number of valid entries in the Instruction Memory. 0 8 read-write NPE Number of parsable entries in the Instruction table This control indicates the number of parsable entries in the Instruction Memory. 16 8 read-write RXPI RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State and waiting for a new packet for processing. 31 1 read-only INACTIVE RX Parser not in Idle state 0 ACTIVE RX Parser in Idle state 0x1 MTL_RXP_INTERRUPT_CONTROL_STATUS RXP Interrupt Control Status 0xCA4 32 read-write 0 0xFFFFFFFF NVEOVIS Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register), then this bit is set to 1. 0 1 read-write INACTIVE Number of Valid Entries Overflow Interrupt Status not detected 0 ACTIVE Number of Valid Entries Overflow Interrupt Status detected 0x1 NPEOVIS Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the number of parsed entries found to be more than NPE[] (Number of Parseable Entries in MTL_RXP_CONTROL register),then this bit is set to 1. 1 1 read-write INACTIVE Number of Parsable Entries Overflow Interrupt Status not detected 0 ACTIVE Number of Parsable Entries Overflow Interrupt Status detected 0x1 FOOVIS Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's 'Frame Offset' found to be more than EOF offset, then then this bit is set. 2 1 read-write INACTIVE Frame Offset Overflow Interrupt Status not detected 0 ACTIVE Frame Offset Overflow Interrupt Status detected 0x1 PDRFIS Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the packet by setting RF=1 in the instruction memory, then this bit is set to 1. 3 1 read-write INACTIVE Packet Dropped due to RF Interrupt Status not detected 0 ACTIVE Packet Dropped due to RF Interrupt Status detected 0x1 NVEOVIE Number of Valid Entries Overflow Interrupt Enable When this bit is set, the NVEOVIS interrupt is enabled. 16 1 read-write DISABLE Number of Valid Entries Overflow Interrupt is disabled 0 ENABLE Number of Valid Entries Overflow Interrupt is enabled 0x1 NPEOVIE Number of Parsable Entries Overflow Interrupt Enable When this bit is set, the NPEOVIS interrupt is enabled. 17 1 read-write DISABLE Number of Parsable Entries Overflow Interrupt is disabled 0 ENABLE Number of Parsable Entries Overflow Interrupt is enabled 0x1 FOOVIE Frame Offset Overflow Interrupt Enable When this bit is set, the FOOVIS interrupt is enabled. 18 1 read-write DISABLE Frame Offset Overflow Interrupt is disabled 0 ENABLE Frame Offset Overflow Interrupt is enabled 0x1 PDRFIE Packet Drop due to RF Interrupt Enable When this bit is set, the PDRFIS interrupt is enabled. 19 1 read-write DISABLE Packet Drop due to RF Interrupt is disabled 0 ENABLE Packet Drop due to RF Interrupt is enabled 0x1 MTL_RXP_DROP_CNT RXP Drop Count 0xCA8 32 read-only 0 0xFFFFFFFF RXPDC Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1. 0 31 read-only RXPDCOVF Rx Parser Drop Counter Overflow Bit When set, this bit indicates that the MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit. 31 1 read-only INACTIVE Rx Parser Drop count overflow not occurred 0 ACTIVE Rx Parser Drop count overflow occurred 0x1 MTL_RXP_ERROR_CNT RXP Error Count 0xCAC 32 read-only 0 0xFFFFFFFF RXPEC Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry address > EOF data entry address The counter is cleared when the register is read. 0 31 read-only RXPECOVF Rx Parser Error Counter Overflow Bit When set, this bit indicates that the MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit. 31 1 read-only INACTIVE Rx Parser Error count overflow not occurred 0 ACTIVE Rx Parser Error count overflow occurred 0x1 MTL_RXP_INDIRECT_ACC_CONTROL_STATUS RXP Indirect Access Control and Status 0xCB0 32 read-write 0 0xFFFFFFFF ADDR FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table. 0 10 read-write WRRDN Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory. 16 1 read-write READ Read operation to the Rx Parser Memory 0 WRITE Write operation to the Rx Parser Memory 0x1 STARTBUSY FRP Instruction Table Access Busy When this bit is set to 1 by the software then it indicates to start the Read/Write operation from/to the Rx Parser Memory. 31 1 read-write INACTIVE hardware not busy 0 ACTIVE hardware is busy (Read/Write operation from/to the Rx Parser Memory) 0x1 MTL_RXP_INDIRECT_ACC_DATA RXP Indirect Access Data 0xCB4 32 read-write 0 0xFFFFFFFF DATA FRP Instruction Table Write/Read Data Software should write this register before issuing any write command. 0 32 read-write MTL_TXQ0_OPERATION_MODE Queue 0 Transmit Operation Mode 0xD00 32 read-write 0 0xFFFFFFFF FTQ Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. 0 1 read-write DISABLE Flush Transmit Queue is disabled 0 ENABLE Flush Transmit Queue is enabled 0x1 TSF Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. 1 1 read-write DISABLE Transmit Store and Forward is disabled 0 ENABLE Transmit Store and Forward is enabled 0x1 TXQEN Transmit Queue Enable This field is used to enable/disable the transmit queue 0. 2 2 read-write DISABLE Not enabled 0 EN_IF_AV Enable in AV mode (Reserved in non-AV) 0x1 ENABLE Enabled 0x2 TTC Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. 4 3 read-write bf_32BYTES 32 0 bf_64BYTES 64 0x1 bf_96BYTES 96 0x2 bf_128BYTES 128 0x3 bf_192BYTES 192 0x4 bf_256BYTES 256 0x5 bf_384BYTES 384 0x6 bf_512BYTES 512 0x7 TQS Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. 16 5 read-write MTL_TXQ0_UNDERFLOW Queue 0 Underflow Counter 0xD04 32 read-only 0 0xFFFFFFFF UFFRMCNT Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. 0 11 read-only UFCNTOVF Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. 11 1 read-only INACTIVE Overflow not detected for Underflow Packet Counter 0 ACTIVE Overflow detected for Underflow Packet Counter 0x1 MTL_TXQ0_DEBUG Queue 0 Transmit Debug 0xD08 32 read-only 0 0xFFFFFFFF TXQPAUSED Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled - Reception of 802. 0 1 read-only INACTIVE Transmit Queue in Pause status is not detected 0 ACTIVE Transmit Queue in Pause status is detected 0x1 TRCSTS MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 1 2 read-only IDLE Idle state 0 READ Read state (transferring data to the MAC transmitter) 0x1 WAIT Waiting for pending Tx Status from the MAC transmitter 0x2 FLUSH Flushing the Tx queue because of the Packet Abort request from the MAC 0x3 TWCSTS MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx Queue Write Controller is active, and it is transferring the data to the Tx Queue. 3 1 read-only INACTIVE MTL Tx Queue Write Controller status is not detected 0 ACTIVE MTL Tx Queue Write Controller status is detected 0x1 TXQSTS MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 4 1 read-only INACTIVE MTL Tx Queue Not Empty status is not detected 0 ACTIVE MTL Tx Queue Not Empty status is detected 0x1 TXSTSFSTS MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. 5 1 read-only INACTIVE MTL Tx Status FIFO Full status is not detected 0 ACTIVE MTL Tx Status FIFO Full status is detected 0x1 PTXQ Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. 16 3 read-only STXSTSF Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. 20 3 read-only MTL_TXQ0_ETS_STATUS Queue 0 ETS Status 0xD14 32 read-only 0 0xFFFFFFFF ABS Average Bits per Slot This field contains the average transmitted bits per slot. 0 24 read-only MTL_TXQ0_QUANTUM_WEIGHT Queue 0 Quantum or Weights 0xD18 32 read-write 0 0xFFFFFFFF ISCQW Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic, this field contains the quantum value in bytes to be added to credit during every queue scanning cycle. 0 21 read-write MTL_Q0_INTERRUPT_CONTROL_STATUS Queue 0 Interrupt Control Status 0xD2C 32 read-write 0 0xFFFFFFFF TXUNFIS Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. 0 1 read-write INACTIVE Transmit Queue Underflow Interrupt Status not detected 0 ACTIVE Transmit Queue Underflow Interrupt Status detected 0x1 ABPSIS Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value. 1 1 read-write INACTIVE Average Bits Per Slot Interrupt Status not detected 0 ACTIVE Average Bits Per Slot Interrupt Status detected 0x1 TXUIE Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. 8 1 read-write DISABLE Transmit Queue Underflow Interrupt Status is disabled 0 ENABLE Transmit Queue Underflow Interrupt Status is enabled 0x1 ABPSIE Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. 9 1 read-write DISABLE Average Bits Per Slot Interrupt is disabled 0 ENABLE Average Bits Per Slot Interrupt is enabled 0x1 RXOVFIS Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. 16 1 read-write INACTIVE Receive Queue Overflow Interrupt Status not detected 0 ACTIVE Receive Queue Overflow Interrupt Status detected 0x1 RXOIE Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. 24 1 read-write DISABLE Receive Queue Overflow Interrupt is disabled 0 ENABLE Receive Queue Overflow Interrupt is enabled 0x1 MTL_RXQ0_OPERATION_MODE Queue 0 Receive Operation Mode 0xD30 32 read-write 0 0xFFFFFFFF RTC Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. 0 2 read-write bf_64BYTE 64 0 bf_32BYTE 32 0x1 bf_96BYTE 96 0x2 bf_128BYTE 128 0x3 FUP Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. 3 1 read-write DISABLE Forward Undersized Good Packets is disabled 0 ENABLE Forward Undersized Good Packets is enabled 0x1 FEP Forward Error Packets When this bit is reset, the Rx queue drops packets with error status (CRC error, GMII_ER, watchdog timeout, or overflow). 4 1 read-write DISABLE Forward Error Packets is disabled 0 ENABLE Forward Error Packets is enabled 0x1 RSF Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. 5 1 read-write DISABLE Receive Queue Store and Forward is disabled 0 ENABLE Receive Queue Store and Forward is enabled 0x1 DIS_TCP_EF Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. 6 1 read-write ENABLE Dropping of TCP/IP Checksum Error Packets is enabled 0 DISABLE Dropping of TCP/IP Checksum Error Packets is disabled 0x1 EHFC Enable Hardware Flow Control When this bit is set, the flow control signal operation, based on the fill-level of Rx queue, is enabled. 7 1 read-write DISABLE Hardware Flow Control is disabled 0 ENABLE Hardware Flow Control is enabled 0x1 RFA Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field, see RFD. 8 4 read-write RFD Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1. 14 4 read-write RQS Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. 20 5 read-write MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT Queue 0 Missed Packet and Overflow Counter 0xD34 32 read-only 0 0xFFFFFFFF OVFPKTCNT Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. 0 11 read-only OVFCNTOVF Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. 11 1 read-only INACTIVE Overflow Counter overflow not detected 0 ACTIVE Overflow Counter overflow detected 0x1 MISPKTCNT Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. 16 11 read-only MISCNTOVF Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. 27 1 read-only INACTIVE Missed Packet Counter overflow not detected 0 ACTIVE Missed Packet Counter overflow detected 0x1 MTL_RXQ0_DEBUG Queue 0 Receive Debug 0xD38 32 read-only 0 0xFFFFFFFF RWCSTS MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue. 0 1 read-only INACTIVE MTL Rx Queue Write Controller Active Status not detected 0 ACTIVE MTL Rx Queue Write Controller Active Status detected 0x1 RRCSTS MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 1 2 read-only IDLE Idle state 0 READ_DATA Reading packet data 0x1 READ_STS Reading packet status (or timestamp) 0x2 FLUSH Flushing the packet data and status 0x3 RXQSTS MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 4 2 read-only EMPTY Rx Queue empty 0 BLW_THR Rx Queue fill-level below flow-control deactivate threshold 0x1 ABV_THR Rx Queue fill-level above flow-control activate threshold 0x2 FULL Rx Queue full 0x3 PRXQ Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. 16 14 read-only MTL_RXQ0_CONTROL Queue 0 Receive Control 0xD3C 32 read-write 0 0xFFFFFFFF RXQ_WEGT Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. 0 3 read-write RXQ_FRM_ARBIT Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. 3 1 read-write DISABLE Receive Queue Packet Arbitration is disabled 0 ENABLE Receive Queue Packet Arbitration is enabled 0x1 MTL_TXQ1_OPERATION_MODE Queue 1 Transmit Operation Mode 0xD40 32 read-write 0 0xFFFFFFFF FTQ Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. 0 1 read-write DISABLE Flush Transmit Queue is disabled 0 ENABLE Flush Transmit Queue is enabled 0x1 TSF Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. 1 1 read-write DISABLE Transmit Store and Forward is disabled 0 ENABLE Transmit Store and Forward is enabled 0x1 TXQEN Transmit Queue Enable This field is used to enable/disable the transmit queue 0. 2 2 read-write DISABLE Not enabled 0 EN_IF_AV Enable in AV mode (Reserved in non-AV) 0x1 ENABLE Enabled 0x2 TTC Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. 4 3 read-write bf_32BYTES 32 0 bf_64BYTES 64 0x1 bf_96BYTES 96 0x2 bf_128BYTES 128 0x3 bf_192BYTES 192 0x4 bf_256BYTES 256 0x5 bf_384BYTES 384 0x6 bf_512BYTES 512 0x7 TQS Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. 16 5 read-write MTL_TXQ1_UNDERFLOW Queue 1 Underflow Counter 0xD44 32 read-only 0 0xFFFFFFFF UFFRMCNT Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. 0 11 read-only UFCNTOVF Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. 11 1 read-only INACTIVE Overflow not detected for Underflow Packet Counter 0 ACTIVE Overflow detected for Underflow Packet Counter 0x1 MTL_TXQ1_DEBUG Queue 1 Transmit Debug 0xD48 32 read-only 0 0xFFFFFFFF TXQPAUSED Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled - Reception of 802. 0 1 read-only INACTIVE Transmit Queue in Pause status is not detected 0 ACTIVE Transmit Queue in Pause status is detected 0x1 TRCSTS MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 1 2 read-only IDLE Idle state 0 READ Read state (transferring data to the MAC transmitter) 0x1 WAIT Waiting for pending Tx Status from the MAC transmitter 0x2 FLUSH Flushing the Tx queue because of the Packet Abort request from the MAC 0x3 TWCSTS MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx Queue Write Controller is active, and it is transferring the data to the Tx Queue. 3 1 read-only INACTIVE MTL Tx Queue Write Controller status is not detected 0 ACTIVE MTL Tx Queue Write Controller status is detected 0x1 TXQSTS MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 4 1 read-only INACTIVE MTL Tx Queue Not Empty status is not detected 0 ACTIVE MTL Tx Queue Not Empty status is detected 0x1 TXSTSFSTS MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. 5 1 read-only INACTIVE MTL Tx Status FIFO Full status is not detected 0 ACTIVE MTL Tx Status FIFO Full status is detected 0x1 PTXQ Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. 16 3 read-only STXSTSF Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. 20 3 read-only MTL_TXQ1_ETS_CONTROL Queue 1 ETS Control 0xD50 32 read-write 0 0xFFFFFFFF AVALG AV Algorithm When Queue 1 is programmed for AV, this field configures the scheduling algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. 2 1 read-write DISABLE CBS Algorithm is disabled 0 ENABLE CBS Algorithm is enabled 0x1 CC Credit Control When this bit is set, the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. 3 1 read-write DISABLE Credit Control is disabled 0 ENABLE Credit Control is enabled 0x1 SLC Slot Count If the credit-based shaper algorithm is enabled, the software can program the number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the average transmitted bits per slot, provided in the MTL_TXQ[N]_ETS_STATUS register, need to be computed for Queue. 4 3 read-write bf_1_SLOT 1 slot 0 bf_2_SLOT 2 slots 0x1 bf_4_SLOT 4 slots 0x2 bf_8_SLOT 8 slots 0x3 bf_16_SLOT 16 slots 0x4 MTL_TXQ1_ETS_STATUS Queue 1 ETS Status 0xD54 32 read-only 0 0xFFFFFFFF ABS Average Bits per Slot This field contains the average transmitted bits per slot. 0 24 read-only MTL_TXQ1_QUANTUM_WEIGHT Queue 1 idleSlopeCredit, Quantum or Weights 0xD58 32 read-write 0 0xFFFFFFFF ISCQW idleSlopeCredit, Quantum or Weights - idleSlopeCredit When AV feature is enabled, this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. 0 21 read-write MTL_TXQ1_SENDSLOPECREDIT Queue 1 sendSlopeCredit 0xD5C 32 read-write 0 0xFFFFFFFF SSC sendSlopeCredit Value When AV operation is enabled, this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. 0 14 read-write MTL_TXQ1_HICREDIT Queue 1 hiCredit 0xD60 32 read-write 0 0xFFFFFFFF HC hiCredit Value When the AV feature is enabled, this field contains the hiCredit value required for the credit-based shaper algorithm. 0 29 read-write MTL_TXQ1_LOCREDIT Queue 1 loCredit 0xD64 32 read-write 0 0xFFFFFFFF LC loCredit Value When AV operation is enabled, this field contains the loCredit value required for the credit-based shaper algorithm. 0 29 read-write MTL_Q1_INTERRUPT_CONTROL_STATUS Queue 1 Interrupt Control Status 0xD6C 32 read-write 0 0xFFFFFFFF TXUNFIS Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. 0 1 read-write INACTIVE Transmit Queue Underflow Interrupt Status not detected 0 ACTIVE Transmit Queue Underflow Interrupt Status detected 0x1 ABPSIS Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value. 1 1 read-write INACTIVE Average Bits Per Slot Interrupt Status not detected 0 ACTIVE Average Bits Per Slot Interrupt Status detected 0x1 TXUIE Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. 8 1 read-write DISABLE Transmit Queue Underflow Interrupt Status is disabled 0 ENABLE Transmit Queue Underflow Interrupt Status is enabled 0x1 ABPSIE Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. 9 1 read-write DISABLE Average Bits Per Slot Interrupt is disabled 0 ENABLE Average Bits Per Slot Interrupt is enabled 0x1 RXOVFIS Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. 16 1 read-write INACTIVE Receive Queue Overflow Interrupt Status not detected 0 ACTIVE Receive Queue Overflow Interrupt Status detected 0x1 RXOIE Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. 24 1 read-write DISABLE Receive Queue Overflow Interrupt is disabled 0 ENABLE Receive Queue Overflow Interrupt is enabled 0x1 MTL_RXQ1_OPERATION_MODE Queue 1 Receive Operation Mode 0xD70 32 read-write 0 0xFFFFFFFF RTC Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. 0 2 read-write bf_64BYTE 64 0 bf_32BYTE 32 0x1 bf_96BYTE 96 0x2 bf_128BYTE 128 0x3 FUP Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. 3 1 read-write DISABLE Forward Undersized Good Packets is disabled 0 ENABLE Forward Undersized Good Packets is enabled 0x1 FEP Forward Error Packets When this bit is reset, the Rx queue drops packets with error status (CRC error, GMII_ER, watchdog timeout, or overflow). 4 1 read-write DISABLE Forward Error Packets is disabled 0 ENABLE Forward Error Packets is enabled 0x1 RSF Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. 5 1 read-write DISABLE Receive Queue Store and Forward is disabled 0 ENABLE Receive Queue Store and Forward is enabled 0x1 DIS_TCP_EF Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. 6 1 read-write ENABLE Dropping of TCP/IP Checksum Error Packets is enabled 0 DISABLE Dropping of TCP/IP Checksum Error Packets is disabled 0x1 EHFC Enable Hardware Flow Control When this bit is set, the flow control signal operation, based on the fill-level of Rx queue, is enabled. 7 1 read-write DISABLE Hardware Flow Control is disabled 0 ENABLE Hardware Flow Control is enabled 0x1 RFA Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field, see RFD. 8 4 read-write RFD Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1. 14 4 read-write RQS Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. 20 5 read-write MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT Queue 1 Missed Packet and Overflow Counter 0xD74 32 read-only 0 0xFFFFFFFF OVFPKTCNT Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. 0 11 read-only OVFCNTOVF Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. 11 1 read-only INACTIVE Overflow Counter overflow not detected 0 ACTIVE Overflow Counter overflow detected 0x1 MISPKTCNT Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. 16 11 read-only MISCNTOVF Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. 27 1 read-only INACTIVE Missed Packet Counter overflow not detected 0 ACTIVE Missed Packet Counter overflow detected 0x1 MTL_RXQ1_DEBUG Queue 1 Receive Debug 0xD78 32 read-only 0 0xFFFFFFFF RWCSTS MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue. 0 1 read-only INACTIVE MTL Rx Queue Write Controller Active Status not detected 0 ACTIVE MTL Rx Queue Write Controller Active Status detected 0x1 RRCSTS MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 1 2 read-only IDLE Idle state 0 READ_DATA Reading packet data 0x1 READ_STS Reading packet status (or timestamp) 0x2 FLUSH Flushing the packet data and status 0x3 RXQSTS MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 4 2 read-only EMPTY Rx Queue empty 0 BLW_THR Rx Queue fill-level below flow-control deactivate threshold 0x1 ABV_THR Rx Queue fill-level above flow-control activate threshold 0x2 FULL Rx Queue full 0x3 PRXQ Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. 16 14 read-only MTL_RXQ1_CONTROL Queue 1 Receive Control 0xD7C 32 read-write 0 0xFFFFFFFF RXQ_WEGT Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. 0 3 read-write RXQ_FRM_ARBIT Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. 3 1 read-write DISABLE Receive Queue Packet Arbitration is disabled 0 ENABLE Receive Queue Packet Arbitration is enabled 0x1 MTL_TXQ2_OPERATION_MODE Queue 2 Transmit Operation Mode 0xD80 32 read-write 0 0xFFFFFFFF FTQ Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. 0 1 read-write DISABLE Flush Transmit Queue is disabled 0 ENABLE Flush Transmit Queue is enabled 0x1 TSF Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. 1 1 read-write DISABLE Transmit Store and Forward is disabled 0 ENABLE Transmit Store and Forward is enabled 0x1 TXQEN Transmit Queue Enable This field is used to enable/disable the transmit queue 0. 2 2 read-write DISABLE Not enabled 0 EN_IF_AV Enable in AV mode (Reserved in non-AV) 0x1 ENABLE Enabled 0x2 TTC Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. 4 3 read-write bf_32BYTES 32 0 bf_64BYTES 64 0x1 bf_96BYTES 96 0x2 bf_128BYTES 128 0x3 bf_192BYTES 192 0x4 bf_256BYTES 256 0x5 bf_384BYTES 384 0x6 bf_512BYTES 512 0x7 TQS Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. 16 5 read-write MTL_TXQ2_UNDERFLOW Queue 2 Underflow Counter 0xD84 32 read-only 0 0xFFFFFFFF UFFRMCNT Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. 0 11 read-only UFCNTOVF Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. 11 1 read-only INACTIVE Overflow not detected for Underflow Packet Counter 0 ACTIVE Overflow detected for Underflow Packet Counter 0x1 MTL_TXQ2_DEBUG Queue 2 Transmit Debug 0xD88 32 read-only 0 0xFFFFFFFF TXQPAUSED Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled - Reception of 802. 0 1 read-only INACTIVE Transmit Queue in Pause status is not detected 0 ACTIVE Transmit Queue in Pause status is detected 0x1 TRCSTS MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 1 2 read-only IDLE Idle state 0 READ Read state (transferring data to the MAC transmitter) 0x1 WAIT Waiting for pending Tx Status from the MAC transmitter 0x2 FLUSH Flushing the Tx queue because of the Packet Abort request from the MAC 0x3 TWCSTS MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx Queue Write Controller is active, and it is transferring the data to the Tx Queue. 3 1 read-only INACTIVE MTL Tx Queue Write Controller status is not detected 0 ACTIVE MTL Tx Queue Write Controller status is detected 0x1 TXQSTS MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 4 1 read-only INACTIVE MTL Tx Queue Not Empty status is not detected 0 ACTIVE MTL Tx Queue Not Empty status is detected 0x1 TXSTSFSTS MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. 5 1 read-only INACTIVE MTL Tx Status FIFO Full status is not detected 0 ACTIVE MTL Tx Status FIFO Full status is detected 0x1 PTXQ Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. 16 3 read-only STXSTSF Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. 20 3 read-only MTL_TXQ2_ETS_CONTROL Queue 2 ETS Control 0xD90 32 read-write 0 0xFFFFFFFF AVALG AV Algorithm When Queue 1 is programmed for AV, this field configures the scheduling algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. 2 1 read-write DISABLE CBS Algorithm is disabled 0 ENABLE CBS Algorithm is enabled 0x1 CC Credit Control When this bit is set, the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. 3 1 read-write DISABLE Credit Control is disabled 0 ENABLE Credit Control is enabled 0x1 SLC Slot Count If the credit-based shaper algorithm is enabled, the software can program the number of slots (of duration programmed in DMA_CH[N]_SLOT_INTERVAL register) over which the average transmitted bits per slot, provided in the MTL_TXQ[N]_ETS_STATUS register, need to be computed for Queue. 4 3 read-write bf_1_SLOT 1 slot 0 bf_2_SLOT 2 slots 0x1 bf_4_SLOT 4 slots 0x2 bf_8_SLOT 8 slots 0x3 bf_16_SLOT 16 slots 0x4 MTL_TXQ2_ETS_STATUS Queue 2 ETS Status 0xD94 32 read-only 0 0xFFFFFFFF ABS Average Bits per Slot This field contains the average transmitted bits per slot. 0 24 read-only MTL_TXQ2_QUANTUM_WEIGHT Queue 2 idleSlopeCredit, Quantum or Weights 0xD98 32 read-write 0 0xFFFFFFFF ISCQW idleSlopeCredit, Quantum or Weights - idleSlopeCredit When AV feature is enabled, this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. 0 21 read-write MTL_TXQ2_SENDSLOPECREDIT Queue 2 sendSlopeCredit 0xD9C 32 read-write 0 0xFFFFFFFF SSC sendSlopeCredit Value When AV operation is enabled, this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. 0 14 read-write MTL_TXQ2_HICREDIT Queue 2 hiCredit 0xDA0 32 read-write 0 0xFFFFFFFF HC hiCredit Value When the AV feature is enabled, this field contains the hiCredit value required for the credit-based shaper algorithm. 0 29 read-write MTL_TXQ2_LOCREDIT Queue 2 loCredit 0xDA4 32 read-write 0 0xFFFFFFFF LC loCredit Value When AV operation is enabled, this field contains the loCredit value required for the credit-based shaper algorithm. 0 29 read-write MTL_Q2_INTERRUPT_CONTROL_STATUS Queue 2 Interrupt Control Status 0xDAC 32 read-write 0 0xFFFFFFFF TXUNFIS Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. 0 1 read-write INACTIVE Transmit Queue Underflow Interrupt Status not detected 0 ACTIVE Transmit Queue Underflow Interrupt Status detected 0x1 ABPSIS Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value. 1 1 read-write INACTIVE Average Bits Per Slot Interrupt Status not detected 0 ACTIVE Average Bits Per Slot Interrupt Status detected 0x1 TXUIE Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. 8 1 read-write DISABLE Transmit Queue Underflow Interrupt Status is disabled 0 ENABLE Transmit Queue Underflow Interrupt Status is enabled 0x1 ABPSIE Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. 9 1 read-write DISABLE Average Bits Per Slot Interrupt is disabled 0 ENABLE Average Bits Per Slot Interrupt is enabled 0x1 RXOVFIS Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. 16 1 read-write INACTIVE Receive Queue Overflow Interrupt Status not detected 0 ACTIVE Receive Queue Overflow Interrupt Status detected 0x1 RXOIE Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. 24 1 read-write DISABLE Receive Queue Overflow Interrupt is disabled 0 ENABLE Receive Queue Overflow Interrupt is enabled 0x1 MTL_RXQ2_OPERATION_MODE Queue 2 Receive Operation Mode 0xDB0 32 read-write 0 0xFFFFFFFF RTC Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. 0 2 read-write bf_64BYTE 64 0 bf_32BYTE 32 0x1 bf_96BYTE 96 0x2 bf_128BYTE 128 0x3 FUP Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. 3 1 read-write DISABLE Forward Undersized Good Packets is disabled 0 ENABLE Forward Undersized Good Packets is enabled 0x1 FEP Forward Error Packets When this bit is reset, the Rx queue drops packets with error status (CRC error, GMII_ER, watchdog timeout, or overflow). 4 1 read-write DISABLE Forward Error Packets is disabled 0 ENABLE Forward Error Packets is enabled 0x1 RSF Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. 5 1 read-write DISABLE Receive Queue Store and Forward is disabled 0 ENABLE Receive Queue Store and Forward is enabled 0x1 DIS_TCP_EF Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. 6 1 read-write ENABLE Dropping of TCP/IP Checksum Error Packets is enabled 0 DISABLE Dropping of TCP/IP Checksum Error Packets is disabled 0x1 EHFC Enable Hardware Flow Control When this bit is set, the flow control signal operation, based on the fill-level of Rx queue, is enabled. 7 1 read-write DISABLE Hardware Flow Control is disabled 0 ENABLE Hardware Flow Control is enabled 0x1 RFA Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field, see RFD. 8 4 read-write RFD Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1. 14 4 read-write RQS Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. 20 5 read-write MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT Queue 2 Missed Packet and Overflow Counter 0xDB4 32 read-only 0 0xFFFFFFFF OVFPKTCNT Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. 0 11 read-only OVFCNTOVF Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. 11 1 read-only INACTIVE Overflow Counter overflow not detected 0 ACTIVE Overflow Counter overflow detected 0x1 MISPKTCNT Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. 16 11 read-only MISCNTOVF Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. 27 1 read-only INACTIVE Missed Packet Counter overflow not detected 0 ACTIVE Missed Packet Counter overflow detected 0x1 MTL_RXQ2_DEBUG Queue 2 Receive Debug 0xDB8 32 read-only 0 0xFFFFFFFF RWCSTS MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue. 0 1 read-only INACTIVE MTL Rx Queue Write Controller Active Status not detected 0 ACTIVE MTL Rx Queue Write Controller Active Status detected 0x1 RRCSTS MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 1 2 read-only IDLE Idle state 0 READ_DATA Reading packet data 0x1 READ_STS Reading packet status (or timestamp) 0x2 FLUSH Flushing the packet data and status 0x3 RXQSTS MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 4 2 read-only EMPTY Rx Queue empty 0 BLW_THR Rx Queue fill-level below flow-control deactivate threshold 0x1 ABV_THR Rx Queue fill-level above flow-control activate threshold 0x2 FULL Rx Queue full 0x3 PRXQ Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. 16 14 read-only MTL_RXQ2_CONTROL Queue 2 Receive Control 0xDBC 32 read-write 0 0xFFFFFFFF RXQ_WEGT Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. 0 3 read-write RXQ_FRM_ARBIT Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. 3 1 read-write DISABLE Receive Queue Packet Arbitration is disabled 0 ENABLE Receive Queue Packet Arbitration is enabled 0x1 MTL_TXQ3_OPERATION_MODE Queue 3 Transmit Operation Mode 0xDC0 32 read-write 0 0xFFFFFFFF FTQ Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. 0 1 read-write DISABLE Flush Transmit Queue is disabled 0 ENABLE Flush Transmit Queue is enabled 0x1 TSF Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. 1 1 read-write DISABLE Transmit Store and Forward is disabled 0 ENABLE Transmit Store and Forward is enabled 0x1 TXQEN Transmit Queue Enable This field is used to enable/disable the transmit queue 0. 2 2 read-write DISABLE Not enabled 0 EN_IF_AV Enable in AV mode (Reserved in non-AV) 0x1 ENABLE Enabled 0x2 TTC Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. 4 3 read-write bf_32BYTES 32 0 bf_64BYTES 64 0x1 bf_96BYTES 96 0x2 bf_128BYTES 128 0x3 bf_192BYTES 192 0x4 bf_256BYTES 256 0x5 bf_384BYTES 384 0x6 bf_512BYTES 512 0x7 TQS Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. 16 5 read-write MTL_TXQ3_UNDERFLOW Queue 3 Underflow Counter 0xDC4 32 read-only 0 0xFFFFFFFF UFFRMCNT Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. 0 11 read-only UFCNTOVF Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. 11 1 read-only INACTIVE Overflow not detected for Underflow Packet Counter 0 ACTIVE Overflow detected for Underflow Packet Counter 0x1 MTL_TXQ3_DEBUG Queue 3 Transmit Debug 0xDC8 32 read-only 0 0xFFFFFFFF TXQPAUSED Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled - Reception of 802. 0 1 read-only INACTIVE Transmit Queue in Pause status is not detected 0 ACTIVE Transmit Queue in Pause status is detected 0x1 TRCSTS MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 1 2 read-only IDLE Idle state 0 READ Read state (transferring data to the MAC transmitter) 0x1 WAIT Waiting for pending Tx Status from the MAC transmitter 0x2 FLUSH Flushing the Tx queue because of the Packet Abort request from the MAC 0x3 TWCSTS MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx Queue Write Controller is active, and it is transferring the data to the Tx Queue. 3 1 read-only INACTIVE MTL Tx Queue Write Controller status is not detected 0 ACTIVE MTL Tx Queue Write Controller status is detected 0x1 TXQSTS MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 4 1 read-only INACTIVE MTL Tx Queue Not Empty status is not detected 0 ACTIVE MTL Tx Queue Not Empty status is detected 0x1 TXSTSFSTS MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. 5 1 read-only INACTIVE MTL Tx Status FIFO Full status is not detected 0 ACTIVE MTL Tx Status FIFO Full status is detected 0x1 PTXQ Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. 16 3 read-only STXSTSF Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. 20 3 read-only MTL_TXQ3_ETS_CONTROL Queue 3 ETS Control 0xDD0 32 read-write 0 0xFFFFFFFF AVALG AV Algorithm When Queue 1 is programmed for AV, this field configures the scheduling algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. 2 1 read-write DISABLE CBS Algorithm is disabled 0 ENABLE CBS Algorithm is enabled 0x1 CC Credit Control When this bit is set, the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. 3 1 read-write DISABLE Credit Control is disabled 0 ENABLE Credit Control is enabled 0x1 SLC Slot Count If the credit-based shaper algorithm is enabled, the software can program the number of slots (of duration programmed in DMA_CH[N]_SLOT_INTERVAL register) over which the average transmitted bits per slot, provided in the MTL_TXQ[N]_ETS_STATUS register, need to be computed for Queue. 4 3 read-write bf_1_SLOT 1 slot 0 bf_2_SLOT 2 slots 0x1 bf_4_SLOT 4 slots 0x2 bf_8_SLOT 8 slots 0x3 bf_16_SLOT 16 slots 0x4 MTL_TXQ3_ETS_STATUS Queue 3 ETS Status 0xDD4 32 read-only 0 0xFFFFFFFF ABS Average Bits per Slot This field contains the average transmitted bits per slot. 0 24 read-only MTL_TXQ3_QUANTUM_WEIGHT Queue 3 idleSlopeCredit, Quantum or Weights 0xDD8 32 read-write 0 0xFFFFFFFF ISCQW idleSlopeCredit, Quantum or Weights - idleSlopeCredit When AV feature is enabled, this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. 0 21 read-write MTL_TXQ3_SENDSLOPECREDIT Queue 3 sendSlopeCredit 0xDDC 32 read-write 0 0xFFFFFFFF SSC sendSlopeCredit Value When AV operation is enabled, this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. 0 14 read-write MTL_TXQ3_HICREDIT Queue 3 hiCredit 0xDE0 32 read-write 0 0xFFFFFFFF HC hiCredit Value When the AV feature is enabled, this field contains the hiCredit value required for the credit-based shaper algorithm. 0 29 read-write MTL_TXQ3_LOCREDIT Queue 3 loCredit 0xDE4 32 read-write 0 0xFFFFFFFF LC loCredit Value When AV operation is enabled, this field contains the loCredit value required for the credit-based shaper algorithm. 0 29 read-write MTL_Q3_INTERRUPT_CONTROL_STATUS Queue 3 Interrupt Control Status 0xDEC 32 read-write 0 0xFFFFFFFF TXUNFIS Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. 0 1 read-write INACTIVE Transmit Queue Underflow Interrupt Status not detected 0 ACTIVE Transmit Queue Underflow Interrupt Status detected 0x1 ABPSIS Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value. 1 1 read-write INACTIVE Average Bits Per Slot Interrupt Status not detected 0 ACTIVE Average Bits Per Slot Interrupt Status detected 0x1 TXUIE Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. 8 1 read-write DISABLE Transmit Queue Underflow Interrupt Status is disabled 0 ENABLE Transmit Queue Underflow Interrupt Status is enabled 0x1 ABPSIE Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. 9 1 read-write DISABLE Average Bits Per Slot Interrupt is disabled 0 ENABLE Average Bits Per Slot Interrupt is enabled 0x1 RXOVFIS Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. 16 1 read-write INACTIVE Receive Queue Overflow Interrupt Status not detected 0 ACTIVE Receive Queue Overflow Interrupt Status detected 0x1 RXOIE Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. 24 1 read-write DISABLE Receive Queue Overflow Interrupt is disabled 0 ENABLE Receive Queue Overflow Interrupt is enabled 0x1 MTL_RXQ3_OPERATION_MODE Queue 3 Receive Operation Mode 0xDF0 32 read-write 0 0xFFFFFFFF RTC Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. 0 2 read-write bf_64BYTE 64 0 bf_32BYTE 32 0x1 bf_96BYTE 96 0x2 bf_128BYTE 128 0x3 FUP Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. 3 1 read-write DISABLE Forward Undersized Good Packets is disabled 0 ENABLE Forward Undersized Good Packets is enabled 0x1 FEP Forward Error Packets When this bit is reset, the Rx queue drops packets with error status (CRC error, GMII_ER, watchdog timeout, or overflow). 4 1 read-write DISABLE Forward Error Packets is disabled 0 ENABLE Forward Error Packets is enabled 0x1 RSF Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. 5 1 read-write DISABLE Receive Queue Store and Forward is disabled 0 ENABLE Receive Queue Store and Forward is enabled 0x1 DIS_TCP_EF Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. 6 1 read-write ENABLE Dropping of TCP/IP Checksum Error Packets is enabled 0 DISABLE Dropping of TCP/IP Checksum Error Packets is disabled 0x1 EHFC Enable Hardware Flow Control When this bit is set, the flow control signal operation, based on the fill-level of Rx queue, is enabled. 7 1 read-write DISABLE Hardware Flow Control is disabled 0 ENABLE Hardware Flow Control is enabled 0x1 RFA Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field, see RFD. 8 4 read-write RFD Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1. 14 4 read-write RQS Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. 20 5 read-write MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT Queue 3 Missed Packet and Overflow Counter 0xDF4 32 read-only 0 0xFFFFFFFF OVFPKTCNT Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. 0 11 read-only OVFCNTOVF Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. 11 1 read-only INACTIVE Overflow Counter overflow not detected 0 ACTIVE Overflow Counter overflow detected 0x1 MISPKTCNT Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. 16 11 read-only MISCNTOVF Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. 27 1 read-only INACTIVE Missed Packet Counter overflow not detected 0 ACTIVE Missed Packet Counter overflow detected 0x1 MTL_RXQ3_DEBUG Queue 3 Receive Debug 0xDF8 32 read-only 0 0xFFFFFFFF RWCSTS MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue. 0 1 read-only INACTIVE MTL Rx Queue Write Controller Active Status not detected 0 ACTIVE MTL Rx Queue Write Controller Active Status detected 0x1 RRCSTS MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 1 2 read-only IDLE Idle state 0 READ_DATA Reading packet data 0x1 READ_STS Reading packet status (or timestamp) 0x2 FLUSH Flushing the packet data and status 0x3 RXQSTS MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 4 2 read-only EMPTY Rx Queue empty 0 BLW_THR Rx Queue fill-level below flow-control deactivate threshold 0x1 ABV_THR Rx Queue fill-level above flow-control activate threshold 0x2 FULL Rx Queue full 0x3 PRXQ Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. 16 14 read-only MTL_RXQ3_CONTROL Queue 3 Receive Control 0xDFC 32 read-write 0 0xFFFFFFFF RXQ_WEGT Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. 0 3 read-write RXQ_FRM_ARBIT Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. 3 1 read-write DISABLE Receive Queue Packet Arbitration is disabled 0 ENABLE Receive Queue Packet Arbitration is enabled 0x1 MTL_TXQ4_OPERATION_MODE Queue 4 Transmit Operation Mode 0xE00 32 read-write 0 0xFFFFFFFF FTQ Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. 0 1 read-write DISABLE Flush Transmit Queue is disabled 0 ENABLE Flush Transmit Queue is enabled 0x1 TSF Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. 1 1 read-write DISABLE Transmit Store and Forward is disabled 0 ENABLE Transmit Store and Forward is enabled 0x1 TXQEN Transmit Queue Enable This field is used to enable/disable the transmit queue 0. 2 2 read-write DISABLE Not enabled 0 EN_IF_AV Enable in AV mode (Reserved in non-AV) 0x1 ENABLE Enabled 0x2 TTC Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. 4 3 read-write bf_32BYTES 32 0 bf_64BYTES 64 0x1 bf_96BYTES 96 0x2 bf_128BYTES 128 0x3 bf_192BYTES 192 0x4 bf_256BYTES 256 0x5 bf_384BYTES 384 0x6 bf_512BYTES 512 0x7 TQS Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. 16 5 read-write MTL_TXQ4_UNDERFLOW Queue 4 Underflow Counter 0xE04 32 read-only 0 0xFFFFFFFF UFFRMCNT Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. 0 11 read-only UFCNTOVF Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. 11 1 read-only INACTIVE Overflow not detected for Underflow Packet Counter 0 ACTIVE Overflow detected for Underflow Packet Counter 0x1 MTL_TXQ4_DEBUG Queue 4 Transmit Debug 0xE08 32 read-only 0 0xFFFFFFFF TXQPAUSED Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled - Reception of 802. 0 1 read-only INACTIVE Transmit Queue in Pause status is not detected 0 ACTIVE Transmit Queue in Pause status is detected 0x1 TRCSTS MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 1 2 read-only IDLE Idle state 0 READ Read state (transferring data to the MAC transmitter) 0x1 WAIT Waiting for pending Tx Status from the MAC transmitter 0x2 FLUSH Flushing the Tx queue because of the Packet Abort request from the MAC 0x3 TWCSTS MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx Queue Write Controller is active, and it is transferring the data to the Tx Queue. 3 1 read-only INACTIVE MTL Tx Queue Write Controller status is not detected 0 ACTIVE MTL Tx Queue Write Controller status is detected 0x1 TXQSTS MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 4 1 read-only INACTIVE MTL Tx Queue Not Empty status is not detected 0 ACTIVE MTL Tx Queue Not Empty status is detected 0x1 TXSTSFSTS MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. 5 1 read-only INACTIVE MTL Tx Status FIFO Full status is not detected 0 ACTIVE MTL Tx Status FIFO Full status is detected 0x1 PTXQ Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. 16 3 read-only STXSTSF Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. 20 3 read-only MTL_TXQ4_ETS_CONTROL Queue 4 ETS Control 0xE10 32 read-write 0 0xFFFFFFFF AVALG AV Algorithm When Queue 1 is programmed for AV, this field configures the scheduling algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. 2 1 read-write DISABLE CBS Algorithm is disabled 0 ENABLE CBS Algorithm is enabled 0x1 CC Credit Control When this bit is set, the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. 3 1 read-write DISABLE Credit Control is disabled 0 ENABLE Credit Control is enabled 0x1 SLC Slot Count If the credit-based shaper algorithm is enabled, the software can program the number of slots (of duration programmed in DMA_CH[N]_SLOT_INTERVAL register) over which the average transmitted bits per slot, provided in the MTL_TXQ[N]_ETS_STATUS register, need to be computed for Queue. 4 3 read-write bf_1_SLOT 1 slot 0 bf_2_SLOT 2 slots 0x1 bf_4_SLOT 4 slots 0x2 bf_8_SLOT 8 slots 0x3 bf_16_SLOT 16 slots 0x4 MTL_TXQ4_ETS_STATUS Queue 4 ETS Status 0xE14 32 read-only 0 0xFFFFFFFF ABS Average Bits per Slot This field contains the average transmitted bits per slot. 0 24 read-only MTL_TXQ4_QUANTUM_WEIGHT Queue 4 idleSlopeCredit, Quantum or Weights 0xE18 32 read-write 0 0xFFFFFFFF ISCQW idleSlopeCredit, Quantum or Weights - idleSlopeCredit When AV feature is enabled, this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. 0 21 read-write MTL_TXQ4_SENDSLOPECREDIT Queue 4 sendSlopeCredit 0xE1C 32 read-write 0 0xFFFFFFFF SSC sendSlopeCredit Value When AV operation is enabled, this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. 0 14 read-write MTL_TXQ4_HICREDIT Queue 4 hiCredit 0xE20 32 read-write 0 0xFFFFFFFF HC hiCredit Value When the AV feature is enabled, this field contains the hiCredit value required for the credit-based shaper algorithm. 0 29 read-write MTL_TXQ4_LOCREDIT Queue 4 loCredit 0xE24 32 read-write 0 0xFFFFFFFF LC loCredit Value When AV operation is enabled, this field contains the loCredit value required for the credit-based shaper algorithm. 0 29 read-write MTL_Q4_INTERRUPT_CONTROL_STATUS Queue 4 Interrupt Control Status 0xE2C 32 read-write 0 0xFFFFFFFF TXUNFIS Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. 0 1 read-write INACTIVE Transmit Queue Underflow Interrupt Status not detected 0 ACTIVE Transmit Queue Underflow Interrupt Status detected 0x1 ABPSIS Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value. 1 1 read-write INACTIVE Average Bits Per Slot Interrupt Status not detected 0 ACTIVE Average Bits Per Slot Interrupt Status detected 0x1 TXUIE Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. 8 1 read-write DISABLE Transmit Queue Underflow Interrupt Status is disabled 0 ENABLE Transmit Queue Underflow Interrupt Status is enabled 0x1 ABPSIE Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. 9 1 read-write DISABLE Average Bits Per Slot Interrupt is disabled 0 ENABLE Average Bits Per Slot Interrupt is enabled 0x1 RXOVFIS Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. 16 1 read-write INACTIVE Receive Queue Overflow Interrupt Status not detected 0 ACTIVE Receive Queue Overflow Interrupt Status detected 0x1 RXOIE Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. 24 1 read-write DISABLE Receive Queue Overflow Interrupt is disabled 0 ENABLE Receive Queue Overflow Interrupt is enabled 0x1 MTL_RXQ4_OPERATION_MODE Queue 4 Receive Operation Mode 0xE30 32 read-write 0 0xFFFFFFFF RTC Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. 0 2 read-write bf_64BYTE 64 0 bf_32BYTE 32 0x1 bf_96BYTE 96 0x2 bf_128BYTE 128 0x3 FUP Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. 3 1 read-write DISABLE Forward Undersized Good Packets is disabled 0 ENABLE Forward Undersized Good Packets is enabled 0x1 FEP Forward Error Packets When this bit is reset, the Rx queue drops packets with error status (CRC error, GMII_ER, watchdog timeout, or overflow). 4 1 read-write DISABLE Forward Error Packets is disabled 0 ENABLE Forward Error Packets is enabled 0x1 RSF Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. 5 1 read-write DISABLE Receive Queue Store and Forward is disabled 0 ENABLE Receive Queue Store and Forward is enabled 0x1 DIS_TCP_EF Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. 6 1 read-write ENABLE Dropping of TCP/IP Checksum Error Packets is enabled 0 DISABLE Dropping of TCP/IP Checksum Error Packets is disabled 0x1 EHFC Enable Hardware Flow Control When this bit is set, the flow control signal operation, based on the fill-level of Rx queue, is enabled. 7 1 read-write DISABLE Hardware Flow Control is disabled 0 ENABLE Hardware Flow Control is enabled 0x1 RFA Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field, see RFD. 8 4 read-write RFD Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1. 14 4 read-write RQS Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. 20 5 read-write MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT Queue 4 Missed Packet and Overflow Counter 0xE34 32 read-only 0 0xFFFFFFFF OVFPKTCNT Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. 0 11 read-only OVFCNTOVF Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. 11 1 read-only INACTIVE Overflow Counter overflow not detected 0 ACTIVE Overflow Counter overflow detected 0x1 MISPKTCNT Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. 16 11 read-only MISCNTOVF Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. 27 1 read-only INACTIVE Missed Packet Counter overflow not detected 0 ACTIVE Missed Packet Counter overflow detected 0x1 MTL_RXQ4_DEBUG Queue 4 Receive Debug 0xE38 32 read-only 0 0xFFFFFFFF RWCSTS MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue. 0 1 read-only INACTIVE MTL Rx Queue Write Controller Active Status not detected 0 ACTIVE MTL Rx Queue Write Controller Active Status detected 0x1 RRCSTS MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 1 2 read-only IDLE Idle state 0 READ_DATA Reading packet data 0x1 READ_STS Reading packet status (or timestamp) 0x2 FLUSH Flushing the packet data and status 0x3 RXQSTS MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 4 2 read-only EMPTY Rx Queue empty 0 BLW_THR Rx Queue fill-level below flow-control deactivate threshold 0x1 ABV_THR Rx Queue fill-level above flow-control activate threshold 0x2 FULL Rx Queue full 0x3 PRXQ Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. 16 14 read-only MTL_RXQ4_CONTROL Queue 4 Receive Control 0xE3C 32 read-write 0 0xFFFFFFFF RXQ_WEGT Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. 0 3 read-write RXQ_FRM_ARBIT Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. 3 1 read-write DISABLE Receive Queue Packet Arbitration is disabled 0 ENABLE Receive Queue Packet Arbitration is enabled 0x1 DMA_MODE DMA Bus Mode 0x1000 32 read-write 0 0xFFFFFFFF SWR Software Reset When this bit is set, the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. 0 1 read-write DISABLE Software Reset is disabled 0 ENABLE Software Reset is enabled 0x1 DSPW Descriptor Posted Write When this bit is set to 0, the descriptor writes are always non-posted. 8 1 read-write DISABLE Descriptor Posted Write is disabled 0 ENABLE Descriptor Posted Write is enabled 0x1 INTM Interrupt Mode This field defines the interrupt mode of DWC_ether_qos. 16 2 read-write MODE0 See above description 0 MODE1 See above description 0x1 MODE2 See above description 0x2 DMA_SYSBUS_MODE DMA System Bus Mode 0x1004 32 read-write 0x1010000 0xFFFFFFFF FB Fixed Burst Length When this bit is set to 1, the EQOS-AXI master initiates burst transfers of specified lengths as given below. 0 1 read-write DISABLE Fixed Burst Length is disabled 0 ENABLE Fixed Burst Length is enabled 0x1 BLEN4 AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI master can select a burst length of 4 on the AXI interface. 1 1 read-write DISABLE No effect 0 ENABLE AXI Burst Length 4 0x1 BLEN8 AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI master can select a burst length of 8 on the AXI interface. 2 1 read-write DISABLE No effect 0 ENABLE AXI Burst Length 8 0x1 BLEN16 AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI master can select a burst length of 16 on the AXI interface. 3 1 read-write DISABLE No effect 0 ENABLE AXI Burst Length 16 0x1 AALE Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in the LPIEI field of DMA_AXI_LPI_ENTRY_INTERVAL register. 10 1 read-write DISABLE Automatic AXI LPI is disabled 0 ENABLE Automatic AXI LPI is enabled 0x1 AAL Address-Aligned Beats When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels. 12 1 read-write DISABLE Address-Aligned Beats is disabled 0 ENABLE Address-Aligned Beats is enabled 0x1 ONEKBBE 1 KB Boundary Crossing Enable for the EQOS-AXI Master When set, the burst transfers performed by the EQOS-AXI master do not cross 1 KB boundary. 13 1 read-write DISABLE 1 KB Boundary Crossing for the EQOS-AXI Master Beats is disabled 0 ENABLE 1 KB Boundary Crossing for the EQOS-AXI Master Beats is enabled 0x1 RD_OSR_LMT AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface. 16 4 read-write WR_OSR_LMT AXI Maximum Write Outstanding Request Limit This value limits the maximum outstanding request on the AXI write interface. 24 4 read-write LPI_XIT_PKT Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet is received. 30 1 read-write DISABLE Unlock on Magic Packet or Remote Wake-Up Packet is disabled 0 ENABLE Unlock on Magic Packet or Remote Wake-Up Packet is enabled 0x1 EN_LPI Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode supported by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock controller. 31 1 read-write DISABLE Low Power Interface (LPI) is disabled 0 ENABLE Low Power Interface (LPI) is enabled 0x1 DMA_INTERRUPT_STATUS DMA Interrupt Status 0x1008 32 read-only 0 0xFFFFFFFF DC0IS DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0. 0 1 read-only INACTIVE DMA Channel 0 Interrupt Status not detected 0 ACTIVE DMA Channel 0 Interrupt Status detected 0x1 DC1IS DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1. 1 1 read-only INACTIVE DMA Channel 1 Interrupt Status not detected 0 ACTIVE DMA Channel 1 Interrupt Status detected 0x1 DC2IS DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2. 2 1 read-only INACTIVE DMA Channel 2 Interrupt Status not detected 0 ACTIVE DMA Channel 2 Interrupt Status detected 0x1 DC3IS DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3. 3 1 read-only INACTIVE DMA Channel 3 Interrupt Status not detected 0 ACTIVE DMA Channel 3 Interrupt Status detected 0x1 DC4IS DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4. 4 1 read-only INACTIVE DMA Channel 4 Interrupt Status not detected 0 ACTIVE DMA Channel 4 Interrupt Status detected 0x1 MTLIS MTL Interrupt Status This bit indicates an interrupt event in the MTL. 16 1 read-only INACTIVE MTL Interrupt Status not detected 0 ACTIVE MTL Interrupt Status detected 0x1 MACIS MAC Interrupt Status This bit indicates an interrupt event in the MAC. 17 1 read-only INACTIVE MAC Interrupt Status not detected 0 ACTIVE MAC Interrupt Status detected 0x1 DMA_DEBUG_STATUS0 DMA Debug Status 0 0x100C 32 read-only 0 0xFFFFFFFF AXWHSTS AXI Master Write Channel When high, this bit indicates that the write channel of the AXI master is active, and it is transferring data. 0 1 read-only INACTIVE AXI Master Write Channel or AHB Master Status not detected 0 ACTIVE AXI Master Write Channel or AHB Master Status detected 0x1 AXRHSTS AXI Master Read Channel Status When high, this bit indicates that the read channel of the AXI master is active, and it is transferring the data. 1 1 read-only INACTIVE AXI Master Read Channel Status not detected 0 ACTIVE AXI Master Read Channel Status detected 0x1 RPS0 DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0. 8 4 read-only STOP Stopped (Reset or Stop Receive Command issued) 0 RUN_FRTD Running (Fetching Rx Transfer Descriptor) 0x1 RUN_WRP Running (Waiting for Rx packet) 0x3 SUSPND Suspended (Rx Descriptor Unavailable) 0x4 RUN_CRD Running (Closing the Rx Descriptor) 0x5 TSTMP Timestamp write state 0x6 RUN_TRP Running (Transferring the received packet data from the Rx buffer to the system memory) 0x7 TPS0 DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0. 12 4 read-only STOP Stopped (Reset or Stop Transmit Command issued) 0 RUN_FTTD Running (Fetching Tx Transfer Descriptor) 0x1 RUN_WS Running (Waiting for status) 0x2 RUN_RDS Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) 0x3 TSTMP_WS Timestamp write state 0x4 SUSPND Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) 0x6 RUN_CTD Running (Closing Tx Descriptor) 0x7 RPS1 DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1. 16 4 read-only STOP Stopped (Reset or Stop Receive Command issued) 0 RUN_FRTD Running (Fetching Rx Transfer Descriptor) 0x1 RUN_WRP Running (Waiting for Rx packet) 0x3 SUSPND Suspended (Rx Descriptor Unavailable) 0x4 RUN_CRD Running (Closing the Rx Descriptor) 0x5 TSTMP Timestamp write state 0x6 RUN_TRP Running (Transferring the received packet data from the Rx buffer to the system memory) 0x7 TPS1 DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1. 20 4 read-only STOP Stopped (Reset or Stop Transmit Command issued) 0 RUN_FTTD Running (Fetching Tx Transfer Descriptor) 0x1 RUN_WS Running (Waiting for status) 0x2 RUN_RDS Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) 0x3 TSTMP_WS Timestamp write state 0x4 SUSPND Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) 0x6 RUN_CTD Running (Closing Tx Descriptor) 0x7 RPS2 DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2. 24 4 read-only STOP Stopped (Reset or Stop Receive Command issued) 0 RUN_FRTD Running (Fetching Rx Transfer Descriptor) 0x1 RUN_WRP Running (Waiting for Rx packet) 0x3 SUSPND Suspended (Rx Descriptor Unavailable) 0x4 RUN_CRD Running (Closing the Rx Descriptor) 0x5 TSTMP Timestamp write state 0x6 RUN_TRP Running (Transferring the received packet data from the Rx buffer to the system memory) 0x7 TPS2 DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2. 28 4 read-only STOP Stopped (Reset or Stop Transmit Command issued) 0 RUN_FTTD Running (Fetching Tx Transfer Descriptor) 0x1 RUN_WS Running (Waiting for status) 0x2 RUN_RDS Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) 0x3 TSTMP_WS Timestamp write state 0x4 SUSPND Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) 0x6 RUN_CTD Running (Closing Tx Descriptor) 0x7 DMA_DEBUG_STATUS1 DMA Debug Status 1 0x1010 32 read-only 0 0xFFFFFFFF RPS3 DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3. 0 4 read-only STOP Stopped (Reset or Stop Receive Command issued) 0 RUN_FRTD Running (Fetching Rx Transfer Descriptor) 0x1 RUN_WRP Running (Waiting for Rx packet) 0x3 SUSPND Suspended (Rx Descriptor Unavailable) 0x4 RUN_CRD Running (Closing the Rx Descriptor) 0x5 TSTMP Timestamp write state 0x6 RUN_TRP Running (Transferring the received packet data from the Rx buffer to the system memory) 0x7 TPS3 DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3. 4 4 read-only STOP Stopped (Reset or Stop Transmit Command issued) 0 RUN_FTTD Running (Fetching Tx Transfer Descriptor) 0x1 RUN_WS Running (Waiting for status) 0x2 RUN_RDS Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) 0x3 TSTMP_WS Timestamp write state 0x4 SUSPND Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) 0x6 RUN_CTD Running (Closing Tx Descriptor) 0x7 RPS4 DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4. 8 4 read-only STOP Stopped (Reset or Stop Receive Command issued) 0 RUN_FRTD Running (Fetching Rx Transfer Descriptor) 0x1 RUN_WRP Running (Waiting for Rx packet) 0x3 SUSPND Suspended (Rx Descriptor Unavailable) 0x4 RUN_CRD Running (Closing the Rx Descriptor) 0x5 TSTMP Timestamp write state 0x6 RUN_TRP Running (Transferring the received packet data from the Rx buffer to the system memory) 0x7 TPS4 DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4. 12 4 read-only STOP Stopped (Reset or Stop Transmit Command issued) 0 RUN_FTTD Running (Fetching Tx Transfer Descriptor) 0x1 RUN_WS Running (Waiting for status) 0x2 RUN_RDS Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) 0x3 TSTMP_WS Timestamp write state 0x4 SUSPND Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) 0x6 RUN_CTD Running (Closing Tx Descriptor) 0x7 DMA_AXI_LPI_ENTRY_INTERVAL AXI LPI Entry Interval Control 0x1040 32 read-write 0 0xFFFFFFFF LPIEI LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64 clock cycles 0 4 read-write DMA_TBS_CTRL TBS Control 0x1050 32 read-write 0 0xFFFFFFFF FTOV Fetch Time Offset Valid When set indicates the FTOS field is valid. 0 1 read-write INVALID Fetch Time Offset is invalid 0 VALID Fetch Time Offset is valid 0x1 FGOS Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. 4 3 read-write FTOS Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the Launch time to compute the Fetch Time. 8 24 read-write DMA_CH0_CONTROL DMA Channel 0 Control 0x1100 32 read-write 0 0xFFFFFFFF PBLx8 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA_CH0_TX_CONTROL and Bits[21:16] in DMA_CH0_RX_CONTROL is multiplied by eight times. 16 1 read-write DISABLE 8xPBL mode is disabled 0 ENABLE 8xPBL mode is enabled 0x1 DSL Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. 18 3 read-write DMA_CH0_TX_CONTROL DMA Channel 0 Transmit Control 0x1104 32 read-write 0 0xFFFFFFFF ST Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. 0 1 read-write STOP Stop Transmission Command 0 START Start Transmission Command 0x1 OSF Operate on Second Packet When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 4 1 read-write DISABLE Operate on Second Packet disabled 0 ENABLE Operate on Second Packet enabled 0x1 IPBL Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of locations in the MTL before initiating a transfer. 15 1 read-write DISABLE Ignore PBL Requirement is disabled 0 ENABLE Ignore PBL Requirement is enabled 0x1 TxPBL Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. 16 6 read-write EDSE Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. 28 1 read-write DISABLE Enhanced Descriptor is disabled 0 ENABLE Enhanced Descriptor is enabled 0x1 DMA_CH0_RX_CONTROL DMA Channel 0 Receive Control 0x1108 32 read-write 0 0xFFFFFFFF SR Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. 0 1 read-write STOP Stop Receive 0 START Start Receive 0x1 RBSZ_x_0 Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. 1 3 read-only RBSZ_13_y Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. 4 11 read-write RxPBL Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. 16 6 read-write RPF Rx Packet Flush. 31 1 read-write DISABLE Rx Packet Flush is disabled 0 ENABLE Rx Packet Flush is enabled 0x1 DMA_CH0_TXDESC_LIST_ADDRESS Channel 0 Tx Descriptor List Address register 0x1114 32 read-write 0 0xFFFFFFFF TDESLA Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. 3 29 read-write DMA_CH0_RXDESC_LIST_ADDRESS Channel 0 Rx Descriptor List Address register 0x111C 32 read-write 0 0xFFFFFFFF RDESLA Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. 3 29 read-write DMA_CH0_TXDESC_TAIL_POINTER Channel 0 Tx Descriptor Tail Pointer 0x1120 32 read-write 0 0xFFFFFFFF TDTP Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. 3 29 read-write DMA_CH0_RXDESC_TAIL_POINTER Channel 0 Rx Descriptor Tail Pointer 0x1128 32 read-write 0 0xFFFFFFFF RDTP Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. 3 29 read-write DMA_CH0_TXDESC_RING_LENGTH Channel 0 Tx Descriptor Ring Length 0x112C 32 read-write 0 0xFFFFFFFF TDRL Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. 0 10 read-write DMA_CH0_RXDESC_RING_LENGTH Channel 0 Rx Descriptor Ring Length 0x1130 32 read-write 0 0xFFFFFFFF RDRL Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. 0 10 read-write DMA_CH0_INTERRUPT_ENABLE Channel 0 Interrupt Enable 0x1134 32 read-write 0 0xFFFFFFFF TIE Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. 0 1 read-write DISABLE Transmit Interrupt is disabled 0 ENABLE Transmit Interrupt is enabled 0x1 TXSE Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. 1 1 read-write DISABLE Transmit Stopped is disabled 0 ENABLE Transmit Stopped is enabled 0x1 TBUE Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. 2 1 read-write DISABLE Transmit Buffer Unavailable is disabled 0 ENABLE Transmit Buffer Unavailable is enabled 0x1 RIE Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled. 6 1 read-write DISABLE Receive Interrupt is disabled 0 ENABLE Receive Interrupt is enabled 0x1 RBUE Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. 7 1 read-write DISABLE Receive Buffer Unavailable is disabled 0 ENABLE Receive Buffer Unavailable is enabled 0x1 RSE Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. 8 1 read-write DISABLE Receive Stopped is disabled 0 ENABLE Receive Stopped is enabled 0x1 RWTE Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. 9 1 read-write DISABLE Receive Watchdog Timeout is disabled 0 ENABLE Receive Watchdog Timeout is enabled 0x1 ETIE Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. 10 1 read-write DISABLE Early Transmit Interrupt is disabled 0 ENABLE Early Transmit Interrupt is enabled 0x1 ERIE Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. 11 1 read-write DISABLE Early Receive Interrupt is disabled 0 ENABLE Early Receive Interrupt is enabled 0x1 FBEE Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. 12 1 read-write DISABLE Fatal Bus Error is disabled 0 ENABLE Fatal Bus Error is enabled 0x1 CDEE Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled. 13 1 read-write DISABLE Context Descriptor Error is disabled 0 ENABLE Context Descriptor Error is enabled 0x1 AIE Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled. 14 1 read-write DISABLE Abnormal Interrupt Summary is disabled 0 ENABLE Abnormal Interrupt Summary is enabled 0x1 NIE Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled. 15 1 read-write DISABLE Normal Interrupt Summary is disabled 0 ENABLE Normal Interrupt Summary is enabled 0x1 DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER Channel 0 Receive Interrupt Watchdog Timer 0x1138 32 read-write 0 0xFFFFFFFF RWT Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. 0 8 read-write RWTU Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. 16 2 read-write DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS Channel 0 Slot Function Control and Status 0x113C 32 read-write 0x7C0 0xFFFFFFFF ESC Enable Slot Comparison When set, this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. 0 1 read-write DISABLE Slot Comparison is disabled 0 ENABLE Slot Comparison is enabled 0x1 ASC Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot number by up to two slots This bit is applicable only when the ESC bit is set. 1 1 read-write DISABLE Advance Slot Check is disabled 0 ENABLE Advance Slot Check is enabled 0x1 SIV Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. 4 12 read-write RSN Reference Slot Number This field gives the current value of the reference slot number in the DMA. 16 4 read-only DMA_CH0_CURRENT_APP_TXDESC Channel 0 Current Application Transmit Descriptor 0x1144 32 read-only 0 0xFFFFFFFF CURTDESAPTR Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. 0 32 read-only DMA_CH0_CURRENT_APP_RXDESC Channel 0 Current Application Receive Descriptor 0x114C 32 read-only 0 0xFFFFFFFF CURRDESAPTR Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. 0 32 read-only DMA_CH0_CURRENT_APP_TXBUFFER Channel 0 Current Application Transmit Buffer Address 0x1154 32 read-only 0 0xFFFFFFFF CURTBUFAPTR Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. 0 32 read-only DMA_CH0_CURRENT_APP_RXBUFFER Channel 0 Current Application Receive Buffer Address 0x115C 32 read-only 0 0xFFFFFFFF CURRBUFAPTR Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. 0 32 read-only DMA_CH0_STATUS DMA Channel 0 Status 0x1160 32 read-write 0 0xFFFFFFFF TI Transmit Interrupt This bit indicates that the packet transmission is complete. 0 1 read-write INACTIVE Transmit Interrupt status not detected 0 ACTIVE Transmit Interrupt status detected 0x1 TPS Transmit Process Stopped This bit is set when the transmission is stopped. 1 1 read-write INACTIVE Transmit Process Stopped status not detected 0 ACTIVE Transmit Process Stopped status detected 0x1 TBU Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. 2 1 read-write INACTIVE Transmit Buffer Unavailable status not detected 0 ACTIVE Transmit Buffer Unavailable status detected 0x1 RI Receive Interrupt This bit indicates that the packet reception is complete. 6 1 read-write INACTIVE Receive Interrupt status not detected 0 ACTIVE Receive Interrupt status detected 0x1 RBU Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. 7 1 read-write INACTIVE Receive Buffer Unavailable status not detected 0 ACTIVE Receive Buffer Unavailable status detected 0x1 RPS Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. 8 1 read-write INACTIVE Receive Process Stopped status not detected 0 ACTIVE Receive Process Stopped status detected 0x1 RWT Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. 9 1 read-write INACTIVE Receive Watchdog Timeout status not detected 0 ACTIVE Receive Watchdog Timeout status detected 0x1 ETI Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. 10 1 read-write INACTIVE Early Transmit Interrupt status not detected 0 ACTIVE Early Transmit Interrupt status detected 0x1 ERI Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. 11 1 read-write INACTIVE Early Receive Interrupt status not detected 0 ACTIVE Early Receive Interrupt status detected 0x1 FBE Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). 12 1 read-write INACTIVE Fatal Bus Error status not detected 0 ACTIVE Fatal Bus Error status detected 0x1 CDE Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow (intermediate descriptor) or all ones descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid. 13 1 read-write INACTIVE Context Descriptor Error status not detected 0 ACTIVE Context Descriptor Error status detected 0x1 AIS Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. 14 1 read-write INACTIVE Abnormal Interrupt Summary status not detected 0 ACTIVE Abnormal Interrupt Summary status detected 0x1 NIS Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_INTERRUPT_ENABLE register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit. 15 1 read-write INACTIVE Normal Interrupt Summary status not detected 0 ACTIVE Normal Interrupt Summary status detected 0x1 TEB Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. 16 3 read-only REB Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. 19 3 read-only DMA_CH0_MISS_FRAME_CNT Channel 0 Missed Frame Counter 0x1164 32 read-only 0 0xFFFFFFFF MFC Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in DMA_CH0_RX_CONTROL register. 0 11 read-only MFCO Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. 15 1 read-only INACTIVE Miss Frame Counter overflow not occurred 0 ACTIVE Miss Frame Counter overflow occurred 0x1 DMA_CH0_RXP_ACCEPT_CNT Channel 0 RXP Frames Accepted Counter 0x1168 32 read-only 0 0xFFFFFFFF RXPAC Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. 0 31 read-only RXPACOF Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC Counter field crossed the maximum limit. 31 1 read-only INACTIVE Rx Parser Accept Counter overflow not occurred 0 ACTIVE Rx Parser Accept Counter overflow occurred 0x1 DMA_CH0_RX_ERI_CNT Channel 0 Receive ERI Counter 0x116C 32 read-only 0 0xFFFFFFFF ECNT ERI Counter When ERIC bit of RX_CONTROL register is set, this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. 0 12 read-only DMA_CH1_CONTROL DMA Channel 1 Control 0x1180 32 read-write 0 0xFFFFFFFF PBLx8 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in TX_CONTROL and Bits[21:16] in DMA_CH1_RX_CONTROL is multiplied by eight times. 16 1 read-write DISABLE 8xPBL mode is disabled 0 ENABLE 8xPBL mode is enabled 0x1 DSL Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. 18 3 read-write DMA_CH1_TX_CONTROL DMA Channel 1 Transmit Control 0x1184 32 read-write 0 0xFFFFFFFF ST Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. 0 1 read-write STOP Stop Transmission Command 0 START Start Transmission Command 0x1 OSF Operate on Second Packet When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 4 1 read-write DISABLE Operate on Second Packet disabled 0 ENABLE Operate on Second Packet enabled 0x1 IPBL Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of locations in the MTL before initiating a transfer. 15 1 read-write DISABLE Ignore PBL Requirement is disabled 0 ENABLE Ignore PBL Requirement is enabled 0x1 TxPBL Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. 16 6 read-write EDSE Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. 28 1 read-write DISABLE Enhanced Descriptor is disabled 0 ENABLE Enhanced Descriptor is enabled 0x1 DMA_CH1_RX_CONTROL DMA Channel 1 Receive Control 0x1188 32 read-write 0 0xFFFFFFFF SR Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. 0 1 read-write STOP Stop Receive 0 START Start Receive 0x1 RBSZ_x_0 Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. 1 3 read-only RBSZ_13_y Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. 4 11 read-write RxPBL Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. 16 6 read-write RPF Rx Packet Flush. 31 1 read-write DISABLE Rx Packet Flush is disabled 0 ENABLE Rx Packet Flush is enabled 0x1 DMA_CH1_TXDESC_LIST_ADDRESS Channel 1 Tx Descriptor List Address 0x1194 32 read-write 0 0xFFFFFFFF TDESLA Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. 3 29 read-write DMA_CH1_RXDESC_LIST_ADDRESS Channel 1 Rx Descriptor List Address 0x119C 32 read-write 0 0xFFFFFFFF RDESLA Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. 3 29 read-write DMA_CH1_TXDESC_TAIL_POINTER Channel 1 Tx Descriptor Tail Pointer 0x11A0 32 read-write 0 0xFFFFFFFF TDTP Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. 3 29 read-write DMA_CH1_RXDESC_TAIL_POINTER Channel 1 Rx Descriptor Tail Pointer 0x11A8 32 read-write 0 0xFFFFFFFF RDTP Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. 3 29 read-write DMA_CH1_TXDESC_RING_LENGTH Channel 1 Tx Descriptor Ring Length 0x11AC 32 read-write 0 0xFFFFFFFF TDRL Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. 0 10 read-write DMA_CH1_RXDESC_RING_LENGTH Channel 1 Rx Descriptor Ring Length 0x11B0 32 read-write 0 0xFFFFFFFF RDRL Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. 0 10 read-write DMA_CH1_INTERRUPT_ENABLE Channel 1 Interrupt Enable 0x11B4 32 read-write 0 0xFFFFFFFF TIE Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. 0 1 read-write DISABLE Transmit Interrupt is disabled 0 ENABLE Transmit Interrupt is enabled 0x1 TXSE Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. 1 1 read-write DISABLE Transmit Stopped is disabled 0 ENABLE Transmit Stopped is enabled 0x1 TBUE Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. 2 1 read-write DISABLE Transmit Buffer Unavailable is disabled 0 ENABLE Transmit Buffer Unavailable is enabled 0x1 RIE Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled. 6 1 read-write DISABLE Receive Interrupt is disabled 0 ENABLE Receive Interrupt is enabled 0x1 RBUE Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. 7 1 read-write DISABLE Receive Buffer Unavailable is disabled 0 ENABLE Receive Buffer Unavailable is enabled 0x1 RSE Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. 8 1 read-write DISABLE Receive Stopped is disabled 0 ENABLE Receive Stopped is enabled 0x1 RWTE Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. 9 1 read-write DISABLE Receive Watchdog Timeout is disabled 0 ENABLE Receive Watchdog Timeout is enabled 0x1 ETIE Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. 10 1 read-write DISABLE Early Transmit Interrupt is disabled 0 ENABLE Early Transmit Interrupt is enabled 0x1 ERIE Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. 11 1 read-write DISABLE Early Receive Interrupt is disabled 0 ENABLE Early Receive Interrupt is enabled 0x1 FBEE Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. 12 1 read-write DISABLE Fatal Bus Error is disabled 0 ENABLE Fatal Bus Error is enabled 0x1 CDEE Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled. 13 1 read-write DISABLE Context Descriptor Error is disabled 0 ENABLE Context Descriptor Error is enabled 0x1 AIE Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled. 14 1 read-write DISABLE Abnormal Interrupt Summary is disabled 0 ENABLE Abnormal Interrupt Summary is enabled 0x1 NIE Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled. 15 1 read-write DISABLE Normal Interrupt Summary is disabled 0 ENABLE Normal Interrupt Summary is enabled 0x1 DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER Channel 1 Receive Interrupt Watchdog Timer 0x11B8 32 read-write 0 0xFFFFFFFF RWT Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. 0 8 read-write RWTU Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. 16 2 read-write DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS Channel 1 Slot Function Control and Status 0x11BC 32 read-write 0x7C0 0xFFFFFFFF ESC Enable Slot Comparison When set, this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. 0 1 read-write DISABLE Slot Comparison is disabled 0 ENABLE Slot Comparison is enabled 0x1 ASC Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot number by up to two slots This bit is applicable only when the ESC bit is set. 1 1 read-write DISABLE Advance Slot Check is disabled 0 ENABLE Advance Slot Check is enabled 0x1 SIV Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. 4 12 read-write RSN Reference Slot Number This field gives the current value of the reference slot number in the DMA. 16 4 read-only DMA_CH1_CURRENT_APP_TXDESC Channel 1 Current Application Transmit Descriptor 0x11C4 32 read-only 0 0xFFFFFFFF CURTDESAPTR Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. 0 32 read-only DMA_CH1_CURRENT_APP_RXDESC Channel 1 Current Application Receive Descriptor 0x11CC 32 read-only 0 0xFFFFFFFF CURRDESAPTR Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. 0 32 read-only DMA_CH1_CURRENT_APP_TXBUFFER Channel 1 Current Application Transmit Buffer Address 0x11D4 32 read-only 0 0xFFFFFFFF CURTBUFAPTR Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. 0 32 read-only DMA_CH1_CURRENT_APP_RXBUFFER Channel 1 Current Application Receive Buffer Address 0x11DC 32 read-only 0 0xFFFFFFFF CURRBUFAPTR Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. 0 32 read-only DMA_CH1_STATUS DMA Channel 1 Status 0x11E0 32 read-write 0 0xFFFFFFFF TI Transmit Interrupt This bit indicates that the packet transmission is complete. 0 1 read-write INACTIVE Transmit Interrupt status not detected 0 ACTIVE Transmit Interrupt status detected 0x1 TPS Transmit Process Stopped This bit is set when the transmission is stopped. 1 1 read-write INACTIVE Transmit Process Stopped status not detected 0 ACTIVE Transmit Process Stopped status detected 0x1 TBU Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. 2 1 read-write INACTIVE Transmit Buffer Unavailable status not detected 0 ACTIVE Transmit Buffer Unavailable status detected 0x1 RI Receive Interrupt This bit indicates that the packet reception is complete. 6 1 read-write INACTIVE Receive Interrupt status not detected 0 ACTIVE Receive Interrupt status detected 0x1 RBU Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. 7 1 read-write INACTIVE Receive Buffer Unavailable status not detected 0 ACTIVE Receive Buffer Unavailable status detected 0x1 RPS Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. 8 1 read-write INACTIVE Receive Process Stopped status not detected 0 ACTIVE Receive Process Stopped status detected 0x1 RWT Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. 9 1 read-write INACTIVE Receive Watchdog Timeout status not detected 0 ACTIVE Receive Watchdog Timeout status detected 0x1 ETI Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. 10 1 read-write INACTIVE Early Transmit Interrupt status not detected 0 ACTIVE Early Transmit Interrupt status detected 0x1 ERI Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. 11 1 read-write INACTIVE Early Receive Interrupt status not detected 0 ACTIVE Early Receive Interrupt status detected 0x1 FBE Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). 12 1 read-write INACTIVE Fatal Bus Error status not detected 0 ACTIVE Fatal Bus Error status detected 0x1 CDE Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid. 13 1 read-write INACTIVE Context Descriptor Error status not detected 0 ACTIVE Context Descriptor Error status detected 0x1 AIS Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. 14 1 read-write INACTIVE Abnormal Interrupt Summary status not detected 0 ACTIVE Abnormal Interrupt Summary status detected 0x1 NIS Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit. 15 1 read-write INACTIVE Normal Interrupt Summary status not detected 0 ACTIVE Normal Interrupt Summary status detected 0x1 TEB Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. 16 3 read-only REB Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. 19 3 read-only DMA_CH1_MISS_FRAME_CNT Channel 1 Missed Frame Counter 0x11E4 32 read-only 0 0xFFFFFFFF MFC Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in RX_CONTROL register. 0 11 read-only MFCO Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. 15 1 read-only INACTIVE Miss Frame Counter overflow not occurred 0 ACTIVE Miss Frame Counter overflow occurred 0x1 DMA_CH1_RXP_ACCEPT_CNT Channel 1 RXP Frames Accepted Counter 0x11E8 32 read-only 0 0xFFFFFFFF RXPAC Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. 0 31 read-only RXPACOF Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC Counter field crossed the maximum limit. 31 1 read-only INACTIVE Rx Parser Accept Counter overflow not occurred 0 ACTIVE Rx Parser Accept Counter overflow occurred 0x1 DMA_CH1_RX_ERI_CNT Channel 1 Receive ERI Counter 0x11EC 32 read-only 0 0xFFFFFFFF ECNT ERI Counter When ERIC bit of RX_CONTROL register is set, this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. 0 12 read-only DMA_CH2_CONTROL DMA Channel 2 Control 0x1200 32 read-write 0 0xFFFFFFFF PBLx8 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA_CH2_TX_CONTROL and Bits[21:16] in DMA_CH2_RX_CONTROL is multiplied by eight times. 16 1 read-write DISABLE 8xPBL mode is disabled 0 ENABLE 8xPBL mode is enabled 0x1 DSL Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. 18 3 read-write DMA_CH2_TX_CONTROL DMA Channel 2 Transmit Control 0x1204 32 read-write 0 0xFFFFFFFF ST Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. 0 1 read-write STOP Stop Transmission Command 0 START Start Transmission Command 0x1 OSF Operate on Second Packet When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 4 1 read-write DISABLE Operate on Second Packet disabled 0 ENABLE Operate on Second Packet enabled 0x1 IPBL Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of locations in the MTL before initiating a transfer. 15 1 read-write DISABLE Ignore PBL Requirement is disabled 0 ENABLE Ignore PBL Requirement is enabled 0x1 TxPBL Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. 16 6 read-write EDSE Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. 28 1 read-write DISABLE Enhanced Descriptor is disabled 0 ENABLE Enhanced Descriptor is enabled 0x1 DMA_CH2_RX_CONTROL DMA Channel 2 Receive Control 0x1208 32 read-write 0 0xFFFFFFFF SR Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. 0 1 read-write STOP Stop Receive 0 START Start Receive 0x1 RBSZ_x_0 Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. 1 3 read-only RBSZ_13_y Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. 4 11 read-write RxPBL Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. 16 6 read-write RPF Rx Packet Flush. 31 1 read-write DISABLE Rx Packet Flush is disabled 0 ENABLE Rx Packet Flush is enabled 0x1 DMA_CH2_TXDESC_LIST_ADDRESS Channel 2 Tx Descriptor List Address 0x1214 32 read-write 0 0xFFFFFFFF TDESLA Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. 3 29 read-write DMA_CH2_RXDESC_LIST_ADDRESS Channel 2 Rx Descriptor List Address 0x121C 32 read-write 0 0xFFFFFFFF RDESLA Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. 3 29 read-write DMA_CH2_TXDESC_TAIL_POINTER Channel 2 Tx Descriptor Tail Pointer 0x1220 32 read-write 0 0xFFFFFFFF TDTP Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. 3 29 read-write DMA_CH2_RXDESC_TAIL_POINTER Channel 2 Rx Descriptor Tail Pointer 0x1228 32 read-write 0 0xFFFFFFFF RDTP Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. 3 29 read-write DMA_CH2_TXDESC_RING_LENGTH Channel 2 Tx Descriptor Ring Length 0x122C 32 read-write 0 0xFFFFFFFF TDRL Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. 0 10 read-write DMA_CH2_RXDESC_RING_LENGTH Channel 2 Rx Descriptor Ring Length 0x1230 32 read-write 0 0xFFFFFFFF RDRL Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. 0 10 read-write DMA_CH2_INTERRUPT_ENABLE Channel 2 Interrupt Enable 0x1234 32 read-write 0 0xFFFFFFFF TIE Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. 0 1 read-write DISABLE Transmit Interrupt is disabled 0 ENABLE Transmit Interrupt is enabled 0x1 TXSE Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. 1 1 read-write DISABLE Transmit Stopped is disabled 0 ENABLE Transmit Stopped is enabled 0x1 TBUE Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. 2 1 read-write DISABLE Transmit Buffer Unavailable is disabled 0 ENABLE Transmit Buffer Unavailable is enabled 0x1 RIE Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled. 6 1 read-write DISABLE Receive Interrupt is disabled 0 ENABLE Receive Interrupt is enabled 0x1 RBUE Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. 7 1 read-write DISABLE Receive Buffer Unavailable is disabled 0 ENABLE Receive Buffer Unavailable is enabled 0x1 RSE Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. 8 1 read-write DISABLE Receive Stopped is disabled 0 ENABLE Receive Stopped is enabled 0x1 RWTE Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. 9 1 read-write DISABLE Receive Watchdog Timeout is disabled 0 ENABLE Receive Watchdog Timeout is enabled 0x1 ETIE Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. 10 1 read-write DISABLE Early Transmit Interrupt is disabled 0 ENABLE Early Transmit Interrupt is enabled 0x1 ERIE Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. 11 1 read-write DISABLE Early Receive Interrupt is disabled 0 ENABLE Early Receive Interrupt is enabled 0x1 FBEE Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. 12 1 read-write DISABLE Fatal Bus Error is disabled 0 ENABLE Fatal Bus Error is enabled 0x1 CDEE Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled. 13 1 read-write DISABLE Context Descriptor Error is disabled 0 ENABLE Context Descriptor Error is enabled 0x1 AIE Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled. 14 1 read-write DISABLE Abnormal Interrupt Summary is disabled 0 ENABLE Abnormal Interrupt Summary is enabled 0x1 NIE Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled. 15 1 read-write DISABLE Normal Interrupt Summary is disabled 0 ENABLE Normal Interrupt Summary is enabled 0x1 DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER Channel 2 Receive Interrupt Watchdog Timer 0x1238 32 read-write 0 0xFFFFFFFF RWT Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. 0 8 read-write RWTU Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. 16 2 read-write DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS Channel 2 Slot Function Control and Status 0x123C 32 read-write 0x7C0 0xFFFFFFFF ESC Enable Slot Comparison When set, this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. 0 1 read-write DISABLE Slot Comparison is disabled 0 ENABLE Slot Comparison is enabled 0x1 ASC Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot number by up to two slots This bit is applicable only when the ESC bit is set. 1 1 read-write DISABLE Advance Slot Check is disabled 0 ENABLE Advance Slot Check is enabled 0x1 SIV Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. 4 12 read-write RSN Reference Slot Number This field gives the current value of the reference slot number in the DMA. 16 4 read-only DMA_CH2_CURRENT_APP_TXDESC Channel 2 Current Application Transmit Descriptor 0x1244 32 read-only 0 0xFFFFFFFF CURTDESAPTR Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. 0 32 read-only DMA_CH2_CURRENT_APP_RXDESC Channel 2 Current Application Receive Descriptor 0x124C 32 read-only 0 0xFFFFFFFF CURRDESAPTR Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. 0 32 read-only DMA_CH2_CURRENT_APP_TXBUFFER Channel 2 Current Application Transmit Buffer Address 0x1254 32 read-only 0 0xFFFFFFFF CURTBUFAPTR Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. 0 32 read-only DMA_CH2_CURRENT_APP_RXBUFFER Channel 2 Current Application Receive Buffer Address 0x125C 32 read-only 0 0xFFFFFFFF CURRBUFAPTR Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. 0 32 read-only DMA_CH2_STATUS DMA Channel 2 Status 0x1260 32 read-write 0 0xFFFFFFFF TI Transmit Interrupt This bit indicates that the packet transmission is complete. 0 1 read-write INACTIVE Transmit Interrupt status not detected 0 ACTIVE Transmit Interrupt status detected 0x1 TPS Transmit Process Stopped This bit is set when the transmission is stopped. 1 1 read-write INACTIVE Transmit Process Stopped status not detected 0 ACTIVE Transmit Process Stopped status detected 0x1 TBU Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. 2 1 read-write INACTIVE Transmit Buffer Unavailable status not detected 0 ACTIVE Transmit Buffer Unavailable status detected 0x1 RI Receive Interrupt This bit indicates that the packet reception is complete. 6 1 read-write INACTIVE Receive Interrupt status not detected 0 ACTIVE Receive Interrupt status detected 0x1 RBU Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. 7 1 read-write INACTIVE Receive Buffer Unavailable status not detected 0 ACTIVE Receive Buffer Unavailable status detected 0x1 RPS Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. 8 1 read-write INACTIVE Receive Process Stopped status not detected 0 ACTIVE Receive Process Stopped status detected 0x1 RWT Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. 9 1 read-write INACTIVE Receive Watchdog Timeout status not detected 0 ACTIVE Receive Watchdog Timeout status detected 0x1 ETI Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. 10 1 read-write INACTIVE Early Transmit Interrupt status not detected 0 ACTIVE Early Transmit Interrupt status detected 0x1 ERI Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. 11 1 read-write INACTIVE Early Receive Interrupt status not detected 0 ACTIVE Early Receive Interrupt status detected 0x1 FBE Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). 12 1 read-write INACTIVE Fatal Bus Error status not detected 0 ACTIVE Fatal Bus Error status detected 0x1 CDE Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid. 13 1 read-write INACTIVE Context Descriptor Error status not detected 0 ACTIVE Context Descriptor Error status detected 0x1 AIS Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH2_INTERRUPT_ENABLE register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. 14 1 read-write INACTIVE Abnormal Interrupt Summary status not detected 0 ACTIVE Abnormal Interrupt Summary status detected 0x1 NIS Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in DMA_CH2_INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit. 15 1 read-write INACTIVE Normal Interrupt Summary status not detected 0 ACTIVE Normal Interrupt Summary status detected 0x1 TEB Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. 16 3 read-only REB Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. 19 3 read-only DMA_CH2_MISS_FRAME_CNT Channel 2 Missed Frame Counter 0x1264 32 read-only 0 0xFFFFFFFF MFC Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in DMA_CH2_RX_CONTROL register. 0 11 read-only MFCO Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. 15 1 read-only INACTIVE Miss Frame Counter overflow not occurred 0 ACTIVE Miss Frame Counter overflow occurred 0x1 DMA_CH2_RXP_ACCEPT_CNT Channel 2 RXP Frames Accepted Counter 0x1268 32 read-only 0 0xFFFFFFFF RXPAC Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. 0 31 read-only RXPACOF Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC Counter field crossed the maximum limit. 31 1 read-only INACTIVE Rx Parser Accept Counter overflow not occurred 0 ACTIVE Rx Parser Accept Counter overflow occurred 0x1 DMA_CH2_RX_ERI_CNT Channel 2 Receive ERI Counter 0x126C 32 read-only 0 0xFFFFFFFF ECNT ERI Counter When ERIC bit of DMA_CH2_RX_CONTROL register is set, this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. 0 12 read-only DMA_CH3_CONTROL DMA Channel 3 Control 0x1280 32 read-write 0 0xFFFFFFFF PBLx8 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA_CH3_TX_CONTROL and Bits[21:16] in DMA_CH3_RX_CONTROL is multiplied by eight times. 16 1 read-write DISABLE 8xPBL mode is disabled 0 ENABLE 8xPBL mode is enabled 0x1 DSL Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. 18 3 read-write DMA_CH3_TX_CONTROL DMA Channel 3 Transmit Control 0x1284 32 read-write 0 0xFFFFFFFF ST Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. 0 1 read-write STOP Stop Transmission Command 0 START Start Transmission Command 0x1 OSF Operate on Second Packet When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 4 1 read-write DISABLE Operate on Second Packet disabled 0 ENABLE Operate on Second Packet enabled 0x1 IPBL Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of locations in the MTL before initiating a transfer. 15 1 read-write DISABLE Ignore PBL Requirement is disabled 0 ENABLE Ignore PBL Requirement is enabled 0x1 TxPBL Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. 16 6 read-write EDSE Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. 28 1 read-write DISABLE Enhanced Descriptor is disabled 0 ENABLE Enhanced Descriptor is enabled 0x1 DMA_CH3_RX_CONTROL DMA Channel 3 Receive Control 0x1288 32 read-write 0 0xFFFFFFFF SR Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. 0 1 read-write STOP Stop Receive 0 START Start Receive 0x1 RBSZ_x_0 Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. 1 3 read-only RBSZ_13_y Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. 4 11 read-write RxPBL Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. 16 6 read-write RPF Rx Packet Flush. 31 1 read-write DISABLE Rx Packet Flush is disabled 0 ENABLE Rx Packet Flush is enabled 0x1 DMA_CH3_TXDESC_LIST_ADDRESS Channel 3 Tx Descriptor List Address 0x1294 32 read-write 0 0xFFFFFFFF TDESLA Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. 3 29 read-write DMA_CH3_RXDESC_LIST_ADDRESS Channel 3 Rx Descriptor List Address 0x129C 32 read-write 0 0xFFFFFFFF RDESLA Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. 3 29 read-write DMA_CH3_TXDESC_TAIL_POINTER Channel 3 Tx Descriptor Tail Pointer 0x12A0 32 read-write 0 0xFFFFFFFF TDTP Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. 3 29 read-write DMA_CH3_RXDESC_TAIL_POINTER Channel 3 Rx Descriptor Tail Pointer 0x12A8 32 read-write 0 0xFFFFFFFF RDTP Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. 3 29 read-write DMA_CH3_TXDESC_RING_LENGTH Channel 3 Tx Descriptor Ring Length 0x12AC 32 read-write 0 0xFFFFFFFF TDRL Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. 0 10 read-write DMA_CH3_RXDESC_RING_LENGTH Channel 3 Rx Descriptor Ring Length 0x12B0 32 read-write 0 0xFFFFFFFF RDRL Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. 0 10 read-write DMA_CH3_INTERRUPT_ENABLE Channel 3 Interrupt Enable 0x12B4 32 read-write 0 0xFFFFFFFF TIE Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. 0 1 read-write DISABLE Transmit Interrupt is disabled 0 ENABLE Transmit Interrupt is enabled 0x1 TXSE Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. 1 1 read-write DISABLE Transmit Stopped is disabled 0 ENABLE Transmit Stopped is enabled 0x1 TBUE Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. 2 1 read-write DISABLE Transmit Buffer Unavailable is disabled 0 ENABLE Transmit Buffer Unavailable is enabled 0x1 RIE Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled. 6 1 read-write DISABLE Receive Interrupt is disabled 0 ENABLE Receive Interrupt is enabled 0x1 RBUE Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. 7 1 read-write DISABLE Receive Buffer Unavailable is disabled 0 ENABLE Receive Buffer Unavailable is enabled 0x1 RSE Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. 8 1 read-write DISABLE Receive Stopped is disabled 0 ENABLE Receive Stopped is enabled 0x1 RWTE Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. 9 1 read-write DISABLE Receive Watchdog Timeout is disabled 0 ENABLE Receive Watchdog Timeout is enabled 0x1 ETIE Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. 10 1 read-write DISABLE Early Transmit Interrupt is disabled 0 ENABLE Early Transmit Interrupt is enabled 0x1 ERIE Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. 11 1 read-write DISABLE Early Receive Interrupt is disabled 0 ENABLE Early Receive Interrupt is enabled 0x1 FBEE Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. 12 1 read-write DISABLE Fatal Bus Error is disabled 0 ENABLE Fatal Bus Error is enabled 0x1 CDEE Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled. 13 1 read-write DISABLE Context Descriptor Error is disabled 0 ENABLE Context Descriptor Error is enabled 0x1 AIE Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled. 14 1 read-write DISABLE Abnormal Interrupt Summary is disabled 0 ENABLE Abnormal Interrupt Summary is enabled 0x1 NIE Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled. 15 1 read-write DISABLE Normal Interrupt Summary is disabled 0 ENABLE Normal Interrupt Summary is enabled 0x1 DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER Channel 3 Receive Interrupt Watchdog Time 0x12B8 32 read-write 0 0xFFFFFFFF RWT Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. 0 8 read-write RWTU Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. 16 2 read-write DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS Channel 3 Slot Function Control and Status 0x12BC 32 read-write 0x7C0 0xFFFFFFFF ESC Enable Slot Comparison When set, this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. 0 1 read-write DISABLE Slot Comparison is disabled 0 ENABLE Slot Comparison is enabled 0x1 ASC Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot number by up to two slots This bit is applicable only when the ESC bit is set. 1 1 read-write DISABLE Advance Slot Check is disabled 0 ENABLE Advance Slot Check is enabled 0x1 SIV Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. 4 12 read-write RSN Reference Slot Number This field gives the current value of the reference slot number in the DMA. 16 4 read-only DMA_CH3_CURRENT_APP_TXDESC Channel 3 Current Application Transmit Descriptor 0x12C4 32 read-only 0 0xFFFFFFFF CURTDESAPTR Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. 0 32 read-only DMA_CH3_CURRENT_APP_RXDESC Channel 3 Current Application Receive Descriptor 0x12CC 32 read-only 0 0xFFFFFFFF CURRDESAPTR Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. 0 32 read-only DMA_CH3_CURRENT_APP_TXBUFFER Channel 3 Current Application Transmit Buffer Address 0x12D4 32 read-only 0 0xFFFFFFFF CURTBUFAPTR Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. 0 32 read-only DMA_CH3_CURRENT_APP_RXBUFFER Channel 3 Current Application Receive Buffer Address 0x12DC 32 read-only 0 0xFFFFFFFF CURRBUFAPTR Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. 0 32 read-only DMA_CH3_STATUS DMA Channel 3 Status 0x12E0 32 read-write 0 0xFFFFFFFF TI Transmit Interrupt This bit indicates that the packet transmission is complete. 0 1 read-write INACTIVE Transmit Interrupt status not detected 0 ACTIVE Transmit Interrupt status detected 0x1 TPS Transmit Process Stopped This bit is set when the transmission is stopped. 1 1 read-write INACTIVE Transmit Process Stopped status not detected 0 ACTIVE Transmit Process Stopped status detected 0x1 TBU Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. 2 1 read-write INACTIVE Transmit Buffer Unavailable status not detected 0 ACTIVE Transmit Buffer Unavailable status detected 0x1 RI Receive Interrupt This bit indicates that the packet reception is complete. 6 1 read-write INACTIVE Receive Interrupt status not detected 0 ACTIVE Receive Interrupt status detected 0x1 RBU Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. 7 1 read-write INACTIVE Receive Buffer Unavailable status not detected 0 ACTIVE Receive Buffer Unavailable status detected 0x1 RPS Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. 8 1 read-write INACTIVE Receive Process Stopped status not detected 0 ACTIVE Receive Process Stopped status detected 0x1 RWT Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. 9 1 read-write INACTIVE Receive Watchdog Timeout status not detected 0 ACTIVE Receive Watchdog Timeout status detected 0x1 ETI Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. 10 1 read-write INACTIVE Early Transmit Interrupt status not detected 0 ACTIVE Early Transmit Interrupt status detected 0x1 ERI Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. 11 1 read-write INACTIVE Early Receive Interrupt status not detected 0 ACTIVE Early Receive Interrupt status detected 0x1 FBE Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). 12 1 read-write INACTIVE Fatal Bus Error status not detected 0 ACTIVE Fatal Bus Error status detected 0x1 CDE Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid. 13 1 read-write INACTIVE Context Descriptor Error status not detected 0 ACTIVE Context Descriptor Error status detected 0x1 AIS Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. 14 1 read-write INACTIVE Abnormal Interrupt Summary status not detected 0 ACTIVE Abnormal Interrupt Summary status detected 0x1 NIS Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in DMA_CH3_INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit. 15 1 read-write INACTIVE Normal Interrupt Summary status not detected 0 ACTIVE Normal Interrupt Summary status detected 0x1 TEB Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. 16 3 read-only REB Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. 19 3 read-only DMA_CH3_MISS_FRAME_CNT Channel 3 Missed Frame Counter 0x12E4 32 read-only 0 0xFFFFFFFF MFC Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in RX_CONTROL register. 0 11 read-only MFCO Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. 15 1 read-only INACTIVE Miss Frame Counter overflow not occurred 0 ACTIVE Miss Frame Counter overflow occurred 0x1 DMA_CH3_RXP_ACCEPT_CNT Channel 3 RXP Frames Accepted Counter 0x12E8 32 read-only 0 0xFFFFFFFF RXPAC Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. 0 31 read-only RXPACOF Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC Counter field crossed the maximum limit. 31 1 read-only INACTIVE Rx Parser Accept Counter overflow not occurred 0 ACTIVE Rx Parser Accept Counter overflow occurred 0x1 DMA_CH3_RX_ERI_CNT Channel 3 Receive ERI Counter 0x12EC 32 read-only 0 0xFFFFFFFF ECNT ERI Counter When ERIC bit of DMA_CH3_RX_CONTROL register is set, this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. 0 12 read-only DMA_CH4_CONTROL DMA Channel 4 Control 0x1300 32 read-write 0 0xFFFFFFFF PBLx8 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA_CH4_TX_CONTROL and Bits[21:16] in DMA_CH4_RX_CONTROL is multiplied by eight times. 16 1 read-write DISABLE 8xPBL mode is disabled 0 ENABLE 8xPBL mode is enabled 0x1 DSL Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. 18 3 read-write DMA_CH4_TX_CONTROL DMA Channel 4 Transmit Control 0x1304 32 read-write 0 0xFFFFFFFF ST Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. 0 1 read-write STOP Stop Transmission Command 0 START Start Transmission Command 0x1 OSF Operate on Second Packet When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 4 1 read-write DISABLE Operate on Second Packet disabled 0 ENABLE Operate on Second Packet enabled 0x1 IPBL Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of locations in the MTL before initiating a transfer. 15 1 read-write DISABLE Ignore PBL Requirement is disabled 0 ENABLE Ignore PBL Requirement is enabled 0x1 TxPBL Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. 16 6 read-write EDSE Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. 28 1 read-write DISABLE Enhanced Descriptor is disabled 0 ENABLE Enhanced Descriptor is enabled 0x1 DMA_CH4_RX_CONTROL DMA Channel 4 Receive Control 0x1308 32 read-write 0 0xFFFFFFFF SR Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. 0 1 read-write STOP Stop Receive 0 START Start Receive 0x1 RBSZ_x_0 Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. 1 3 read-only RBSZ_13_y Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. 4 11 read-write RxPBL Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. 16 6 read-write RPF Rx Packet Flush. 31 1 read-write DISABLE Rx Packet Flush is disabled 0 ENABLE Rx Packet Flush is enabled 0x1 DMA_CH4_TXDESC_LIST_ADDRESS Channel 4 Tx Descriptor List Address 0x1314 32 read-write 0 0xFFFFFFFF TDESLA Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. 3 29 read-write DMA_CH4_RXDESC_LIST_ADDRESS Channel 4 Rx Descriptor List Address 0x131C 32 read-write 0 0xFFFFFFFF RDESLA Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. 3 29 read-write DMA_CH4_TXDESC_TAIL_POINTER Channel 4 Tx Descriptor Tail Pointer 0x1320 32 read-write 0 0xFFFFFFFF TDTP Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. 3 29 read-write DMA_CH4_RXDESC_TAIL_POINTER Channel 4 Rx Descriptor Tail Pointer 0x1328 32 read-write 0 0xFFFFFFFF RDTP Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. 3 29 read-write DMA_CH4_TXDESC_RING_LENGTH Channel 4 Tx Descriptor Ring Length 0x132C 32 read-write 0 0xFFFFFFFF TDRL Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. 0 10 read-write DMA_CH4_RXDESC_RING_LENGTH Channel 4 Rx Descriptor Ring Length 0x1330 32 read-write 0 0xFFFFFFFF RDRL Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. 0 10 read-write DMA_CH4_INTERRUPT_ENABLE Channel 4 Interrupt Enable 0x1334 32 read-write 0 0xFFFFFFFF TIE Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. 0 1 read-write DISABLE Transmit Interrupt is disabled 0 ENABLE Transmit Interrupt is enabled 0x1 TXSE Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. 1 1 read-write DISABLE Transmit Stopped is disabled 0 ENABLE Transmit Stopped is enabled 0x1 TBUE Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. 2 1 read-write DISABLE Transmit Buffer Unavailable is disabled 0 ENABLE Transmit Buffer Unavailable is enabled 0x1 RIE Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled. 6 1 read-write DISABLE Receive Interrupt is disabled 0 ENABLE Receive Interrupt is enabled 0x1 RBUE Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. 7 1 read-write DISABLE Receive Buffer Unavailable is disabled 0 ENABLE Receive Buffer Unavailable is enabled 0x1 RSE Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. 8 1 read-write DISABLE Receive Stopped is disabled 0 ENABLE Receive Stopped is enabled 0x1 RWTE Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. 9 1 read-write DISABLE Receive Watchdog Timeout is disabled 0 ENABLE Receive Watchdog Timeout is enabled 0x1 ETIE Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. 10 1 read-write DISABLE Early Transmit Interrupt is disabled 0 ENABLE Early Transmit Interrupt is enabled 0x1 ERIE Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. 11 1 read-write DISABLE Early Receive Interrupt is disabled 0 ENABLE Early Receive Interrupt is enabled 0x1 FBEE Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. 12 1 read-write DISABLE Fatal Bus Error is disabled 0 ENABLE Fatal Bus Error is enabled 0x1 CDEE Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled. 13 1 read-write DISABLE Context Descriptor Error is disabled 0 ENABLE Context Descriptor Error is enabled 0x1 AIE Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled. 14 1 read-write DISABLE Abnormal Interrupt Summary is disabled 0 ENABLE Abnormal Interrupt Summary is enabled 0x1 NIE Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled. 15 1 read-write DISABLE Normal Interrupt Summary is disabled 0 ENABLE Normal Interrupt Summary is enabled 0x1 DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER Channel 4 Receive Interrupt Watchdog Timer 0x1338 32 read-write 0 0xFFFFFFFF RWT Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. 0 8 read-write RWTU Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. 16 2 read-write DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS Channel 4 Slot Function Control and Status 0x133C 32 read-write 0x7C0 0xFFFFFFFF ESC Enable Slot Comparison When set, this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. 0 1 read-write DISABLE Slot Comparison is disabled 0 ENABLE Slot Comparison is enabled 0x1 ASC Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot number by up to two slots This bit is applicable only when the ESC bit is set. 1 1 read-write DISABLE Advance Slot Check is disabled 0 ENABLE Advance Slot Check is enabled 0x1 SIV Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. 4 12 read-write RSN Reference Slot Number This field gives the current value of the reference slot number in the DMA. 16 4 read-only DMA_CH4_CURRENT_APP_TXDESC Channel 4 Current Application Transmit Descriptor 0x1344 32 read-only 0 0xFFFFFFFF CURTDESAPTR Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. 0 32 read-only DMA_CH4_CURRENT_APP_RXDESC Channel 4 Current Application Receive Descriptor 0x134C 32 read-only 0 0xFFFFFFFF CURRDESAPTR Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. 0 32 read-only DMA_CH4_CURRENT_APP_TXBUFFER Channel 4 Current Application Transmit Buffer Address 0x1354 32 read-only 0 0xFFFFFFFF CURTBUFAPTR Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. 0 32 read-only DMA_CH4_CURRENT_APP_RXBUFFER Channel 4 Current Application Receive Buffer Address 0x135C 32 read-only 0 0xFFFFFFFF CURRBUFAPTR Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. 0 32 read-only DMA_CH4_STATUS DMA Channel 4 Status 0x1360 32 read-write 0 0xFFFFFFFF TI Transmit Interrupt This bit indicates that the packet transmission is complete. 0 1 read-write INACTIVE Transmit Interrupt status not detected 0 ACTIVE Transmit Interrupt status detected 0x1 TPS Transmit Process Stopped This bit is set when the transmission is stopped. 1 1 read-write INACTIVE Transmit Process Stopped status not detected 0 ACTIVE Transmit Process Stopped status detected 0x1 TBU Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. 2 1 read-write INACTIVE Transmit Buffer Unavailable status not detected 0 ACTIVE Transmit Buffer Unavailable status detected 0x1 RI Receive Interrupt This bit indicates that the packet reception is complete. 6 1 read-write INACTIVE Receive Interrupt status not detected 0 ACTIVE Receive Interrupt status detected 0x1 RBU Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. 7 1 read-write INACTIVE Receive Buffer Unavailable status not detected 0 ACTIVE Receive Buffer Unavailable status detected 0x1 RPS Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. 8 1 read-write INACTIVE Receive Process Stopped status not detected 0 ACTIVE Receive Process Stopped status detected 0x1 RWT Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. 9 1 read-write INACTIVE Receive Watchdog Timeout status not detected 0 ACTIVE Receive Watchdog Timeout status detected 0x1 ETI Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. 10 1 read-write INACTIVE Early Transmit Interrupt status not detected 0 ACTIVE Early Transmit Interrupt status detected 0x1 ERI Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. 11 1 read-write INACTIVE Early Receive Interrupt status not detected 0 ACTIVE Early Receive Interrupt status detected 0x1 FBE Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). 12 1 read-write INACTIVE Fatal Bus Error status not detected 0 ACTIVE Fatal Bus Error status detected 0x1 CDE Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid. 13 1 read-write INACTIVE Context Descriptor Error status not detected 0 ACTIVE Context Descriptor Error status detected 0x1 AIS Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. 14 1 read-write INACTIVE Abnormal Interrupt Summary status not detected 0 ACTIVE Abnormal Interrupt Summary status detected 0x1 NIS Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit. 15 1 read-write INACTIVE Normal Interrupt Summary status not detected 0 ACTIVE Normal Interrupt Summary status detected 0x1 TEB Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. 16 3 read-only REB Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. 19 3 read-only DMA_CH4_MISS_FRAME_CNT Channel 4 Missed Frame Counter 0x1364 32 read-only 0 0xFFFFFFFF MFC Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in RX_CONTROL register. 0 11 read-only MFCO Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. 15 1 read-only INACTIVE Miss Frame Counter overflow not occurred 0 ACTIVE Miss Frame Counter overflow occurred 0x1 DMA_CH4_RXP_ACCEPT_CNT Channel 4 RXP Frames Accepted Counter 0x1368 32 read-only 0 0xFFFFFFFF RXPAC Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. 0 31 read-only RXPACOF Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC Counter field crossed the maximum limit. 31 1 read-only INACTIVE Rx Parser Accept Counter overflow not occurred 0 ACTIVE Rx Parser Accept Counter overflow occurred 0x1 DMA_CH4_RX_ERI_CNT Channel 4 Receive ERI Counter 0x136C 32 read-only 0 0xFFFFFFFF ECNT ERI Counter When ERIC bit of DMA_CH4_RX_CONTROL register is set, this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. 0 12 read-only CAAM CAAM CAAM 0x40440000 0 0x100000 registers CAAM_IRQ0 69 CAAM_IRQ1 70 CAAM_IRQ2 71 CAAM_IRQ3 72 CAAM_RECORVE_ERRPR 73 CAAM_RTIC 74 4 0x20 RMaAb[%s] no description available 0 2 0x10 RM[%s] no description available 0x60100 RMA RTIC Memory Block memoryBlock Address segment Register 0 64 read-write 0 0xFFFFFFFFFFFFFFFF MEMBLKADDR Memory Block Address 0 36 read-write RML RTIC Memory Block memoryBlock Length segment Register 0xC 32 read-write 0 0xFFFFFFFF MEMBLKLEN Memory Block Lengths 0 32 read-write 4 0x100 RaMD[%s] no description available 0 2 0x80 RaMD[%s] no description available 0x60200 32 0x4 RMD_[%s] RTIC Memory Block memoryBlock endianness_full Endian Hash Result Word word 0 32 read-write 0 0xFFFFFFFF RTIC_Hash_Result RTIC_Hash_Result 0 32 read-write MCFGR Master Configuration Register 0x4 32 read-write 0x82301 0xFFFFFFFF NORMAL_BURST Normal Burst Size 0 1 read-only ALIGNED_32B_TARGET Aligned 32 byte burst size target 0 ALIGNED_64B_TARGET Aligned 64 byte burst size target 0x1 LARGE_BURST Enable Large Bursts 2 1 read-write AXIPIPE AXI Pipeline Depth 4 4 read-write AWCACHE AXI Write Transaction Attributes 8 4 read-write ARCACHE AXI Read Transaction Attributes 12 4 read-write PS Pointer Size. This bit determines the size of address pointers. (see Address pointers). 16 1 read-write SML_32Bit_PTRS Pointers fit in one 32-bit word (pointers are 32-bit addresses). 0 LRG_64BIT_PTRS Pointers require two 32-bit words (pointers are 36-bit addresses). 0x1 DWT Double Word Transpose 19 1 read-write WRHD Write Handoff Disable 27 1 read-write DMA_RST DMA Reset 28 1 write-only WDF Watchdog Fast 29 1 read-write WDE DECO Watchdog Enable 30 1 read-write SWRST Software Reset 31 1 read-write PAGE0_SDID Page 0 SDID Register 0x8 32 read-write 0 0xFFFFFFFF SDID Security Domain Identifier 0 15 read-write SCFGR Security Configuration Register 0xC 32 read-write 0 0xFFFFFFFF PRIBLOB Private Blob 0 2 read-write PRIV_SEC_BOOT_SW Private secure boot software blobs 0 PRIV_PROV_TYPE_1 Private provisioning type 1 blobs 0x1 PRIV_PROV_TYPE_2 Private provisioning type 2 blobs 0x2 NORMAL_OPERATION Normal operation blobs 0x3 RNGSH0 Random Number Generator State Handle 0. 9 1 read-write SH0_ANY_MODE When RNGSH0 is 0, RNG DRNG State Handle 0 can be instantiated in any mode. RNGSH0 is set to 0 only for testing. 0 SH0_RANDOM_MODE When RNGSH0 is 1, RNG DRNG State Handle 0 cannot be instantiated in deterministic (test) mode. RNGSHO should be set to 1 before the RNG is instantiated. If it is currently instantiated in a deterministic mode, it will be un-instantiated. Once this bit has been written to a 1, it cannot be changed to a 0 until the next power on reset. 0x1 LCK_TRNG Lock TRNG Program Mode 11 1 read-write VIRT_EN Virtualization enable 15 1 read-write DISABLE_JR_VIRT Disable job ring virtualization 0 ENABLE_JR_VIRT Enable job ring virtualization 0x1 MPMRL Manufacturing Protection Message Register Lock 26 1 read-write MPPKRC Manufacturing Protection Private Key Register Clear 27 1 write-only MPCURVE Manufacturing Protection Curve 28 4 read-only 4 0x8 JRaDID[%s] no description available 0x10 JRDID_MS Job Ring Job_Ring DID Register - most significant half 0 32 read-write 0 0xFFFFFFFF PRIM_DID Job Ring Owner's DID 0 4 read-write PRIM_TZ Primary TZ 4 1 read-write SDID_MS Security Domain Identifier most significant bits 5 10 read-write TZ_OWN TrustZone SecureWorld 15 1 read-write AMTD Allow Make Trusted Descriptor 16 1 read-write LAMTD Lock AMTD 17 1 read-write PRIM_ICID Primary ICID 19 11 read-write USE_OUT USE_OUT 30 1 read-write LDID Lock DIDs 31 1 read-write JRDID_LS Job Ring Job_Ring DID Register - least significant half 0x4 32 read-write 0 0xFFFFFFFF OUT_DID Output DID 0 4 read-write OUT_ICID Job Ring Output ICID 19 11 read-write DEBUGCTL Debug Control Register 0x58 32 read-write 0 0xFFFFFFFF STOP STOP is written to 1 to request that CAAM stop processing jobs 16 1 read-write STOP_ACK STOP_ACK will assert when the job queue controller acknowledges that it is stopped. 17 1 read-only JRSTARTR Job Ring Start Register 0x5C 32 read-write 0 0xFFFFFFFF Start_JR0 Start Job Ring 0 0 1 read-write JR0_STOP_MODE Stop Mode. The JR0DID register and the SMVBA register for Job Ring 0 can be written but the IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 0 are NOT accessible. If Job Ring 0 is allocated to TrustZone SecureWorld (JR0DID[TZ]=1), the JR0DID and SMVBA register can be written only via a bus transaction that has ns=0. 0 JR0_START_MODE Start Mode. The JR0DID register and the SMVBA register for Job Ring 0 CANNOT be written but the IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 0 ARE accessible. If Job Ring 0 is allocated to TrustZone SecureWorld (JR0DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR registers for Job Ring 0 can be written only via a bus transaction that has ns=0. 0x1 Start_JR1 Start Job Ring 1 1 1 read-write JR1_STOP_MODE Stop Mode. The JR1DID register and the SMVBA register for Job Ring 1 can be written but the IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 1 are NOT accessible. If Job Ring 1 is allocated to TrustZone SecureWorld (JR1DID[TZ]=1), the JR1DID and SMVBA register can be written only via a bus transaction that has ns=0. 0 JR1_START_MODE Start Mode. The JR1DID register and the SMVBA register for Job Ring 1 CANNOT be written but the IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 1 ARE accessible. If Job Ring 1 is allocated to TrustZone SecureWorld (JR1DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR registers for Job Ring 1 can be written only via a bus transaction that has ns=0. 0x1 Start_JR2 Start Job Ring 2 2 1 read-write JR2_STOP_MODE Stop Mode. The JR2DID register and the SMVBA register for Job Ring 2 can be written but the IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 2 are NOT accessible. If Job Ring 2 is allocated to TrustZone SecureWorld (JR2DID[TZ]=1), the JR2DID and SMVBA register can be written only via a bus transaction that has ns=0. 0 JR2_START_MODE Start Mode. The JR2DID register and the SMVBA register for Job Ring 2 CANNOT be written but the IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 2 ARE accessible. If Job Ring 2 is allocated to TrustZone SecureWorld (JR2DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR registers for Job Ring 2 can be written only via a bus transaction that has ns=0. 0x1 Start_JR3 Start Job Ring 3 3 1 read-write JR3_STOP_MODE Stop Mode. The JR3DID register and the SMVBA register for Job Ring 3 can be written but the IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 3 are NOT accessible. If Job Ring 3 is allocated to TrustZone SecureWorld (JR3DID[TZ]=1), the JR3DID and SMVBA register can be written only via a bus transaction that has ns=0. 0 JR3_START_MODE Start Mode. The JR3DID register and the SMVBA register for Job Ring 3 CANNOT be written but the IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 3 ARE accessible. If Job Ring 3 is allocated to TrustZone SecureWorld (JR3DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR registers for Job Ring 3 can be written only via a bus transaction that has ns=0. 0x1 RTIC_OWN RTIC OWN Register 0x60 32 read-write 0 0xFFFFFFFF ROWN_DID RTIC Owner's DID 0 4 read-write ROWN_TZ RTIC Owner's TZ 4 1 read-write LCK RTIC OWN Lock 31 1 read-write 4 0x8 RTICaDID[%s] no description available 0x60 RTIC_DID RTIC DID Register for Block RTIC_hash_block 0x4 32 read-write 0 0xFFFFFFFF RTIC_DID RTIC DID 0 4 read-write RTIC_TZ RTIC_TZ 4 1 read-write RTIC_ICID RTIC ICID 19 11 read-write DECORSR DECO Request Source Register 0x94 32 read-write 0 0xFFFFFFFF JR Job Ring number 0 2 read-write VALID Valid 31 1 read-only DECORR DECO Request Register 0x9C 32 read-write 0 0xFFFFFFFF RQD0 This bit is set by software to request direct access to DECO 0/CCB 0 0 1 read-write DEN0 The job queue controller asserts this bit when permission is granted for the software to directly access DECO 0/CCB 0 16 1 read-only DECO0DID_MS DECO0 DID Register - most significant half 0xA0 32 read-write 0 0xFFFFFFFF DPRIM_DID DECO Owner 0 4 read-write D_NS DECO Owner's ns 4 1 read-write LCK Lock 31 1 read-write DECO0DID_LS DECO0 DID Register - least significant half 0xA4 32 read-write 0 0xFFFFFFFF DSEQ_DID DECO SEQ DID 0 4 read-write DSEQ_NS DECO SEQ NonSecure 4 1 read-write DNSEQ_DID DECO Non-SEQ DID 16 4 read-write DNONSEQ_NS DECO NONSEQ NonSecure 20 1 read-write DAR DECO Availability Register 0x120 32 read-write 0 0xFFFFFFFF NYA0 This bit is set by software to start polling for the availability of DECO 0 0 1 read-write DRR DECO Reset Register 0x124 32 write-only 0 0xFFFFFFFF RST0 Software writes a 1 to this bit to initiate a soft reset of DECO 0 0 1 write-only 4 0x8 JRnSMVBAR[%s] no description available 0x184 JRSMVBAR Job Ring Job_Ring Secure Memory Virtual Base Address Register 0 32 read-write 0 0 SMVBA Secure Memory Virtual Base Address 0 32 read-write PBSL Peak Bandwidth Smoothing Limit Register 0x220 32 read-write 0 0xFFFFFFFF PBSL Whenever the number of outstanding AXI read bursts exceeds the value programmed in this field, the Job Rings will be prevented from issuing additional AXI reads 0 7 read-write DMA0_AIDL_MAP_MS DMA0_AIDL_MAP_MS 0x240 32 read-only 0 0 AID4_BID This field shows the CAAM Block ID that uses AXI ID 4. 0 8 read-only AID5_BID This field shows the CAAM Block ID that uses AXI ID 5. 8 8 read-only AID6_BID This field shows the CAAM Block ID that uses AXI ID 6. 16 8 read-only AID7_BID This field shows the CAAM Block ID that uses AXI ID 7. 24 8 read-only DMA0_AIDL_MAP_LS DMA0_AIDL_MAP_LS 0x244 32 read-only 0 0 AID0_BID This field shows the CAAM Block ID that uses AXI ID 0. 0 8 read-only AID1_BID This field shows the CAAM Block ID that uses AXI ID 1. 8 8 read-only AID2_BID This field shows the CAAM Block ID that uses AXI ID 2. 16 8 read-only AID3_BID This field shows the CAAM Block ID that uses AXI ID 3. 24 8 read-only DMA0_AIDM_MAP_MS DMA0_AIDM_MAP_MS 0x248 32 read-only 0 0 AID12_BID This field shows the CAAM Block ID that uses AXI ID 12. 0 8 read-only AID13_BID This field shows the CAAM Block ID that uses AXI ID 13. 8 8 read-only AID14_BID This field shows the CAAM Block ID that uses AXI ID 14. 16 8 read-only AID15_BID This field shows the CAAM Block ID that uses AXI ID 15. 24 8 read-only DMA0_AIDM_MAP_LS DMA0_AIDM_MAP_LS 0x24C 32 read-only 0 0 AID8_BID This field shows the CAAM Block ID that uses AXI ID 8. 0 8 read-only AID9_BID This field shows the CAAM Block ID that uses AXI ID 9. 8 8 read-only AID10_BID This field shows the CAAM Block ID that uses AXI ID 10. 16 8 read-only AID11_BID This field shows the CAAM Block ID that uses AXI ID 11. 24 8 read-only DMA0_AID_ENB DMA0 AXI ID Enable Register 0x250 32 read-only 0 0 AID0E If AID0E=1 then AXI ID 0 is enabled for this DMA engine. 0 1 read-only AID1E If AID1E=1 then AXI ID 1 is enabled for this DMA engine. 1 1 read-only AID2E If AID2E=1 then AXI ID 2 is enabled for this DMA engine. 2 1 read-only AID3E If AID3E=1 then AXI ID 3 is enabled for this DMA engine. 3 1 read-only AID4E If AID4E=1 then AXI ID 4 is enabled for this DMA engine. 4 1 read-only AID5E If AID5E=1 then AXI ID 5 is enabled for this DMA engine. 5 1 read-only AID6E If AID6E=1 then AXI ID 6 is enabled for this DMA engine. 6 1 read-only AID7E If AID7E=1 then AXI ID 7 is enabled for this DMA engine. 7 1 read-only AID8E If AID8E=1 then AXI ID 8 is enabled for this DMA engine. 8 1 read-only AID9E If AID9E=1 then AXI ID 9 is enabled for this DMA engine. 9 1 read-only AID10E If AID10E=1 then AXI ID 10 is enabled for this DMA engine. 10 1 read-only AID11E If AID11E=1 then AXI ID 11 is enabled for this DMA engine. 11 1 read-only AID12E If AID12E=1 then AXI ID 12 is enabled for this DMA engine. 12 1 read-only AID13E If AID13E=1 then AXI ID 13 is enabled for this DMA engine. 13 1 read-only AID14E If AID14E=1 then AXI ID 14 is enabled for this DMA engine. 14 1 read-only AID15E If AID15E=1 then AXI ID 15 is enabled for this DMA engine. 15 1 read-only DMA0_ARD_TC DMA0 AXI Read Timing Check Register 0x260 64 read-write 0 0xFFFFFFFFFFFFFFFF ARSC AXI Read Sample Count 0 20 read-write ARLC AXI Read Late Count 24 20 read-write ARL AXI Read Limit 48 12 read-write ARTL AXI Read Timer Last 60 1 read-write ARTT AXI Read Timer Test 61 1 read-write ARCT AXI Read Counter Test 62 1 read-write ARTCE AXI Read Timing Check Enable 63 1 read-write DMA0_ARD_LAT DMA0 Read Timing Check Latency Register 0x26C 32 read-write 0 0xFFFFFFFF SARL Sum of the AXI Read Latencies 0 32 read-write DMA0_AWR_TC DMA0 AXI Write Timing Check Register 0x270 64 read-write 0 0xFFFFFFFFFFFFFFFF AWSC AXI Write Sample Count 0 20 read-write AWLC AXI Write Late Count 24 20 read-write AWL AXI Write Limit 48 12 read-write AWTT AXI Write Timer Test 61 1 read-write AWCT AXI Write Counter Test 62 1 read-write AWTCE AXI Write Timing Check Enable 63 1 read-write DMA0_AWR_LAT DMA0 Write Timing Check Latency Register 0x27C 32 read-write 0 0xFFFFFFFF SAWL Sum of the AXI Write Latencies 0 32 read-write 64 0x1 MPPKR[%s] Manufacturing Protection Private Key Register 0x300 8 read-write 0 0xFF MPPrivK MPPrivK. The 512-bit Manufacturing Protection Private Key. 0 8 read-write 32 0x1 MPMR[%s] Manufacturing Protection Message Register 0x380 8 read-write 0 0xFF MPMSG Holds 256 bits of message data that will be prepended to the input data to the MPSIGN operation 0 8 read-write 32 0x1 MPTESTR[%s] Manufacturing Protection Test Register 0x3C0 8 read-only 0 0xFF TEST_VALUE TEST_VALUE 0 8 read-only MPECC Manufacturing Protection ECC Register 0x3F8 32 read-only 0 0xFFFFFFFF MP_SYNDROME This is the syndrome produced by the ECC check on the Manufacturing Protection Key that is programmed in the Security Fuse Processor 16 9 read-only KEYOK The MP Key in the SFP passes the ECC check. 0 KEYBAD The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome. 0x1 KEYBAD The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome. 0x2 KEYBAD The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome. 0x3 KEYBAD The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome. 0x4 KEYBAD The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome. 0x5 KEYBAD The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome. 0x6 KEYBAD The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome. 0x7 KEYBAD The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome. 0x8 KEYBAD The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome. 0x9 MP_ZERO This bit indicates if the Manufacturing Protection Key that is programmed in the Security Fuse Processor has an all-zero value 27 1 read-only NONZERO The MP Key in the SFP has a non-zero value. 0 ALLZERO The MP Key in the SFP is all zeros (unprogrammed). 0x1 8 0x4 JDKEKR[%s] Job Descriptor Key Encryption Key Register 0x400 32 read-write 0 0 JDKEK The 256-bit Job Descriptor Key Encryption Key used to encrypt and decrypt Black Keys. 0 32 read-write 8 0x4 TDKEKR[%s] Trusted Descriptor Key Encryption Key Register 0x420 32 read-write 0 0 TDKEK The 256-bit Trusted Descriptor Key Encryption Key used to encrypt and decrypt Black Keys. 0 32 read-write 8 0x4 TDSKR[%s] Trusted Descriptor Signing Key Register 0x440 32 read-write 0 0 TDSK The 256-bit Trusted Descriptor Signing Key used to sign and verify Trusted Descriptors. 0 32 read-write SKNR Secure Key Nonce Register 0x4E0 64 read-write 0 0xFFFFFFFFFFFFFFFF SK_NONCE_LS Secure Key Nonce - Least Significant Bits 0 32 read-write SK_NONCE_MS Secure Key Nonce - Most Significant Bits 32 15 read-write DMA_STA DMA Status Register 0x50C 32 read-only 0x80 0xFFFFFFFF DMA0_ETIF DMA0 External Transactions in Flight 0 5 read-only DMA0_ITIF DMA0 Internal Transactions in Flight 5 1 read-only DMA0_IDLE DMA0 is idle. DMA0's command queue is empty. 7 1 read-only DMA_X_AID_7_4_MAP DMA_X_AID_7_4_MAP 0x510 32 read-only 0 0 AID4_BID This field shows the CAAM Block ID that uses AXI ID 4. 0 8 read-only AID5_BID This field shows the CAAM Block ID that uses AXI ID 5. 8 8 read-only AID6_BID This field shows the CAAM Block ID that uses AXI ID 6. 16 8 read-only AID7_BID This field shows the CAAM Block ID that uses AXI ID 7. 24 8 read-only DMA_X_AID_3_0_MAP DMA_X_AID_3_0_MAP 0x514 32 read-only 0 0 AID0_BID This field shows the CAAM Block ID that uses AXI ID 0. 0 8 read-only AID1_BID This field shows the CAAM Block ID that uses AXI ID 1. 8 8 read-only AID2_BID This field shows the CAAM Block ID that uses AXI ID 2. 16 8 read-only AID3_BID This field shows the CAAM Block ID that uses AXI ID 3. 24 8 read-only DMA_X_AID_15_12_MAP DMA_X_AID_15_12_MAP 0x518 32 read-only 0 0 AID12_BID This field shows the CAAM Block ID that uses AXI ID 12. 0 8 read-only AID13_BID This field shows the CAAM Block ID that uses AXI ID 13. 8 8 read-only AID14_BID This field shows the CAAM Block ID that uses AXI ID 14. 16 8 read-only AID15_BID This field shows the CAAM Block ID that uses AXI ID 15. 24 8 read-only DMA_X_AID_11_8_MAP DMA_X_AID_11_8_MAP 0x51C 32 read-only 0 0 AID8_BID This field shows the CAAM Block ID that uses AXI ID 8. 0 8 read-only AID9_BID This field shows the CAAM Block ID that uses AXI ID 9. 8 8 read-only AID10_BID This field shows the CAAM Block ID that uses AXI ID 10. 16 8 read-only AID11_BID This field shows the CAAM Block ID that uses AXI ID 11. 24 8 read-only DMA_X_AID_15_0_EN DMA_X AXI ID Map Enable Register 0x524 32 read-only 0 0 AID0E If AID0E=1 then AXI ID 0 is enabled for this DMA engine. 0 1 read-only AID1E If AID1E=1 then AXI ID 1 is enabled for this DMA engine. 1 1 read-only AID2E If AID2E=1 then AXI ID 2 is enabled for this DMA engine. 2 1 read-only AID3E If AID3E=1 then AXI ID 3 is enabled for this DMA engine. 3 1 read-only AID4E If AID4E=1 then AXI ID 4 is enabled for this DMA engine. 4 1 read-only AID5E If AID5E=1 then AXI ID 5 is enabled for this DMA engine. 5 1 read-only AID6E If AID6E=1 then AXI ID 6 is enabled for this DMA engine. 6 1 read-only AID7E If AID7E=1 then AXI ID 7 is enabled for this DMA engine. 7 1 read-only AID8E If AID8E=1 then AXI ID 8 is enabled for this DMA engine. 8 1 read-only AID9E If AID9E=1 then AXI ID 9 is enabled for this DMA engine. 9 1 read-only AID10E If AID10E=1 then AXI ID 10 is enabled for this DMA engine. 10 1 read-only AID11E If AID11E=1 then AXI ID 11 is enabled for this DMA engine. 11 1 read-only AID12E If AID12E=1 then AXI ID 12 is enabled for this DMA engine. 12 1 read-only AID13E If AID13E=1 then AXI ID 13 is enabled for this DMA engine. 13 1 read-only AID14E If AID14E=1 then AXI ID 14 is enabled for this DMA engine. 14 1 read-only AID15E If AID15E=1 then AXI ID 15 is enabled for this DMA engine. 15 1 read-only DMA_X_ARTC_CTL DMA_X AXI Read Timing Check Control Register 0x530 32 read-write 0 0xFFFFFFFF ART AXI Read Timer 0 12 read-write ARL AXI Read Limit 16 12 read-write ARTL AXI Read Timer Last 28 1 read-write ARTT AXI Read Timer Test 29 1 read-write ARCT AXI Read Counter Test 30 1 read-write ARTCE AXI Read Timing Check Enable 31 1 read-write DMA_X_ARTC_LC DMA_X AXI Read Timing Check Late Count Register 0x534 32 read-write 0 0xFFFFFFFF ARLC AXI Read Late Count 0 20 read-write DMA_X_ARTC_SC DMA_X AXI Read Timing Check Sample Count Register 0x538 32 read-write 0 0xFFFFFFFF ARSC AXI Read Sample Count 0 20 read-write DMA_X_ARTC_LAT DMA_X Read Timing Check Latency Register 0x53C 32 read-write 0 0xFFFFFFFF SARL Sum of the AXI Read Latencies 0 32 read-write DMA_X_AWTC_CTL DMA_X AXI Write Timing Check Control Register 0x540 32 read-write 0 0xFFFFFFFF AWT AXI Write Timer 0 12 read-write AWL AXI Write Limit 16 12 read-write AWTT AXI Write Timer Test 29 1 read-write AWCT AXI Write Counter Test 30 1 read-write AWTCE AXI Write Timing Check Enable 31 1 read-write DMA_X_AWTC_LC DMA_X AXI Write Timing Check Late Count Register 0x544 32 read-write 0 0xFFFFFFFF AWLC AXI Write Late Count 0 20 read-write DMA_X_AWTC_SC DMA_X AXI Write Timing Check Sample Count Register 0x548 32 read-write 0 0xFFFFFFFF AWSC AXI Write Sample Count 0 20 read-write DMA_X_AWTC_LAT DMA_X Write Timing Check Latency Register 0x54C 32 read-write 0 0xFFFFFFFF SAWL Sum of the AXI Write Latencies 0 32 read-write RTMCTL RNG TRNG Miscellaneous Control Register 0x600 32 read-write 0x1 0xFFFFFFFF SAMP_MODE Sample Mode 0 2 read-write VON_DATA_4_SHIFTER_N_CHECKER use Von Neumann data into both Entropy shifter and Statistical Checker 0 RAW_DATA_4_SHIFTER_N_CHECKER use raw data into both Entropy shifter and Statistical Checker 0x1 VON_4_SHIFTER_N_RAW_4_CHECKER use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker 0x2 OSC_DIV Oscillator Divide 2 2 read-write OSC_NOT_DIVIDED use ring oscillator with no divide 0 OSC_DIVIDE_BY_2 use ring oscillator divided-by-2 0x1 OSC_DIVIDE_BY_4 use ring oscillator divided-by-4 0x2 OSC_DIVIDE_BY_8 use ring oscillator divided-by-8 0x3 CLK_OUT_EN Clock Output Enable 4 1 read-write TRNG_ACC TRNG Access Mode 5 1 read-write RST_DEF Reset Defaults 6 1 write-only FORCE_SYSCLK Force System Clock 7 1 read-write FCT_FAIL Read only: Frequency Count Fail 8 1 read-only FCT_VAL Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from RTFRQCNT. 9 1 read-only ENT_VAL Read only: Entropy Valid 10 1 read-only TST_OUT Read only: Test point inside ring oscillator. 11 1 read-only ERR Read: Error status 12 1 read-write oneToClear TSTOP_OK TRNG_OK_TO_STOP 13 1 read-only PRGM Programming Mode Select 16 1 read-write RTSCMISC RNG TRNG Statistical Check Miscellaneous Register 0x604 32 read-write 0x10022 0xFFFFFFFF LRUN_MAX LONG RUN MAX LIMIT 0 8 read-write RTY_CNT RETRY COUNT 16 4 read-write RTPKRRNG RNG TRNG Poker Range Register 0x608 32 read-write 0x9A3 0xFFFFFFFF PKR_RNG Poker Range 0 16 read-write RTPKRMAX RNG TRNG Poker Maximum Limit Register MAX_RSQ 0x60C 32 read-write 0x6920 0xFFFFFFFF PKR_MAX Poker Maximum Limit 0 24 read-write RTPKRSQ RNG TRNG Poker Square Calculation Result Register MAX_RSQ 0x60C 32 read-only 0 0xFFFFFFFF PKR_SQ Poker Square Calculation Result 0 24 read-only RTSDCTL RNG TRNG Seed Control Register 0x610 32 read-write 0xC8009C4 0xFFFFFFFF SAMP_SIZE Sample Size 0 16 read-write ENT_DLY Entropy Delay 16 16 read-write RTSBLIM RNG TRNG Sparse Bit Limit Register SBLIM_TOTSAM 0x614 32 read-write 0x3F 0xFFFFFFFF SB_LIM Sparse Bit Limit 0 10 read-write RTTOTSAM RNG TRNG Total Samples Register SBLIM_TOTSAM 0x614 32 read-only 0 0xFFFFFFFF TOT_SAM Total Samples 0 20 read-only RTFRQMIN RNG TRNG Frequency Count Minimum Limit Register 0x618 32 read-write 0x640 0xFFFFFFFF FRQ_MIN Frequency Count Minimum Limit 0 22 read-write RTFRQCNT RNG TRNG Frequency Count Register RTFRQ 0x61C 32 read-only 0 0xFFFFFFFF FRQ_CNT Frequency Count 0 22 read-only RTFRQMAX RNG TRNG Frequency Count Maximum Limit Register RTFRQ 0x61C 32 read-write 0x6400 0xFFFFFFFF FRQ_MAX Frequency Counter Maximum Limit 0 22 read-write RTSCMC RNG TRNG Statistical Check Monobit Count Register RTFRQ 0x620 32 read-only 0 0xFFFFFFFF MONO_CNT Monobit Count 0 16 read-only RTSCML RNG TRNG Statistical Check Monobit Limit Register RTFRQ 0x620 32 read-write 0x10C0568 0xFFFFFFFF MONO_MAX Monobit Maximum Limit 0 16 read-write MONO_RNG Monobit Range 16 16 read-write RTSCR1C RNG TRNG Statistical Check Run Length 1 Count Register RTFRQ 0x624 32 read-only 0 0xFFFFFFFF R1_0_COUNT Runs of Zero, Length 1 Count 0 15 read-only R1_1_COUNT Runs of One, Length 1 Count 16 15 read-only RTSCR1L RNG TRNG Statistical Check Run Length 1 Limit Register RTFRQ 0x624 32 read-write 0xB20195 0xFFFFFFFF RUN1_MAX Run Length 1 Maximum Limit 0 15 read-write RUN1_RNG Run Length 1 Range 16 15 read-write RTSCR2C RNG TRNG Statistical Check Run Length 2 Count Register RTFRQ 0x628 32 read-only 0 0xFFFFFFFF R2_0_COUNT Runs of Zero, Length 2 Count 0 14 read-only R2_1_COUNT Runs of One, Length 2 Count 16 14 read-only RTSCR2L RNG TRNG Statistical Check Run Length 2 Limit Register RTFRQ 0x628 32 read-write 0x7A00DC 0xFFFFFFFF RUN2_MAX Run Length 2 Maximum Limit 0 14 read-write RUN2_RNG Run Length 2 Range 16 14 read-write RTSCR3C RNG TRNG Statistical Check Run Length 3 Count Register RTFRQ 0x62C 32 read-only 0 0xFFFFFFFF R3_0_COUNT Runs of Zeroes, Length 3 Count 0 13 read-only R3_1_COUNT Runs of Ones, Length 3 Count 16 13 read-only RTSCR3L RNG TRNG Statistical Check Run Length 3 Limit Register RTFRQ 0x62C 32 read-write 0x58007D 0xFFFFFFFF RUN3_MAX Run Length 3 Maximum Limit 0 13 read-write RUN3_RNG Run Length 3 Range 16 13 read-write RTSCR4C RNG TRNG Statistical Check Run Length 4 Count Register RTFRQ 0x630 32 read-only 0 0xFFFFFFFF R4_0_COUNT Runs of Zero, Length 4 Count 0 12 read-only R4_1_COUNT Runs of One, Length 4 Count 16 12 read-only RTSCR4L RNG TRNG Statistical Check Run Length 4 Limit Register RTFRQ 0x630 32 read-write 0x40004B 0xFFFFFFFF RUN4_MAX Run Length 4 Maximum Limit 0 12 read-write RUN4_RNG Run Length 4 Range 16 12 read-write RTSCR5C RNG TRNG Statistical Check Run Length 5 Count Register RTFRQ 0x634 32 read-only 0 0xFFFFFFFF R5_0_COUNT Runs of Zero, Length 5 Count 0 11 read-only R5_1_COUNT Runs of One, Length 5 Count 16 11 read-only RTSCR5L RNG TRNG Statistical Check Run Length 5 Limit Register RTFRQ 0x634 32 read-write 0x2E002F 0xFFFFFFFF RUN5_MAX Run Length 5 Maximum Limit 0 11 read-write RUN5_RNG Run Length 5 Range 16 11 read-write RTSCR6PC RNG TRNG Statistical Check Run Length 6+ Count Register RTFRQ 0x638 32 read-only 0 0xFFFFFFFF R6P_0_COUNT Runs of Zero, Length 6+ Count 0 11 read-only R6P_1_COUNT Runs of One, Length 6+ Count 16 11 read-only RTSCR6PL RNG TRNG Statistical Check Run Length 6+ Limit Register RTFRQ 0x638 32 read-write 0x2E002F 0xFFFFFFFF RUN6P_MAX Run Length 6+ Maximum Limit 0 11 read-write RUN6P_RNG Run Length 6+ Range 16 11 read-write RTSTATUS RNG TRNG Status Register 0x63C 32 read-only 0 0xFFFFFFFF F1BR0TF 1-Bit Run, Sampling 0s, Test Fail. If 1BR0TF=1, the 1-Bit Run, Sampling 0s Test has failed. 0 1 read-only F1BR1TF 1-Bit Run, Sampling 1s, Test Fail. If 1BR1TF=1, the 1-Bit Run, Sampling 1s Test has failed. 1 1 read-only F2BR0TF 2-Bit Run, Sampling 0s, Test Fail. If 2BR0TF=1, the 2-Bit Run, Sampling 0s Test has failed. 2 1 read-only F2BR1TF 2-Bit Run, Sampling 1s, Test Fail. If 2BR1TF=1, the 2-Bit Run, Sampling 1s Test has failed. 3 1 read-only F3BR01TF 3-Bit Run, Sampling 0s, Test Fail. If 3BR0TF=1, the 3-Bit Run, Sampling 0s Test has failed. 4 1 read-only F3BR1TF 3-Bit Run, Sampling 1s, Test Fail. If 3BR1TF=1, the 3-Bit Run, Sampling 1s Test has failed. 5 1 read-only F4BR0TF 4-Bit Run, Sampling 0s, Test Fail. If 4BR0TF=1, the 4-Bit Run, Sampling 0s Test has failed. 6 1 read-only F4BR1TF 4-Bit Run, Sampling 1s, Test Fail. If 4BR1TF=1, the 4-Bit Run, Sampling 1s Test has failed. 7 1 read-only F5BR0TF 5-Bit Run, Sampling 0s, Test Fail. If 5BR0TF=1, the 5-Bit Run, Sampling 0s Test has failed. 8 1 read-only F5BR1TF 5-Bit Run, Sampling 1s, Test Fail. If 5BR1TF=1, the 5-Bit Run, Sampling 1s Test has failed. 9 1 read-only F6PBR0TF 6 Plus Bit Run, Sampling 0s, Test Fail 10 1 read-only F6PBR1TF 6 Plus Bit Run, Sampling 1s, Test Fail 11 1 read-only FSBTF Sparse Bit Test Fail. If SBTF=1, the Sparse Bit Test has failed. 12 1 read-only FLRTF Long Run Test Fail. If LRTF=1, the Long Run Test has failed. 13 1 read-only FPTF Poker Test Fail. If PTF=1, the Poker Test has failed. 14 1 read-only FMBTF Mono Bit Test Fail. If MBTF=1, the Mono Bit Test has failed. 15 1 read-only RETRY_COUNT RETRY COUNT 16 4 read-only 16 0x4 RTENT[%s] RNG TRNG Entropy Read Register 0x640 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only RTPKRCNT10 RNG TRNG Statistical Check Poker Count 1 and 0 Register 0x680 32 read-only 0 0xFFFFFFFF PKR_0_CNT Poker 0h Count 0 16 read-only PKR_1_CNT Poker 1h Count 16 16 read-only RTPKRCNT32 RNG TRNG Statistical Check Poker Count 3 and 2 Register 0x684 32 read-only 0 0xFFFFFFFF PKR_2_CNT Poker 2h Count 0 16 read-only PKR_3_CNT Poker 3h Count 16 16 read-only RTPKRCNT54 RNG TRNG Statistical Check Poker Count 5 and 4 Register 0x688 32 read-only 0 0xFFFFFFFF PKR_4_CNT Poker 4h Count 0 16 read-only PKR_5_CNT Poker 5h Count 16 16 read-only RTPKRCNT76 RNG TRNG Statistical Check Poker Count 7 and 6 Register 0x68C 32 read-only 0 0xFFFFFFFF PKR_6_CNT Poker 6h Count 0 16 read-only PKR_7_CNT Poker 7h Count 16 16 read-only RTPKRCNT98 RNG TRNG Statistical Check Poker Count 9 and 8 Register 0x690 32 read-only 0 0xFFFFFFFF PKR_8_CNT Poker 8h Count 0 16 read-only PKR_9_CNT Poker 9h Count 16 16 read-only RTPKRCNTBA RNG TRNG Statistical Check Poker Count B and A Register 0x694 32 read-only 0 0xFFFFFFFF PKR_A_CNT Poker Ah Count 0 16 read-only PKR_B_CNT Poker Bh Count 16 16 read-only RTPKRCNTDC RNG TRNG Statistical Check Poker Count D and C Register 0x698 32 read-only 0 0xFFFFFFFF PKR_C_CNT Poker Ch Count 0 16 read-only PKR_D_CNT Poker Dh Count 16 16 read-only RTPKRCNTFE RNG TRNG Statistical Check Poker Count F and E Register 0x69C 32 read-only 0 0xFFFFFFFF PKR_E_CNT Poker Eh Count 0 16 read-only PKR_F_CNT Poker Fh Count 16 16 read-only RDSTA RNG DRNG Status Register 0x6C0 32 read-only 0 0xFFFFFFFF IF0 Instantiated Flag State Handle 0. State Handle 0 has been instantiated. 0 1 read-only IF1 Instantiated Flag State Handle 1. State Handle 1 has been instantiated. 1 1 read-only PR0 Prediction Resistance Flag State Handle 0 4 1 read-only PR1 Prediction Resistance Flag State Handle 1 5 1 read-only TF0 Test Flag State Handle 0. State handle 0 has been instantiated as a test (deterministic) instance. 8 1 read-only TF1 Test Flag State Handle 1. State handle 1 has been instantiated as a test (deterministic) instance. 9 1 read-only ERRCODE Error Code. These bits represent the current error in the RNG. 16 4 read-only CE Catastrophic Error 20 1 read-only SKVN Secure Key Valid Non-Test 30 1 read-only SKVT Secure Key Valid Test 31 1 read-only RDINT0 RNG DRNG State Handle 0 Reseed Interval Register 0x6D0 32 read-only 0 0xFFFFFFFF RESINT0 RESINT0. This read-only register holds the Reseed Interval for State Handle 0. 0 32 read-only RDINT1 RNG DRNG State Handle 1 Reseed Interval Register 0x6D4 32 read-only 0 0xFFFFFFFF RESINT1 RESINT1. This read-only register holds the Reseed Interval for State Handle 1. 0 32 read-only RDHCNTL RNG DRNG Hash Control Register 0x6E0 32 read-write 0 0xFFFFFFFF HD Hashing Done. This bit asserts when the hashing engine is done. 0 1 read-only HB Hashing Begin. Writing this bit will causing the Hashing Engine to begin hashing. 1 1 write-only HI Hashing Initialize. Writing to this bit will initialize the Hashing Engine. 2 1 write-only HTM Hashing Test Mode. Writing this bit will put RNG in Hashing Test Mode. 3 1 read-write HTC Hashing Test Mode Clear. Writing this bit will take the RNG out of hashing test mode. 4 1 write-only RDHDIG RNG DRNG Hash Digest Register 0x6E4 32 read-only 0 0xFFFFFFFF HASHMD HASHMD 0 32 read-only RDHBUF RNG DRNG Hash Buffer Register 0x6E8 32 write-only 0 0xFFFFFFFF HASHBUF HASHBUF 0 32 write-only P0SDID_PG0 Partition 0 SDID register 0xA00 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P0SMAPR_PG0 Secure Memory Access Permissions register 0xA04 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P0SMAG2_PG0 Secure Memory Access Group Registers 0xA08 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P0SMAG1_PG0 Secure Memory Access Group Registers 0xA0C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P1SDID_PG0 Partition 1 SDID register 0xA10 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P1SMAPR_PG0 Secure Memory Access Permissions register 0xA14 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P1SMAG2_PG0 Secure Memory Access Group Registers 0xA18 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P1SMAG1_PG0 Secure Memory Access Group Registers 0xA1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P2SDID_PG0 Partition 2 SDID register 0xA20 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P2SMAPR_PG0 Secure Memory Access Permissions register 0xA24 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P2SMAG2_PG0 Secure Memory Access Group Registers 0xA28 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P2SMAG1_PG0 Secure Memory Access Group Registers 0xA2C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P3SDID_PG0 Partition 3 SDID register 0xA30 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P3SMAPR_PG0 Secure Memory Access Permissions register 0xA34 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P3SMAG2_PG0 Secure Memory Access Group Registers 0xA38 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P3SMAG1_PG0 Secure Memory Access Group Registers 0xA3C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P4SDID_PG0 Partition 4 SDID register 0xA40 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P4SMAPR_PG0 Secure Memory Access Permissions register 0xA44 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P4SMAG2_PG0 Secure Memory Access Group Registers 0xA48 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P4SMAG1_PG0 Secure Memory Access Group Registers 0xA4C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P5SDID_PG0 Partition 5 SDID register 0xA50 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P5SMAPR_PG0 Secure Memory Access Permissions register 0xA54 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P5SMAG2_PG0 Secure Memory Access Group Registers 0xA58 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P5SMAG1_PG0 Secure Memory Access Group Registers 0xA5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P6SDID_PG0 Partition 6 SDID register 0xA60 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P6SMAPR_PG0 Secure Memory Access Permissions register 0xA64 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P6SMAG2_PG0 Secure Memory Access Group Registers 0xA68 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P6SMAG1_PG0 Secure Memory Access Group Registers 0xA6C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P7SDID_PG0 Partition 7 SDID register 0xA70 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P7SMAPR_PG0 Secure Memory Access Permissions register 0xA74 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P7SMAG2_PG0 Secure Memory Access Group Registers 0xA78 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P7SMAG1_PG0 Secure Memory Access Group Registers 0xA7C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P8SDID_PG0 Partition 8 SDID register 0xA80 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P8SMAPR_PG0 Secure Memory Access Permissions register 0xA84 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P8SMAG2_PG0 Secure Memory Access Group Registers 0xA88 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P8SMAG1_PG0 Secure Memory Access Group Registers 0xA8C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P9SDID_PG0 Partition 9 SDID register 0xA90 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P9SMAPR_PG0 Secure Memory Access Permissions register 0xA94 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P9SMAG2_PG0 Secure Memory Access Group Registers 0xA98 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P9SMAG1_PG0 Secure Memory Access Group Registers 0xA9C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P10SDID_PG0 Partition 10 SDID register 0xAA0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P10SMAPR_PG0 Secure Memory Access Permissions register 0xAA4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P10SMAG2_PG0 Secure Memory Access Group Registers 0xAA8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P10SMAG1_PG0 Secure Memory Access Group Registers 0xAAC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P11SDID_PG0 Partition 11 SDID register 0xAB0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P11SMAPR_PG0 Secure Memory Access Permissions register 0xAB4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P11SMAG2_PG0 Secure Memory Access Group Registers 0xAB8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P11SMAG1_PG0 Secure Memory Access Group Registers 0xABC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P12SDID_PG0 Partition 12 SDID register 0xAC0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P12SMAPR_PG0 Secure Memory Access Permissions register 0xAC4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P12SMAG2_PG0 Secure Memory Access Group Registers 0xAC8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P12SMAG1_PG0 Secure Memory Access Group Registers 0xACC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P13SDID_PG0 Partition 13 SDID register 0xAD0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P13SMAPR_PG0 Secure Memory Access Permissions register 0xAD4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P13SMAG2_PG0 Secure Memory Access Group Registers 0xAD8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P13SMAG1_PG0 Secure Memory Access Group Registers 0xADC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P14SDID_PG0 Partition 14 SDID register 0xAE0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P14SMAPR_PG0 Secure Memory Access Permissions register 0xAE4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P14SMAG2_PG0 Secure Memory Access Group Registers 0xAE8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P14SMAG1_PG0 Secure Memory Access Group Registers 0xAEC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P15SDID_PG0 Partition 15 SDID register 0xAF0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P15SMAPR_PG0 Secure Memory Access Permissions register 0xAF4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P15SMAG2_PG0 Secure Memory Access Group Registers 0xAF8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P15SMAG1_PG0 Secure Memory Access Group Registers 0xAFC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write REIS Recoverable Error Interrupt Status 0xB00 32 read-write 0 0xFFFFFFFF oneToClear CWDE The CAAM watchdog timer expired. 0 1 read-write oneToClear RBAE A bus transaction initiated by CAAM RTIC resulted in a bus access error. 16 1 read-write oneToClear JBAE0 A job descriptor executed from Job Ring 0 caused a bus access error. 24 1 read-write oneToClear JBAE1 A job descriptor executed from Job Ring 1 caused a bus access error. 25 1 read-write oneToClear JBAE2 A job descriptor executed from Job Ring 2 caused a bus access error. 26 1 read-write oneToClear JBAE3 A job descriptor executed from Job Ring 3 caused a bus access error. 27 1 read-write oneToClear REIE Recoverable Error Interrupt Enable 0xB04 32 read-write 0 0xFFFFFFFF CWDE CAAM watchdog timer expired 0 1 read-write RBAE RTIC-initiated job execution caused bus access error. 16 1 read-write JBAE0 JR0-initiated job execution caused bus access error 24 1 read-write JBAE1 JR1-initiated job execution caused bus access error 25 1 read-write JBAE2 JR2-initiated job execution caused bus access error 26 1 read-write JBAE3 JR3-initiated job execution caused bus access error 27 1 read-write REIF Recoverable Error Interrupt Force 0xB08 32 read-only 0 0xFFFFFFFF CWDE CAAM watchdog timer expired 0 1 read-only RBAE RTIC-initiated job execution caused bus access error. 16 1 read-only JBAE0 JR0-initiated job execution caused bus access error 24 1 read-only JBAE1 JR1-initiated job execution caused bus access error 25 1 read-only JBAE2 JR2-initiated job execution caused bus access error 26 1 read-only JBAE3 JR3-initiated job execution caused bus access error 27 1 read-only REIH Recoverable Error Interrupt Halt 0xB0C 32 read-write 0 0xFFFFFFFF CWDE Halt CAAM if CAAM watchdog timer expires. 0 1 read-write DONT_HALT Don't halt CAAM if CAAM watchdog expired. 0 HALT Halt CAAM if CAAM watchdog expired.. 0x1 RBAE Halt CAAM if RTIC-initiated job execution caused bus access error. 16 1 read-write DONT_HALT Don't halt CAAM if RTIC-initiated job execution caused bus access error. 0 HALT Halt CAAM if RTIC-initiated job execution caused bus access error. 0x1 JBAE0 Halt CAAM if JR0-initiated job execution caused bus access error. 24 1 read-write DONT_HALT Don't halt CAAM if JR0-initiated job execution caused bus access error. 0 HALT Halt CAAM if JR0-initiated job execution caused bus access error. 0x1 JBAE1 Halt CAAM if JR1-initiated job execution caused bus access error. 25 1 read-write DONT_HALT Don't halt CAAM if JR1-initiated job execution caused bus access error. 0 HALT Halt CAAM if JR1-initiated job execution caused bus access error. 0x1 JBAE2 Halt CAAM if JR2-initiated job execution caused bus access error. 26 1 read-write DONT_HALT Don't halt CAAM if JR2-initiated job execution caused bus access error. 0 HALT Halt CAAM if JR2-initiated job execution caused bus access error. 0x1 JBAE3 Halt CAAM if JR3-initiated job execution caused bus access error. 27 1 read-write DONT_HALT Don't halt CAAM if JR3-initiated job execution caused bus access error. 0 HALT Halt CAAM if JR3-initiated job execution caused bus access error. 0x1 4 0x4 SMWPJRR[%s] Secure Memory Write Protect Job Ring Register 0xBD0 32 read-write 0 0xFFFFFFFF SMR_WP_JRa Secure Memory Registers Write Protect 0 1 read-write SMCR_PG0 Secure Memory Command Register 0xBE4 32 write-only 0 0xFFFFFFFF CMD Command: 1h: Allocate Page - This command allocates the page specified in the PAGE field to the partition specified in the PRTN field 0 4 write-only PRTN Partition: When an Allocate Page or De-allocate Partition command is issued, the action is performed on the partition indicated in the PRTN field 8 4 write-only PAGE This is the number of the page to be referenced in field CMD 16 16 write-only SMCSR_PG0 Secure Memory Command Status Register 0xBEC 32 read-only 0 0xFFFFFFFF PRTN Following a Page Inquiry Command, if the PO field is 10 or 11, this field indicates the partition to which the page specified in the PAGE field is allocated 0 4 read-only PO Page Owner: Following a Page Inquiry Command, this field indicates if the Page is owned by the entity that issued the inquiry, owned by another entity, or unowned 6 2 read-only AVAILABLE Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No zeroization is needed since it has already been cleared, therefore no interrupt should be expected. 0 NOT_PRESENT_OR_INITIALIZED Page does not exist in this version or is not initialized yet. 0x1 UNAVAILABLE Another entity owns the page. This page is unavailable to the issuer of the inquiry. 0x2 OWNED Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized upon de-allocation. 0x3 AERR Allocation Error 12 2 read-only CERR Command Error 14 2 read-only NO_ERROR No Error. 0 CMD_INCOMPLETE_ERROR Command has not yet completed. 0x1 SECURITY_FAILURE A security failure occurred. 0x2 CMD_OVERFLOW_ERROR Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous command completed. The additional command was ignored. 0x3 PAGE Page 16 12 read-only HT0_JD_ADDR Holding Tank 0 Job Descriptor Address 0xC00 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only HT0_SD_ADDR Holding Tank 0 Shared Descriptor Address 0xC08 64 read-only 0 0xFFFFFFFFFFFFFFFF SD_ADDR Shared Descriptor Address. 0 36 read-only HT0_JQ_CTRL_MS Holding Tank 0 Job Queue Control, most-significant half 0xC10 32 read-only 0 0xFFFFFFFF ID Job ID 0 3 read-only SRC Job Source 8 3 read-only JR0 Job Ring 0 0 JR1 Job Ring 1 0x1 JR2 Job Ring 2 0x2 JR3 Job Ring 3 0x3 RTIC RTIC 0x4 JDDS Job Descriptor DID Select 14 1 read-only NON_SEQ_DID Non-SEQ DID 0 SEQ_DID SEQ DID 0x1 AMTD Allow Make Trusted Descriptor 15 1 read-only SOB Shared or Burst 16 1 read-only HT_ERROR Holding Tank Error. (This field is implemented only in versions of CAAM that support prefetching.) 17 2 read-only NO_ERROR No error 0 JD_OR_SD_LENGTH_ERROR Job Descriptor or Shared Descriptor length error 0x1 JD_OR_SD_READ_ERROR AXI_error while reading a Job Ring Shared Descriptor or the remainder of a Job Ring Job Descriptor 0x2 DWORD_SWAP Double Word Swap. 19 1 read-only SRC_IN_MS_LS_ORDER DWords are in the order most-significant word, least-significant word. 0 SRC_IN_LS_MS_ORDER DWords are in the order least-significant word, most-significant word. 0x1 SHR_FROM Share From 22 5 read-only ILE Immediate Little Endian 27 1 read-only NO_BYTE_SWAP No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer. 0 BYTE_SWAP Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer. 0x1 FOUR Four Words. Job Queue Controller will pass at least 4 words of the descriptor to DECO. 28 1 read-only WHL Whole Descriptor 29 1 read-only HT0_JQ_CTRL_LS Holding Tank 0 Job Queue Control, least-significant half 0xC14 32 read-only 0 0xFFFFFFFF PRIM_DID Primary DID 0 4 read-only PRIM_TZ Primary TZ 4 1 read-only NONSECUREWORLD TrustZone NonSecureWorld 0 SECUREWORLD TrustZone SecureWorld 0x1 PRIM_ICID Primary ICID 5 11 read-only OUT_DID Output DID 16 4 read-only OUT_ICID Output ICID 21 11 read-only HT0_STATUS Holding Tank Status 0xC1C 32 read-only 0 0xFFFFFFFF PEND_0 Pending for DECO 0 0 1 read-only IN_USE In Use 30 1 read-only BC Been Changed 31 1 read-only JQ_DEBUG_SEL Job Queue Debug Select Register 0xC24 32 read-write 0 0xFFFFFFFF HT_SEL Holding Tank Select 0 1 read-write JOB_ID Job ID 16 3 read-only JRJIDU_LS Job Ring Job IDs in Use Register, least-significant half 0xDBC 32 read-only 0 0xFFFFFFFF JID00 Job ID 00 0 1 read-only JID01 Job ID 01 1 1 read-only JID02 Job ID 02 2 1 read-only JID03 Job ID 03 3 1 read-only JRJDJIFBC Job Ring Job-Done Job ID FIFO BC 0xDC0 32 read-only 0 0xFFFFFFFF BC Been changed 31 1 read-only JRJDJIF Job Ring Job-Done Job ID FIFO 0xDC4 32 read-only 0 0xFFFFFFFF JOB_ID_ENTRY Job ID entry 0 3 read-only JRJDS1 Job Ring Job-Done Source 1 0xDE4 32 read-only 0 0xFFFFFFFF SRC Source 0 2 read-only VALID Valid 31 1 read-only JRJDDA Job Ring Job-Done Descriptor Address 0 Register 0xE00 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only CRNR_MS CHA Revision Number Register, most-significant half 0xFA0 32 read-only 0x1000006 0xFFFFFFFF CRCRN CRC Hardware Accelerator Revision Number 0 4 read-only SNW9RN SNOW-f9 Hardware Accelerator Revision Number 4 4 read-only ZERN ZUC Encryption Hardware Accelerator Revision Number 8 4 read-only ZARN ZUC Authentication Hardware Accelerator Revision Number 12 4 read-only DECORN DECO Revision Number 24 4 read-only JRRN Job Ring Revision Number 28 4 read-only CRNR_LS CHA Revision Number Register, least-significant half 0xFA4 32 read-only 0x7003401A 0xFFFFFFFF AESRN AES Accelerator Revision Number 0 4 read-only DESRN DES Accelerator Revision Number. 4 4 read-only MDRN Message Digest Hardware Accelerator module Revision Number. 12 4 read-only RNGRN Random Number Generator Revision Number. 16 4 read-only SNW8RN SNOW-f8 Hardware Accelerator Revision Number 20 4 read-only KASRN Kasumi f8/f9 Hardware Accelerator Revision Number 24 4 read-only PKRN Public Key Hardware Accelerator Revision Number For PKHA-XT, PKRN=1. For PKHA-SD, see below. 28 4 read-only PKHA_SDV0 PKHA-SDv1 0 PKHA_SDV1 PKHA-SDv2 0x1 PKHA_SDV2 PKHA-SDv3 0x2 PKHA_SDV3 PKHA-SDv4 0x3 CTPR_MS Compile Time Parameters Register, most-significant half 0xFA8 32 read-only 0x1934211 0xFFFFFFFF VIRT_EN_INCL Job Ring Virtualization programmable 0 1 read-only VIRT_EN_POR_VALUE Job Ring Virtualization POR state 1 1 read-only REG_PG_SIZE CAAM register page size. 0: CAAM uses 4Kbyte register pages. 1: CAAM uses 64Kbyte register pages. 4 1 read-only RNG_I RNG Instantiations 8 3 read-only AI_INCL AIOP interface implemented 11 1 read-only DPAA2 ICIDs with AMQs supported 13 1 read-only IP_CLK IP Bus Slave Clock 14 1 read-only MCFG_BURST Burst Configurability If MCFG_BURST is 0, the normal burst size is limited to 32 bytes and large bursts cannot be enabled 16 1 read-only MCFG_PS Pointer Size field implemented 0: The Master Configuration Register does not contain a Pointer Size field 17 1 read-only SG8 Eight Scatter-Gather Tables implemented 0: CAAM implements one Scatter-Gather Table register 18 1 read-only PM_EVT_BUS Performance Monitor Event Bus implemented 0: CAAM does not implement a Performance Monitor Event Bus 19 1 read-only DECO_WD DECO Watchdog Counter implemented 0: CAAM does not implement a DECO Watchdog Counter 20 1 read-only PC Performance Counter registers implemented 0: CAAM does not implement Performance Counter registers 21 1 read-only C1C2 Separate C1 and C2 registers 0: In this implementation of CAAM the Class 2 Key and Context registers are shared with the Class 1 Key and Context registers 23 1 read-only ACC_CTL System/user partition-based CAAM IP Bus register access control 0: CAAM does not implement partition-based access control for its IP Bus registers, i 24 1 read-only QI Queue Manager interface (QI) implemented 25 1 read-only AXI_PRI AXI Master Priority implemented 26 1 read-only AXI_LIODN LIODN logic included 27 1 read-only AXI_PIPE_DEPTH AXI Pipeline Depth 28 4 read-only CTPR_LS Compile Time Parameters Register, least-significant half 0xFAC 32 read-only 0x6403 0xFFFFFFFF KG_DS PK generation and digital signature protcols 0 1 read-only KG_DS_PROTOCOL_ABSENT CAAM does not implement specialized support for Public Key Generation and Digital Signatures. 0 KG_DS_PROTOCOL_EXISTS CAAM implements specialized support for Public Key Generation and Digital Signatures. 0x1 BLOB Blob protocol 1 1 read-only BLOB_PROTOCOL_ABSENT CAAM does not implement specialized support for encapsulating and decapsulating cryptographic blobs. 0 BLOB_PROTOCOL_EXISTS CAAM implements specialized support for encapsulating and decapsulating cryptographic blobs. 0x1 WIFI WiFi protocol 2 1 read-only WIFI_PROTOCOL_ABSENT CAAM does not implement specialized support for the WIFI protocol. 0 WIFI_PROTOCOL_EXISTS CAAM implements specialized support for the WIFI protocol. 0x1 WIMAX WiMax protocol 3 1 read-only WIMAX_PROTOCOL_ABSENT CAAM does not implement specialized support for the WIMAX protocol. 0 WIMAX_PROTOCOL_EXISTS CAAM implements specialized support for the WIMAX protocol. 0x1 SRTP SRTP protocol 4 1 read-only SRTP_PROTOCOL_ABSENT CAAM does not implement specialized support for the SRTP protocol. 0 SRTP_PROTOCOL_EXISTS CAAM implements specialized support for the SRTP protocol. 0x1 IPSEC IPSEC protocols 5 1 read-only IPSEC_PROTOCOL_ABSENT CAAM does not implement specialized support for the IPSEC protocol. 0 IPSEC_PROTOCOL_EXISTS CAAM implements specialized support for the IPSEC protocol. 0x1 IKE IKE protocols 6 1 read-only IKE_PROTOCOL_ABSENT CAAM does not implement specialized support for the IKE protocol. 0 IKE_PROTOCOL_EXISTS CAAM implements specialized support for the IKE protocol. 0x1 SSL_TLS SSL/TLS protocol 7 1 read-only SSL_TLS_PROTOCOL_ABSENT CAAM does not implement specialized support for the SSL and TLS protocols. 0 SSL_TLS_PROTOCOL_EXISTS CAAM implements specialized support for the SSL and TLS protocols. 0x1 TLS_PRF TLS PRF protocol 8 1 read-only TLS_PRF_PROTOCOL_ABSENT CAAM does not implement specialized support for the TLS protocol pseudo-random function. 0 TLS_PRF_PROTOCOL_EXISTS CAAM implements specialized support for the TLS protocol pseudo-random function. 0x1 MACSEC MACSEC protocol 9 1 read-only MACSEC_PROTOCOL_ABSENT CAAM does not implement specialized support for the MACSEC protocol. 0 MACSEC_PROTOCOL_EXISTS CAAM implements specialized support for the MACSEC protocol. 0x1 RSA RSA protocol 10 1 read-only RSA_PROTOCOL_ABSENT CAAM does not implement specialized support for RSA encrypt and decrypt operations. 0 RSA_PROTOCOL_EXISTS CAAM implements specialized support for RSA encrypt and decrypt operations. 0x1 P3G_LTE 3GPP/LTE protocol 11 1 read-only P3G_LTE_PROTOCOL_ABSENT CAAM does not implement specialized support for 3G and LTE protocols. 0 P3G_LTE_PROTOCOL_EXISTS CAAM implements specialized support for 3G and LTE protocols. 0x1 DBL_CRC Double CRC protocol 12 1 read-only DBL_CRC_PROTOCOL_ABSENT CAAM does not implement specialized support for Double CRC. 0 DBL_CRC_PROTOCOL_EXISTS CAAM implements specialized support for Double CRC. 0x1 MAN_PROT Manufacturing Protection protocol 13 1 read-only MAN_PROTOCOL_ABSENT CAAM does not implement Manufacturing Protection functions. 0 MAN_PROTOCOL_EXISTS CAAM implements Manufacturing Protection functions. 0x1 DKP Derived Key Protocol 14 1 read-only DERIVED_KEY_PROTOCOL_ABSENT CAAM does not implement the Derived Key Protocol. 0 DERIVED_KEY_PROTOCOL_EXISTS CAAM implements the Derived Key Protocol. 0x1 SMSTA Secure Memory Status Register 0xFB4 32 read-only 0 0xFFFFFFFF STATE Current State. This field represents the current state of the Secure Memory Controller. 0 4 read-only RESET Reset State 0 INIT Initialize State 0x1 NORMAL Normal State 0x2 FAIL Fail State 0x3 ACCERR Access Error 4 4 read-only NO_ERROR No error occurred 0 PAGE_NOT_ALLOCATED_ACCESS_ERROR A bus transaction attempted to access a page in Secure Memory, but the page was not allocated to any partition. 0x1 PARTITION_NOT_GRANTED_ACCESS_ERROR A bus transaction attempted to access a partition, but the transaction's TrustZone World, DID was not granted access to the partition in the partition's SMAG2/1JR registers. 0x2 READ_NOT_ALLOWED_ACCESS_ERROR A bus transaction attempted to read, but reads from this partition are not allowed. 0x3 WRITE_NOT_ALLOWED_ACCESS_ERROR A bus transaction attempted to write, but writes to this partition are not allowed. 0x4 NON_KEY_READ_NOT_ALLOWED_ACCESS_ERROR A bus transaction attempted a non-key read, but the only reads permitted from this partition are key reads. 0x6 BLOB_IMPORT_EXPORT_ACCESS_ERROR Secure Memory Blob import or export was attempted, but Secure Memory Blob access is not allowed for this partition. 0x9 MULTI_PARTITION_BLOB_IMPORT_EXPORT_ERROR A Descriptor attempted a Secure Memory Blob import or export, but not all of the pages referenced were from the same partition. 0xA INVALID_SECURE_MEMORY_ADDRESS_ERROR A memory access was directed to Secure Memory, but the specified address is not implemented in Secure Memory. The address was either outside the address range occupied by Secure Memory, or was within an unimplemented portion of the 4kbyte address block occupied by a 1Kbyte or 2Kbyte Secure Memory page. 0xB PAGE_BOUNDARY_CROSSING_ERROR A bus transaction was attempted, but the burst would have crossed a page boundary. 0xC UNINITIALIZED_PAGE_ACCESS_ERROR An attempt was made to access a page while it was still being initialized. 0xD DID The DID of the bus master whose access to Secure Memory was denied. 8 4 read-only NS The TrustZone nonsecure bit of the bus master whose access to Secure Memory was denied 12 1 read-only SMR_WP Secure Memory Registers Write Protected 15 1 read-only PAGE Page 16 11 read-only PART Partition 28 4 read-only SMPO Secure Memory Partition Owners Register 0xFBC 32 read-only 0x3 0xFFFFFFFF PO0 Partition Owner for partition 0: When read by a Job Ring owner, this field indicates if partition 0 is owned by that Job Ring, another Job Ring, Unowned, or Unimplemented 0 2 read-only AVAILABLE Available; Unowned. A Job Ring owner may claim partition 0 by writing to the appropriate SMAPJR register address alias. Note that the entire register will return all 0s if read by a entity that does not own the Job Ring associated with the SMPO address alias that was read. 0 NOT_PRESENT Partition 0 does not exist in this version 0x1 UNAVAILABLE Another entity owns partition 0. Partition 0 is unavailable to the reader. If the reader attempts to de-allocate partition 0 or write to the SMAPJR register or SMAGJR register for partition 0 or allocate a page to or de-allocate a page from partition 0 the command will be ignored. (Note that if a CSP partition is de-allocated, all entities (including the owner that de-allocated the partition) will see a 0b10 value for that partition until all its pages have been zeroized.) 0x2 OWNED The entity that read the SMPO register owns partition 0. Ownership is claimed when the access permissions register (SMAPJR) of an available partition is first written. 0x3 PO1 Partition Owner for partition 1. See PO0. 2 2 read-only PO2 Partition Owner for partition 2. See PO0. 4 2 read-only PO3 Partition Owner for partition 3. See PO0. 6 2 read-only PO4 Partition Owner for partition 4. See PO0. 8 2 read-only PO5 Partition Owner for partition 5. See PO0. 10 2 read-only PO6 Partition Owner for partition 6. See PO0. 12 2 read-only PO7 Partition Owner for partition 7. See PO0. 14 2 read-only PO8 Partition Owner for partition 8. See PO0. 16 2 read-only PO9 Partition Owner for partition 9. See PO0. 18 2 read-only PO10 Partition Owner for partition 10. See PO0. 20 2 read-only PO11 Partition Owner for partition 11. See PO0. 22 2 read-only PO12 Partition Owner for partition 12. See PO0. 24 2 read-only PO13 Partition Owner for partition 13. See PO0. 26 2 read-only PO14 Partition Owner for partition 14. See PO0. 28 2 read-only PO15 Partition Owner for partition 15. See PO0. 30 2 read-only FAR Fault Address Register 0xFC0 64 read-only 0 0xFFFFFFFFFFFFFFFF FAR Fault Address 0 36 read-only FADID Fault Address DID Register 0xFC8 32 read-only 0 0xFFFFFFFF FDID DMA transaction DID. This was the DID associated with the DMA transaction that failed. 0 4 read-only FNS DMA transaction ns 4 1 read-only FICID DMA transaction ICID. This was the ICID value associated with the DMA transaction that failed. 5 11 read-only FADR Fault Address Detail Register 0xFCC 32 read-only 0 0xFFFFFFFF FSZ AXI Transaction Transfer Size 0 7 read-only TYP AXI Transaction Type 7 1 read-only READ Read. 0 WRITE Write. 0x1 BLKID Block ID 8 4 read-only JQ job queue controller Burst Buffer 0x4 JRN One of the Job Rings (see JSRC field) 0x5 DECO0 DECO0 0x8 JSRC Job Source. The source of the job whose AXI transfer ended with an error: 12 3 read-only JR0 Job Ring 0 0 JR1 Job Ring 1 0x1 JR2 Job Ring 2 0x2 JR3 Job Ring 3 0x3 RTIC RTIC 0x4 DTYP Data Type. The type of data being processed when the AXI transfer error occurred. 15 1 read-only MSG_DATA message data 0 CTL_DATA control data 0x1 FSZ_EXT AXI Transaction Transfer Size - extended 16 3 read-only FKMOD Key Modifier Read 24 1 read-only NOT CAAM DMA was not attempting to read the key modifier from Secure Memory at the time that the DMA error occurred. 0 YES CAAM DMA was attempting to read the key modifier from Secure Memory at the time that the DMA error occurred. 0x1 FKEY Key Access Read 25 1 read-only NOT CAAM DMA was not attempting to perform a key read from Secure Memory at the time of the DMA error. 0 YES CAAM DMA was attempting to perform a key read from Secure Memory at the time of the DMA error. 0x1 FTDSC Trusted Descriptor access to Secure Memory 26 1 read-only NOT CAAM DMA was not executing a Trusted Descriptor at the time of the DMA error. 0 YES CAAM DMA was executing a Trusted Descriptor at the time of the DMA error. 0x1 FBNDG Access permission binding access to Secure Memory. 27 1 read-only NOT CAAM DMA was not reading access permissions from a Secure Memory partition at the time of the DMA error. 0 YES CAAM DMA was reading access permissions from a Secure Memory partition at the time of the DMA error. 0x1 FNS Non-secure (AXI bus ns bit) access to Secure Memory. 28 1 read-only YES CAAM DMA was asserting ns=0 at the time of the DMA error. 0 NOT CAAM DMA was asserting ns=1 at the time of the DMA error. 0x1 FERR Fault Error Code. This is the AXI Error Response Code. 30 2 read-only OKAY OKAY - Normal Access 0 SLVERR SLVERR - Slave Error 0x2 DECERR DECERR - Decode Error 0x3 CSTA CAAM Status Register 0xFD4 32 read-only 0x2 0xFFFFFFFF BSY CAAM Busy 0 1 read-only IDLE CAAM Idle 1 1 read-only TRNG_IDLE TRNG Idle 2 1 read-only MOO Mode of Operation 8 2 read-only NON_SECURE Non-Secure 0 SECURE Secure 0x1 TRUSTED Trusted 0x2 FAIL Fail 0x3 PLEND Platform Endianness 10 1 read-only LITTLE Platform default is Little Endian 0 BIG Platform default is Big Endian 0x1 SMVID_MS Secure Memory Version ID Register, most-significant half 0xFD8 32 read-only 0xFF00F 0xFFFFFFFF NPAG This is the highest numbered page of Secure Memory 0 10 read-only NPRT This is the highest numbered Secure Memory partition, so there can be 1 to 16 partitions. 12 4 read-only MAX_NPAG Maximum allowable value for NPAG 16 10 read-only SMVID_LS Secure Memory Version ID Register, least-significant half 0xFDC 32 read-only 0x20301 0xFFFFFFFF SMNV Secure Memory Minor Version ID. 0 8 read-only SMJV Secure Memory Major Version ID 8 8 read-only PSIZ Page Size 16 3 read-only RVID RTIC Version ID Register 0xFE0 32 read-only 0xF0A0004 0xFFFFFFFF RMNV RTIC Minor Version 0 8 read-only RMJV RTIC Major Version 8 8 read-only SHA_256 SHA-256. 17 1 read-only SHA256_ABSENT RTIC cannot use the SHA-256 hashing algorithm. 0 SHA256_EXISTS RTIC can use the SHA-256 hashing algorithm. 0x1 SHA_512 SHA-512. 19 1 read-only SHA512_ABSENT RTIC cannot use the SHA-512 hashing algorithm. 0 SHA512_EXISTS RTIC can use the SHA-512 hashing algorithm. 0x1 MA Memory Block A Available 24 1 read-only MB Memory Block B Available 25 1 read-only MC Memory Block C Available 26 1 read-only MD Memory Block D Available 27 1 read-only CCBVID CHA Cluster Block Version ID Register 0xFE4 32 read-only 0x9000005 0xFFFFFFFF AMNV Accelerator Minor Revision Number 0 8 read-only AMJV Accelerator Major Revision Number 8 8 read-only CAAM_ERA CAAM Era. This version of CAAM is based on Era 9 RTL. A value of 0 implies CAAM Era 5 or earlier. 24 8 read-only CHAVID_MS CHA Version ID Register, most-significant half 0xFE8 32 read-only 0x45000001 0xFFFFFFFF CRCVID CRC Hardware Accelerator Version ID 0 4 read-only SNW9VID SNOW-f9 Hardware Accelerator Version ID 4 4 read-only ZEVID ZUC Encryption Hardware Accelerator Version ID 8 4 read-only ZAVID ZUC Authentication Hardware Accelerator Version ID 12 4 read-only DECOVID DECO Version ID 24 4 read-only JRVID Job Ring Version ID 28 4 read-only CHAVID_LS CHA Version ID Register, least-significant half 0xFEC 32 read-only 0x20041033 0xFFFFFFFF AESVID AES Accelerator Version ID. 0 4 read-only AESA_LP Low-power AESA, implementing ECB, CBC, CBC-CS2, CFB128, OFB, CTR, CCM, CMAC, XCBC-MAC, and GCM modes 0x3 AESA_HP High-performance AESA, implementing ECB, CBC, CBC-CS2, CFB128, OFB, CTR, CCM, CMAC, XCBC-MAC, CBCXCBC, CTRXCBC, XTS, and GCM modes 0x4 DESVID DES Accelerator Version ID. 4 4 read-only MDVID Message Digest Hardware Accelerator Version ID. 12 4 read-only MDHA_LP0 Low-power MDHA, with SHA-1, SHA-256, SHA 224, MD5 and HMAC 0 MDHA_LP1 Low-power MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5 and HMAC 0x1 MDHA_MP Medium-performance MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5, HMAC & SMAC 0x2 MDHA_HP High-performance MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5, HMAC & SMAC 0x3 RNGVID Random Number Generator Version ID. 16 4 read-only RNGB RNGB 0x2 RNG4 RNG4 0x4 SNW8VID SNOW-f8 Hardware Accelerator Version ID. 20 4 read-only KASVID Kasumi f8/f9 Hardware Accelerator Version ID. 24 4 read-only PKVID Public Key Hardware Accelerator Version ID 28 4 read-only PKHA_XT PKHA-XT (32-bit); minimum modulus five bytes 0 PKHA_SD32 PKHA-SD (32-bit) 0x1 PKHA_SD64 PKHA-SD (64-bit) 0x2 PKHA_SD128 PKHA-SD (128-bit) 0x3 CHANUM_MS CHA Number Register, most-significant half 0xFF0 32 read-only 0x41000001 0xFFFFFFFF CRCNUM The number of copies of the CRC module that are implemented in this version of CAAM 0 4 read-only SNW9NUM The number of copies of the SNOW-f9 module that are implemented in this version of CAAM 4 4 read-only ZENUM The number of copies of ZUCE that are implemented in this version of CAAM 8 4 read-only ZANUM The number of copies of ZUCA that are implemented in this version of CAAM 12 4 read-only DECONUM The number of copies of the DECO that are implemented in this version of CAAM 24 4 read-only JRNUM The number of copies of the Job Ring that are implemented in this version of CAAM 28 4 read-only CHANUM_LS CHA Number Register, least-significant half 0xFF4 32 read-only 0x10011011 0xFFFFFFFF AESNUM The number of copies of the AES module that are implemented in this version of CAAM. 0 4 read-only DESNUM The number of copies of the DES module that are implemented in this version of CAAM. 4 4 read-only ARC4NUM The number of copies of the ARC4 module that are implemented in this version of CAAM. 8 4 read-only MDNUM The number of copies of the MDHA (Hashing module) that are implemented in this version of CAAM. 12 4 read-only RNGNUM The number of copies of the Random Number Generator that are implemented in this version of CAAM. 16 4 read-only SNW8NUM The number of copies of the SNOW-f8 module that are implemented in this version of CAAM 20 4 read-only KASNUM The number of copies of the Kasumi module that are implemented in this version of CAAM 24 4 read-only PKNUM The number of copies of the Public Key module that are implemented in this version of CAAM 28 4 read-only CAAMVID_MS CAAM Version ID Register, most-significant half 0xFF8 32 read-only 0xA160402 0xFFFFFFFF MIN_REV Minor revision number for CAAM. 0 8 read-only MAJ_REV Major revision number for CAAM. 8 8 read-only IP_ID ID for CAAM. 16 16 read-only CAAMVID_LS CAAM Version ID Register, least-significant half 0xFFC 32 read-only 0 0xFFFFFFFF CONFIG_OPT Configuration options for CAAM. 0 8 read-only ECO_REV ECO revision for CAAM. 8 8 read-only INTG_OPT Integration options for CAAM. 16 8 read-only COMPILE_OPT Compile options for CAAM. 24 8 read-only IRBAR_JR0 Input Ring Base Address Register for Job Ring 0 0x10000 64 read-write 0 0xFFFFFFFFFFFFFFFF IRBA Input Ring Base Address. 0 36 read-write IRSR_JR0 Input Ring Size Register for Job Ring 0 0x1000C 32 read-write 0 0xFFFFFFFF IRS Input Ring Size. (measured in number of entries) 0 10 read-write IRSAR_JR0 Input Ring Slots Available Register for Job Ring 0 0x10014 32 read-write 0 0xFFFFFFFF IRSA Input Ring Slots Available. (measured in number of available job slots) 0 10 read-write IRJAR_JR0 Input Ring Jobs Added Register for Job Ring0 0x1001C 32 read-write 0 0xFFFFFFFF IRJA Input Ring Jobs Added. (measured in number of entries) 0 10 read-write ORBAR_JR0 Output Ring Base Address Register for Job Ring 0 0x10020 64 read-write 0 0xFFFFFFFFFFFFFFFF ORBA Output Ring Base Address. 0 36 read-write ORSR_JR0 Output Ring Size Register for Job Ring 0 0x1002C 32 read-write 0 0xFFFFFFFF ORS Output Ring Size. (measured in number of entries) 0 10 read-write ORJRR_JR0 Output Ring Jobs Removed Register for Job Ring 0 0x10034 32 read-write 0 0xFFFFFFFF ORJR Output Ring Jobs Removed. (measured in number of entries) 0 10 read-write ORSFR_JR0 Output Ring Slots Full Register for Job Ring 0 0x1003C 32 read-write 0 0xFFFFFFFF ORSF Output Ring Slots Full. (measured in number of entries) 0 10 read-write JRSTAR_JR0 Job Ring Output Status Register for Job Ring 0 0x10044 32 read-only 0 0xFFFFFFFF SSED Source-specific error details 0 28 read-only SSRC Status source. These bits define which source is reporting the status. All other values - reserved 28 4 read-only NO_STATUS No Status Source (No Error or Status Reported) 0 CCB_STATUS CCB Status Source (CCB Error Reported) 0x2 JMP_USR_STATUS Jump Halt User Status Source (User-Provided Status Reported) 0x3 DECO_STATUS DECO Status Source (DECO Error Reported) 0x4 JR_STATUS Job Ring Status Source (Job Ring Error Reported) 0x6 JMP_COND_STATUS Jump Halt Condition Codes (Condition Code Status Reported) 0x7 JRINTR_JR0 Job Ring Interrupt Status Register for Job Ring 0 0x1004C 32 read-write 0 0xFFFFFFFF JRI Job Ring Interrupt 0 1 read-write oneToClear JRE Job Ring Error 1 1 read-write oneToClear HALT Halt the Job Ring 2 2 read-write oneToClear ENTER_FAIL Enter SNVS Fail State 4 1 read-write oneToClear EXIT_FAIL Exit SNVS Fail State 5 1 read-write oneToClear ERR_TYPE Error type 8 5 read-only OR_WR_ERR Error writing status to Output Ring 0x1 BAD_IR_ADDR_ERR Bad input ring base address (not on a 4-byte boundary). 0x3 BAD_OR_ADDR_ERR Bad output ring base address (not on a 4-byte boundary). 0x4 INV_IR_REG_WR_ERR Invalid write to Input Ring Base Address Register or Input Ring Size Register. Can be written when there are no jobs in the input ring or when the Job Ring is halted. These are fatal and will likely result in not being able to get all jobs out into the output ring for processing by software. Resetting the job ring will almost certainly be necessary. 0x5 INV_OR_REG_WR_ERR Invalid write to Output Ring Base Address Register or Output Ring Size Register. Can be written when there are no jobs in the output ring and no jobs from this queue are already processing in CAAM (in the holding tanks or DECOs), or when the Job Ring is halted. 0x6 INV_JR_RESET_ERR Job Ring reset released before Job Ring is halted. 0x7 ORJRR_GT_ORSFR_ERR Removed too many jobs (ORJRR larger than ORSFR). 0x8 IRJAR_GT_IRSAR_ERR Added too many jobs (IRJAR larger than IRSAR). 0x9 ORSF_GT_ORS_ERR Writing ORSF > ORS In these error cases the write is ignored, the interrupt is asserted (unless masked) and the error bit and error_type fields are set in the Job Ring Interrupt Status Register. 0xA IRSA_GT_IRS_ERR Writing IRSA > IRS 0xB ORWI_GT_ORS_ERR Writing ORWI > ORS in bytes 0xC IRRI_GT_IRS_ERR Writing IRRI > IRS in bytes 0xD INV_IRSA_WR_ERR Writing IRSA when ring is active 0xE INV_IRRI_WR_ERR Writing IRRI when ring is active 0xF INV_ORSF_WR_ERR Writing ORSF when ring is active 0x10 INV_ORWI_WR_ERR Writing ORWI when ring is active 0x11 ERR_ORWI Output ring write index with error 16 14 read-only JRCFGR_JR0_MS Job Ring Configuration Register for Job Ring 0, most-significant half 0x10050 32 read-write 0 0xFFFFFFFF MBSI To assist with mixed Endianness platforms, this bit configures a byte swap of message data read by CAAM DMA 0 1 read-write MHWSI To assist with mixed Endianness platforms, this bit configures a halfword swap of message data read by CAAM DMA 1 1 read-write MWSI To assist with mixed Endianness platforms, this bit configures a fullword swap of message data read by CAAM DMA 2 1 read-write CBSI To assist with mixed Endianness platforms, this bit configures a byte swap of control data read by CAAM DMA 4 1 read-write CHWSI To assist with mixed Endianness platforms, this bit configures a halfword swap of control data read by CAAM DMA 5 1 read-write CWSI To assist with mixed Endianness platforms, this bit configures a fullword swap of control data read by CAAM DMA 6 1 read-write MBSO To assist with mixed Endianness platforms, this bit configures a byte swap of message data written by CAAM DMA 8 1 read-write MHWSO To assist with mixed Endianness platforms, this bit configures a halfword swap of message data written by CAAM DMA 9 1 read-write MWSO To assist with mixed Endianness platforms, this bit configures a fullword swap of message data written by CAAM DMA 10 1 read-write CBSO To assist with mixed Endianness platforms, this bit configures a byte swap of control data written by CAAM DMA 12 1 read-write CHWSO To assist with mixed Endianness platforms, this bit configures a halfword swap of control data written by CAAM DMA 13 1 read-write CWSO To assist with mixed Endianness platforms, this bit configures a fullword swap of control data written by CAAM DMA 14 1 read-write DMBS Descriptor Message Data Byte Swap (this applies only to internal message data transfers to/from DECO Descriptor Buffers) 16 1 read-write PEO Platform Endian Override - The bit is XORed with the PLEND bit in the CaCSTA Register and the other "swap" bits in the Job Ring Configuration Register to determine the AXI Master's view of memory endianness when executing Job Descriptors from this Job Ring 17 1 read-write DWSO Double Word Swap Override 18 1 read-write FAIL_MODE Fail mode control 29 1 read-write INCL_SEQ_OUT Include Sequence Out Length 30 1 read-write JRCFGR_JR0_LS Job Ring Configuration Register for Job Ring 0, least-significant half 0x10054 32 read-write 0 0xFFFFFFFF IMSK Interrupt Mask. Mask the interrupt that is associated with the particular processor. 0 1 read-write INTR_ENABLED Interrupt enabled. 0 INTR_MASKED Interrupt masked. 0x1 ICEN Interrupt Coalescing Enable. 1 1 read-write INTR_COAL_DISABLED Interrupt coalescing is disabled. If the IMSK bit is cleared, an interrupt is asserted whenever a job is written to the output ring. ICDCT is ignored. Note that if software removes one or more jobs and clears the interrupt but the output rings slots full is still greater than 0 (ORSF > 0), then the interrupt will clear but reassert on the next clock cycle. 0 INTR_COAL_ENABLED Interrupt coalescing is enabled. If the IMSK bit is cleared, an interrupt is asserted whenever the threshold number of frames is reached (ICDCT) or when the threshold timer expires (ICTT). Note that if software removes one or more jobs and clears the interrupt but the interrupt coalescing threshold is still met (ORSF >= ICDCT), then the interrupt will clear but reassert on the next clock cycle. 0x1 ICDCT Interrupt Coalescing Descriptor Count Threshold 8 8 read-write ICTT Interrupt Coalescing Timer Threshold 16 16 read-write IRRIR_JR0 Input Ring Read Index Register for Job Ring 0 0x1005C 32 read-write 0 0xFFFFFFFF IRRI Input Ring Read Index. 0 13 read-write ORWIR_JR0 Output Ring Write Index Register for Job Ring 0 0x10064 32 read-write 0 0xFFFFFFFF ORWI Output Ring Write Index. The pointer to the next entry in the output ring. 0 14 read-write JRCR_JR0 Job Ring Command Register for Job Ring 0 0x1006C 32 write-only 0 0xFFFFFFFF RESET Reset - When RESET is 0, software writes a 1 to RESET to request a flush of the Job Ring 0 1 write-only PARK Park - When PARK is 0, software writes a 1 to PARK to request that the Job Ring be "parked", i 1 1 write-only JR0AAV Job Ring 0 Address-Array Valid Register 0x10704 32 read-only 0 0xFFFFFFFF V0 Valid 0 0 1 read-only V1 Valid 1 1 1 read-only V2 Valid 2 2 1 read-only V3 Valid 3 3 1 read-only BC Been Changed 31 1 read-only JR0AAA0 Job Ring 0 Address-Array Address 0 Register 0x10800 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR0AAA1 Job Ring 0 Address-Array Address 1 Register 0x10808 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR0AAA2 Job Ring 0 Address-Array Address 2 Register 0x10810 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR0AAA3 Job Ring 0 Address-Array Address 3 Register 0x10818 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only P0SDID_JR0 Partition 0 SDID register 0x10A00 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P0SMAPR_JR0 Secure Memory Access Permissions register 0x10A04 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P0SMAG2_JR0 Secure Memory Access Group Registers 0x10A08 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P0SMAG1_JR0 Secure Memory Access Group Registers 0x10A0C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P1SDID_JR0 Partition 1 SDID register 0x10A10 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P1SMAPR_JR0 Secure Memory Access Permissions register 0x10A14 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P1SMAG2_JR0 Secure Memory Access Group Registers 0x10A18 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P1SMAG1_JR0 Secure Memory Access Group Registers 0x10A1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P2SDID_JR0 Partition 2 SDID register 0x10A20 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P2SMAPR_JR0 Secure Memory Access Permissions register 0x10A24 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P2SMAG2_JR0 Secure Memory Access Group Registers 0x10A28 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P2SMAG1_JR0 Secure Memory Access Group Registers 0x10A2C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P3SDID_JR0 Partition 3 SDID register 0x10A30 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P3SMAPR_JR0 Secure Memory Access Permissions register 0x10A34 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P3SMAG2_JR0 Secure Memory Access Group Registers 0x10A38 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P3SMAG1_JR0 Secure Memory Access Group Registers 0x10A3C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P4SDID_JR0 Partition 4 SDID register 0x10A40 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P4SMAPR_JR0 Secure Memory Access Permissions register 0x10A44 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P4SMAG2_JR0 Secure Memory Access Group Registers 0x10A48 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P4SMAG1_JR0 Secure Memory Access Group Registers 0x10A4C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P5SDID_JR0 Partition 5 SDID register 0x10A50 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P5SMAPR_JR0 Secure Memory Access Permissions register 0x10A54 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P5SMAG2_JR0 Secure Memory Access Group Registers 0x10A58 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P5SMAG1_JR0 Secure Memory Access Group Registers 0x10A5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P6SDID_JR0 Partition 6 SDID register 0x10A60 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P6SMAPR_JR0 Secure Memory Access Permissions register 0x10A64 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P6SMAG2_JR0 Secure Memory Access Group Registers 0x10A68 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P6SMAG1_JR0 Secure Memory Access Group Registers 0x10A6C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P7SDID_JR0 Partition 7 SDID register 0x10A70 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P7SMAPR_JR0 Secure Memory Access Permissions register 0x10A74 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P7SMAG2_JR0 Secure Memory Access Group Registers 0x10A78 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P7SMAG1_JR0 Secure Memory Access Group Registers 0x10A7C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P8SDID_JR0 Partition 8 SDID register 0x10A80 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P8SMAPR_JR0 Secure Memory Access Permissions register 0x10A84 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P8SMAG2_JR0 Secure Memory Access Group Registers 0x10A88 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P8SMAG1_JR0 Secure Memory Access Group Registers 0x10A8C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P9SDID_JR0 Partition 9 SDID register 0x10A90 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P9SMAPR_JR0 Secure Memory Access Permissions register 0x10A94 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P9SMAG2_JR0 Secure Memory Access Group Registers 0x10A98 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P9SMAG1_JR0 Secure Memory Access Group Registers 0x10A9C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P10SDID_JR0 Partition 10 SDID register 0x10AA0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P10SMAPR_JR0 Secure Memory Access Permissions register 0x10AA4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P10SMAG2_JR0 Secure Memory Access Group Registers 0x10AA8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P10SMAG1_JR0 Secure Memory Access Group Registers 0x10AAC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P11SDID_JR0 Partition 11 SDID register 0x10AB0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P11SMAPR_JR0 Secure Memory Access Permissions register 0x10AB4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P11SMAG2_JR0 Secure Memory Access Group Registers 0x10AB8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P11SMAG1_JR0 Secure Memory Access Group Registers 0x10ABC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P12SDID_JR0 Partition 12 SDID register 0x10AC0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P12SMAPR_JR0 Secure Memory Access Permissions register 0x10AC4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P12SMAG2_JR0 Secure Memory Access Group Registers 0x10AC8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P12SMAG1_JR0 Secure Memory Access Group Registers 0x10ACC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P13SDID_JR0 Partition 13 SDID register 0x10AD0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P13SMAPR_JR0 Secure Memory Access Permissions register 0x10AD4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P13SMAG2_JR0 Secure Memory Access Group Registers 0x10AD8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P13SMAG1_JR0 Secure Memory Access Group Registers 0x10ADC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P14SDID_JR0 Partition 14 SDID register 0x10AE0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P14SMAPR_JR0 Secure Memory Access Permissions register 0x10AE4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P14SMAG2_JR0 Secure Memory Access Group Registers 0x10AE8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P14SMAG1_JR0 Secure Memory Access Group Registers 0x10AEC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P15SDID_JR0 Partition 15 SDID register 0x10AF0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P15SMAPR_JR0 Secure Memory Access Permissions register 0x10AF4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P15SMAG2_JR0 Secure Memory Access Group Registers 0x10AF8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P15SMAG1_JR0 Secure Memory Access Group Registers 0x10AFC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write SMCR_JR0 Secure Memory Command Register 0x10BE4 32 write-only 0 0xFFFFFFFF CMD Command: 1h: Allocate Page - This command allocates the page specified in the PAGE field to the partition specified in the PRTN field 0 4 write-only PRTN Partition: When an Allocate Page or De-allocate Partition command is issued, the action is performed on the partition indicated in the PRTN field 8 4 write-only PAGE This is the number of the page to be referenced in field CMD 16 16 write-only SMCSR_JR0 Secure Memory Command Status Register 0x10BEC 32 read-only 0 0xFFFFFFFF PRTN Following a Page Inquiry Command, if the PO field is 10 or 11, this field indicates the partition to which the page specified in the PAGE field is allocated 0 4 read-only PO Page Owner: Following a Page Inquiry Command, this field indicates if the Page is owned by the entity that issued the inquiry, owned by another entity, or unowned 6 2 read-only AVAILABLE Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No zeroization is needed since it has already been cleared, therefore no interrupt should be expected. 0 NOT_PRESENT_OR_INITIALIZED Page does not exist in this version or is not initialized yet. 0x1 UNAVAILABLE Another entity owns the page. This page is unavailable to the issuer of the inquiry. 0x2 OWNED Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized upon de-allocation. 0x3 AERR Allocation Error 12 2 read-only CERR Command Error 14 2 read-only NO_ERROR No Error. 0 CMD_INCOMPLETE_ERROR Command has not yet completed. 0x1 SECURITY_FAILURE A security failure occurred. 0x2 CMD_OVERFLOW_ERROR Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous command completed. The additional command was ignored. 0x3 PAGE Page 16 12 read-only REIR0JR0 Recoverable Error Interrupt Record 0 for Job Ring 0 0x10E00 32 read-only 0 0xFFFFFFFF TYPE This field indicates the type of the recoverable error 24 2 read-only MISS If MISS=1, a second recoverable error associated with JR occurred before REIR0JR was written following a previous JR recoverable error 31 1 read-only REIR2JR0 Recoverable Error Interrupt Record 2 for Job Ring 0 0x10E08 64 read-only 0 0xFFFFFFFFFFFFFFFF ADDR Address associated with the recoverable JR error. 0 36 read-only REIR4JR0 Recoverable Error Interrupt Record 4 for Job Ring 0 0x10E10 32 read-only 0 0xFFFFFFFF ICID This field holds the ICID associated with the recoverable error. 0 11 read-only DID This field holds the DID associated with the recoverable error. 11 4 read-only AXCACHE This field holds the AXI cache control transaction attribute used for the memory access. 16 4 read-only AXPROT This field holds the AXI protection transaction attribute used for the memory access. 20 3 read-only RWB This field specifies whether the memory access was a read or write. 23 1 read-only ERR This field holds the AXI error response associated with the recoverable error. 28 2 read-only MIX This field holds the memory interface index associated with the recoverable error. 30 2 read-only REIR5JR0 Recoverable Error Interrupt Record 5 for Job Ring 0 0x10E14 32 read-only 0 0xFFFFFFFF BID This field holds the block identifier (see Internal Block ID) of the source of the AXI transaction associated with the recoverable error 16 4 read-only BNDG This field indicates whether the bus transaction associated with the recoverable error was initiating an CAAM Secure Memory blob operation 25 1 read-only TDSC This field indicates whether the bus transaction associated with the recoverable error was an attempt to assert trusted descriptor privilege when accessing an CAAM Secure Memory partition 26 1 read-only KMOD This field indicates whether the bus transaction associated with the recoverable error was an attempt to read the key modifier associated with an CAAM Secure Memory partition 27 1 read-only KEY This field indicates whether the bus transaction associated with the recoverable error was an attempted key access to CAAM Secure Memory 28 1 read-only SMA This field indicates whether the bus transaction associated with the recoverable error was an attempted access to CAAM Secure Memory 29 1 read-only IRBAR_JR1 Input Ring Base Address Register for Job Ring 1 0x20000 64 read-write 0 0xFFFFFFFFFFFFFFFF IRBA Input Ring Base Address. 0 36 read-write IRSR_JR1 Input Ring Size Register for Job Ring 1 0x2000C 32 read-write 0 0xFFFFFFFF IRS Input Ring Size. (measured in number of entries) 0 10 read-write IRSAR_JR1 Input Ring Slots Available Register for Job Ring 1 0x20014 32 read-write 0 0xFFFFFFFF IRSA Input Ring Slots Available. (measured in number of available job slots) 0 10 read-write IRJAR_JR1 Input Ring Jobs Added Register for Job Ring1 0x2001C 32 read-write 0 0xFFFFFFFF IRJA Input Ring Jobs Added. (measured in number of entries) 0 10 read-write ORBAR_JR1 Output Ring Base Address Register for Job Ring 1 0x20020 64 read-write 0 0xFFFFFFFFFFFFFFFF ORBA Output Ring Base Address. 0 36 read-write ORSR_JR1 Output Ring Size Register for Job Ring 1 0x2002C 32 read-write 0 0xFFFFFFFF ORS Output Ring Size. (measured in number of entries) 0 10 read-write ORJRR_JR1 Output Ring Jobs Removed Register for Job Ring 1 0x20034 32 read-write 0 0xFFFFFFFF ORJR Output Ring Jobs Removed. (measured in number of entries) 0 10 read-write ORSFR_JR1 Output Ring Slots Full Register for Job Ring 1 0x2003C 32 read-write 0 0xFFFFFFFF ORSF Output Ring Slots Full. (measured in number of entries) 0 10 read-write JRSTAR_JR1 Job Ring Output Status Register for Job Ring 1 0x20044 32 read-only 0 0xFFFFFFFF SSED Source-specific error details 0 28 read-only SSRC Status source. These bits define which source is reporting the status. All other values - reserved 28 4 read-only NO_STATUS No Status Source (No Error or Status Reported) 0 CCB_STATUS CCB Status Source (CCB Error Reported) 0x2 JMP_USR_STATUS Jump Halt User Status Source (User-Provided Status Reported) 0x3 DECO_STATUS DECO Status Source (DECO Error Reported) 0x4 JR_STATUS Job Ring Status Source (Job Ring Error Reported) 0x6 JMP_COND_STATUS Jump Halt Condition Codes (Condition Code Status Reported) 0x7 JRINTR_JR1 Job Ring Interrupt Status Register for Job Ring 1 0x2004C 32 read-write 0 0xFFFFFFFF JRI Job Ring Interrupt 0 1 read-write oneToClear JRE Job Ring Error 1 1 read-write oneToClear HALT Halt the Job Ring 2 2 read-write oneToClear ENTER_FAIL Enter SNVS Fail State 4 1 read-write oneToClear EXIT_FAIL Exit SNVS Fail State 5 1 read-write oneToClear ERR_TYPE Error type 8 5 read-only OR_WR_ERR Error writing status to Output Ring 0x1 BAD_IR_ADDR_ERR Bad input ring base address (not on a 4-byte boundary). 0x3 BAD_OR_ADDR_ERR Bad output ring base address (not on a 4-byte boundary). 0x4 INV_IR_REG_WR_ERR Invalid write to Input Ring Base Address Register or Input Ring Size Register. Can be written when there are no jobs in the input ring or when the Job Ring is halted. These are fatal and will likely result in not being able to get all jobs out into the output ring for processing by software. Resetting the job ring will almost certainly be necessary. 0x5 INV_OR_REG_WR_ERR Invalid write to Output Ring Base Address Register or Output Ring Size Register. Can be written when there are no jobs in the output ring and no jobs from this queue are already processing in CAAM (in the holding tanks or DECOs), or when the Job Ring is halted. 0x6 INV_JR_RESET_ERR Job Ring reset released before Job Ring is halted. 0x7 ORJRR_GT_ORSFR_ERR Removed too many jobs (ORJRR larger than ORSFR). 0x8 IRJAR_GT_IRSAR_ERR Added too many jobs (IRJAR larger than IRSAR). 0x9 ORSF_GT_ORS_ERR Writing ORSF > ORS In these error cases the write is ignored, the interrupt is asserted (unless masked) and the error bit and error_type fields are set in the Job Ring Interrupt Status Register. 0xA IRSA_GT_IRS_ERR Writing IRSA > IRS 0xB ORWI_GT_ORS_ERR Writing ORWI > ORS in bytes 0xC IRRI_GT_IRS_ERR Writing IRRI > IRS in bytes 0xD INV_IRSA_WR_ERR Writing IRSA when ring is active 0xE INV_IRRI_WR_ERR Writing IRRI when ring is active 0xF INV_ORSF_WR_ERR Writing ORSF when ring is active 0x10 INV_ORWI_WR_ERR Writing ORWI when ring is active 0x11 ERR_ORWI Output ring write index with error 16 14 read-only JRCFGR_JR1_MS Job Ring Configuration Register for Job Ring 1, most-significant half 0x20050 32 read-write 0 0xFFFFFFFF MBSI To assist with mixed Endianness platforms, this bit configures a byte swap of message data read by CAAM DMA 0 1 read-write MHWSI To assist with mixed Endianness platforms, this bit configures a halfword swap of message data read by CAAM DMA 1 1 read-write MWSI To assist with mixed Endianness platforms, this bit configures a fullword swap of message data read by CAAM DMA 2 1 read-write CBSI To assist with mixed Endianness platforms, this bit configures a byte swap of control data read by CAAM DMA 4 1 read-write CHWSI To assist with mixed Endianness platforms, this bit configures a halfword swap of control data read by CAAM DMA 5 1 read-write CWSI To assist with mixed Endianness platforms, this bit configures a fullword swap of control data read by CAAM DMA 6 1 read-write MBSO To assist with mixed Endianness platforms, this bit configures a byte swap of message data written by CAAM DMA 8 1 read-write MHWSO To assist with mixed Endianness platforms, this bit configures a halfword swap of message data written by CAAM DMA 9 1 read-write MWSO To assist with mixed Endianness platforms, this bit configures a fullword swap of message data written by CAAM DMA 10 1 read-write CBSO To assist with mixed Endianness platforms, this bit configures a byte swap of control data written by CAAM DMA 12 1 read-write CHWSO To assist with mixed Endianness platforms, this bit configures a halfword swap of control data written by CAAM DMA 13 1 read-write CWSO To assist with mixed Endianness platforms, this bit configures a fullword swap of control data written by CAAM DMA 14 1 read-write DMBS Descriptor Message Data Byte Swap (this applies only to internal message data transfers to/from DECO Descriptor Buffers) 16 1 read-write PEO Platform Endian Override - The bit is XORed with the PLEND bit in the CaCSTA Register and the other "swap" bits in the Job Ring Configuration Register to determine the AXI Master's view of memory endianness when executing Job Descriptors from this Job Ring 17 1 read-write DWSO Double Word Swap Override 18 1 read-write FAIL_MODE Fail mode control 29 1 read-write INCL_SEQ_OUT Include Sequence Out Length 30 1 read-write JRCFGR_JR1_LS Job Ring Configuration Register for Job Ring 1, least-significant half 0x20054 32 read-write 0 0xFFFFFFFF IMSK Interrupt Mask. Mask the interrupt that is associated with the particular processor. 0 1 read-write INTR_ENABLED Interrupt enabled. 0 INTR_MASKED Interrupt masked. 0x1 ICEN Interrupt Coalescing Enable. 1 1 read-write INTR_COAL_DISABLED Interrupt coalescing is disabled. If the IMSK bit is cleared, an interrupt is asserted whenever a job is written to the output ring. ICDCT is ignored. Note that if software removes one or more jobs and clears the interrupt but the output rings slots full is still greater than 0 (ORSF > 0), then the interrupt will clear but reassert on the next clock cycle. 0 INTR_COAL_ENABLED Interrupt coalescing is enabled. If the IMSK bit is cleared, an interrupt is asserted whenever the threshold number of frames is reached (ICDCT) or when the threshold timer expires (ICTT). Note that if software removes one or more jobs and clears the interrupt but the interrupt coalescing threshold is still met (ORSF >= ICDCT), then the interrupt will clear but reassert on the next clock cycle. 0x1 ICDCT Interrupt Coalescing Descriptor Count Threshold 8 8 read-write ICTT Interrupt Coalescing Timer Threshold 16 16 read-write IRRIR_JR1 Input Ring Read Index Register for Job Ring 1 0x2005C 32 read-write 0 0xFFFFFFFF IRRI Input Ring Read Index. 0 13 read-write ORWIR_JR1 Output Ring Write Index Register for Job Ring 1 0x20064 32 read-write 0 0xFFFFFFFF ORWI Output Ring Write Index. The pointer to the next entry in the output ring. 0 14 read-write JRCR_JR1 Job Ring Command Register for Job Ring 1 0x2006C 32 write-only 0 0xFFFFFFFF RESET Reset - When RESET is 0, software writes a 1 to RESET to request a flush of the Job Ring 0 1 write-only PARK Park - When PARK is 0, software writes a 1 to PARK to request that the Job Ring be "parked", i 1 1 write-only JR1AAV Job Ring 1 Address-Array Valid Register 0x20704 32 read-only 0 0xFFFFFFFF V0 Valid 0 0 1 read-only V1 Valid 1 1 1 read-only V2 Valid 2 2 1 read-only V3 Valid 3 3 1 read-only BC Been Changed 31 1 read-only JR1AAA0 Job Ring 1 Address-Array Address 0 Register 0x20800 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR1AAA1 Job Ring 1 Address-Array Address 1 Register 0x20808 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR1AAA2 Job Ring 1 Address-Array Address 2 Register 0x20810 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR1AAA3 Job Ring 1 Address-Array Address 3 Register 0x20818 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only P0SDID_JR1 Partition 0 SDID register 0x20A00 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P0SMAPR_JR1 Secure Memory Access Permissions register 0x20A04 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P0SMAG2_JR1 Secure Memory Access Group Registers 0x20A08 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P0SMAG1_JR1 Secure Memory Access Group Registers 0x20A0C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P1SDID_JR1 Partition 1 SDID register 0x20A10 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P1SMAPR_JR1 Secure Memory Access Permissions register 0x20A14 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P1SMAG2_JR1 Secure Memory Access Group Registers 0x20A18 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P1SMAG1_JR1 Secure Memory Access Group Registers 0x20A1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P2SDID_JR1 Partition 2 SDID register 0x20A20 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P2SMAPR_JR1 Secure Memory Access Permissions register 0x20A24 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P2SMAG2_JR1 Secure Memory Access Group Registers 0x20A28 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P2SMAG1_JR1 Secure Memory Access Group Registers 0x20A2C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P3SDID_JR1 Partition 3 SDID register 0x20A30 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P3SMAPR_JR1 Secure Memory Access Permissions register 0x20A34 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P3SMAG2_JR1 Secure Memory Access Group Registers 0x20A38 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P3SMAG1_JR1 Secure Memory Access Group Registers 0x20A3C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P4SDID_JR1 Partition 4 SDID register 0x20A40 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P4SMAPR_JR1 Secure Memory Access Permissions register 0x20A44 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P4SMAG2_JR1 Secure Memory Access Group Registers 0x20A48 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P4SMAG1_JR1 Secure Memory Access Group Registers 0x20A4C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P5SDID_JR1 Partition 5 SDID register 0x20A50 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P5SMAPR_JR1 Secure Memory Access Permissions register 0x20A54 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P5SMAG2_JR1 Secure Memory Access Group Registers 0x20A58 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P5SMAG1_JR1 Secure Memory Access Group Registers 0x20A5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P6SDID_JR1 Partition 6 SDID register 0x20A60 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P6SMAPR_JR1 Secure Memory Access Permissions register 0x20A64 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P6SMAG2_JR1 Secure Memory Access Group Registers 0x20A68 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P6SMAG1_JR1 Secure Memory Access Group Registers 0x20A6C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P7SDID_JR1 Partition 7 SDID register 0x20A70 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P7SMAPR_JR1 Secure Memory Access Permissions register 0x20A74 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P7SMAG2_JR1 Secure Memory Access Group Registers 0x20A78 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P7SMAG1_JR1 Secure Memory Access Group Registers 0x20A7C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P8SDID_JR1 Partition 8 SDID register 0x20A80 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P8SMAPR_JR1 Secure Memory Access Permissions register 0x20A84 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P8SMAG2_JR1 Secure Memory Access Group Registers 0x20A88 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P8SMAG1_JR1 Secure Memory Access Group Registers 0x20A8C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P9SDID_JR1 Partition 9 SDID register 0x20A90 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P9SMAPR_JR1 Secure Memory Access Permissions register 0x20A94 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P9SMAG2_JR1 Secure Memory Access Group Registers 0x20A98 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P9SMAG1_JR1 Secure Memory Access Group Registers 0x20A9C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P10SDID_JR1 Partition 10 SDID register 0x20AA0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P10SMAPR_JR1 Secure Memory Access Permissions register 0x20AA4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P10SMAG2_JR1 Secure Memory Access Group Registers 0x20AA8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P10SMAG1_JR1 Secure Memory Access Group Registers 0x20AAC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P11SDID_JR1 Partition 11 SDID register 0x20AB0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P11SMAPR_JR1 Secure Memory Access Permissions register 0x20AB4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P11SMAG2_JR1 Secure Memory Access Group Registers 0x20AB8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P11SMAG1_JR1 Secure Memory Access Group Registers 0x20ABC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P12SDID_JR1 Partition 12 SDID register 0x20AC0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P12SMAPR_JR1 Secure Memory Access Permissions register 0x20AC4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P12SMAG2_JR1 Secure Memory Access Group Registers 0x20AC8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P12SMAG1_JR1 Secure Memory Access Group Registers 0x20ACC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P13SDID_JR1 Partition 13 SDID register 0x20AD0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P13SMAPR_JR1 Secure Memory Access Permissions register 0x20AD4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P13SMAG2_JR1 Secure Memory Access Group Registers 0x20AD8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P13SMAG1_JR1 Secure Memory Access Group Registers 0x20ADC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P14SDID_JR1 Partition 14 SDID register 0x20AE0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P14SMAPR_JR1 Secure Memory Access Permissions register 0x20AE4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P14SMAG2_JR1 Secure Memory Access Group Registers 0x20AE8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P14SMAG1_JR1 Secure Memory Access Group Registers 0x20AEC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P15SDID_JR1 Partition 15 SDID register 0x20AF0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P15SMAPR_JR1 Secure Memory Access Permissions register 0x20AF4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P15SMAG2_JR1 Secure Memory Access Group Registers 0x20AF8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P15SMAG1_JR1 Secure Memory Access Group Registers 0x20AFC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write SMCR_JR1 Secure Memory Command Register 0x20BE4 32 write-only 0 0xFFFFFFFF CMD Command: 1h: Allocate Page - This command allocates the page specified in the PAGE field to the partition specified in the PRTN field 0 4 write-only PRTN Partition: When an Allocate Page or De-allocate Partition command is issued, the action is performed on the partition indicated in the PRTN field 8 4 write-only PAGE This is the number of the page to be referenced in field CMD 16 16 write-only SMCSR_JR1 Secure Memory Command Status Register 0x20BEC 32 read-only 0 0xFFFFFFFF PRTN Following a Page Inquiry Command, if the PO field is 10 or 11, this field indicates the partition to which the page specified in the PAGE field is allocated 0 4 read-only PO Page Owner: Following a Page Inquiry Command, this field indicates if the Page is owned by the entity that issued the inquiry, owned by another entity, or unowned 6 2 read-only AVAILABLE Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No zeroization is needed since it has already been cleared, therefore no interrupt should be expected. 0 NOT_PRESENT_OR_INITIALIZED Page does not exist in this version or is not initialized yet. 0x1 UNAVAILABLE Another entity owns the page. This page is unavailable to the issuer of the inquiry. 0x2 OWNED Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized upon de-allocation. 0x3 AERR Allocation Error 12 2 read-only CERR Command Error 14 2 read-only NO_ERROR No Error. 0 CMD_INCOMPLETE_ERROR Command has not yet completed. 0x1 SECURITY_FAILURE A security failure occurred. 0x2 CMD_OVERFLOW_ERROR Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous command completed. The additional command was ignored. 0x3 PAGE Page 16 12 read-only REIR0JR1 Recoverable Error Interrupt Record 0 for Job Ring 1 0x20E00 32 read-only 0 0xFFFFFFFF TYPE This field indicates the type of the recoverable error 24 2 read-only MISS If MISS=1, a second recoverable error associated with JR occurred before REIR0JR was written following a previous JR recoverable error 31 1 read-only REIR2JR1 Recoverable Error Interrupt Record 2 for Job Ring 1 0x20E08 64 read-only 0 0xFFFFFFFFFFFFFFFF ADDR Address associated with the recoverable JR error. 0 36 read-only REIR4JR1 Recoverable Error Interrupt Record 4 for Job Ring 1 0x20E10 32 read-only 0 0xFFFFFFFF ICID This field holds the ICID associated with the recoverable error. 0 11 read-only DID This field holds the DID associated with the recoverable error. 11 4 read-only AXCACHE This field holds the AXI cache control transaction attribute used for the memory access. 16 4 read-only AXPROT This field holds the AXI protection transaction attribute used for the memory access. 20 3 read-only RWB This field specifies whether the memory access was a read or write. 23 1 read-only ERR This field holds the AXI error response associated with the recoverable error. 28 2 read-only MIX This field holds the memory interface index associated with the recoverable error. 30 2 read-only REIR5JR1 Recoverable Error Interrupt Record 5 for Job Ring 1 0x20E14 32 read-only 0 0xFFFFFFFF BID This field holds the block identifier (see Internal Block ID) of the source of the AXI transaction associated with the recoverable error 16 4 read-only BNDG This field indicates whether the bus transaction associated with the recoverable error was initiating an CAAM Secure Memory blob operation 25 1 read-only TDSC This field indicates whether the bus transaction associated with the recoverable error was an attempt to assert trusted descriptor privilege when accessing an CAAM Secure Memory partition 26 1 read-only KMOD This field indicates whether the bus transaction associated with the recoverable error was an attempt to read the key modifier associated with an CAAM Secure Memory partition 27 1 read-only KEY This field indicates whether the bus transaction associated with the recoverable error was an attempted key access to CAAM Secure Memory 28 1 read-only SMA This field indicates whether the bus transaction associated with the recoverable error was an attempted access to CAAM Secure Memory 29 1 read-only IRBAR_JR2 Input Ring Base Address Register for Job Ring 2 0x30000 64 read-write 0 0xFFFFFFFFFFFFFFFF IRBA Input Ring Base Address. 0 36 read-write IRSR_JR2 Input Ring Size Register for Job Ring 2 0x3000C 32 read-write 0 0xFFFFFFFF IRS Input Ring Size. (measured in number of entries) 0 10 read-write IRSAR_JR2 Input Ring Slots Available Register for Job Ring 2 0x30014 32 read-write 0 0xFFFFFFFF IRSA Input Ring Slots Available. (measured in number of available job slots) 0 10 read-write IRJAR_JR2 Input Ring Jobs Added Register for Job Ring2 0x3001C 32 read-write 0 0xFFFFFFFF IRJA Input Ring Jobs Added. (measured in number of entries) 0 10 read-write ORBAR_JR2 Output Ring Base Address Register for Job Ring 2 0x30020 64 read-write 0 0xFFFFFFFFFFFFFFFF ORBA Output Ring Base Address. 0 36 read-write ORSR_JR2 Output Ring Size Register for Job Ring 2 0x3002C 32 read-write 0 0xFFFFFFFF ORS Output Ring Size. (measured in number of entries) 0 10 read-write ORJRR_JR2 Output Ring Jobs Removed Register for Job Ring 2 0x30034 32 read-write 0 0xFFFFFFFF ORJR Output Ring Jobs Removed. (measured in number of entries) 0 10 read-write ORSFR_JR2 Output Ring Slots Full Register for Job Ring 2 0x3003C 32 read-write 0 0xFFFFFFFF ORSF Output Ring Slots Full. (measured in number of entries) 0 10 read-write JRSTAR_JR2 Job Ring Output Status Register for Job Ring 2 0x30044 32 read-only 0 0xFFFFFFFF SSED Source-specific error details 0 28 read-only SSRC Status source. These bits define which source is reporting the status. All other values - reserved 28 4 read-only NO_STATUS No Status Source (No Error or Status Reported) 0 CCB_STATUS CCB Status Source (CCB Error Reported) 0x2 JMP_USR_STATUS Jump Halt User Status Source (User-Provided Status Reported) 0x3 DECO_STATUS DECO Status Source (DECO Error Reported) 0x4 JR_STATUS Job Ring Status Source (Job Ring Error Reported) 0x6 JMP_COND_STATUS Jump Halt Condition Codes (Condition Code Status Reported) 0x7 JRINTR_JR2 Job Ring Interrupt Status Register for Job Ring 2 0x3004C 32 read-write 0 0xFFFFFFFF JRI Job Ring Interrupt 0 1 read-write oneToClear JRE Job Ring Error 1 1 read-write oneToClear HALT Halt the Job Ring 2 2 read-write oneToClear ENTER_FAIL Enter SNVS Fail State 4 1 read-write oneToClear EXIT_FAIL Exit SNVS Fail State 5 1 read-write oneToClear ERR_TYPE Error type 8 5 read-only OR_WR_ERR Error writing status to Output Ring 0x1 BAD_IR_ADDR_ERR Bad input ring base address (not on a 4-byte boundary). 0x3 BAD_OR_ADDR_ERR Bad output ring base address (not on a 4-byte boundary). 0x4 INV_IR_REG_WR_ERR Invalid write to Input Ring Base Address Register or Input Ring Size Register. Can be written when there are no jobs in the input ring or when the Job Ring is halted. These are fatal and will likely result in not being able to get all jobs out into the output ring for processing by software. Resetting the job ring will almost certainly be necessary. 0x5 INV_OR_REG_WR_ERR Invalid write to Output Ring Base Address Register or Output Ring Size Register. Can be written when there are no jobs in the output ring and no jobs from this queue are already processing in CAAM (in the holding tanks or DECOs), or when the Job Ring is halted. 0x6 INV_JR_RESET_ERR Job Ring reset released before Job Ring is halted. 0x7 ORJRR_GT_ORSFR_ERR Removed too many jobs (ORJRR larger than ORSFR). 0x8 IRJAR_GT_IRSAR_ERR Added too many jobs (IRJAR larger than IRSAR). 0x9 ORSF_GT_ORS_ERR Writing ORSF > ORS In these error cases the write is ignored, the interrupt is asserted (unless masked) and the error bit and error_type fields are set in the Job Ring Interrupt Status Register. 0xA IRSA_GT_IRS_ERR Writing IRSA > IRS 0xB ORWI_GT_ORS_ERR Writing ORWI > ORS in bytes 0xC IRRI_GT_IRS_ERR Writing IRRI > IRS in bytes 0xD INV_IRSA_WR_ERR Writing IRSA when ring is active 0xE INV_IRRI_WR_ERR Writing IRRI when ring is active 0xF INV_ORSF_WR_ERR Writing ORSF when ring is active 0x10 INV_ORWI_WR_ERR Writing ORWI when ring is active 0x11 ERR_ORWI Output ring write index with error 16 14 read-only JRCFGR_JR2_MS Job Ring Configuration Register for Job Ring 2, most-significant half 0x30050 32 read-write 0 0xFFFFFFFF MBSI To assist with mixed Endianness platforms, this bit configures a byte swap of message data read by CAAM DMA 0 1 read-write MHWSI To assist with mixed Endianness platforms, this bit configures a halfword swap of message data read by CAAM DMA 1 1 read-write MWSI To assist with mixed Endianness platforms, this bit configures a fullword swap of message data read by CAAM DMA 2 1 read-write CBSI To assist with mixed Endianness platforms, this bit configures a byte swap of control data read by CAAM DMA 4 1 read-write CHWSI To assist with mixed Endianness platforms, this bit configures a halfword swap of control data read by CAAM DMA 5 1 read-write CWSI To assist with mixed Endianness platforms, this bit configures a fullword swap of control data read by CAAM DMA 6 1 read-write MBSO To assist with mixed Endianness platforms, this bit configures a byte swap of message data written by CAAM DMA 8 1 read-write MHWSO To assist with mixed Endianness platforms, this bit configures a halfword swap of message data written by CAAM DMA 9 1 read-write MWSO To assist with mixed Endianness platforms, this bit configures a fullword swap of message data written by CAAM DMA 10 1 read-write CBSO To assist with mixed Endianness platforms, this bit configures a byte swap of control data written by CAAM DMA 12 1 read-write CHWSO To assist with mixed Endianness platforms, this bit configures a halfword swap of control data written by CAAM DMA 13 1 read-write CWSO To assist with mixed Endianness platforms, this bit configures a fullword swap of control data written by CAAM DMA 14 1 read-write DMBS Descriptor Message Data Byte Swap (this applies only to internal message data transfers to/from DECO Descriptor Buffers) 16 1 read-write PEO Platform Endian Override - The bit is XORed with the PLEND bit in the CaCSTA Register and the other "swap" bits in the Job Ring Configuration Register to determine the AXI Master's view of memory endianness when executing Job Descriptors from this Job Ring 17 1 read-write DWSO Double Word Swap Override 18 1 read-write FAIL_MODE Fail mode control 29 1 read-write INCL_SEQ_OUT Include Sequence Out Length 30 1 read-write JRCFGR_JR2_LS Job Ring Configuration Register for Job Ring 2, least-significant half 0x30054 32 read-write 0 0xFFFFFFFF IMSK Interrupt Mask. Mask the interrupt that is associated with the particular processor. 0 1 read-write INTR_ENABLED Interrupt enabled. 0 INTR_MASKED Interrupt masked. 0x1 ICEN Interrupt Coalescing Enable. 1 1 read-write INTR_COAL_DISABLED Interrupt coalescing is disabled. If the IMSK bit is cleared, an interrupt is asserted whenever a job is written to the output ring. ICDCT is ignored. Note that if software removes one or more jobs and clears the interrupt but the output rings slots full is still greater than 0 (ORSF > 0), then the interrupt will clear but reassert on the next clock cycle. 0 INTR_COAL_ENABLED Interrupt coalescing is enabled. If the IMSK bit is cleared, an interrupt is asserted whenever the threshold number of frames is reached (ICDCT) or when the threshold timer expires (ICTT). Note that if software removes one or more jobs and clears the interrupt but the interrupt coalescing threshold is still met (ORSF >= ICDCT), then the interrupt will clear but reassert on the next clock cycle. 0x1 ICDCT Interrupt Coalescing Descriptor Count Threshold 8 8 read-write ICTT Interrupt Coalescing Timer Threshold 16 16 read-write IRRIR_JR2 Input Ring Read Index Register for Job Ring 2 0x3005C 32 read-write 0 0xFFFFFFFF IRRI Input Ring Read Index. 0 13 read-write ORWIR_JR2 Output Ring Write Index Register for Job Ring 2 0x30064 32 read-write 0 0xFFFFFFFF ORWI Output Ring Write Index. The pointer to the next entry in the output ring. 0 14 read-write JRCR_JR2 Job Ring Command Register for Job Ring 2 0x3006C 32 write-only 0 0xFFFFFFFF RESET Reset - When RESET is 0, software writes a 1 to RESET to request a flush of the Job Ring 0 1 write-only PARK Park - When PARK is 0, software writes a 1 to PARK to request that the Job Ring be "parked", i 1 1 write-only JR2AAV Job Ring 2 Address-Array Valid Register 0x30704 32 read-only 0 0xFFFFFFFF V0 Valid 0 0 1 read-only V1 Valid 1 1 1 read-only V2 Valid 2 2 1 read-only V3 Valid 3 3 1 read-only BC Been Changed 31 1 read-only JR2AAA0 Job Ring 2 Address-Array Address 0 Register 0x30800 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR2AAA1 Job Ring 2 Address-Array Address 1 Register 0x30808 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR2AAA2 Job Ring 2 Address-Array Address 2 Register 0x30810 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR2AAA3 Job Ring 2 Address-Array Address 3 Register 0x30818 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only P0SDID_JR2 Partition 0 SDID register 0x30A00 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P0SMAPR_JR2 Secure Memory Access Permissions register 0x30A04 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P0SMAG2_JR2 Secure Memory Access Group Registers 0x30A08 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P0SMAG1_JR2 Secure Memory Access Group Registers 0x30A0C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P1SDID_JR2 Partition 1 SDID register 0x30A10 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P1SMAPR_JR2 Secure Memory Access Permissions register 0x30A14 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P1SMAG2_JR2 Secure Memory Access Group Registers 0x30A18 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P1SMAG1_JR2 Secure Memory Access Group Registers 0x30A1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P2SDID_JR2 Partition 2 SDID register 0x30A20 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P2SMAPR_JR2 Secure Memory Access Permissions register 0x30A24 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P2SMAG2_JR2 Secure Memory Access Group Registers 0x30A28 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P2SMAG1_JR2 Secure Memory Access Group Registers 0x30A2C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P3SDID_JR2 Partition 3 SDID register 0x30A30 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P3SMAPR_JR2 Secure Memory Access Permissions register 0x30A34 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P3SMAG2_JR2 Secure Memory Access Group Registers 0x30A38 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P3SMAG1_JR2 Secure Memory Access Group Registers 0x30A3C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P4SDID_JR2 Partition 4 SDID register 0x30A40 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P4SMAPR_JR2 Secure Memory Access Permissions register 0x30A44 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P4SMAG2_JR2 Secure Memory Access Group Registers 0x30A48 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P4SMAG1_JR2 Secure Memory Access Group Registers 0x30A4C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P5SDID_JR2 Partition 5 SDID register 0x30A50 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P5SMAPR_JR2 Secure Memory Access Permissions register 0x30A54 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P5SMAG2_JR2 Secure Memory Access Group Registers 0x30A58 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P5SMAG1_JR2 Secure Memory Access Group Registers 0x30A5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P6SDID_JR2 Partition 6 SDID register 0x30A60 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P6SMAPR_JR2 Secure Memory Access Permissions register 0x30A64 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P6SMAG2_JR2 Secure Memory Access Group Registers 0x30A68 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P6SMAG1_JR2 Secure Memory Access Group Registers 0x30A6C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P7SDID_JR2 Partition 7 SDID register 0x30A70 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P7SMAPR_JR2 Secure Memory Access Permissions register 0x30A74 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P7SMAG2_JR2 Secure Memory Access Group Registers 0x30A78 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P7SMAG1_JR2 Secure Memory Access Group Registers 0x30A7C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P8SDID_JR2 Partition 8 SDID register 0x30A80 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P8SMAPR_JR2 Secure Memory Access Permissions register 0x30A84 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P8SMAG2_JR2 Secure Memory Access Group Registers 0x30A88 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P8SMAG1_JR2 Secure Memory Access Group Registers 0x30A8C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P9SDID_JR2 Partition 9 SDID register 0x30A90 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P9SMAPR_JR2 Secure Memory Access Permissions register 0x30A94 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P9SMAG2_JR2 Secure Memory Access Group Registers 0x30A98 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P9SMAG1_JR2 Secure Memory Access Group Registers 0x30A9C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P10SDID_JR2 Partition 10 SDID register 0x30AA0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P10SMAPR_JR2 Secure Memory Access Permissions register 0x30AA4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P10SMAG2_JR2 Secure Memory Access Group Registers 0x30AA8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P10SMAG1_JR2 Secure Memory Access Group Registers 0x30AAC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P11SDID_JR2 Partition 11 SDID register 0x30AB0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P11SMAPR_JR2 Secure Memory Access Permissions register 0x30AB4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P11SMAG2_JR2 Secure Memory Access Group Registers 0x30AB8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P11SMAG1_JR2 Secure Memory Access Group Registers 0x30ABC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P12SDID_JR2 Partition 12 SDID register 0x30AC0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P12SMAPR_JR2 Secure Memory Access Permissions register 0x30AC4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P12SMAG2_JR2 Secure Memory Access Group Registers 0x30AC8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P12SMAG1_JR2 Secure Memory Access Group Registers 0x30ACC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P13SDID_JR2 Partition 13 SDID register 0x30AD0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P13SMAPR_JR2 Secure Memory Access Permissions register 0x30AD4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P13SMAG2_JR2 Secure Memory Access Group Registers 0x30AD8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P13SMAG1_JR2 Secure Memory Access Group Registers 0x30ADC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P14SDID_JR2 Partition 14 SDID register 0x30AE0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P14SMAPR_JR2 Secure Memory Access Permissions register 0x30AE4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P14SMAG2_JR2 Secure Memory Access Group Registers 0x30AE8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P14SMAG1_JR2 Secure Memory Access Group Registers 0x30AEC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P15SDID_JR2 Partition 15 SDID register 0x30AF0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P15SMAPR_JR2 Secure Memory Access Permissions register 0x30AF4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P15SMAG2_JR2 Secure Memory Access Group Registers 0x30AF8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P15SMAG1_JR2 Secure Memory Access Group Registers 0x30AFC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write SMCR_JR2 Secure Memory Command Register 0x30BE4 32 write-only 0 0xFFFFFFFF CMD Command: 1h: Allocate Page - This command allocates the page specified in the PAGE field to the partition specified in the PRTN field 0 4 write-only PRTN Partition: When an Allocate Page or De-allocate Partition command is issued, the action is performed on the partition indicated in the PRTN field 8 4 write-only PAGE This is the number of the page to be referenced in field CMD 16 16 write-only SMCSR_JR2 Secure Memory Command Status Register 0x30BEC 32 read-only 0 0xFFFFFFFF PRTN Following a Page Inquiry Command, if the PO field is 10 or 11, this field indicates the partition to which the page specified in the PAGE field is allocated 0 4 read-only PO Page Owner: Following a Page Inquiry Command, this field indicates if the Page is owned by the entity that issued the inquiry, owned by another entity, or unowned 6 2 read-only AVAILABLE Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No zeroization is needed since it has already been cleared, therefore no interrupt should be expected. 0 NOT_PRESENT_OR_INITIALIZED Page does not exist in this version or is not initialized yet. 0x1 UNAVAILABLE Another entity owns the page. This page is unavailable to the issuer of the inquiry. 0x2 OWNED Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized upon de-allocation. 0x3 AERR Allocation Error 12 2 read-only CERR Command Error 14 2 read-only NO_ERROR No Error. 0 CMD_INCOMPLETE_ERROR Command has not yet completed. 0x1 SECURITY_FAILURE A security failure occurred. 0x2 CMD_OVERFLOW_ERROR Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous command completed. The additional command was ignored. 0x3 PAGE Page 16 12 read-only REIR0JR2 Recoverable Error Interrupt Record 0 for Job Ring 2 0x30E00 32 read-only 0 0xFFFFFFFF TYPE This field indicates the type of the recoverable error 24 2 read-only MISS If MISS=1, a second recoverable error associated with JR occurred before REIR0JR was written following a previous JR recoverable error 31 1 read-only REIR2JR2 Recoverable Error Interrupt Record 2 for Job Ring 2 0x30E08 64 read-only 0 0xFFFFFFFFFFFFFFFF ADDR Address associated with the recoverable JR error. 0 36 read-only REIR4JR2 Recoverable Error Interrupt Record 4 for Job Ring 2 0x30E10 32 read-only 0 0xFFFFFFFF ICID This field holds the ICID associated with the recoverable error. 0 11 read-only DID This field holds the DID associated with the recoverable error. 11 4 read-only AXCACHE This field holds the AXI cache control transaction attribute used for the memory access. 16 4 read-only AXPROT This field holds the AXI protection transaction attribute used for the memory access. 20 3 read-only RWB This field specifies whether the memory access was a read or write. 23 1 read-only ERR This field holds the AXI error response associated with the recoverable error. 28 2 read-only MIX This field holds the memory interface index associated with the recoverable error. 30 2 read-only REIR5JR2 Recoverable Error Interrupt Record 5 for Job Ring 2 0x30E14 32 read-only 0 0xFFFFFFFF BID This field holds the block identifier (see Internal Block ID) of the source of the AXI transaction associated with the recoverable error 16 4 read-only BNDG This field indicates whether the bus transaction associated with the recoverable error was initiating an CAAM Secure Memory blob operation 25 1 read-only TDSC This field indicates whether the bus transaction associated with the recoverable error was an attempt to assert trusted descriptor privilege when accessing an CAAM Secure Memory partition 26 1 read-only KMOD This field indicates whether the bus transaction associated with the recoverable error was an attempt to read the key modifier associated with an CAAM Secure Memory partition 27 1 read-only KEY This field indicates whether the bus transaction associated with the recoverable error was an attempted key access to CAAM Secure Memory 28 1 read-only SMA This field indicates whether the bus transaction associated with the recoverable error was an attempted access to CAAM Secure Memory 29 1 read-only IRBAR_JR3 Input Ring Base Address Register for Job Ring 3 0x40000 64 read-write 0 0xFFFFFFFFFFFFFFFF IRBA Input Ring Base Address. 0 36 read-write IRSR_JR3 Input Ring Size Register for Job Ring 3 0x4000C 32 read-write 0 0xFFFFFFFF IRS Input Ring Size. (measured in number of entries) 0 10 read-write IRSAR_JR3 Input Ring Slots Available Register for Job Ring 3 0x40014 32 read-write 0 0xFFFFFFFF IRSA Input Ring Slots Available. (measured in number of available job slots) 0 10 read-write IRJAR_JR3 Input Ring Jobs Added Register for Job Ring3 0x4001C 32 read-write 0 0xFFFFFFFF IRJA Input Ring Jobs Added. (measured in number of entries) 0 10 read-write ORBAR_JR3 Output Ring Base Address Register for Job Ring 3 0x40020 64 read-write 0 0xFFFFFFFFFFFFFFFF ORBA Output Ring Base Address. 0 36 read-write ORSR_JR3 Output Ring Size Register for Job Ring 3 0x4002C 32 read-write 0 0xFFFFFFFF ORS Output Ring Size. (measured in number of entries) 0 10 read-write ORJRR_JR3 Output Ring Jobs Removed Register for Job Ring 3 0x40034 32 read-write 0 0xFFFFFFFF ORJR Output Ring Jobs Removed. (measured in number of entries) 0 10 read-write ORSFR_JR3 Output Ring Slots Full Register for Job Ring 3 0x4003C 32 read-write 0 0xFFFFFFFF ORSF Output Ring Slots Full. (measured in number of entries) 0 10 read-write JRSTAR_JR3 Job Ring Output Status Register for Job Ring 3 0x40044 32 read-only 0 0xFFFFFFFF SSED Source-specific error details 0 28 read-only SSRC Status source. These bits define which source is reporting the status. All other values - reserved 28 4 read-only NO_STATUS No Status Source (No Error or Status Reported) 0 CCB_STATUS CCB Status Source (CCB Error Reported) 0x2 JMP_USR_STATUS Jump Halt User Status Source (User-Provided Status Reported) 0x3 DECO_STATUS DECO Status Source (DECO Error Reported) 0x4 JR_STATUS Job Ring Status Source (Job Ring Error Reported) 0x6 JMP_COND_STATUS Jump Halt Condition Codes (Condition Code Status Reported) 0x7 JRINTR_JR3 Job Ring Interrupt Status Register for Job Ring 3 0x4004C 32 read-write 0 0xFFFFFFFF JRI Job Ring Interrupt 0 1 read-write oneToClear JRE Job Ring Error 1 1 read-write oneToClear HALT Halt the Job Ring 2 2 read-write oneToClear ENTER_FAIL Enter SNVS Fail State 4 1 read-write oneToClear EXIT_FAIL Exit SNVS Fail State 5 1 read-write oneToClear ERR_TYPE Error type 8 5 read-only OR_WR_ERR Error writing status to Output Ring 0x1 BAD_IR_ADDR_ERR Bad input ring base address (not on a 4-byte boundary). 0x3 BAD_OR_ADDR_ERR Bad output ring base address (not on a 4-byte boundary). 0x4 INV_IR_REG_WR_ERR Invalid write to Input Ring Base Address Register or Input Ring Size Register. Can be written when there are no jobs in the input ring or when the Job Ring is halted. These are fatal and will likely result in not being able to get all jobs out into the output ring for processing by software. Resetting the job ring will almost certainly be necessary. 0x5 INV_OR_REG_WR_ERR Invalid write to Output Ring Base Address Register or Output Ring Size Register. Can be written when there are no jobs in the output ring and no jobs from this queue are already processing in CAAM (in the holding tanks or DECOs), or when the Job Ring is halted. 0x6 INV_JR_RESET_ERR Job Ring reset released before Job Ring is halted. 0x7 ORJRR_GT_ORSFR_ERR Removed too many jobs (ORJRR larger than ORSFR). 0x8 IRJAR_GT_IRSAR_ERR Added too many jobs (IRJAR larger than IRSAR). 0x9 ORSF_GT_ORS_ERR Writing ORSF > ORS In these error cases the write is ignored, the interrupt is asserted (unless masked) and the error bit and error_type fields are set in the Job Ring Interrupt Status Register. 0xA IRSA_GT_IRS_ERR Writing IRSA > IRS 0xB ORWI_GT_ORS_ERR Writing ORWI > ORS in bytes 0xC IRRI_GT_IRS_ERR Writing IRRI > IRS in bytes 0xD INV_IRSA_WR_ERR Writing IRSA when ring is active 0xE INV_IRRI_WR_ERR Writing IRRI when ring is active 0xF INV_ORSF_WR_ERR Writing ORSF when ring is active 0x10 INV_ORWI_WR_ERR Writing ORWI when ring is active 0x11 ERR_ORWI Output ring write index with error 16 14 read-only JRCFGR_JR3_MS Job Ring Configuration Register for Job Ring 3, most-significant half 0x40050 32 read-write 0 0xFFFFFFFF MBSI To assist with mixed Endianness platforms, this bit configures a byte swap of message data read by CAAM DMA 0 1 read-write MHWSI To assist with mixed Endianness platforms, this bit configures a halfword swap of message data read by CAAM DMA 1 1 read-write MWSI To assist with mixed Endianness platforms, this bit configures a fullword swap of message data read by CAAM DMA 2 1 read-write CBSI To assist with mixed Endianness platforms, this bit configures a byte swap of control data read by CAAM DMA 4 1 read-write CHWSI To assist with mixed Endianness platforms, this bit configures a halfword swap of control data read by CAAM DMA 5 1 read-write CWSI To assist with mixed Endianness platforms, this bit configures a fullword swap of control data read by CAAM DMA 6 1 read-write MBSO To assist with mixed Endianness platforms, this bit configures a byte swap of message data written by CAAM DMA 8 1 read-write MHWSO To assist with mixed Endianness platforms, this bit configures a halfword swap of message data written by CAAM DMA 9 1 read-write MWSO To assist with mixed Endianness platforms, this bit configures a fullword swap of message data written by CAAM DMA 10 1 read-write CBSO To assist with mixed Endianness platforms, this bit configures a byte swap of control data written by CAAM DMA 12 1 read-write CHWSO To assist with mixed Endianness platforms, this bit configures a halfword swap of control data written by CAAM DMA 13 1 read-write CWSO To assist with mixed Endianness platforms, this bit configures a fullword swap of control data written by CAAM DMA 14 1 read-write DMBS Descriptor Message Data Byte Swap (this applies only to internal message data transfers to/from DECO Descriptor Buffers) 16 1 read-write PEO Platform Endian Override - The bit is XORed with the PLEND bit in the CaCSTA Register and the other "swap" bits in the Job Ring Configuration Register to determine the AXI Master's view of memory endianness when executing Job Descriptors from this Job Ring 17 1 read-write DWSO Double Word Swap Override 18 1 read-write FAIL_MODE Fail mode control 29 1 read-write INCL_SEQ_OUT Include Sequence Out Length 30 1 read-write JRCFGR_JR3_LS Job Ring Configuration Register for Job Ring 3, least-significant half 0x40054 32 read-write 0 0xFFFFFFFF IMSK Interrupt Mask. Mask the interrupt that is associated with the particular processor. 0 1 read-write INTR_ENABLED Interrupt enabled. 0 INTR_MASKED Interrupt masked. 0x1 ICEN Interrupt Coalescing Enable. 1 1 read-write INTR_COAL_DISABLED Interrupt coalescing is disabled. If the IMSK bit is cleared, an interrupt is asserted whenever a job is written to the output ring. ICDCT is ignored. Note that if software removes one or more jobs and clears the interrupt but the output rings slots full is still greater than 0 (ORSF > 0), then the interrupt will clear but reassert on the next clock cycle. 0 INTR_COAL_ENABLED Interrupt coalescing is enabled. If the IMSK bit is cleared, an interrupt is asserted whenever the threshold number of frames is reached (ICDCT) or when the threshold timer expires (ICTT). Note that if software removes one or more jobs and clears the interrupt but the interrupt coalescing threshold is still met (ORSF >= ICDCT), then the interrupt will clear but reassert on the next clock cycle. 0x1 ICDCT Interrupt Coalescing Descriptor Count Threshold 8 8 read-write ICTT Interrupt Coalescing Timer Threshold 16 16 read-write IRRIR_JR3 Input Ring Read Index Register for Job Ring 3 0x4005C 32 read-write 0 0xFFFFFFFF IRRI Input Ring Read Index. 0 13 read-write ORWIR_JR3 Output Ring Write Index Register for Job Ring 3 0x40064 32 read-write 0 0xFFFFFFFF ORWI Output Ring Write Index. The pointer to the next entry in the output ring. 0 14 read-write JRCR_JR3 Job Ring Command Register for Job Ring 3 0x4006C 32 write-only 0 0xFFFFFFFF RESET Reset - When RESET is 0, software writes a 1 to RESET to request a flush of the Job Ring 0 1 write-only PARK Park - When PARK is 0, software writes a 1 to PARK to request that the Job Ring be "parked", i 1 1 write-only JR3AAV Job Ring 3 Address-Array Valid Register 0x40704 32 read-only 0 0xFFFFFFFF V0 Valid 0 0 1 read-only V1 Valid 1 1 1 read-only V2 Valid 2 2 1 read-only V3 Valid 3 3 1 read-only BC Been Changed 31 1 read-only JR3AAA0 Job Ring 3 Address-Array Address 0 Register 0x40800 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR3AAA1 Job Ring 3 Address-Array Address 1 Register 0x40808 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR3AAA2 Job Ring 3 Address-Array Address 2 Register 0x40810 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only JR3AAA3 Job Ring 3 Address-Array Address 3 Register 0x40818 64 read-only 0 0xFFFFFFFFFFFFFFFF JD_ADDR Job Descriptor Address. 0 36 read-only P0SDID_JR3 Partition 0 SDID register 0x40A00 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P0SMAPR_JR3 Secure Memory Access Permissions register 0x40A04 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P0SMAG2_JR3 Secure Memory Access Group Registers 0x40A08 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P0SMAG1_JR3 Secure Memory Access Group Registers 0x40A0C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P1SDID_JR3 Partition 1 SDID register 0x40A10 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P1SMAPR_JR3 Secure Memory Access Permissions register 0x40A14 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P1SMAG2_JR3 Secure Memory Access Group Registers 0x40A18 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P1SMAG1_JR3 Secure Memory Access Group Registers 0x40A1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P2SDID_JR3 Partition 2 SDID register 0x40A20 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P2SMAPR_JR3 Secure Memory Access Permissions register 0x40A24 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P2SMAG2_JR3 Secure Memory Access Group Registers 0x40A28 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P2SMAG1_JR3 Secure Memory Access Group Registers 0x40A2C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P3SDID_JR3 Partition 3 SDID register 0x40A30 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P3SMAPR_JR3 Secure Memory Access Permissions register 0x40A34 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P3SMAG2_JR3 Secure Memory Access Group Registers 0x40A38 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P3SMAG1_JR3 Secure Memory Access Group Registers 0x40A3C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P4SDID_JR3 Partition 4 SDID register 0x40A40 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P4SMAPR_JR3 Secure Memory Access Permissions register 0x40A44 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P4SMAG2_JR3 Secure Memory Access Group Registers 0x40A48 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P4SMAG1_JR3 Secure Memory Access Group Registers 0x40A4C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P5SDID_JR3 Partition 5 SDID register 0x40A50 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P5SMAPR_JR3 Secure Memory Access Permissions register 0x40A54 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P5SMAG2_JR3 Secure Memory Access Group Registers 0x40A58 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P5SMAG1_JR3 Secure Memory Access Group Registers 0x40A5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P6SDID_JR3 Partition 6 SDID register 0x40A60 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P6SMAPR_JR3 Secure Memory Access Permissions register 0x40A64 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P6SMAG2_JR3 Secure Memory Access Group Registers 0x40A68 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P6SMAG1_JR3 Secure Memory Access Group Registers 0x40A6C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P7SDID_JR3 Partition 7 SDID register 0x40A70 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P7SMAPR_JR3 Secure Memory Access Permissions register 0x40A74 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P7SMAG2_JR3 Secure Memory Access Group Registers 0x40A78 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P7SMAG1_JR3 Secure Memory Access Group Registers 0x40A7C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P8SDID_JR3 Partition 8 SDID register 0x40A80 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P8SMAPR_JR3 Secure Memory Access Permissions register 0x40A84 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P8SMAG2_JR3 Secure Memory Access Group Registers 0x40A88 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P8SMAG1_JR3 Secure Memory Access Group Registers 0x40A8C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P9SDID_JR3 Partition 9 SDID register 0x40A90 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P9SMAPR_JR3 Secure Memory Access Permissions register 0x40A94 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P9SMAG2_JR3 Secure Memory Access Group Registers 0x40A98 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P9SMAG1_JR3 Secure Memory Access Group Registers 0x40A9C 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P10SDID_JR3 Partition 10 SDID register 0x40AA0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P10SMAPR_JR3 Secure Memory Access Permissions register 0x40AA4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P10SMAG2_JR3 Secure Memory Access Group Registers 0x40AA8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P10SMAG1_JR3 Secure Memory Access Group Registers 0x40AAC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P11SDID_JR3 Partition 11 SDID register 0x40AB0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P11SMAPR_JR3 Secure Memory Access Permissions register 0x40AB4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P11SMAG2_JR3 Secure Memory Access Group Registers 0x40AB8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P11SMAG1_JR3 Secure Memory Access Group Registers 0x40ABC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P12SDID_JR3 Partition 12 SDID register 0x40AC0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P12SMAPR_JR3 Secure Memory Access Permissions register 0x40AC4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P12SMAG2_JR3 Secure Memory Access Group Registers 0x40AC8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P12SMAG1_JR3 Secure Memory Access Group Registers 0x40ACC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P13SDID_JR3 Partition 13 SDID register 0x40AD0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P13SMAPR_JR3 Secure Memory Access Permissions register 0x40AD4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P13SMAG2_JR3 Secure Memory Access Group Registers 0x40AD8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P13SMAG1_JR3 Secure Memory Access Group Registers 0x40ADC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P14SDID_JR3 Partition 14 SDID register 0x40AE0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P14SMAPR_JR3 Secure Memory Access Permissions register 0x40AE4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P14SMAG2_JR3 Secure Memory Access Group Registers 0x40AE8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P14SMAG1_JR3 Secure Memory Access Group Registers 0x40AEC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P15SDID_JR3 Partition 15 SDID register 0x40AF0 32 read-only 0 0xFFFFFFFF SDID Security Domain Identifier 0 16 read-only P15SMAPR_JR3 Secure Memory Access Permissions register 0x40AF4 32 read-write 0xFF 0xFFFFFFFF G1_READ Access Group 1 Read 0 1 read-write G1_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_WRITE Access Group 1 Write 1 1 read-write G1_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1). 0 G1_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). 0x1 G1_TDO Access Group 1 Trusted Descriptor Override 2 1 read-write G1_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G1_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB, G1_WRITE and G1_READ settings. 0x1 G1_SMBLOB Access Group 1 Secure Memory Blobs 3 1 read-write G1_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1. 0 G1_SM_B_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. 0x1 G2_READ Access Group 2 Read 4 1 read-write G2_READ_PROHIB Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_READ_ALLOWED Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_WRITE Access Group 2 Write 5 1 read-write G2_WRITE_PROHIB Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1). 0 G2_WRITE_ALLOWED Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). 0x1 G2_TDO Access Group 2 Trusted Descriptor Override 6 1 read-write G2_TD_PRIVILEGE_AS_JD Trusted Descriptors have the same access privileges as Job Descriptors 0 G2_TD_OVERIDE_ALLOWED Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB, G2_WRITE and G2_READ settings. 0x1 G2_SMBLOB Access Group 2 Secure Memory Blobs 7 1 read-write G2_SM_BLOB_EXPORT_IMPORT_PROHIB Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1. 0 G2_SM_BLOB_EXPORT_IMPORT_ALLOWED Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. 0x1 SMAG_LCK SMAG LOCK bit 12 1 read-write SMAG_UNLOCKED The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers. 0 SMAG_LOCKED The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed until the partition is de-allocated or a POR occurs. 0x1 SMAP_LCK SMAP LOCK bit 13 1 read-write SMAP_UNLOCKED The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register. 0 SMAP_LOCKED The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. 0x1 PSP Public Security Parameters 14 1 read-write NOT_DEALLOCATABLE The partition and any of the pages allocated to the partition can be de-allocated. 0 DEALLOCATABLE The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. 0x1 CSP Critical Security Parameters 15 1 read-write NOT_ZEROIZED The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is released or a security alarm occurs. 0 ZEROIZED The pages allocated to the partition will be zeroized when they are individually de-allocated or the partition is released or a security alarm occurs. 0x1 PARTITION_KMOD The value in this field is used to modify the Blob Key Encryption Key when exporting cryptographic Blobs from, or importing cryptographic Blobs to, this partition 16 16 read-write P15SMAG2_JR3 Secure Memory Access Group Registers 0x40AF8 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write P15SMAG1_JR3 Secure Memory Access Group Registers 0x40AFC 32 read-write 0xFFFFFFFF 0xFFFFFFFF Gx_ID00 Bit set to 1 indicates SecureWorld DID 00 is a member of Access Group x. 0 1 read-write Gx_ID01 Bit set to 1 indicates SecureWorld DID 01 is a member of Access Group x. 1 1 read-write Gx_ID02 Bit set to 1 indicates SecureWorld DID 02 is a member of Access Group x (1 or 2). 2 1 read-write Gx_ID03 Bit set to 1 indicates SecureWorld DID 03 is a member of Access Group x (1 or 2). 3 1 read-write Gx_ID04 Bit set to 1 indicates SecureWorld DID 04 is a member of Access Group x (1 or 2). 4 1 read-write Gx_ID05 Bit set to 1 indicates SecureWorld DID 05 is a member of Access Group x (1 or 2). 5 1 read-write Gx_ID06 Bit set to 1 indicates SecureWorld DID 06 is a member of Access Group x (1 or 2). 6 1 read-write Gx_ID07 Bit set to 1 indicates SecureWorld DID 07 is a member of Access Group x (1 or 2). 7 1 read-write Gx_ID08 Bit set to 1 indicates SecureWorld DID 08 is a member of Access Group x (1 or 2). 8 1 read-write Gx_ID09 Bit set to 1 indicates SecureWorld DID 09 is a member of Access Group x (1 or 2). 9 1 read-write Gx_ID10 Bit set to 1 indicates SecureWorld DID 10 is a member of Access Group x (1 or 2). 10 1 read-write Gx_ID11 Bit set to 1 indicates SecureWorld DID 11 is a member of Access Group x (1 or 2). 11 1 read-write Gx_ID12 Bit set to 1 indicates SecureWorld DID 12 is a member of Access Group x (1 or 2). 12 1 read-write Gx_ID13 Bit set to 1 indicates SecureWorld DID 13 is a member of Access Group x (1 or 2). 13 1 read-write Gx_ID14 Bit set to 1 indicates SecureWorld DID 14 is a member of Access Group x (1 or 2). 14 1 read-write Gx_ID15 Bit set to 1 indicates SecureWorld DID 15 is a member of Access Group x (1 or 2). 15 1 read-write Gx_ID16 Bit set to 1 indicates NonSecureWorld DID 00 is a member of Access Group x (1 or 2). 16 1 read-write Gx_ID17 Bit set to 1 indicates NonSecureWorld DID 01 is a member of Access Group x (1 or 2). 17 1 read-write Gx_ID18 Bit set to 1 indicates NonSecureWorld DID 02 is a member of Access Group x (1 or 2). 18 1 read-write Gx_ID19 Bit set to 1 indicates NonSecureWorld DID 03 is a member of Access Group x (1 or 2). 19 1 read-write Gx_ID20 Bit set to 1 indicates NonSecureWorld DID 04 is a member of Access Group x (1 or 2). 20 1 read-write Gx_ID21 Bit set to 1 indicates NonSecureWorld DID 05 is a member of Access Group x (1 or 2). 21 1 read-write Gx_ID22 Bit set to 1 indicates NonSecureWorld DID 06 is a member of Access Group x (1 or 2). 22 1 read-write Gx_ID23 Bit set to 1 indicates NonSecureWorld DID 07 is a member of Access Group x (1 or 2). 23 1 read-write Gx_ID24 Bit set to 1 indicates NonSecureWorld DID 08 is a member of Access Group x (1 or 2). 24 1 read-write Gx_ID25 Bit set to 1 indicates NonSecureWorld DID 09 is a member of Access Group x (1 or 2). 25 1 read-write Gx_ID26 Bit set to 1 indicates NonSecureWorld DID 10 is a member of Access Group x (1 or 2). 26 1 read-write Gx_ID27 Bit set to 1 indicates NonSecureWorld DID 11 is a member of Access Group x (1 or 2). 27 1 read-write Gx_ID28 Bit set to 1 indicates NonSecureWorld DID 12 is a member of Access Group x (1 or 2). 28 1 read-write Gx_ID29 Bit set to 1 indicates NonSecureWorld DID 13 is a member of Access Group x (1 or 2). 29 1 read-write Gx_ID30 Bit set to 1 indicates NonSecureWorld DID 14 is a member of Access Group x (1 or 2). 30 1 read-write Gx_ID31 Bit set to 1 indicates NonSecureWorld DID 15 is a member of Access Group x (1 or 2). 31 1 read-write SMCR_JR3 Secure Memory Command Register 0x40BE4 32 write-only 0 0xFFFFFFFF CMD Command: 1h: Allocate Page - This command allocates the page specified in the PAGE field to the partition specified in the PRTN field 0 4 write-only PRTN Partition: When an Allocate Page or De-allocate Partition command is issued, the action is performed on the partition indicated in the PRTN field 8 4 write-only PAGE This is the number of the page to be referenced in field CMD 16 16 write-only SMCSR_JR3 Secure Memory Command Status Register 0x40BEC 32 read-only 0 0xFFFFFFFF PRTN Following a Page Inquiry Command, if the PO field is 10 or 11, this field indicates the partition to which the page specified in the PAGE field is allocated 0 4 read-only PO Page Owner: Following a Page Inquiry Command, this field indicates if the Page is owned by the entity that issued the inquiry, owned by another entity, or unowned 6 2 read-only AVAILABLE Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No zeroization is needed since it has already been cleared, therefore no interrupt should be expected. 0 NOT_PRESENT_OR_INITIALIZED Page does not exist in this version or is not initialized yet. 0x1 UNAVAILABLE Another entity owns the page. This page is unavailable to the issuer of the inquiry. 0x2 OWNED Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized upon de-allocation. 0x3 AERR Allocation Error 12 2 read-only CERR Command Error 14 2 read-only NO_ERROR No Error. 0 CMD_INCOMPLETE_ERROR Command has not yet completed. 0x1 SECURITY_FAILURE A security failure occurred. 0x2 CMD_OVERFLOW_ERROR Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous command completed. The additional command was ignored. 0x3 PAGE Page 16 12 read-only REIR0JR3 Recoverable Error Interrupt Record 0 for Job Ring 3 0x40E00 32 read-only 0 0xFFFFFFFF TYPE This field indicates the type of the recoverable error 24 2 read-only MISS If MISS=1, a second recoverable error associated with JR occurred before REIR0JR was written following a previous JR recoverable error 31 1 read-only REIR2JR3 Recoverable Error Interrupt Record 2 for Job Ring 3 0x40E08 64 read-only 0 0xFFFFFFFFFFFFFFFF ADDR Address associated with the recoverable JR error. 0 36 read-only REIR4JR3 Recoverable Error Interrupt Record 4 for Job Ring 3 0x40E10 32 read-only 0 0xFFFFFFFF ICID This field holds the ICID associated with the recoverable error. 0 11 read-only DID This field holds the DID associated with the recoverable error. 11 4 read-only AXCACHE This field holds the AXI cache control transaction attribute used for the memory access. 16 4 read-only AXPROT This field holds the AXI protection transaction attribute used for the memory access. 20 3 read-only RWB This field specifies whether the memory access was a read or write. 23 1 read-only ERR This field holds the AXI error response associated with the recoverable error. 28 2 read-only MIX This field holds the memory interface index associated with the recoverable error. 30 2 read-only REIR5JR3 Recoverable Error Interrupt Record 5 for Job Ring 3 0x40E14 32 read-only 0 0xFFFFFFFF BID This field holds the block identifier (see Internal Block ID) of the source of the AXI transaction associated with the recoverable error 16 4 read-only BNDG This field indicates whether the bus transaction associated with the recoverable error was initiating an CAAM Secure Memory blob operation 25 1 read-only TDSC This field indicates whether the bus transaction associated with the recoverable error was an attempt to assert trusted descriptor privilege when accessing an CAAM Secure Memory partition 26 1 read-only KMOD This field indicates whether the bus transaction associated with the recoverable error was an attempt to read the key modifier associated with an CAAM Secure Memory partition 27 1 read-only KEY This field indicates whether the bus transaction associated with the recoverable error was an attempted key access to CAAM Secure Memory 28 1 read-only SMA This field indicates whether the bus transaction associated with the recoverable error was an attempted access to CAAM Secure Memory 29 1 read-only RSTA RTIC Status Register 0x60004 32 read-only 0x40000 0xFFFFFFFF BSY RTIC Idle/Busy Status. When busy, the RTIC cannot be written to. 0 1 read-only IDLE RTIC Idle. 0 BUSY RTIC Busy. 0x1 HD Hash Once Operation Completed (Hash Done) 1 1 read-only BOOT_AUTH_DISABLED Boot authentication disabled 0 BOOT_AUTH_ENABLED Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode. 0x1 SV Security Violation 2 1 read-only BLOCKS_AUTHENTICATED Memory block contents authenticated. 0 BLOCKS_HASH_MISMATCH Memory block hash doesn't match reference value. 0x1 HE Hashing Error 3 1 read-only BLOCKS_AUTHENTICATED Memory block contents authenticated. 0 BLOCKS_HASH_MISMATCH Memory block hash doesn't match reference value. 0x1 MIS Memory Integrity Status 4 4 read-only VALID_OR_UNKNOWN Memory Block X is valid or state unknown 0 CORRUPTED Memory Block X has been corrupted 0x1 AE Address Error 8 4 read-only ADDR_VALID All reads by RTIC were valid. 0 ADDR_ERROR An illegal address was accessed by the RTIC 0x1 WE RTIC Watchdog Error 16 1 read-only WATCHDOG_GOING No RTIC Watchdog timer error has occurred. 0 WATCHDOG_ERROR RTIC Watchdog timer has expired prior to completing a round of hashing. 0x1 ABH All Blocks Hashed 17 1 read-only HOD Hash Once Blocks Disabled 18 1 read-only RTD Run Time Blocks Disabled 19 1 read-only CS RTIC Current State. Indicates the current state of the RTIC controller. 25 2 read-only IDLE Idle State 0 SINGLE_HASH Single Hash State 0x1 RUN_TIME Run-time State 0x2 ERROR Error State 0x3 RCMD RTIC Command Register 0x6000C 32 read-write 0 0xFFFFFFFF CINT Clear Interrupt 0 1 write-only KEEP_INTR Do not clear interrupt 0 CLEAR_INTR Clear interrupt. This bit cannot be modified during run-time checking mode 0x1 HO Hash once 1 1 write-only BOOT_AUTH_DISABLED Boot authentication disabled 0 BOOT_AUTH_ENABLED Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode. 0x1 RTC Run time check 2 1 write-only DISABLED Run-time checking disabled 0 CONTINOUS Verify run-time memory blocks continually 0x1 RTD Run Time Disable 3 1 read-write ENABLED Allow Run Time Mode 0 DISABLED Prevent Run Time Mode 0x1 RCTL RTIC Control Register 0x60014 32 read-write 0 0xFFFFFFFF IE Interrupt Enable 0 1 read-write DISABLED Interrupts disabled 0 ENABLED Interrupts enabled 0x1 RREQS RTIC Request Size 1 3 read-write HOME Hash Once Memory Enable 4 4 read-write RTME Run Time Memory Enable 8 4 read-write RTMU Run Time Memory Unlock 12 4 read-write RALG RTIC Algorithm Select 16 4 read-write RIDLE RTIC setting for the IPG_IDLE signal 20 1 read-write RTHR RTIC Throttle Register 0x6001C 32 read-write 0 0xFFFFFFFF RTHR Run Time Mode DMA Throttle 0 16 read-write RWDOG RTIC Watchdog Timer 0x60028 64 read-write 0 0xFFFFFFFFFFFFFFFF RWDOG Run Time Watchdog Time-Out value 0 32 read-write REND RTIC Endian Register 0x60034 32 read-write 0 0xFFFFFFFF REPO RTIC Endian Platform Override 0 4 read-write BYTE_SWAP_BLOCK_A Byte Swap Memory Block A #xxx1 RBS RTIC Byte Swap 4 4 read-write BYTE_SWAP_BLOCK_A Byte Swap Memory Block A #xxx1 RHWS RTIC Half-Word Swap 8 4 read-write HALFWORD_SWAP_BLOCK_A Half-Word Swap Memory Block A #xxx1 RWS RTIC Word Swap 12 4 read-write WORD_SWAP_BLOCK_A Word Swap Memory Block A #xxx1 REIR0RTIC Recoverable Error Interrupt Record 0 for RTIC 0x60E00 32 read-only 0 0xFFFFFFFF TYPE This field indicates the type of the recoverable error 24 2 read-only MISS If MISS=1, a second recoverable error associated with RTIC occurred before REIR0RTIC was written following a previous RTIC recoverable error 31 1 read-only REIR2RTIC Recoverable Error Interrupt Record 2 for RTIC 0x60E08 64 read-only 0 0xFFFFFFFFFFFFFFFF ADDR This register holds the address associated with the recoverable RTIC error. 0 64 read-only REIR4RTIC Recoverable Error Interrupt Record 4 for RTIC 0x60E10 32 read-only 0 0xFFFFFFFF ICID This field holds the ICID associated with the recoverable error. 0 11 read-only DID This field holds the DID associated with the recoverable error. 11 4 read-only AXCACHE This field holds the AXI cache control transaction attribute used for the memory access. 16 4 read-only AXPROT This field holds the AXI protection transaction attribute used for the memory access. 20 3 read-only RWB This field specifies whether the memory access was a read or write. 23 1 read-only ERR This field holds the AXI error response associated with the recoverable error. 28 2 read-only MIX This field holds the memory interface index associated with the recoverable error. 30 2 read-only REIR5RTIC Recoverable Error Interrupt Record 5 for RTIC 0x60E14 32 read-only 0 0xFFFFFFFF BID This field holds the block identifier (see Internal Block ID) of the source of the AXI transaction associated with the recoverable error 16 4 read-only SAFE SAFE indicates whether the AXI transaction associated with the recoverable error was a "safe" transaction 24 1 read-only SMA This field indicates whether the bus transaction associated with the recoverable error was an attempted access to CAAM Secure Memory 25 1 read-only C0C1MR CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms C1MR_RNG 0x80004 32 read-write 0 0xFFFFFFFF ENC Encrypt/Decrypt 0 1 read-write DECRYPT Decrypt. 0 ENCRYPT Encrypt. 0x1 ICV_TEST ICV Checking / Test AESA fault detection 1 1 read-write AS Algorithm State 2 2 read-write UPDATE Update 0 INITIALIZE Initialize 0x1 FINALIZE Finalize 0x2 INIT_FINAL Initialize/Finalize 0x3 AAI Additional Algorithm information 4 9 read-write ALG Algorithm. This field specifies which algorithm is being selected. 16 8 read-write AES AES 0x10 DES DES 0x20 DES_3 3DES 0x21 RNG RNG 0x50 C0C1MR_PK CCB 0 Class 1 Mode Register Format for Public Key Algorithms C1MR_RNG 0x80004 32 read-write 0 0xFFFFFFFF PKHA_MODE_LS PKHA_MODE least significant 12 bits 0 12 read-write PKHA_MODE_MS PKHA_MODE most-significant 4 bits 16 4 read-write C0C1MR_RNG CCB 0 Class 1 Mode Register Format for RNG4 C1MR_RNG 0x80004 32 read-write 0 0xFFFFFFFF TST Test Mode Request 0 1 read-write PR Prediction Resistance 1 1 read-write AS Algorithm State 2 2 read-write SH State Handle 4 2 read-write SH0 State Handle 0 0 SH1 State Handle 1 0x1 NZB NonZero bytes 8 1 read-write ZERO_BYTES_OK Generate random data with all-zero bytes permitted. 0 NO_ZERO_BYTES Generate random data without any all-zero bytes. 0x1 OBP Odd Byte Parity 9 1 read-write NOT_ODD_BYTE_PARITY No odd byte parity. 0 ODD_BYTE_PARITY Generate random data with odd byte parity. 0x1 PS Personalization String Included 10 1 read-write NO_PS_STRING No personalization string is included. 0 PS_STRING_INCL A personalization string is included. 0x1 AI Additional Input Included 11 1 read-write NO_ADDL_INPUT No additional entropy input has been provided. 0 ADDL_INPUT Additional entropy input has been provided. 0x1 SK Secure Key 12 1 read-write RNG_DEST_SPECD_BY_FIFO_STORE The destination for the RNG data is specified by the FIFO STORE command. 0 RNG_DATA_TO_KEKR The RNG data will go to the JDKEKR, TDKEKR and DSKR. 0x1 ALG Algorithm. This field specifies which algorithm is being selected. 16 8 read-write RNG RNG 0x50 C0C1KSR CCB 0 Class 1 Key Size Register 0x8000C 32 read-write 0 0xFFFFFFFF C1KS Class 1 Key Size. This is the size of a Class 1 Key measured in bytes 0 7 read-write C0C1DSR CCB 0 Class 1 Data Size Register 0x80010 64 read-write 0 0xFFFFFFFFFFFFFFFF C1DS Class 1 Data Size 0 32 read-write C1CY Class 1 Data Size Carry 32 1 read-only NO_C1DS_CARRY No carry out of the C1 Data Size Reg. 0 C1DS_CARRY There was a carry out of the C1 Data Size Reg. 0x1 NUMBITS Class 1 Data Size Number of bits 61 3 read-only C0C1ICVSR CCB 0 Class 1 ICV Size Register 0x8001C 32 read-write 0 0xFFFFFFFF C1ICVS Class 1 ICV Size, in Bytes. 0 5 read-write C0CCTRL CCB 0 CHA Control Register 0x80034 32 write-only 0 0xFFFFFFFF CCB Reset CCB 0 1 write-only DO_NOT_CCB Do Not Reset 0 RESET_CCB Reset CCB 0x1 AES Reset AESA. Writing a 1 to this bit resets the AES Accelerator. 1 1 write-only DO_NOT_RESET_AESA Do Not Reset 0 RESET_AESA Reset AES Accelerator 0x1 DES Reset DESA. Writing a 1 to this bit resets the DES Accelerator. 2 1 write-only DO_NOT_RESET_DESA Do Not Reset 0 RESET_DESA Reset DES Accelerator 0x1 PK Reset PKHA. Writing a 1 to this bit resets the Public Key Hardware Accelerator. 6 1 write-only DO_NOT_RESET_PKHA Do Not Reset 0 RESET_PKHA Reset Public Key Hardware Accelerator 0x1 MD Reset MDHA. Writing a 1 to this bit resets the Message Digest Hardware Accelerator. 7 1 write-only DO_NOT_RESET_MDHA Do Not Reset 0 RESET_MDHA Reset Message Digest Hardware Accelerator 0x1 CRC Reset CRCA. Writing a 1 to this bit resets the CRC Accelerator. 8 1 write-only DO_NOT_RESET_CRCA Do Not Reset 0 RESET_CRCA Reset CRC Accelerator 0x1 RNG Reset Random Number Generator. Writing a 1 to this bit resets the Random Number Generator. 9 1 write-only DO_NOT_RESET_RNG Do Not Reset 0 RESET_RNG Reset Random Number Generator Block. 0x1 UA0 Unload the PKHA A0 Memory 16 1 write-only DONT_UNLOAD_PKHA_A0 Don't unload the PKHA A0 Memory. 0 UNLOAD_PKHA_A0 Unload the PKHA A0 Memory into OFIFO. 0x1 UA1 Unload the PKHA A1 Memory 17 1 write-only DONT_UNLOAD_PKHA_A1 Don't unload the PKHA A1 Memory. 0 UNLOAD_PKHA_A1 Unload the PKHA A1 Memory into OFIFO. 0x1 UA2 Unload the PKHA A2 Memory 18 1 write-only DONT_UNLOAD_PKHA_A2 Don't unload the PKHA A2 Memory. 0 UNLOAD_PKHA_A2 Unload the PKHA A2 Memory into OFIFO. 0x1 UA3 Unload the PKHA A3 Memory 19 1 write-only DONT_UNLOAD_PKHA_A3 Don't unload the PKHA A3 Memory. 0 UNLOAD_PKHA_A3 Unload the PKHA A3 Memory into OFIFO. 0x1 UB0 Unload the PKHA B0 Memory 20 1 write-only DONT_UNLOAD_PKHA_B0 Don't unload the PKHA B0 Memory. 0 UNLOAD_PKHA_B0 Unload the PKHA B0 Memory into OFIFO. 0x1 UB1 Unload the PKHA B1 Memory 21 1 write-only DONT_UNLOAD_PKHA_B1 Don't unload the PKHA B1 Memory. 0 UNLOAD_PKHA_B1 Unload the PKHA B1 Memory into OFIFO. 0x1 UB2 Unload the PKHA B2 Memory 22 1 write-only DONT_UNLOAD_PKHA_B2 Don't unload the PKHA B2 Memory. 0 UNLOAD_PKHA_B2 Unload the PKHA B2 Memory into OFIFO. 0x1 UB3 Unload the PKHA B3 Memory 23 1 write-only DONT_UNLOAD_PKHA_B3 Don't unload the PKHA B3 Memory. 0 UNLOAD_PKHA_B3 Unload the PKHA B3 Memory into OFIFO. 0x1 UN Unload the PKHA N Memory 24 1 write-only DONT_UNLOAD_PKHA_N Don't unload the PKHA N Memory. 0 UNLOAD_PKHA_N Unload the PKHA N Memory into OFIFO. 0x1 UA Unload the PKHA A Memory 26 1 write-only DONT_UNLOAD_PKHA_A Don't unload the PKHA A Memory. 0 UNLOAD_PKHA_A Unload the PKHA A Memory into OFIFO. 0x1 UB Unload the PKHA B Memory 27 1 write-only DONT_UNLOAD_PKHA_B Don't unload the PKHA B Memory. 0 UNLOAD_PKHA_B Unload the PKHA B Memory into OFIFO. 0x1 C0ICTL CCB 0 Interrupt Control Register 0x8003C 32 read-write 0 0xFFFFFFFF ADI AESA done interrupt 1 1 read-write oneToClear DDI DESA done interrupt 2 1 read-write oneToClear PDI PKHA (Public Key) done interrupt 6 1 read-write oneToClear MDI MDHA (hashing) done interrupt 7 1 read-write oneToClear CDI CRCA done interrupt 8 1 read-write oneToClear RNDI RNG done interrupt 9 1 read-write oneToClear AEI AESA Error Interrupt asserted. 17 1 read-only NO_AESA_ERROR No AESA error detected 0 AESA_ERROR AESA error detected 0x1 DEI DESA Error Interrupt asserted. 18 1 read-only NO_DESA_ERROR No DESA error detected 0 DESA_ERROR DESA error detected 0x1 PEI PKHA (Public Key) Error Interrupt asserted. 22 1 read-only NO_PKHA_ERROR No PKHA error detected 0 PKHA_ERROR PKHA error detected 0x1 MEI MDHA (hashing) Error Interrupt asserted. 23 1 read-only NO_MDHA_ERROR No MDHA error detected 0 MDHA_ERROR MDHA error detected 0x1 CEI CRCA Error Interrupt asserted. 24 1 read-only NO_CRCA_ERROR No CRCA error detected 0 CRCA_ERROR CRCA error detected 0x1 RNEI RNG Error Interrupt asserted. 25 1 read-only NO_RNG_ERROR No RNG error detected 0 RNG_ERROR RNG error detected 0x1 C0CWR CCB 0 Clear Written Register 0x80044 32 write-only 0 0xFFFFFFFF C1M Clear the Class 1 Mode Register 0 1 write-only DONT_CLEAR_C1_MODE Don't clear the Class 1 Mode Register. 0 CLEAR_C1_MODE Clear the Class 1 Mode Register. 0x1 C1DS Clear the Class 1 Data Size Register 2 1 write-only DONT_CLEAR_C1_DATA_SIZE Don't clear the Class 1 Data Size Register. 0 CLEAR_C1_DATA_SIZE Clear the Class 1 Data Size Register. 0x1 C1ICV Clear the Class 1 ICV Size Register 3 1 write-only DONT_CLEAR_C1_ICV_SIZE Don't clear the Class 1 ICV Size Register. 0 CLEAR_C1_ICV_SIZE Clear the Class 1 ICV Size Register. 0x1 C1C Clear the Class 1 Context Register 5 1 write-only DONT_CLEAR_C1_CTXR Don't clear the Class 1 Context Register. 0 CLEAR_C1_CTXR Clear the Class 1 Context Register. 0x1 C1K Clear the Class 1 Key Register 6 1 write-only DONT_CLEAR_C1_KEYR Don't clear the Class 1 Key Register. 0 CLEAR_C1_KEYR Clear the Class 1 Key Register. 0x1 CPKA Clear the PKHA A Size Register 12 1 write-only DONT_CLEAR_PKHA_A_SIZE Don't clear the PKHA A Size Register. 0 CLEAR_PKHA_A_SIZE Clear the PKHA A Size Register. 0x1 CPKB Clear the PKHA B Size Register 13 1 write-only DONT_CLEAR_PKHA_B_SIZE Don't clear the PKHA B Size Register. 0 CLEAR_PKHA_B_SIZE Clear the PKHA B Size Register. 0x1 CPKN Clear the PKHA N Size Register 14 1 write-only DONT_CLEAR_PKHA_N_SIZE Don't clear the PKHA N Size Register. 0 CLEAR_PKHA_N_SIZE Clear the PKHA N Size Register. 0x1 CPKE Clear the PKHA E Size Register 15 1 write-only DONT_CLEAR_PKHA_E_SIZE Don't clear the PKHA E Size Register.. 0 CLEAR_PKHA_E_SIZE Clear the PKHA E Size Register. 0x1 C2M Clear the Class 2 Mode Register 16 1 write-only DONT_CLEAR_C2_MODE Don't clear the Class 2 Mode Register. 0 CLEAR_C2_MODE Clear the Class 2 Mode Register. 0x1 C2DS Clear the Class 2 Data Size Registers 18 1 write-only DONT_CLEAR_C2_DATA_SIZE Don't clear the Class 2 Data Size Register. 0 CLEAR_C2_DATA_SIZE Clear the Class 2 Data Size Register. 0x1 C2C Clear the Class 2 Context Register 21 1 write-only DONT_CLEAR_C2_CTXR Don't clear the Class 2 Context Register. 0 CLEAR_C2_CTXR Clear the Class 2 Context Register. 0x1 C2K Clear the Class 2 Key Register 22 1 write-only DONT_CLEAR_C2_KEYR Don't clear the Class 2 Key Register. 0 CLEAR_C2_KEYR Clear the Class 2 Key Register. 0x1 CDS Clear Descriptor Sharing signal 25 1 write-only DONT_CLEAR_SD_SIGNAL Don't clear the shared descriptor signal. 0 CLEAR_SD_SIGNAL Clear the shared descriptor signal. 0x1 C2D Clear Class 2 Done Interrupt. Writing a 1 to this bit clears the Class 2 done interrupt. 26 1 write-only DONT_CLEAR_C2_DONE_INT Don't clear the Class 2 done interrrupt. 0 CLEAR_C2_DONE_INT Clear the Class 2 done interrrupt. 0x1 C1D Clear Class 1 Done Interrupt. Writing a 1 to this bit clears the Class 1 done interrupt. 27 1 write-only DONT_CLEAR_C1_DONE_INT Don't clear the Class 1 done interrrupt. 0 CLEAR_C1_DONE_INT Clear the Class 1 done interrrupt. 0x1 C2RST Reset Class 2 CHA 28 1 write-only DONT_RESET_C2_CHA Don't reset the Class 2 CHA. 0 RESET_C2_CHA Reset the Class 2 CHA. 0x1 C1RST Reset Class 1 CHA 29 1 write-only DONT_RESET_C1_CHA Don't reset the Class 1 CHA. 0 RESET_C1_CHA Reset the Class 1 CHA. 0x1 COF Clear Output FIFO. Writing a 1 to this bit causes the Output FIFO to be cleared. 30 1 write-only DONT_CLEAR_OFIFO Don't clear the OFIFO. 0 CLEAR_OFIFO Clear the OFIFO. 0x1 CIF Clear Input FIFO (and NFIFO) 31 1 write-only DONT_CLEAR_IFIFO Don't clear the IFIFO. 0 CLEAR_IFIFO Clear the IFIFO. 0x1 C0CSTA_MS CCB 0 Status and Error Register, most-significant half 0x80048 32 read-only 0 0xFFFFFFFF ERRID1 Error ID 1 0 4 read-only MODE_ERROR Mode Error 0x1 DATA_SIZE_ERROR Data Size Error, including PKHA N Memory Size Error 0x2 KEY_SIZE_ERROR Key Size Error, including PKHA E Memory Size Error 0x3 PKHA_A_SIZE_ERROR PKHA A Memory Size Error 0x4 PKHA_B_SIZE_ERROR PKHA B Memory Size Error 0x5 OUT_OF_SEQ_ERROR Data Arrived out of Sequence Error 0x6 DIVIDE_BY_0_ERROR PKHA Divide by Zero Error 0x7 MOD_EVEN_ERROR PKHA Modulus Even Error 0x8 DES_KEY_PARITY_ERROR DES Key Parity Error 0x9 ICV_CHECK_FAILED_ERROR ICV Check Failed 0xA INTERNAL_HW_FAIL Internal Hardware Failure 0xB CCM_AAD_SISE_ERROR CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and AAD provided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.) 0xC C1_CHA_NOT_RESET_ERROR Class 1 CHA is not reset 0xD INVALID_CHA_COMBO_ERROR Invalid CHA combination was selected 0xE INVALID_CHA_SELECTED_ERROR Invalid CHA Selected 0xF CL1 Class 1 algorithms 12 4 read-only AES AES 0x1 DES DES 0x2 RNG RNG 0x5 PK Public Key 0x8 ERRID2 Error ID 2 16 4 read-only MODE_ERROR Mode Error 0x1 DATA_SIZE_ERROR Data Size Error 0x2 KEY_SIZE_ERROR Key Size Error 0x3 DATA_OUT_OF_SEQ_ERROR Data Arrived out of Sequence Error 0x6 ICV_CHECK_ERROR ICV Check Failed 0xA INTERNAL_HW_ERROR Internal Hardware Failure 0xB INVALID_CHA_COMBO_ERROR Invalid CHA combination was selected. 0xE INVALID_CHA_SELECT_ERROR Invalid CHA Selected 0xF CL2 Class 2 Algorithms 28 4 read-only MD MD5, SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 and SHA-512/224, SHA-512/256 0x4 CRC CRC 0x9 C0CSTA_LS CCB 0 Status and Error Register, least-significant half 0x8004C 32 read-only 0 0xFFFFFFFF AB AESA Busy 1 1 read-only AESA_IDLE AESA Idle 0 AESA_BUSY AESA Busy 0x1 DB DESA Busy 2 1 read-only DESA_IDLE DESA Idle 0 DESA_BUSY DESA Busy 0x1 PB PKHA Busy 6 1 read-only PKHA_IDLE PKHA Idle 0 PKHA_BUSY PKHA Busy 0x1 MB MDHA Busy 7 1 read-only MDHA_IDLE MDHA Idle 0 MDHA_BUSY MDHA Busy 0x1 CB CRC Block Busy 8 1 read-only CRCA_IDLE CRCA Idle 0 CRCA_BUSY CRCA Busy 0x1 RNB RNG Block Busy 9 1 read-only RNG_IDLE RNG Idle 0 RNG_BUSY RNG Busy 0x1 PDI Class 1 Done Interrupt. The Class 1 Done Interrupt has been asserted. 16 1 read-only C1_NOT_DONE Not Done 0 C1_DONE_INT Done Interrupt 0x1 SDI Class 2 Done Interrupt. The Class 2 Done Interrupt has been asserted. 17 1 read-only C2_NOT_DONE Not Done 0 C2_DONE_INT Done Interrupt 0x1 PEI Class 1 Error Interrupt. The Class 1 Error Interrupt has been asserted. 20 1 read-only NO_C1_ERROR No Error 0 C1_ERROR_INT Error Interrupt 0x1 SEI Class 2 Error Interrupt. The Class 2 Error Interrupt has been asserted. 21 1 read-only NO_C2_ERROR No Error 0 C2_ERROR_INT Error Interrupt 0x1 PRM Public Key is Prime 28 1 read-only NOT_PRIME The given number is NOT prime. 0 PROBABLY_PRIME The given number is probably prime. 0x1 GCD GCD is One 29 1 read-only GCD_IS_NOT_1 The greatest common divisor of two numbers is NOT one. 0 GCD_IS_1 The greatest common divisor of two numbers is one. 0x1 PIZ Public Key Operation is Zero 30 1 read-only PK_RESULT_NONZERO The result of a Public Key operation is not zero. 0 PK_RESULT_ZERO The result of a Public Key operation is zero. 0x1 C0C1AADSZR CCB 0 Class 1 AAD Size Register 0x8005C 32 read-write 0 0xFFFFFFFF AASZ AAD size in Bytes, mod 16. 0 4 read-write C0C1IVSZR CCB 0 Class 1 IV Size Register 0x80064 32 read-write 0 0xFFFFFFFF IVSZ IV size in bytes, mod 16. 0 4 read-write C0PKASZR PKHA A Size Register 0x80084 32 read-write 0 0xFFFFFFFF PKASZ PKHA A Memory key size in bytes. 0 10 read-write C0PKBSZR PKHA B Size Register 0x8008C 32 read-write 0 0xFFFFFFFF PKBSZ PKHA B Memory key size in bytes. 0 10 read-write C0PKNSZR PKHA N Size Register 0x80094 32 read-write 0 0xFFFFFFFF PKNSZ PKHA N Memory key size in bytes. 0 10 read-write C0PKESZR PKHA E Size Register 0x8009C 32 read-write 0 0xFFFFFFFF PKESZ PKHA E Memory key size in bytes. 0 10 read-write C0C1CTXR0 CCB 0 Class 1 Context Register Word 0 0x80100 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR1 CCB 0 Class 1 Context Register Word 1 0x80104 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR2 CCB 0 Class 1 Context Register Word 2 0x80108 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR3 CCB 0 Class 1 Context Register Word 3 0x8010C 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR4 CCB 0 Class 1 Context Register Word 4 0x80110 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR5 CCB 0 Class 1 Context Register Word 5 0x80114 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR6 CCB 0 Class 1 Context Register Word 6 0x80118 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR7 CCB 0 Class 1 Context Register Word 7 0x8011C 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR8 CCB 0 Class 1 Context Register Word 8 0x80120 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR9 CCB 0 Class 1 Context Register Word 9 0x80124 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR10 CCB 0 Class 1 Context Register Word 10 0x80128 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR11 CCB 0 Class 1 Context Register Word 11 0x8012C 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR12 CCB 0 Class 1 Context Register Word 12 0x80130 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR13 CCB 0 Class 1 Context Register Word 13 0x80134 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR14 CCB 0 Class 1 Context Register Word 14 0x80138 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1CTXR15 CCB 0 Class 1 Context Register Word 15 0x8013C 32 read-write 0 0xFFFFFFFF C1CTX Class 1 Context. 0 32 read-write C0C1KR0 CCB 0 Class 1 Key Registers Word 0 0x80200 32 read-write 0 0xFFFFFFFF C1KEY Class 1 Key. 0 32 read-write C0C1KR1 CCB 0 Class 1 Key Registers Word 1 0x80204 32 read-write 0 0xFFFFFFFF C1KEY Class 1 Key. 0 32 read-write C0C1KR2 CCB 0 Class 1 Key Registers Word 2 0x80208 32 read-write 0 0xFFFFFFFF C1KEY Class 1 Key. 0 32 read-write C0C1KR3 CCB 0 Class 1 Key Registers Word 3 0x8020C 32 read-write 0 0xFFFFFFFF C1KEY Class 1 Key. 0 32 read-write C0C1KR4 CCB 0 Class 1 Key Registers Word 4 0x80210 32 read-write 0 0xFFFFFFFF C1KEY Class 1 Key. 0 32 read-write C0C1KR5 CCB 0 Class 1 Key Registers Word 5 0x80214 32 read-write 0 0xFFFFFFFF C1KEY Class 1 Key. 0 32 read-write C0C1KR6 CCB 0 Class 1 Key Registers Word 6 0x80218 32 read-write 0 0xFFFFFFFF C1KEY Class 1 Key. 0 32 read-write C0C1KR7 CCB 0 Class 1 Key Registers Word 7 0x8021C 32 read-write 0 0xFFFFFFFF C1KEY Class 1 Key. 0 32 read-write C0C2MR CCB 0 Class 2 Mode Register 0x80404 32 read-write 0 0xFFFFFFFF AP Authenticate / Protect 0 1 read-write AUTHENTICATE Authenticate 0 PROTECT Protect 0x1 ICV ICV Checking 1 1 read-write NO_COMPARISON Don't compare the calculated ICV against a received ICV. 0 COMPARISON Compare the calculated ICV against a received ICV. 0x1 AS Algorithm State 2 2 read-write UPDATE Update. 0 INITIALIZE Initialize. 0x1 FINALIZE Finalize. 0x2 INITIALIZE_FINALIZE Initialize/Finalize. 0x3 AAI Additional Algorithm information 4 9 read-write ALG Algorithm. This field specifies which algorithm has been requested for an OPERATION command. 16 8 read-write MD5 MD5 0x40 SHA_1 SHA-1 0x41 SHA_224 SHA-224 0x42 SHA_256 SHA-256 0x43 SHA_384 SHA-384 0x44 SHA_512 SHA-512 0x45 SHA_512_224 SHA-512/224 0x46 SHA_512_256 SHA-512/256 0x47 CRC CRC 0x90 C0C2KSR CCB 0 Class 2 Key Size Register 0x8040C 32 read-write 0 0xFFFFFFFF C2KS Class 2 key size in bytes. 0 8 read-write C0C2DSR CCB 0 Class 2 Data Size Register 0x80410 64 read-write 0 0xFFFFFFFFFFFFFFFF C2DS Class 2 Data Size in Bytes 0 32 read-write C2CY Class 2 Data Size Carry 32 1 read-only NO_C2DS_CARRY A write to the Class 2 Data Size Register did not cause a carry. 0 C2DS_CARRY A write to the Class 2 Data Size Register caused a carry. 0x1 NUMBITS Class 2 Data Size Number of bits 61 3 read-only C0C2ICVSZR CCB 0 Class 2 ICV Size Register 0x8041C 32 read-write 0 0xFFFFFFFF ICVSZ Class 2 ICV size (mod 8) in bytes 0 4 read-write C0C2CTXR0 CCB 0 Class 2 Context Register Word 0 0x80500 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR1 CCB 0 Class 2 Context Register Word 1 0x80504 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR2 CCB 0 Class 2 Context Register Word 2 0x80508 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR3 CCB 0 Class 2 Context Register Word 3 0x8050C 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR4 CCB 0 Class 2 Context Register Word 4 0x80510 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR5 CCB 0 Class 2 Context Register Word 5 0x80514 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR6 CCB 0 Class 2 Context Register Word 6 0x80518 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR7 CCB 0 Class 2 Context Register Word 7 0x8051C 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR8 CCB 0 Class 2 Context Register Word 8 0x80520 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR9 CCB 0 Class 2 Context Register Word 9 0x80524 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR10 CCB 0 Class 2 Context Register Word 10 0x80528 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR11 CCB 0 Class 2 Context Register Word 11 0x8052C 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR12 CCB 0 Class 2 Context Register Word 12 0x80530 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR13 CCB 0 Class 2 Context Register Word 13 0x80534 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR14 CCB 0 Class 2 Context Register Word 14 0x80538 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR15 CCB 0 Class 2 Context Register Word 15 0x8053C 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR16 CCB 0 Class 2 Context Register Word 16 0x80540 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2CTXR17 CCB 0 Class 2 Context Register Word 17 0x80544 32 read-write 0 0xFFFFFFFF C2CTXR Class 2 Context. 0 32 read-write C0C2KEYR0 CCB 0 Class 2 Key Register Word 0 0x80600 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR1 CCB 0 Class 2 Key Register Word 1 0x80604 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR2 CCB 0 Class 2 Key Register Word 2 0x80608 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR3 CCB 0 Class 2 Key Register Word 3 0x8060C 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR4 CCB 0 Class 2 Key Register Word 4 0x80610 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR5 CCB 0 Class 2 Key Register Word 5 0x80614 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR6 CCB 0 Class 2 Key Register Word 6 0x80618 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR7 CCB 0 Class 2 Key Register Word 7 0x8061C 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR8 CCB 0 Class 2 Key Register Word 8 0x80620 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR9 CCB 0 Class 2 Key Register Word 9 0x80624 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR10 CCB 0 Class 2 Key Register Word 10 0x80628 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR11 CCB 0 Class 2 Key Register Word 11 0x8062C 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR12 CCB 0 Class 2 Key Register Word 12 0x80630 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR13 CCB 0 Class 2 Key Register Word 13 0x80634 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR14 CCB 0 Class 2 Key Register Word 14 0x80638 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR15 CCB 0 Class 2 Key Register Word 15 0x8063C 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR16 CCB 0 Class 2 Key Register Word 16 0x80640 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR17 CCB 0 Class 2 Key Register Word 17 0x80644 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR18 CCB 0 Class 2 Key Register Word 18 0x80648 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR19 CCB 0 Class 2 Key Register Word 19 0x8064C 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR20 CCB 0 Class 2 Key Register Word 20 0x80650 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR21 CCB 0 Class 2 Key Register Word 21 0x80654 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR22 CCB 0 Class 2 Key Register Word 22 0x80658 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR23 CCB 0 Class 2 Key Register Word 23 0x8065C 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR24 CCB 0 Class 2 Key Register Word 24 0x80660 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR25 CCB 0 Class 2 Key Register Word 25 0x80664 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR26 CCB 0 Class 2 Key Register Word 26 0x80668 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR27 CCB 0 Class 2 Key Register Word 27 0x8066C 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR28 CCB 0 Class 2 Key Register Word 28 0x80670 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR29 CCB 0 Class 2 Key Register Word 29 0x80674 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR30 CCB 0 Class 2 Key Register Word 30 0x80678 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0C2KEYR31 CCB 0 Class 2 Key Register Word 31 0x8067C 32 read-write 0 0xFFFFFFFF C2KEY Class 2 Key. 0 32 read-write C0FIFOSTA CCB 0 FIFO Status Register 0x807C0 32 read-only 0 0xFFFFFFFF DECOOQHEAD This is the current head of the DECO Alignment Block queue located within the Output Data FIFO 0 8 read-only DMAOQHEAD This is the current head of the DMA queue located within the Output Data FIFO 8 8 read-only C2IQHEAD This is the current head of the Class 2 Alignment Block queue located within the Input Data FIFO 16 8 read-only C1IQHEAD This is the current head of the Class 1 Alignment Block queue located within the Input Data FIFO 24 8 read-only C0NFIFO CCB 0 iNformation FIFO When STYPE != 10b NFIFO2 0x807D0 32 write-only 0 0xFFFFFFFF DL Data Length 0 12 write-only AST Additional Source Types 14 1 write-only OC OFIFO Continuation - This bit causes the final word to not be popped from the Output Data FIFO. 15 1 write-only POP_OFIFO_FINAL Allow the final word to be popped from the Output Data FIFO. 0 DONT_POP_OFIFO_FINAL Don't pop the final word from the Output Data FIFO. 0x1 PTYPE Pad Type 16 3 write-only BND Boundary padding 19 1 write-only DONT_PAD Don't pad. 0 PAD_TO_BOUNDARY Pad to the next 16-byte boundary. 0x1 DTYPE Data Type 20 4 write-only STYPE Source Type 24 2 write-only FC1 Flush Class 1. Flush the remainder of the data out of the Class 1 alignment block. 26 1 write-only DONT_FLUSH_C1 Don't flush Class 1 data. 0 FLUSH_C1 Flush Class 1 data. 0x1 FC2 Flush Class 2 27 1 write-only DONT_FLUSH_C2 Don't flush Class 2 data. 0 FLUSH_C2 Flush Class 2 data. 0x1 LC1 Last Class 1 28 1 write-only NOT_LAST_C1 This is not the last Class 1 data. 0 LAST_C1 This is the last Class 1 data. 0x1 LC2 Last Class 2 29 1 write-only NOT_LAST_C2 This is not the last Class 2 data. 0 LAST_C2 This is the last Class 2 data. 0x1 DEST Destination 30 2 write-only DECO DECO Alignment Block. If DTYPE == Eh, data sent to the DECO Alignment Block is dropped. This is used to skip over input data. An error is generated if a DTYPE other than Eh (drop) or Fh (message) is used with the DECO Alignment Block destination. 0 CLASS_1 Class 1. 0x1 CLASS_2 Class 2. 0x2 CLASS_1_2 Both Class 1 and Class 2. 0x3 C0NFIFO_2 CCB 0 iNformation FIFO When STYPE == 10b NFIFO2 0x807D0 32 write-only 0 0xFFFFFFFF PL Pad Length 0 7 write-only PS Pad Snoop 10 1 write-only FROM_PAD_BLOCK C2 CHA snoops pad data from padding block. 0 FROM_OFIFO C2 CHA snoops pad data from OFIFO. 0x1 BM Boundary Minus 1 11 1 write-only BOUND_PAD_NOT_MINUS_1 When padding, pad to power-of-2 boundary. 0 BOUND_PAD_MINUS_1 When padding, pad to power-of-2 boundary minus 1 byte. 0x1 PR Prediction Resistance - If PTYPE specifies random data, setting PR=1 causes the RNG to supply random data for prediction resistance (i 15 1 write-only NO_PRED_RES No prediction resistance. 0 PRED_RES Prediction resistance. 0x1 PTYPE Pad Type 16 3 write-only ALL_0 All Zero. 0 RANDOM_NON_0 Random with nonzero bytes. 0x1 INCREMENT_START_1 Incremented (starting with 01h), followed by a byte containing the value N-1, i.e., if N==1, a single byte is output with value 0h. 0x2 RANDOM Random. 0x3 ALL_0_LAST_BYTE_NUMBER_OF_BYTES All Zero with last byte containing the number of 0 bytes, i.e., if N==1, a single byte is output with value 0h. 0x4 RANDOM_NON_0_LAST_BYTE_0 Random with nonzero bytes with last byte 0. 0x5 ALL_NUMBER_OF_BYTES_MINUS_1 N bytes of padding all containing the value N-1. 0x6 RANDOM_NON_0_LAST_BYTE_NUMBER_OF_BYTES Random with nonzero bytes, with the last byte containing the value N-1. 0x7 BND Boundary padding 19 1 write-only NO_PADDING Don't add boundary padding. 0 PADDING Add boundary padding. 0x1 DTYPE Data Type 20 4 write-only STYPE Source Type 24 2 write-only FC1 Flush Class 1. Flush the remainder of the data out of the Class 1 alignment block. 26 1 write-only DONT_FLUSH_C1 Don't flush the Class 1 data. 0 FLUSH_C1 Flush the Class 1 data. 0x1 FC2 Flush Class 2 27 1 write-only DONT_FLUSH_C2 Don't flush the Class 2 data. 0 FLUSH_C2 Flush the Class 2 data. 0x1 LC1 Last Class 1 28 1 write-only NOT_LC1_DATA This is not the last Class 1 data. 0 LC1_DATA This is the last Class 1 data. 0x1 LC2 Last Class 2 29 1 write-only NOT_LC2_DATA This is not the last Class 2 data. 0 LC2_DATA This is the last Class 2 data. 0x1 DEST Destination 30 2 write-only DECO DECO Alignment Block. If DTYPE is Eh, data sent to the DECO Alignment Block is dropped. This is used to skip over input data. An error is generated if a DTYPE other than Eh (drop) or Fh (message) is used with the DECO Alignment Block destination. 0 CLASS_1 Class 1. 0x1 CLASS_2 Class 2. 0x2 CLASS_1_2 Both Class 1 and Class 2. 0x3 C0IFIFO CCB 0 Input Data FIFO 0x807E0 32 write-only 0 0xFFFFFFFF IFIFO Input Data FIFO. 0 32 write-only C0OFIFO CCB 0 Output Data FIFO 0x807F0 64 read-only 0 0xFFFFFFFFFFFFFFFF OFIFO Output FIFO 0 64 read-only D0JQCR_MS DECO0 Job Queue Control Register, most-significant half 0x80800 32 read-write 0 0xFFFFFFFF ID Job ID 0 3 read-write SRC Job Source 8 3 read-only JR0 Job Ring 0 0 JR1 Job Ring 1 0x1 JR2 Job Ring 2 0x2 JR3 Job Ring 3 0x3 RTIC RTIC 0x4 AMTD Allow Make Trusted Descriptor 15 1 read-only AMTD_NOT_SET The Allowed Make Trusted Descriptor bit was NOT set. 0 AMTD_SET The Allowed Make Trusted Descriptor bit was set. 0x1 SOB Shared Descriptor burst 16 1 read-write SD_NOT_LOADED Shared Descriptor has NOT been loaded. 0 SD_LOADED Shared Descriptor HAS been loaded. 0x1 DWS Double word swap. Causes/allows dword swapping of addresses, and MOVE and MATH immediate values. 19 1 read-write NO_DWS Double Word Swap is NOT set. 0 DWS Double Word Swap is set. 0x1 SHR_FROM Share From 24 3 read-write ILE Immediate Little Endian 27 1 read-write NO_BYTE_SWAP No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer. 0 BYTE_SWAP Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer. 0x1 FOUR Four Words. job queue controller is passing at least 4 words of the Descriptor to DECO. 28 1 read-write NOT_FOUR_WORDS DECO has not been given at least four words of the descriptor. 0 FOUR_WORDS DECO has been given at least four words of the descriptor. 0x1 WHL Whole Descriptor 29 1 read-write NOT_WHOLE_DESC DECO has not been given the whole descriptor. 0 WHOLE_DESC DECO has been given the whole descriptor. 0x1 SING Single Step Mode 30 1 read-write NOT_SINGLE_STEP_MODE Do not tell DECO to execute the descriptor in single-step mode. 0 SINGLE_STEP_MODE Tell DECO to execute the descriptor in single-step mode. 0x1 STEP Step 31 1 read-write DONT_STEP DECO has not been told to execute the next command in the descriptor. 0 STEP DECO has been told to execute the next command in the descriptor. 0x1 D0JQCR_LS DECO0 Job Queue Control Register, least-significant half 0x80804 32 read-only 0 0xFFFFFFFF CMD Command 0 32 read-only D0DAR DECO0 Descriptor Address Register 0x80808 64 read-only 0 0xFFFFFFFFFFFFFFFF DPTR Descriptor Pointer. Memory address of the Descriptor. Needed for write-back purposes. 0 36 read-only D0OPSTA_MS DECO0 Operation Status Register, most-significant half 0x80810 32 read-only 0 0xFFFFFFFF STATUS If ERRTYP indicates no error, this field contains PKHA/Math Status, as defined below 0 8 read-only COMMAND_INDEX Command index: A pointer to a 32-bit word within the descriptor 8 7 read-only NLJ Non-Local Jump 27 1 read-only ORIGINAL_DESC The original job descriptor running in this DECO has not caused another job descriptor to be executed. 0 NON_LOCAL_DECR The original job descriptor running in this DECO has caused another job descriptor to be executed. 0x1 STATUS_TYPE Status Type 28 4 read-only NOT_AN_ERROR no error 0 DMA_ERROR DMA error 0x1 CCB_ERROR CCB error 0x2 JHALT_STATUS Jump Halt User Status 0x3 DECO_ERROR DECO error 0x4 JHALT_COND Jump Halt Condition Code 0x7 D0OPSTA_LS DECO0 Operation Status Register, least-significant half 0x80814 32 read-only 0 0xFFFFFFFF OUT_CT Output Count. Number of bytes written to sequential out pointer. 0 32 read-only D0PDIDSR DECO0 Primary DID Status Register 0x80820 32 read-only 0 0xFFFFFFFF PRIM_DID DECO Primary DID 0 4 read-only PRIM_ICID DECO Primary ICID 19 11 read-only D0ODIDSR DECO0 Output DID Status Register 0x80824 32 read-only 0 0xFFFFFFFF OUT_DID DECO Output DID 0 4 read-only OUT_ICID DECO Output ICID 19 11 read-only D0MTH0_MS DECO0 Math Register 0_MS 0x80840 32 read-write 0 0xFFFFFFFF MATH_MS MATH register, most-significant 32 bits. 0 32 read-write D0MTH0_LS DECO0 Math Register 0_LS 0x80844 32 read-write 0 0xFFFFFFFF MATH_LS MATH register, least-significant 32 bits. 0 32 read-write D0MTH1_MS DECO0 Math Register 1_MS 0x80848 32 read-write 0 0xFFFFFFFF MATH_MS MATH register, most-significant 32 bits. 0 32 read-write D0MTH1_LS DECO0 Math Register 1_LS 0x8084C 32 read-write 0 0xFFFFFFFF MATH_LS MATH register, least-significant 32 bits. 0 32 read-write D0MTH2_MS DECO0 Math Register 2_MS 0x80850 32 read-write 0 0xFFFFFFFF MATH_MS MATH register, most-significant 32 bits. 0 32 read-write D0MTH2_LS DECO0 Math Register 2_LS 0x80854 32 read-write 0 0xFFFFFFFF MATH_LS MATH register, least-significant 32 bits. 0 32 read-write D0MTH3_MS DECO0 Math Register 3_MS 0x80858 32 read-write 0 0xFFFFFFFF MATH_MS MATH register, most-significant 32 bits. 0 32 read-write D0MTH3_LS DECO0 Math Register 3_LS 0x8085C 32 read-write 0 0xFFFFFFFF MATH_LS MATH register, least-significant 32 bits. 0 32 read-write D0GTR0_0 DECO0 Gather Table Register 0 Word 0 0x80880 32 read-write 0 0xFFFFFFFF ADDRESS_POINTER most-significant bits of memory address pointed to by table entry 0 4 read-write D0GTR0_1 DECO0 Gather Table Register 0 Word 1 0x80884 32 read-write 0 0xFFFFFFFF ADDRESS_POINTER This field holds the least-significant 32 bits of the memory address to which this table entry points 0 32 read-write D0GTR0_2 DECO0 Gather Table Register 0 Word 2 0x80888 32 read-write 0 0xFFFFFFFF Length This field specifies how many bytes of data (for Gather Tables) or available space (for Scatter Tables) are located at the address pointed to by the Address Pointer 0 30 read-write F Final Bit. If set, this is the last entry of this Scatter/Gather Table. 30 1 read-write NOT_LAST This is not the last entry of the SGT. 0 LAST This is the last entry of the SGT. 0x1 E Extension bit 31 1 read-write MEM_BUFFER Address Pointer points to a memory buffer. 0 SGTE Address Pointer points to a Scatter/Gather Table Entry. 0x1 D0GTR0_3 DECO0 Gather Table Register 0 Word 3 0x8088C 32 read-write 0 0xFFFFFFFF Offset Offset (measured in bytes) into memory where significant data is to be found 0 13 read-write D0STR0_0 DECO0 Scatter Table Register 0 Word 0 0x80900 32 read-write 0 0xFFFFFFFF ADDRESS_POINTER most-significant bits of memory address pointed to by table entry 0 4 read-write D0STR0_1 DECO0 Scatter Table Register 0 Word 1 0x80904 32 read-write 0 0xFFFFFFFF ADDRESS_POINTER This field holds the least-significant 32 bits of the memory address to which this table entry points 0 32 read-write D0STR0_2 DECO0 Scatter Table Register 0 Word 2 0x80908 32 read-write 0 0xFFFFFFFF Length This field specifies how many bytes of data (for Gather Tables) or available space (for Scatter Tables) are located at the address pointed to by the Address Pointer 0 30 read-write F Final Bit. If set, this is the last entry of this Scatter/Gather Table. 30 1 read-write NOT_LAST This is not the last entry of the SGT. 0 LAST This is the last entry of the SGT. 0x1 E Extension bit 31 1 read-write MEM_BUFFER Address Pointer points to a memory buffer. 0 SGTE Address Pointer points to a Scatter/Gather Table Entry. 0x1 D0STR0_3 DECO0 Scatter Table Register 0 Word 3 0x8090C 32 read-write 0 0xFFFFFFFF Offset Offset (measured in bytes) into memory where significant data is to be found 0 13 read-write D0DESB0 DECO0 Descriptor Buffer Word 0 0x80A00 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB1 DECO0 Descriptor Buffer Word 1 0x80A04 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB2 DECO0 Descriptor Buffer Word 2 0x80A08 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB3 DECO0 Descriptor Buffer Word 3 0x80A0C 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB4 DECO0 Descriptor Buffer Word 4 0x80A10 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB5 DECO0 Descriptor Buffer Word 5 0x80A14 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB6 DECO0 Descriptor Buffer Word 6 0x80A18 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB7 DECO0 Descriptor Buffer Word 7 0x80A1C 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB8 DECO0 Descriptor Buffer Word 8 0x80A20 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB9 DECO0 Descriptor Buffer Word 9 0x80A24 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB10 DECO0 Descriptor Buffer Word 10 0x80A28 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB11 DECO0 Descriptor Buffer Word 11 0x80A2C 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB12 DECO0 Descriptor Buffer Word 12 0x80A30 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB13 DECO0 Descriptor Buffer Word 13 0x80A34 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB14 DECO0 Descriptor Buffer Word 14 0x80A38 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB15 DECO0 Descriptor Buffer Word 15 0x80A3C 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB16 DECO0 Descriptor Buffer Word 16 0x80A40 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB17 DECO0 Descriptor Buffer Word 17 0x80A44 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB18 DECO0 Descriptor Buffer Word 18 0x80A48 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB19 DECO0 Descriptor Buffer Word 19 0x80A4C 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB20 DECO0 Descriptor Buffer Word 20 0x80A50 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB21 DECO0 Descriptor Buffer Word 21 0x80A54 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB22 DECO0 Descriptor Buffer Word 22 0x80A58 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB23 DECO0 Descriptor Buffer Word 23 0x80A5C 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB24 DECO0 Descriptor Buffer Word 24 0x80A60 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB25 DECO0 Descriptor Buffer Word 25 0x80A64 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB26 DECO0 Descriptor Buffer Word 26 0x80A68 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB27 DECO0 Descriptor Buffer Word 27 0x80A6C 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB28 DECO0 Descriptor Buffer Word 28 0x80A70 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB29 DECO0 Descriptor Buffer Word 29 0x80A74 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB30 DECO0 Descriptor Buffer Word 30 0x80A78 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB31 DECO0 Descriptor Buffer Word 31 0x80A7C 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB32 DECO0 Descriptor Buffer Word 32 0x80A80 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB33 DECO0 Descriptor Buffer Word 33 0x80A84 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB34 DECO0 Descriptor Buffer Word 34 0x80A88 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB35 DECO0 Descriptor Buffer Word 35 0x80A8C 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB36 DECO0 Descriptor Buffer Word 36 0x80A90 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB37 DECO0 Descriptor Buffer Word 37 0x80A94 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB38 DECO0 Descriptor Buffer Word 38 0x80A98 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB39 DECO0 Descriptor Buffer Word 39 0x80A9C 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB40 DECO0 Descriptor Buffer Word 40 0x80AA0 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB41 DECO0 Descriptor Buffer Word 41 0x80AA4 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB42 DECO0 Descriptor Buffer Word 42 0x80AA8 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB43 DECO0 Descriptor Buffer Word 43 0x80AAC 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB44 DECO0 Descriptor Buffer Word 44 0x80AB0 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB45 DECO0 Descriptor Buffer Word 45 0x80AB4 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB46 DECO0 Descriptor Buffer Word 46 0x80AB8 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB47 DECO0 Descriptor Buffer Word 47 0x80ABC 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB48 DECO0 Descriptor Buffer Word 48 0x80AC0 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB49 DECO0 Descriptor Buffer Word 49 0x80AC4 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB50 DECO0 Descriptor Buffer Word 50 0x80AC8 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB51 DECO0 Descriptor Buffer Word 51 0x80ACC 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB52 DECO0 Descriptor Buffer Word 52 0x80AD0 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB53 DECO0 Descriptor Buffer Word 53 0x80AD4 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB54 DECO0 Descriptor Buffer Word 54 0x80AD8 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB55 DECO0 Descriptor Buffer Word 55 0x80ADC 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB56 DECO0 Descriptor Buffer Word 56 0x80AE0 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB57 DECO0 Descriptor Buffer Word 57 0x80AE4 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB58 DECO0 Descriptor Buffer Word 58 0x80AE8 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB59 DECO0 Descriptor Buffer Word 59 0x80AEC 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB60 DECO0 Descriptor Buffer Word 60 0x80AF0 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB61 DECO0 Descriptor Buffer Word 61 0x80AF4 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB62 DECO0 Descriptor Buffer Word 62 0x80AF8 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DESB63 DECO0 Descriptor Buffer Word 63 0x80AFC 32 read-write 0 0xFFFFFFFF DESBW Descriptor Buffer Word 0 32 read-write D0DJR DECO0 Debug Job Register 0x80E00 32 read-only 0 0xFFFFFFFF ID Job ID 0 3 read-only SRC Job Source 8 3 read-only JR0 Job Ring 0 0 JR1 Job Ring 1 0x1 JR2 Job Ring 2 0x2 JR3 Job Ring 3 0x3 RTIC RTIC 0x4 JDDS Job Descriptor DID Select 14 1 read-only NON_SEQ_DID Non-SEQ DID 0 SEQ_DID SEQ DID 0x1 AMTD Allow Make Trusted Descriptor 15 1 read-only AMTD_NOT_SET The Allowed Make Trusted Descriptor bit was NOT set. 0 AMTD_SET The Allowed Make Trusted Descriptor bit was set. 0x1 GSD Got Shared Descriptor 16 1 read-only DID_NOT_GET_SD Shared Descriptor was NOT obtained from another DECO. 0 GOT_SD Shared Descriptor was obtained from another DECO. 0x1 DWS Double Word Swap. Double word swapping was set. 19 1 read-only NO_DWS Double Word Swap is NOT set. 0 DWS Double Word Swap is set. 0x1 SHR_FROM Share From 24 3 read-only ILE Immediate Little Endian 27 1 read-only NO_BYTE_SWAP No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer. 0 BYTE_SWAP Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer. 0x1 FOUR Four Words 28 1 read-only NOT_FOUR_WORDS DECO has not been given at least four words of the descriptor. 0 FOUR_WORDS DECO has been given at least four words of the descriptor. 0x1 WHL Whole Descriptor 29 1 read-only NOT_WHOLE_DESC DECO has not been given the whole descriptor. 0 WHOLE_DESC DECO has been given the whole descriptor. 0x1 SING Single Step Mode 30 1 read-only NOT_SINGLE_STEP_MODE DECO has not been told to execute the descriptor in single-step mode. 0 SINGLE_STEP_MODE DECO has been told to execute the descriptor in single-step mode. 0x1 STEP Step 31 1 read-only DONT_STEP DECO has not been told to execute the next command in the descriptor. 0 STEP DECO has been told to execute the next command in the descriptor. 0x1 D0DDR DECO0 Debug DECO Register 0x80E04 32 read-only 0 0xFFFFFFFF CT Checking Trusted 0 1 read-only NOT_CHECKING This DECO is NOTcurrently generating the signature of a Trusted Descriptor. 0 CHECKING This DECO is currently generating the signature of a Trusted Descriptor. 0x1 BRB Burster Read Busy 1 1 read-only NOT_BUSY The READ machine in the Burster is not busy. 0 BUSY The READ machine in the Burster is busy. 0x1 BWB Burster Write Busy 2 1 read-only NOT_BUSY The WRITE machine in the Burster is not busy. 0 BUSY The WRITE machine in the Burster is busy. 0x1 NC No Command 3 1 read-only CMD_EXEC This DECO is currently executing a command. 0 NO_CMD_EXEC This DECO is not currently executing a command. 0x1 CSA Command Stage Aux 4 1 read-only CMD_STAGE Command Stage 5 3 read-only CMD_INDEX Command Index 8 6 read-only NLJ Took Non-local JUMP 14 1 read-only ORIGINAL_DESC The original job descriptor running in this DECO has not caused another job descriptor to be executed. 0 NON_LOCAL_DECR The original job descriptor running in this DECO has caused another job descriptor to be executed. 0x1 PTCL_RUN Protocol running. PTCL_RUN=1 indicates that a protocol is running in this DECO. 15 1 read-only NOT_RUNNING No protocol is running in this DECO. 0 RUNNING A protocol is running in this DECO. 0x1 PDB_STALL PDB Stall State 16 2 read-only PDB_WB_ST PDB Writeback State. Lower two bits of the state machine that tracks the state of PDB writebacks. 18 2 read-only DECO_STATE DECO State. The current state of DECO's main state machine. 20 4 read-only NSEQLSEL Non-SEQ DID Select. This indicates which type of DID is being used for Non-SEQ commands: 24 2 read-only SEQ_DID SEQ DID 0x1 NONSEQ_DID Non-SEQ DID 0x2 TRUSTED_DID Trusted DID 0x3 SEQLSEL SEQ DID Select. This indicates which type of DID is being used for SEQ commands: 26 2 read-only SEQ_DID SEQ DID 0x1 NONSEQ_DID Non-SEQ DID 0x2 TRUSTED_DID Trusted DID 0x3 TRCT DMA Transaction Count 28 2 read-only SD Shared Descriptor 30 1 read-only NO_SD_RCVD This DECO has not received a shared descriptor from another DECO. 0 SD_RCVD This DECO has received a shared descriptor from another DECO. 0x1 VALID Valid 31 1 read-only NO_DESC_RUNNING No descriptor is currently running in this DECO. 0 DESC_RUNNING There is currently a descriptor running in this DECO. 0x1 D0DJP DECO0 Debug Job Pointer 0x80E08 64 read-only 0 0xFFFFFFFFFFFFFFFF JDPTR Job Descriptor Pointer. 0 36 read-only D0SDP DECO0 Debug Shared Pointer 0x80E10 64 read-only 0 0xFFFFFFFFFFFFFFFF SDPTR Shared Descriptor Pointer. 0 36 read-only D0DDR_MS DECO0 Debug DID, most-significant half 0x80E18 32 read-only 0 0xFFFFFFFF PRIM_DID Primary DID 0 4 read-only PRIM_TZ Primary TZ 4 1 read-only NONSECUREWORLD TrustZone NonSecureWorld 0 SECUREWORLD TrustZone SecureWorld 0x1 PRIM_ICID Primary ICID 5 11 read-only OUT_DID Output DID 16 4 read-only OUT_ICID Output ICID 21 11 read-only D0DDR_LS DECO0 Debug DID, least-significant half 0x80E1C 32 read-only 0 0xFFFFFFFF OUT_DID DECO Output Domain Identifier 0 4 read-only OUT_ICID Output ICID 19 11 read-only SOL0 Sequence Output Length Register 0x80E20 32 read-write 0 0xFFFFFFFF SOL Output Sequence Length 0 32 read-write VSOL0 Variable Sequence Output Length Register 0x80E24 32 read-write 0 0xFFFFFFFF VSOL This value is used in variable-length output data sequences 0 32 read-write SIL0 Sequence Input Length Register 0x80E28 32 read-write 0 0xFFFFFFFF SIL This value is used in input data sequences 0 32 read-write VSIL0 Variable Sequence Input Length Register 0x80E2C 32 read-write 0 0xFFFFFFFF VSIL This value is used in variable-length input data sequences 0 32 read-write D0POVRD Protocol Override Register 0x80E30 32 read-write 0 0xFFFFFFFF DPOVRD DPOVRD can be used as a general purpose math register. 0 32 read-write UVSOL0 Variable Sequence Output Length Register; Upper 32 bits 0x80E34 32 read-write 0 0xFFFFFFFF UVSOL This value is used in variable-length output data sequences 0 32 read-write UVSIL0 Variable Sequence Input Length Register; Upper 32 bits 0x80E38 32 read-write 0 0xFFFFFFFF UVSIL This value is used in variable-length input data sequences 0 32 read-write CSI CSI CSI CSI_ 0x40800000 0 0x454 registers CSI 56 CR1 CSI Control Register 1 0 32 read-write 0x40000800 0xFFFFFFFF PIXEL_BIT Pixel Bit 0 1 read-write PIXEL_BIT_0 8-bit data for each pixel 0 PIXEL_BIT_1 10-bit data for each pixel 0x1 REDGE Valid Pixel Clock Edge Select 1 1 read-write REDGE_0 Pixel data is latched at the falling edge of CSI_PIXCLK 0 REDGE_1 Pixel data is latched at the rising edge of CSI_PIXCLK 0x1 INV_PCLK Invert Pixel Clock Input 2 1 read-write INV_PCLK_0 CSI_PIXCLK is directly applied to internal circuitry 0 INV_PCLK_1 CSI_PIXCLK is inverted before applied to internal circuitry 0x1 INV_DATA Invert Data Input. This bit enables or disables internal inverters on the data lines. 3 1 read-write INV_DATA_0 CSI_D[7:0] data lines are directly applied to internal circuitry 0 INV_DATA_1 CSI_D[7:0] data lines are inverted before applied to internal circuitry 0x1 GCLK_MODE Gated Clock Mode Enable 4 1 read-write GCLK_MODE_0 Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. 0 GCLK_MODE_1 Gated clock mode. Pixel clock signal is valid only when HSYNC is active. 0x1 CLR_RXFIFO Asynchronous RXFIFO Clear 5 1 read-write CLR_STATFIFO Asynchronous STATFIFO Clear 6 1 read-write PACK_DIR Data Packing Direction 7 1 read-write PACK_DIR_0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. 0 PACK_DIR_1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. 0x1 FCC FIFO Clear Control 8 1 read-write FCC_0 Asynchronous FIFO clear is selected. 0 FCC_1 Synchronous FIFO clear is selected. 0x1 CCIR_EN BT.656 Interface Enable. This bit selects the type of interface used. 10 1 read-write CCIR_EN_0 Traditional interface is selected. 0 CCIR_EN_1 BT.656 interface is selected. 0x1 HSYNC_POL HSYNC Polarity Select 11 1 read-write HSYNC_POL_0 HSYNC is active low 0 HSYNC_POL_1 HSYNC is active high 0x1 HISTOGRAM_CALC_DONE_IE Histogram Interrupt Enable 12 1 read-write HISTOGRAM_CALC_DONE_IE_0 Histogram done interrupt disable 0 HISTOGRAM_CALC_DONE_IE_1 Histogram done interrupt enable 0x1 SOF_INTEN Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. 16 1 read-write SOF_INTEN_0 SOF interrupt disable 0 SOF_INTEN_1 SOF interrupt enable 0x1 SOF_POL SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. 17 1 read-write SOF_POL_0 SOF interrupt is generated on SOF falling edge 0 SOF_POL_1 SOF interrupt is generated on SOF rising edge 0x1 RXFF_INTEN RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt. 18 1 read-write RXFF_INTEN_0 RxFIFO full interrupt disable 0 RXFF_INTEN_1 RxFIFO full interrupt enable 0x1 FB1_DMA_DONE_INTEN Frame Buffer1 DMA Transfer Done Interrupt Enable 19 1 read-write FB1_DMA_DONE_INTEN_0 Frame Buffer1 DMA Transfer Done interrupt disable 0 FB1_DMA_DONE_INTEN_1 Frame Buffer1 DMA Transfer Done interrupt enable 0x1 FB2_DMA_DONE_INTEN Frame Buffer2 DMA Transfer Done Interrupt Enable 20 1 read-write FB2_DMA_DONE_INTEN_0 Frame Buffer2 DMA Transfer Done interrupt disable 0 FB2_DMA_DONE_INTEN_1 Frame Buffer2 DMA Transfer Done interrupt enable 0x1 STATFF_INTEN STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt. 21 1 read-write STATFF_INTEN_0 STATFIFO full interrupt disable 0 STATFF_INTEN_1 STATFIFO full interrupt enable 0x1 SFF_DMA_DONE_INTEN STATFIFO DMA Transfer Done Interrupt Enable 22 1 read-write SFF_DMA_DONE_INTEN_0 STATFIFO DMA Transfer Done interrupt disable 0 SFF_DMA_DONE_INTEN_1 STATFIFO DMA Transfer Done interrupt enable 0x1 RF_OR_INTEN RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. 24 1 read-write RF_OR_INTEN_0 RxFIFO overrun interrupt is disabled 0 RF_OR_INTEN_1 RxFIFO overrun interrupt is enabled 0x1 SF_OR_INTEN STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt. 25 1 read-write SF_OR_INTEN_0 STATFIFO overrun interrupt is disabled 0 SF_OR_INTEN_1 STATFIFO overrun interrupt is enabled 0x1 COF_INT_EN Change Of Image Field (COF) Interrupt Enable 26 1 read-write COF_INT_EN_0 COF interrupt is disabled 0 COF_INT_EN_1 COF interrupt is enabled 0x1 VIDEO_MODE Video mode select. This bit controls the video mode in BT.656 mode and TV decoder input. 27 1 read-write VIDEO_MODE_0 Progressive mode is selected 0 VIDEO_MODE_1 Interlace mode is selected 0x1 EOF_INT_EN End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. 29 1 read-write EOF_INT_EN_0 EOF interrupt is disabled. 0 EOF_INT_EN_1 EOF interrupt is generated when RX count value is reached. 0x1 EXT_VSYNC External VSYNC Enable 30 1 read-write EXT_VSYNC_0 Internal VSYNC mode 0 EXT_VSYNC_1 External VSYNC mode 0x1 SWAP16_EN SWAP 16-Bit Enable 31 1 read-write SWAP16_EN_0 Disable swapping 0 SWAP16_EN_1 Enable swapping 0x1 CR2 CSI Control Register 2 0x4 32 read-write 0 0xFFFFFFFF HSC Horizontal Skip Count 0 8 read-write HSC_0 Number of pixels to skip minus 1 0 HSC_1 Number of pixels to skip minus 1 0x1 HSC_2 Number of pixels to skip minus 1 0x2 HSC_3 Number of pixels to skip minus 1 0x3 HSC_4 Number of pixels to skip minus 1 0x4 HSC_5 Number of pixels to skip minus 1 0x5 HSC_6 Number of pixels to skip minus 1 0x6 HSC_7 Number of pixels to skip minus 1 0x7 HSC_8 Number of pixels to skip minus 1 0x8 HSC_9 Number of pixels to skip minus 1 0x9 VSC Vertical Skip Count. Contains the number of rows to skip. SCE must be 1, otherwise VSC is ignored. 8 8 read-write VSC_0 Number of rows to skip minus 1 0 VSC_1 Number of rows to skip minus 1 0x1 VSC_2 Number of rows to skip minus 1 0x2 VSC_3 Number of rows to skip minus 1 0x3 VSC_4 Number of rows to skip minus 1 0x4 VSC_5 Number of rows to skip minus 1 0x5 VSC_6 Number of rows to skip minus 1 0x6 VSC_7 Number of rows to skip minus 1 0x7 VSC_8 Number of rows to skip minus 1 0x8 VSC_9 Number of rows to skip minus 1 0x9 LVRM Live View Resolution Mode. Selects the grid size used for live view resolution. 16 3 read-write LVRM_0 512 x 384 0 LVRM_1 448 x 336 0x1 LVRM_2 384 x 288 0x2 LVRM_3 384 x 256 0x3 LVRM_4 320 x 240 0x4 LVRM_5 288 x 216 0x5 LVRM_6 400 x 300 0x6 BTS Bayer Tile Start. Controls the Bayer pattern starting point. 19 2 read-write BTS_0 GR 0 BTS_1 RG 0x1 BTS_2 BG 0x2 BTS_3 GB 0x3 SCE Skip Count Enable 23 1 read-write SCE_0 Skip count disable 0 SCE_1 Skip count enable 0x1 AFS Auto Focus Spread. Selects which green pixels are used for auto-focus. 24 2 read-write AFS_0 Abs Diff on consecutive green pixels 0 AFS_1 Abs Diff on every third green pixels 0x1 AFS_2 Abs Diff on every four green pixels #1x DRM Double Resolution Mode. Controls size of statistics grid. 26 1 read-write DRM_0 Stats grid of 8 x 6 0 DRM_1 Stats grid of 8 x 12 0x1 DMA_BURST_TYPE_SFF Burst Type of DMA Transfer from STATFIFO. Selects the burst type of DMA transfer from STATFIFO. 28 2 read-write DMA_BURST_TYPE_SFF_0 INCR8 #x0 DMA_BURST_TYPE_SFF_1 INCR4 0x1 DMA_BURST_TYPE_SFF_3 INCR16 0x3 DMA_BURST_TYPE_RFF Burst Type of DMA Transfer from RxFIFO. Selects the burst type of DMA transfer from RxFIFO. 30 2 read-write DMA_BURST_TYPE_RFF_0 INCR8 #x0 DMA_BURST_TYPE_RFF_1 INCR4 0x1 DMA_BURST_TYPE_RFF_3 INCR16 0x3 CR3 CSI Control Register 3 0x8 32 read-write 0 0xFFFFFFFF ECC_AUTO_EN Automatic Error Correction Enable 0 1 read-write ECC_AUTO_EN_0 Auto Error correction is disabled. 0 ECC_AUTO_EN_1 Auto Error correction is enabled. 0x1 ECC_INT_EN Error Detection Interrupt Enable 1 1 read-write ECC_INT_EN_0 No interrupt is generated when error is detected. Only the status bit ECC_INT is set. 0 ECC_INT_EN_1 Interrupt is generated when error is detected. 0x1 ZERO_PACK_EN Dummy Zero Packing Enable 2 1 read-write ZERO_PACK_EN_0 Zero packing disabled 0 ZERO_PACK_EN_1 Zero packing enabled 0x1 SENSOR_16BITS 16-bit Sensor Mode 3 1 read-write SENSOR_16BITS_0 Only one 8-bit sensor is connected. 0 SENSOR_16BITS_1 One 16-bit sensor is connected. 0x1 RxFF_LEVEL RxFIFO Full Level 4 3 read-write RxFF_LEVEL_0 4 Double words 0 RxFF_LEVEL_1 8 Double words 0x1 RxFF_LEVEL_2 16 Double words 0x2 RxFF_LEVEL_3 24 Double words 0x3 RxFF_LEVEL_4 32 Double words 0x4 RxFF_LEVEL_5 48 Double words 0x5 RxFF_LEVEL_6 64 Double words 0x6 RxFF_LEVEL_7 96 Double words 0x7 HRESP_ERR_EN Hresponse Error Enable. This bit enables the hresponse (AHB protocol standard) error interrupt. 7 1 read-write HRESP_ERR_EN_0 Disable hresponse error interrupt 0 HRESP_ERR_EN_1 Enable hresponse error interrupt 0x1 STATFF_LEVEL STATFIFO Full Level 8 3 read-write STATFF_LEVEL_0 4 Double words 0 STATFF_LEVEL_1 8 Double words 0x1 STATFF_LEVEL_2 12 Double words 0x2 STATFF_LEVEL_3 16 Double words 0x3 STATFF_LEVEL_4 24 Double words 0x4 STATFF_LEVEL_5 32 Double words 0x5 STATFF_LEVEL_6 48 Double words 0x6 STATFF_LEVEL_7 64 Double words 0x7 DMA_REQ_EN_SFF DMA Request Enable for STATFIFO 11 1 read-write DMA_REQ_EN_SFF_0 Disable the dma request 0 DMA_REQ_EN_SFF_1 Enable the dma request 0x1 DMA_REQ_EN_RFF DMA Request Enable for RxFIFO 12 1 read-write DMA_REQ_EN_RFF_0 Disable the dma request 0 DMA_REQ_EN_RFF_1 Enable the dma request 0x1 DMA_REFLASH_SFF Reflash DMA Controller for STATFIFO 13 1 read-write DMA_REFLASH_SFF_0 No reflashing 0 DMA_REFLASH_SFF_1 Reflash the embedded DMA controller 0x1 DMA_REFLASH_RFF Reflash DMA Controller for RxFIFO 14 1 read-write DMA_REFLASH_RFF_0 No reflashing 0 DMA_REFLASH_RFF_1 Reflash the embedded DMA controller 0x1 FRMCNT_RST Frame Count Reset. Resets the Frame Counter. (Cleared automatically after reset is done) 15 1 read-write FRMCNT_RST_0 Do not reset 0 FRMCNT_RST_1 Reset frame counter immediately 0x1 FRMCNT Frame Counter 16 16 read-write STATFIFO CSI Statistic FIFO Register 0xC 32 read-only 0 0xFFFFFFFF STAT Static data from sensor 0 32 read-only RFIFO CSI RX FIFO Register 0x10 32 read-only 0 0xFFFFFFFF IMAGE Received image data 0 32 read-only RXCNT CSI RX Count Register 0x14 32 read-write 0x9600 0xFFFFFFFF RXCNT RxFIFO Count 0 22 read-write SR CSI Status Register 0x18 32 read-write 0x80004000 0xFFFFFFFF DRDY RXFIFO Data Ready 0 1 read-write DRDY_0 No data (word) is ready 0 DRDY_1 At least 1 datum (word) is ready in RXFIFO. 0x1 ECC_INT BT 1 1 read-write ECC_INT_0 No error detected 0 ECC_INT_1 Error is detected in BT.656 coding 0x1 HISTOGRAM_CALC_DONE_INT no description available 2 1 read-write HISTOGRAM_CALC_DONE_INT_0 Histogram calculation is not finished 0 HISTOGRAM_CALC_DONE_INT_1 Histogram calculation is done and driver can access the PIXEL_COUNTERS(CSI_CSICR21~CSI_CSICR276) to get the gray level 0x1 HRESP_ERR_INT Hresponse Error Interrupt Status 7 1 read-write HRESP_ERR_INT_0 No hresponse error. 0 HRESP_ERR_INT_1 Hresponse error is detected. 0x1 COF_INT Change Of Field Interrupt Status 13 1 read-write COF_INT_0 Video field has no change. 0 COF_INT_1 Change of video field is detected. 0x1 F1_INT BT 14 1 read-write F1_INT_0 Field 1 of video is not detected. 0 F1_INT_1 Field 1 of video is about to start. 0x1 F2_INT BT 15 1 read-write F2_INT_0 Field 2 of video is not detected 0 F2_INT_1 Field 2 of video is about to start 0x1 SOF_INT Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) 16 1 read-write SOF_INT_0 SOF is not detected. 0 SOF_INT_1 SOF is detected. 0x1 EOF_INT End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) 17 1 read-write EOF_INT_0 EOF is not detected. 0 EOF_INT_1 EOF is detected. 0x1 RxFF_INT RXFIFO Full Interrupt Status 18 1 read-write RxFF_INT_0 RxFIFO is not full. 0 RxFF_INT_1 RxFIFO is full. 0x1 DMA_TSF_DONE_FB1 DMA Transfer Done in Frame Buffer1 19 1 read-write DMA_TSF_DONE_FB1_0 DMA transfer is not completed. 0 DMA_TSF_DONE_FB1_1 DMA transfer is completed. 0x1 DMA_TSF_DONE_FB2 DMA Transfer Done in Frame Buffer2 20 1 read-write DMA_TSF_DONE_FB2_0 DMA transfer is not completed. 0 DMA_TSF_DONE_FB2_1 DMA transfer is completed. 0x1 STATFF_INT STATFIFO Full Interrupt Status 21 1 read-write STATFF_INT_0 STATFIFO is not full. 0 STATFF_INT_1 STATFIFO is full. 0x1 DMA_TSF_DONE_SFF DMA Transfer Done from StatFIFO 22 1 read-write DMA_TSF_DONE_SFF_0 DMA transfer is not completed. 0 DMA_TSF_DONE_SFF_1 DMA transfer is completed. 0x1 RF_OR_INT RxFIFO Overrun Interrupt Status 24 1 read-write RF_OR_INT_0 RXFIFO has not overflowed. 0 RF_OR_INT_1 RXFIFO has overflowed. 0x1 SF_OR_INT STATFIFO Overrun Interrupt Status 25 1 read-write SF_OR_INT_0 STATFIFO has not overflowed. 0 SF_OR_INT_1 STATFIFO has overflowed. 0x1 DMA_FIELD1_DONE When DMA field 1 is complete, this bit will be set to 1(clear by writing 1). 26 1 read-write DMA_FIELD0_DONE When DMA field 0 is complete, this bit will be set to 1(clear by writing 1). 27 1 read-write BASEADDR_CHHANGE_ERROR When using base address switching enable, this bit will be 1 when switching occur before DMA complete 28 1 read-write DMASA_STATFIFO CSI DMA Start Address Register - for STATFIFO 0x20 32 read-write 0 0xFFFFFFFF DMA_START_ADDR_SFF DMA Start Address for STATFIFO 2 30 read-write DMATS_STATFIFO CSI DMA Transfer Size Register - for STATFIFO 0x24 32 read-write 0 0xFFFFFFFF DMA_TSF_SIZE_SFF DMA Transfer Size for STATFIFO 0 32 read-write DMASA_FB1 CSI DMA Start Address Register - for Frame Buffer1 0x28 32 read-write 0 0xFFFFFFFF DMA_START_ADDR_FB1 DMA Start Address in Frame Buffer1 2 30 read-write DMASA_FB2 CSI DMA Transfer Size Register - for Frame Buffer2 0x2C 32 read-write 0 0xFFFFFFFF DMA_START_ADDR_FB2 DMA Start Address in Frame Buffer2 2 30 read-write FBUF_PARA CSI Frame Buffer Parameter Register 0x30 32 read-write 0 0xFFFFFFFF FBUF_STRIDE Frame Buffer Parameter 0 16 read-write DEINTERLACE_STRIDE DEINTERLACE_STRIDE is only used in the deinterlace mode 16 16 read-write IMAG_PARA CSI Image Parameter Register 0x34 32 read-write 0 0xFFFFFFFF IMAGE_HEIGHT Image Height. Indicates how many pixels in a column of the image from the sensor. 0 16 read-write IMAGE_WIDTH This field indicates the number of active pixel cycles per line 16 16 read-write CR18 CSI Control Register 18 0x48 32 read-write 0x2D000 0xFFFFFFFF NTSC_EN This bit is used to select NTSC/PAL mode When input is TVDECODER or standard BT.656 video. 0 1 read-write NTSC_EN_0 PAL 0 NTSC_EN_1 NTSC 0x1 TVDECODER_IN_EN When input is from TV decoder, this bit is enabled. 1 1 read-write DEINTERLACE_EN This bit is used to select the output method When input is TVDECODER or standard BT.656 video. 2 1 read-write DEINTERLACE_EN_0 Deinterlace disabled 0 DEINTERLACE_EN_1 Deinterlace enabled 0x1 PARALLEL24_EN Enable bit for Parallel RGB888/YUV444 24bit input 3 1 read-write PARALLEL24_EN_0 Input is disabled 0 PARALLEL24_EN_1 Input is enabled 0x1 BASEADDR_SWITCH_EN When this bit is enabled, CSI DMA will switch the base address according to BASEADDR_SWITCH_SEL rather than automatically by DMA completed 4 1 read-write BASEADDR_SWITCH_SEL CSI 2 base addresses switching method. When using this bit, BASEADDR_SWITCH_EN is 1. 5 1 read-write BASEADDR_SWITCH_SEL_0 Switching base address at the edge of the vsync 0 BASEADDR_SWITCH_SEL_1 Switching base address at the edge of the first data of each frame 0x1 FIELD0_DONE_IE In interlace mode, field 0 means interrupt enabled. 6 1 read-write FIELD0_DONE_IE_0 Interrupt disabled 0 FIELD0_DONE_IE_1 Interrupt enabled 0x1 DMA_FIELD1_DONE_IE When in interlace mode, field 1 done interrupt enable. 7 1 read-write DMA_FIELD1_DONE_IE_0 Interrupt disabled 0 DMA_FIELD1_DONE_IE_1 Interrupt enabled 0x1 LAST_DMA_REQ_SEL Choosing the last DMA request condition 8 1 read-write LAST_DMA_REQ_SEL_0 fifo_full_level 0 LAST_DMA_REQ_SEL_1 hburst_length 0x1 BASEADDR_CHANGE_ERROR_IE Base address change error interrupt enable signal. 9 1 read-write BASEADDR_CHANGE_ERROR_IE_0 Interrupt disabled 0 BASEADDR_CHANGE_ERROR_IE_1 Interrupt enabled 0x1 RGB888A_FORMAT_SEL Output is 32-bit format. 10 1 read-write RGB888A_FORMAT_SEL_0 {8'h0, data[23:0]} 0 RGB888A_FORMAT_SEL_1 {data[23:0], 8'h0} 0x1 AHB_HPROT Hprot value in AHB bus protocol. 12 4 read-write MASK_OPTION These bits used to choose the method to mask the CSI input. 18 2 read-write MASK_OPTION_0 Writing to memory (OCRAM or external DDR) from first completely frame, when using this option, the CSI_ENABLE should be 1. 0 MASK_OPTION_1 Writing to memory when CSI_ENABLE is 1. 0x1 MASK_OPTION_2 Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. 0x2 MASK_OPTION_3 Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0. 0x3 MIPI_DOUBLE_CMPNT Double component per clock cycle in YUV422 formats. 20 1 read-write MIPI_DOUBLE_CMPNT_0 Single component per clock cycle (half pixel per clock cycle) 0 MIPI_DOUBLE_CMPNT_1 Double component per clock cycle (a pixel per clock cycle) 0x1 MIPI_YU_SWAP It only works in MIPI CSI YUV422 double component mode. 21 1 read-write DATA_FROM_MIPI no description available 22 1 read-write DATA_FROM_MIPI_0 Data from parallel sensor 0 DATA_FROM_MIPI_1 Data from MIPI 0x1 LINE_STRIDE_EN When the line width are not the multiple of the burst length, assert this bit. 24 1 read-write MIPI_DATA_FORMAT Image Data Format 25 6 read-only CSI_ENABLE CSI global enable signal 31 1 read-write CR19 CSI Control Register 19 0x4C 32 read-write 0 0xFFFFFFFF DMA_RFIFO_HIGHEST_FIFO_LEVEL This byte stores the highest FIFO level achieved by CSI FIFO timely and will be clear by writing 8'ff to it 0 8 read-write CR20 CSI Control Register 20 0x50 32 read-write 0 0xFFFFFFFF THRESHOLD THRESHOLD used for binary function. When data value > THRESHOLD, output will be 1 Else will be 0. 0 8 read-write BINARY_EN no description available 8 1 read-write BINARY_EN_0 Output is Y8 format(8 bits each pixel) 0 BINARY_EN_1 Output is Y1 format(1 bit each pixel) 0x1 QR_DATA_FORMAT no description available 9 3 read-write QR_DATA_FORMAT_0 YU YV one cycle per 1 pixel input 0 QR_DATA_FORMAT_1 UY VY one cycle per1 pixel input 0x1 QR_DATA_FORMAT_2 Y U Y V two cycles per 1 pixel input 0x2 QR_DATA_FORMAT_3 U Y V Y two cycles per 1 pixel input 0x3 QR_DATA_FORMAT_4 YUV one cycle per 1 pixel input 0x4 QR_DATA_FORMAT_5 Y U V three cycles per 1 pixel input 0x5 BIG_END no description available 12 1 read-write BIG_END_0 The newest (most recent) data will be assigned the lowest position when store to memory. 0 BIG_END_1 The newest (most recent) data will be assigned the highest position when store to memory. 0x1 _10BIT_NEW_EN no description available 29 1 read-write 10BIT_NEW_EN_0 When input 8bits data, it will use the data[9:2] 0 10BIT_NEW_EN_1 If input is 10bits data, it will use the data[7:0] (optional) 0x1 HISTOGRAM_EN Histogram enable 30 1 read-write HISTOGRAM_EN_0 Histogram disable 0 HISTOGRAM_EN_1 Histogram enable 0x1 QRCODE_EN Gray scale mode enable 31 1 read-write QRCODE_EN_0 Normal mode 0 QRCODE_EN_1 Gray scale mode 0x1 256 0x4 21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276 CR%s CSI Control Register 0x54 32 read-write 0 0xFFFFFFFF PIXEL_COUNTERS Number of pixels (Y component of the input pixel) equals: 0 (CSICR21) 1 (CSICR22) 0 24 read-write LCDIF LCDIF Register Reference Index LCDIF LCDIF_ 0x40804000 0 0xB44 registers eLCDIF 54 CTRL LCDIF General Control Register 0 32 read-write 0xC0000000 0xFFFFFFFF RUN When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display 0 1 read-write DATA_FORMAT_24_BIT Used only when WORD_LENGTH = 3, i 1 1 read-write ALL_24_BITS_VALID Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0 DROP_UPPER_2_BITS_PER_BYTE Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. 0x1 DATA_FORMAT_18_BIT Used only when WORD_LENGTH = 2, i.e. 18-bit. 2 1 read-write LOWER_18_BITS_VALID Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0 UPPER_18_BITS_VALID Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. 0x1 DATA_FORMAT_16_BIT When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format 3 1 read-write MASTER Set this bit to make the LCDIF act as a bus master 5 1 read-write ENABLE_PXP_HANDSHAKE If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on 6 1 read-write WORD_LENGTH Input data format. 8 2 read-write 16_BIT Input data is 16 bits per pixel. 0 8_BIT Input data is 8 bits wide. 0x1 18_BIT Input data is 18 bits per pixel. 0x2 24_BIT Input data is 24 bits per pixel. 0x3 LCD_DATABUS_WIDTH LCD Data bus transfer width. When LUT enabled, this field should be set to 0x01. 10 2 read-write 16_BIT 16-bit data bus mode. 0 8_BIT 8-bit data bus mode. 0x1 18_BIT 18-bit data bus mode. 0x2 24_BIT 24-bit data bus mode. 0x3 CSC_DATA_SWIZZLE This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus 12 2 read-write NO_SWAP No byte swapping.(Little endian) 0 BIG_ENDIAN_SWAP Big Endian swap (swap bytes 0,3 and 1,2). 0x1 HWD_SWAP Swap half-words. 0x2 HWD_BYTE_SWAP Swap bytes within each half-word. 0x3 INPUT_DATA_SWIZZLE This field specifies how to swap the bytes fetched by the bus master interface 14 2 read-write NO_SWAP No byte swapping.(Little endian) 0 BIG_ENDIAN_SWAP Big Endian swap (swap bytes 0,3 and 1,2). 0x1 HWD_SWAP Swap half-words. 0x2 HWD_BYTE_SWAP Swap bytes within each half-word. 0x3 DOTCLK_MODE Set this bit to 1 to make the hardware go into the DOTCLK mode, i 17 1 read-write BYPASS_COUNT When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out 19 1 read-write SHIFT_NUM_BITS The data to be transmitted is shifted left or right by this number of bits. 21 5 read-write DATA_SHIFT_DIR Use this bit to determine the direction of shift of transmit data. 26 1 read-write TXDATA_SHIFT_LEFT Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0 TXDATA_SHIFT_RIGHT Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. 0x1 CLKGATE This bit must be set to zero for normal operation 30 1 read-write SFTRST This bit must be set to zero to enable normal operation of the LCDIF 31 1 read-write CTRL_SET LCDIF General Control Register 0x4 32 read-write 0xC0000000 0xFFFFFFFF RUN When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display 0 1 read-write DATA_FORMAT_24_BIT Used only when WORD_LENGTH = 3, i 1 1 read-write ALL_24_BITS_VALID Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0 DROP_UPPER_2_BITS_PER_BYTE Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. 0x1 DATA_FORMAT_18_BIT Used only when WORD_LENGTH = 2, i.e. 18-bit. 2 1 read-write LOWER_18_BITS_VALID Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0 UPPER_18_BITS_VALID Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. 0x1 DATA_FORMAT_16_BIT When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format 3 1 read-write MASTER Set this bit to make the LCDIF act as a bus master 5 1 read-write ENABLE_PXP_HANDSHAKE If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on 6 1 read-write WORD_LENGTH Input data format. 8 2 read-write 16_BIT Input data is 16 bits per pixel. 0 8_BIT Input data is 8 bits wide. 0x1 18_BIT Input data is 18 bits per pixel. 0x2 24_BIT Input data is 24 bits per pixel. 0x3 LCD_DATABUS_WIDTH LCD Data bus transfer width. When LUT enabled, this field should be set to 0x01. 10 2 read-write 16_BIT 16-bit data bus mode. 0 8_BIT 8-bit data bus mode. 0x1 18_BIT 18-bit data bus mode. 0x2 24_BIT 24-bit data bus mode. 0x3 CSC_DATA_SWIZZLE This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus 12 2 read-write NO_SWAP No byte swapping.(Little endian) 0 BIG_ENDIAN_SWAP Big Endian swap (swap bytes 0,3 and 1,2). 0x1 HWD_SWAP Swap half-words. 0x2 HWD_BYTE_SWAP Swap bytes within each half-word. 0x3 INPUT_DATA_SWIZZLE This field specifies how to swap the bytes fetched by the bus master interface 14 2 read-write NO_SWAP No byte swapping.(Little endian) 0 BIG_ENDIAN_SWAP Big Endian swap (swap bytes 0,3 and 1,2). 0x1 HWD_SWAP Swap half-words. 0x2 HWD_BYTE_SWAP Swap bytes within each half-word. 0x3 DOTCLK_MODE Set this bit to 1 to make the hardware go into the DOTCLK mode, i 17 1 read-write BYPASS_COUNT When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out 19 1 read-write SHIFT_NUM_BITS The data to be transmitted is shifted left or right by this number of bits. 21 5 read-write DATA_SHIFT_DIR Use this bit to determine the direction of shift of transmit data. 26 1 read-write TXDATA_SHIFT_LEFT Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0 TXDATA_SHIFT_RIGHT Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. 0x1 CLKGATE This bit must be set to zero for normal operation 30 1 read-write SFTRST This bit must be set to zero to enable normal operation of the LCDIF 31 1 read-write CTRL_CLR LCDIF General Control Register 0x8 32 read-write 0xC0000000 0xFFFFFFFF RUN When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display 0 1 read-write DATA_FORMAT_24_BIT Used only when WORD_LENGTH = 3, i 1 1 read-write ALL_24_BITS_VALID Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0 DROP_UPPER_2_BITS_PER_BYTE Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. 0x1 DATA_FORMAT_18_BIT Used only when WORD_LENGTH = 2, i.e. 18-bit. 2 1 read-write LOWER_18_BITS_VALID Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0 UPPER_18_BITS_VALID Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. 0x1 DATA_FORMAT_16_BIT When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format 3 1 read-write MASTER Set this bit to make the LCDIF act as a bus master 5 1 read-write ENABLE_PXP_HANDSHAKE If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on 6 1 read-write WORD_LENGTH Input data format. 8 2 read-write 16_BIT Input data is 16 bits per pixel. 0 8_BIT Input data is 8 bits wide. 0x1 18_BIT Input data is 18 bits per pixel. 0x2 24_BIT Input data is 24 bits per pixel. 0x3 LCD_DATABUS_WIDTH LCD Data bus transfer width. When LUT enabled, this field should be set to 0x01. 10 2 read-write 16_BIT 16-bit data bus mode. 0 8_BIT 8-bit data bus mode. 0x1 18_BIT 18-bit data bus mode. 0x2 24_BIT 24-bit data bus mode. 0x3 CSC_DATA_SWIZZLE This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus 12 2 read-write NO_SWAP No byte swapping.(Little endian) 0 BIG_ENDIAN_SWAP Big Endian swap (swap bytes 0,3 and 1,2). 0x1 HWD_SWAP Swap half-words. 0x2 HWD_BYTE_SWAP Swap bytes within each half-word. 0x3 INPUT_DATA_SWIZZLE This field specifies how to swap the bytes fetched by the bus master interface 14 2 read-write NO_SWAP No byte swapping.(Little endian) 0 BIG_ENDIAN_SWAP Big Endian swap (swap bytes 0,3 and 1,2). 0x1 HWD_SWAP Swap half-words. 0x2 HWD_BYTE_SWAP Swap bytes within each half-word. 0x3 DOTCLK_MODE Set this bit to 1 to make the hardware go into the DOTCLK mode, i 17 1 read-write BYPASS_COUNT When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out 19 1 read-write SHIFT_NUM_BITS The data to be transmitted is shifted left or right by this number of bits. 21 5 read-write DATA_SHIFT_DIR Use this bit to determine the direction of shift of transmit data. 26 1 read-write TXDATA_SHIFT_LEFT Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0 TXDATA_SHIFT_RIGHT Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. 0x1 CLKGATE This bit must be set to zero for normal operation 30 1 read-write SFTRST This bit must be set to zero to enable normal operation of the LCDIF 31 1 read-write CTRL_TOG LCDIF General Control Register 0xC 32 read-write 0xC0000000 0xFFFFFFFF RUN When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display 0 1 read-write DATA_FORMAT_24_BIT Used only when WORD_LENGTH = 3, i 1 1 read-write ALL_24_BITS_VALID Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0 DROP_UPPER_2_BITS_PER_BYTE Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. 0x1 DATA_FORMAT_18_BIT Used only when WORD_LENGTH = 2, i.e. 18-bit. 2 1 read-write LOWER_18_BITS_VALID Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0 UPPER_18_BITS_VALID Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. 0x1 DATA_FORMAT_16_BIT When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format 3 1 read-write MASTER Set this bit to make the LCDIF act as a bus master 5 1 read-write ENABLE_PXP_HANDSHAKE If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on 6 1 read-write WORD_LENGTH Input data format. 8 2 read-write 16_BIT Input data is 16 bits per pixel. 0 8_BIT Input data is 8 bits wide. 0x1 18_BIT Input data is 18 bits per pixel. 0x2 24_BIT Input data is 24 bits per pixel. 0x3 LCD_DATABUS_WIDTH LCD Data bus transfer width. When LUT enabled, this field should be set to 0x01. 10 2 read-write 16_BIT 16-bit data bus mode. 0 8_BIT 8-bit data bus mode. 0x1 18_BIT 18-bit data bus mode. 0x2 24_BIT 24-bit data bus mode. 0x3 CSC_DATA_SWIZZLE This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus 12 2 read-write NO_SWAP No byte swapping.(Little endian) 0 BIG_ENDIAN_SWAP Big Endian swap (swap bytes 0,3 and 1,2). 0x1 HWD_SWAP Swap half-words. 0x2 HWD_BYTE_SWAP Swap bytes within each half-word. 0x3 INPUT_DATA_SWIZZLE This field specifies how to swap the bytes fetched by the bus master interface 14 2 read-write NO_SWAP No byte swapping.(Little endian) 0 BIG_ENDIAN_SWAP Big Endian swap (swap bytes 0,3 and 1,2). 0x1 HWD_SWAP Swap half-words. 0x2 HWD_BYTE_SWAP Swap bytes within each half-word. 0x3 DOTCLK_MODE Set this bit to 1 to make the hardware go into the DOTCLK mode, i 17 1 read-write BYPASS_COUNT When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out 19 1 read-write SHIFT_NUM_BITS The data to be transmitted is shifted left or right by this number of bits. 21 5 read-write DATA_SHIFT_DIR Use this bit to determine the direction of shift of transmit data. 26 1 read-write TXDATA_SHIFT_LEFT Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0 TXDATA_SHIFT_RIGHT Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. 0x1 CLKGATE This bit must be set to zero for normal operation 30 1 read-write SFTRST This bit must be set to zero to enable normal operation of the LCDIF 31 1 read-write CTRL1 LCDIF General Control1 Register 0x10 32 read-write 0xF0000 0xFFFFFFFF VSYNC_EDGE_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 8 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 CUR_FRAME_DONE_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 9 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 UNDERFLOW_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 10 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 OVERFLOW_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 11 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 VSYNC_EDGE_IRQ_EN This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode 12 1 read-write CUR_FRAME_DONE_IRQ_EN This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state 13 1 read-write UNDERFLOW_IRQ_EN This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. 14 1 read-write OVERFLOW_IRQ_EN This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. 15 1 read-write BYTE_PACKING_FORMAT This bitfield is used to show which data bytes in a 32-bit word are valid 16 4 read-write IRQ_ON_ALTERNATE_FIELDS If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field 20 1 read-write FIFO_CLEAR Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. 21 1 read-write START_INTERLACE_FROM_SECOND_FIELD The default is to grab the odd lines first and then the even lines 22 1 read-write INTERLACE_FIELDS Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field 23 1 read-write RECOVER_ON_UNDERFLOW Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame 24 1 read-write BM_ERROR_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 25 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 BM_ERROR_IRQ_EN This bit is set to enable bus master error interrupt in the LCDIF master mode. 26 1 read-write CS_OUT_SELECT This bit is CS0/CS1 valid select signals 30 1 read-write IMAGE_DATA_SELECT Command Mode MIPI image data select bit 31 1 read-write CTRL1_SET LCDIF General Control1 Register 0x14 32 read-write 0xF0000 0xFFFFFFFF VSYNC_EDGE_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 8 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 CUR_FRAME_DONE_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 9 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 UNDERFLOW_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 10 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 OVERFLOW_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 11 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 VSYNC_EDGE_IRQ_EN This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode 12 1 read-write CUR_FRAME_DONE_IRQ_EN This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state 13 1 read-write UNDERFLOW_IRQ_EN This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. 14 1 read-write OVERFLOW_IRQ_EN This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. 15 1 read-write BYTE_PACKING_FORMAT This bitfield is used to show which data bytes in a 32-bit word are valid 16 4 read-write IRQ_ON_ALTERNATE_FIELDS If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field 20 1 read-write FIFO_CLEAR Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. 21 1 read-write START_INTERLACE_FROM_SECOND_FIELD The default is to grab the odd lines first and then the even lines 22 1 read-write INTERLACE_FIELDS Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field 23 1 read-write RECOVER_ON_UNDERFLOW Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame 24 1 read-write BM_ERROR_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 25 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 BM_ERROR_IRQ_EN This bit is set to enable bus master error interrupt in the LCDIF master mode. 26 1 read-write CS_OUT_SELECT This bit is CS0/CS1 valid select signals 30 1 read-write IMAGE_DATA_SELECT Command Mode MIPI image data select bit 31 1 read-write CTRL1_CLR LCDIF General Control1 Register 0x18 32 read-write 0xF0000 0xFFFFFFFF VSYNC_EDGE_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 8 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 CUR_FRAME_DONE_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 9 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 UNDERFLOW_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 10 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 OVERFLOW_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 11 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 VSYNC_EDGE_IRQ_EN This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode 12 1 read-write CUR_FRAME_DONE_IRQ_EN This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state 13 1 read-write UNDERFLOW_IRQ_EN This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. 14 1 read-write OVERFLOW_IRQ_EN This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. 15 1 read-write BYTE_PACKING_FORMAT This bitfield is used to show which data bytes in a 32-bit word are valid 16 4 read-write IRQ_ON_ALTERNATE_FIELDS If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field 20 1 read-write FIFO_CLEAR Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. 21 1 read-write START_INTERLACE_FROM_SECOND_FIELD The default is to grab the odd lines first and then the even lines 22 1 read-write INTERLACE_FIELDS Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field 23 1 read-write RECOVER_ON_UNDERFLOW Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame 24 1 read-write BM_ERROR_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 25 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 BM_ERROR_IRQ_EN This bit is set to enable bus master error interrupt in the LCDIF master mode. 26 1 read-write CS_OUT_SELECT This bit is CS0/CS1 valid select signals 30 1 read-write IMAGE_DATA_SELECT Command Mode MIPI image data select bit 31 1 read-write CTRL1_TOG LCDIF General Control1 Register 0x1C 32 read-write 0xF0000 0xFFFFFFFF VSYNC_EDGE_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 8 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 CUR_FRAME_DONE_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 9 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 UNDERFLOW_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 10 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 OVERFLOW_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 11 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 VSYNC_EDGE_IRQ_EN This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode 12 1 read-write CUR_FRAME_DONE_IRQ_EN This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state 13 1 read-write UNDERFLOW_IRQ_EN This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. 14 1 read-write OVERFLOW_IRQ_EN This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. 15 1 read-write BYTE_PACKING_FORMAT This bitfield is used to show which data bytes in a 32-bit word are valid 16 4 read-write IRQ_ON_ALTERNATE_FIELDS If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field 20 1 read-write FIFO_CLEAR Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. 21 1 read-write START_INTERLACE_FROM_SECOND_FIELD The default is to grab the odd lines first and then the even lines 22 1 read-write INTERLACE_FIELDS Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field 23 1 read-write RECOVER_ON_UNDERFLOW Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame 24 1 read-write BM_ERROR_IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block 25 1 read-write NO_REQUEST No Interrupt Request Pending. 0 REQUEST Interrupt Request Pending. 0x1 BM_ERROR_IRQ_EN This bit is set to enable bus master error interrupt in the LCDIF master mode. 26 1 read-write CS_OUT_SELECT This bit is CS0/CS1 valid select signals 30 1 read-write IMAGE_DATA_SELECT Command Mode MIPI image data select bit 31 1 read-write CTRL2 LCDIF General Control2 Register 0x20 32 read-write 0x200000 0xFFFFFFFF EVEN_LINE_PATTERN This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, 12 3 read-write RGB RGB 0 RBG RBG 0x1 GBR GBR 0x2 GRB GRB 0x3 BRG BRG 0x4 BGR BGR 0x5 ODD_LINE_PATTERN This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, 16 3 read-write RGB RGB 0 RBG RBG 0x1 GBR GBR 0x2 GRB GRB 0x3 BRG BRG 0x4 BGR BGR 0x5 BURST_LEN_8 By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) 20 1 read-write OUTSTANDING_REQS This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master 21 3 read-write REQ_1 REQ_1 0 REQ_2 REQ_2 0x1 REQ_4 REQ_4 0x2 REQ_8 REQ_8 0x3 REQ_16 REQ_16 0x4 CTRL2_SET LCDIF General Control2 Register 0x24 32 read-write 0x200000 0xFFFFFFFF EVEN_LINE_PATTERN This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, 12 3 read-write RGB RGB 0 RBG RBG 0x1 GBR GBR 0x2 GRB GRB 0x3 BRG BRG 0x4 BGR BGR 0x5 ODD_LINE_PATTERN This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, 16 3 read-write RGB RGB 0 RBG RBG 0x1 GBR GBR 0x2 GRB GRB 0x3 BRG BRG 0x4 BGR BGR 0x5 BURST_LEN_8 By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) 20 1 read-write OUTSTANDING_REQS This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master 21 3 read-write REQ_1 REQ_1 0 REQ_2 REQ_2 0x1 REQ_4 REQ_4 0x2 REQ_8 REQ_8 0x3 REQ_16 REQ_16 0x4 CTRL2_CLR LCDIF General Control2 Register 0x28 32 read-write 0x200000 0xFFFFFFFF EVEN_LINE_PATTERN This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, 12 3 read-write RGB RGB 0 RBG RBG 0x1 GBR GBR 0x2 GRB GRB 0x3 BRG BRG 0x4 BGR BGR 0x5 ODD_LINE_PATTERN This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, 16 3 read-write RGB RGB 0 RBG RBG 0x1 GBR GBR 0x2 GRB GRB 0x3 BRG BRG 0x4 BGR BGR 0x5 BURST_LEN_8 By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) 20 1 read-write OUTSTANDING_REQS This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master 21 3 read-write REQ_1 REQ_1 0 REQ_2 REQ_2 0x1 REQ_4 REQ_4 0x2 REQ_8 REQ_8 0x3 REQ_16 REQ_16 0x4 CTRL2_TOG LCDIF General Control2 Register 0x2C 32 read-write 0x200000 0xFFFFFFFF EVEN_LINE_PATTERN This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, 12 3 read-write RGB RGB 0 RBG RBG 0x1 GBR GBR 0x2 GRB GRB 0x3 BRG BRG 0x4 BGR BGR 0x5 ODD_LINE_PATTERN This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, 16 3 read-write RGB RGB 0 RBG RBG 0x1 GBR GBR 0x2 GRB GRB 0x3 BRG BRG 0x4 BGR BGR 0x5 BURST_LEN_8 By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) 20 1 read-write OUTSTANDING_REQS This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master 21 3 read-write REQ_1 REQ_1 0 REQ_2 REQ_2 0x1 REQ_4 REQ_4 0x2 REQ_8 REQ_8 0x3 REQ_16 REQ_16 0x4 TRANSFER_COUNT LCDIF Horizontal and Vertical Valid Data Count Register 0x30 32 read-write 0x10000 0xFFFFFFFF H_COUNT Total valid data (pixels) in each horizontal line 0 16 read-write V_COUNT Number of horizontal lines per frame which contain valid data 16 16 read-write CUR_BUF LCD Interface Current Buffer Address Register 0x40 32 read-write 0 0xFFFFFFFF ADDR Address of the current frame being transmitted by LCDIF. 0 32 read-write NEXT_BUF LCD Interface Next Buffer Address Register 0x50 32 read-write 0 0xFFFFFFFF ADDR Address of the next frame that will be transmitted by LCDIF. 0 32 read-write VDCTRL0 LCDIF VSYNC Mode and Dotclk Mode Control Register0 0x70 32 read-write 0 0xFFFFFFFF VSYNC_PULSE_WIDTH Number of units for which VSYNC signal is active 0 18 read-write HALF_LINE_MODE When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line 18 1 read-write HALF_LINE Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i 19 1 read-write VSYNC_PULSE_WIDTH_UNIT Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles 20 1 read-write VSYNC_PERIOD_UNIT Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles 21 1 read-write ENABLE_POL Default 0 active low during valid data transfer on each horizontal line. 24 1 read-write DOTCLK_POL Default is data launched at negative edge of DOTCLK and captured at positive edge 25 1 read-write HSYNC_POL Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period 26 1 read-write VSYNC_POL Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period 27 1 read-write ENABLE_PRESENT Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK 28 1 read-write VSYNC_OEB 0 means the VSYNC signal is an output, 1 means it is an input 29 1 read-write VSYNC_OUTPUT The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0 VSYNC_INPUT The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. 0x1 VDCTRL0_SET LCDIF VSYNC Mode and Dotclk Mode Control Register0 0x74 32 read-write 0 0xFFFFFFFF VSYNC_PULSE_WIDTH Number of units for which VSYNC signal is active 0 18 read-write HALF_LINE_MODE When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line 18 1 read-write HALF_LINE Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i 19 1 read-write VSYNC_PULSE_WIDTH_UNIT Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles 20 1 read-write VSYNC_PERIOD_UNIT Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles 21 1 read-write ENABLE_POL Default 0 active low during valid data transfer on each horizontal line. 24 1 read-write DOTCLK_POL Default is data launched at negative edge of DOTCLK and captured at positive edge 25 1 read-write HSYNC_POL Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period 26 1 read-write VSYNC_POL Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period 27 1 read-write ENABLE_PRESENT Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK 28 1 read-write VSYNC_OEB 0 means the VSYNC signal is an output, 1 means it is an input 29 1 read-write VSYNC_OUTPUT The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0 VSYNC_INPUT The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. 0x1 VDCTRL0_CLR LCDIF VSYNC Mode and Dotclk Mode Control Register0 0x78 32 read-write 0 0xFFFFFFFF VSYNC_PULSE_WIDTH Number of units for which VSYNC signal is active 0 18 read-write HALF_LINE_MODE When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line 18 1 read-write HALF_LINE Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i 19 1 read-write VSYNC_PULSE_WIDTH_UNIT Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles 20 1 read-write VSYNC_PERIOD_UNIT Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles 21 1 read-write ENABLE_POL Default 0 active low during valid data transfer on each horizontal line. 24 1 read-write DOTCLK_POL Default is data launched at negative edge of DOTCLK and captured at positive edge 25 1 read-write HSYNC_POL Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period 26 1 read-write VSYNC_POL Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period 27 1 read-write ENABLE_PRESENT Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK 28 1 read-write VSYNC_OEB 0 means the VSYNC signal is an output, 1 means it is an input 29 1 read-write VSYNC_OUTPUT The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0 VSYNC_INPUT The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. 0x1 VDCTRL0_TOG LCDIF VSYNC Mode and Dotclk Mode Control Register0 0x7C 32 read-write 0 0xFFFFFFFF VSYNC_PULSE_WIDTH Number of units for which VSYNC signal is active 0 18 read-write HALF_LINE_MODE When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line 18 1 read-write HALF_LINE Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i 19 1 read-write VSYNC_PULSE_WIDTH_UNIT Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles 20 1 read-write VSYNC_PERIOD_UNIT Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles 21 1 read-write ENABLE_POL Default 0 active low during valid data transfer on each horizontal line. 24 1 read-write DOTCLK_POL Default is data launched at negative edge of DOTCLK and captured at positive edge 25 1 read-write HSYNC_POL Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period 26 1 read-write VSYNC_POL Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period 27 1 read-write ENABLE_PRESENT Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK 28 1 read-write VSYNC_OEB 0 means the VSYNC signal is an output, 1 means it is an input 29 1 read-write VSYNC_OUTPUT The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0 VSYNC_INPUT The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. 0x1 VDCTRL1 LCDIF VSYNC Mode and Dotclk Mode Control Register1 0x80 32 read-write 0 0xFFFFFFFF VSYNC_PERIOD Total number of units between two positive or two negative edges of the VSYNC signal 0 32 read-write VDCTRL2 LCDIF VSYNC Mode and Dotclk Mode Control Register2 0x90 32 read-write 0 0xFFFFFFFF HSYNC_PERIOD Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal 0 18 read-write HSYNC_PULSE_WIDTH Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active. 18 14 read-write VDCTRL3 LCDIF VSYNC Mode and Dotclk Mode Control Register3 0xA0 32 read-write 0 0xFFFFFFFF VERTICAL_WAIT_CNT In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set 0 16 read-write HORIZONTAL_WAIT_CNT In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins 16 12 read-write VSYNC_ONLY This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation. 28 1 read-write MUX_SYNC_SIGNALS When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins 29 1 read-write VDCTRL4 LCDIF VSYNC Mode and Dotclk Mode Control Register4 0xB0 32 read-write 0 0xFFFFFFFF DOTCLK_H_VALID_DATA_CNT Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode 0 18 read-write SYNC_SIGNALS_ON Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end 18 1 read-write DOTCLK_DLY_SEL This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin 29 3 read-write BM_ERROR_STAT Bus Master Error Status Register 0x190 32 read-write 0 0xFFFFFFFF ADDR Virtual address at which bus master error occurred. 0 32 read-write CRC_STAT CRC Status Register 0x1A0 32 read-write 0 0xFFFFFFFF CRC_VALUE Calculated CRC value. 0 32 read-write STAT LCD Interface Status Register 0x1B0 32 read-only 0x95000000 0xFFFFFFFF LFIFO_COUNT Read only view of the current count in Latency buffer (LFIFO). 0 9 read-only TXFIFO_EMPTY Read only view of the signals that indicates LCD TXFIFO is empty. 26 1 read-only TXFIFO_FULL Read only view of the signals that indicates LCD TXFIFO is full. 27 1 read-only LFIFO_EMPTY Read only view of the signals that indicates LCD LFIFO is empty. 28 1 read-only LFIFO_FULL Read only view of the signals that indicates LCD LFIFO is full. 29 1 read-only DMA_REQ Reflects the current state of the DMA Request line for the LCDIF 30 1 read-only PRESENT 0: LCDIF not present on this product 1: LCDIF is present. 31 1 read-only THRES LCDIF Threshold Register 0x200 32 read-write 0x100000F 0xFFFFFFFF FASTCLOCK This value should be set to a value of pixels, from 0 to 511 16 9 read-write PIGEONCTRL0 LCDIF Pigeon Mode Control0 Register 0x380 32 read-write 0 0xFFFFFFFF FD_PERIOD Period of line counter during FD phase 0 12 read-write LD_PERIOD Period of pclk counter during LD phase 16 12 read-write PIGEONCTRL0_SET LCDIF Pigeon Mode Control0 Register 0x384 32 read-write 0 0xFFFFFFFF FD_PERIOD Period of line counter during FD phase 0 12 read-write LD_PERIOD Period of pclk counter during LD phase 16 12 read-write PIGEONCTRL0_CLR LCDIF Pigeon Mode Control0 Register 0x388 32 read-write 0 0xFFFFFFFF FD_PERIOD Period of line counter during FD phase 0 12 read-write LD_PERIOD Period of pclk counter during LD phase 16 12 read-write PIGEONCTRL0_TOG LCDIF Pigeon Mode Control0 Register 0x38C 32 read-write 0 0xFFFFFFFF FD_PERIOD Period of line counter during FD phase 0 12 read-write LD_PERIOD Period of pclk counter during LD phase 16 12 read-write PIGEONCTRL1 LCDIF Pigeon Mode Control1 Register 0x390 32 read-write 0 0xFFFFFFFF FRAME_CNT_PERIOD Period of frame counter 0 12 read-write FRAME_CNT_CYCLES Max cycles of frame counter 16 12 read-write PIGEONCTRL1_SET LCDIF Pigeon Mode Control1 Register 0x394 32 read-write 0 0xFFFFFFFF FRAME_CNT_PERIOD Period of frame counter 0 12 read-write FRAME_CNT_CYCLES Max cycles of frame counter 16 12 read-write PIGEONCTRL1_CLR LCDIF Pigeon Mode Control1 Register 0x398 32 read-write 0 0xFFFFFFFF FRAME_CNT_PERIOD Period of frame counter 0 12 read-write FRAME_CNT_CYCLES Max cycles of frame counter 16 12 read-write PIGEONCTRL1_TOG LCDIF Pigeon Mode Control1 Register 0x39C 32 read-write 0 0xFFFFFFFF FRAME_CNT_PERIOD Period of frame counter 0 12 read-write FRAME_CNT_CYCLES Max cycles of frame counter 16 12 read-write PIGEONCTRL2 LCDIF Pigeon Mode Control2 Register 0x3A0 32 read-write 0 0xFFFFFFFF PIGEON_DATA_EN Pigeon mode data enable 0 1 read-write PIGEON_CLK_GATE Pigeon mode dot clock gate enable 1 1 read-write PIGEONCTRL2_SET LCDIF Pigeon Mode Control2 Register 0x3A4 32 read-write 0 0xFFFFFFFF PIGEON_DATA_EN Pigeon mode data enable 0 1 read-write PIGEON_CLK_GATE Pigeon mode dot clock gate enable 1 1 read-write PIGEONCTRL2_CLR LCDIF Pigeon Mode Control2 Register 0x3A8 32 read-write 0 0xFFFFFFFF PIGEON_DATA_EN Pigeon mode data enable 0 1 read-write PIGEON_CLK_GATE Pigeon mode dot clock gate enable 1 1 read-write PIGEONCTRL2_TOG LCDIF Pigeon Mode Control2 Register 0x3AC 32 read-write 0 0xFFFFFFFF PIGEON_DATA_EN Pigeon mode data enable 0 1 read-write PIGEON_CLK_GATE Pigeon mode dot clock gate enable 1 1 read-write PIGEON_0_0 Panel Interface Signal Generator Register 0x800 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_0_1 Panel Interface Signal Generator Register 0x810 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_0_2 Panel Interface Signal Generator Register 0x820 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_1_0 Panel Interface Signal Generator Register 0x840 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_1_1 Panel Interface Signal Generator Register 0x850 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_1_2 Panel Interface Signal Generator Register 0x860 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_2_0 Panel Interface Signal Generator Register 0x880 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_2_1 Panel Interface Signal Generator Register 0x890 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_2_2 Panel Interface Signal Generator Register 0x8A0 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_3_0 Panel Interface Signal Generator Register 0x8C0 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_3_1 Panel Interface Signal Generator Register 0x8D0 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_3_2 Panel Interface Signal Generator Register 0x8E0 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_4_0 Panel Interface Signal Generator Register 0x900 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_4_1 Panel Interface Signal Generator Register 0x910 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_4_2 Panel Interface Signal Generator Register 0x920 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_5_0 Panel Interface Signal Generator Register 0x940 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_5_1 Panel Interface Signal Generator Register 0x950 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_5_2 Panel Interface Signal Generator Register 0x960 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_6_0 Panel Interface Signal Generator Register 0x980 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_6_1 Panel Interface Signal Generator Register 0x990 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_6_2 Panel Interface Signal Generator Register 0x9A0 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_7_0 Panel Interface Signal Generator Register 0x9C0 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_7_1 Panel Interface Signal Generator Register 0x9D0 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_7_2 Panel Interface Signal Generator Register 0x9E0 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_8_0 Panel Interface Signal Generator Register 0xA00 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_8_1 Panel Interface Signal Generator Register 0xA10 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_8_2 Panel Interface Signal Generator Register 0xA20 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_9_0 Panel Interface Signal Generator Register 0xA40 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_9_1 Panel Interface Signal Generator Register 0xA50 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_9_2 Panel Interface Signal Generator Register 0xA60 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_10_0 Panel Interface Signal Generator Register 0xA80 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_10_1 Panel Interface Signal Generator Register 0xA90 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_10_2 Panel Interface Signal Generator Register 0xAA0 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_11_0 Panel Interface Signal Generator Register 0xAC0 32 read-write 0 0xFFFFFFFF EN Enable pigeon Mode on this signal 0 1 read-write POL Polarity of signal output 1 1 read-write ACTIVE_HIGH Normal Signal (Active high) 0 ACTIVE_LOW Inverted signal (Active low) 0x1 INC_SEL Event to incrment local counter 2 2 read-write PCLK pclk 0 LINE Line start pulse 0x1 FRAME Frame start pulse 0x2 SIG_ANOTHER Use another signal as tick event 0x3 OFFSET offset on pclk unit 4 4 read-write MASK_CNT_SEL select global counters as mask condition, use together with MASK_CNT 8 4 read-write HSTATE_CNT pclk counter within one hscan state 0 HSTATE_CYCLE pclk cycle within one hscan state 0x1 VSTATE_CNT line counter within one vscan state 0x2 VSTATE_CYCLE line cycle within one vscan state 0x3 FRAME_CNT frame counter 0x4 FRAME_CYCLE frame cycle 0x5 HCNT horizontal counter (pclk counter within one line ) 0x6 VCNT vertical counter (line counter within one frame) 0x7 MASK_CNT When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking 12 12 read-write STATE_MASK state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking 24 8 read-write FS FRAME SYNC 0x1 FB FRAME BEGIN 0x2 FD FRAME DATA 0x4 FE FRAME END 0x8 LS LINE SYNC 0x10 LB LINE BEGIN 0x20 LD LINE DATA 0x40 LE LINE END 0x80 PIGEON_11_1 Panel Interface Signal Generator Register 0xAD0 32 read-write 0 0xFFFFFFFF SET_CNT Assert signal output when counter match this value 0 16 read-write START_ACTIVE Start as active 0 CLR_CNT Deassert signal output when counter match this value 16 16 read-write CLEAR_USING_MASK Keep active until mask off 0 PIGEON_11_2 Panel Interface Signal Generator Register 0xAE0 32 read-write 0 0xFFFFFFFF SIG_LOGIC Logic operation with another signal: DIS/AND/OR/COND 0 4 read-write DIS No logic operation 0 AND sigout = sig_another AND this_sig 0x1 OR sigout = sig_another OR this_sig 0x2 MASK mask = sig_another AND other_masks 0x3 SIG_ANOTHER Select another signal for logic operation or as mask or counter tick event 4 5 read-write CLEAR_USING_MASK Keep active until mask off 0 LUT_CTRL Look Up Table Control Register 0xB00 32 read-write 0x1 0xFFFFFFFF LUT_BYPASS Setting this bit will bypass the LUT memory resource completely 0 1 read-write LUT0_ADDR Lookup Table 0 Index Register 0xB10 32 read-write 0 0xFFFFFFFF ADDR LUT indexed address pointer 0 8 read-write LUT0_DATA Lookup Table 0 Data Register 0xB20 32 read-write 0 0xFFFFFFFF DATA Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register 0 32 read-write LUT1_ADDR Lookup Table 1 Index Register 0xB30 32 read-write 0 0xFFFFFFFF ADDR LUT indexed address pointer 0 8 read-write LUT1_DATA Lookup Table 1 Data Register 0xB40 32 read-write 0 0xFFFFFFFF DATA Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register 0 32 read-write LCDIFV2 LCDIF_V2 LCDIFV2 0x40808000 0 0x2000 registers LCDIFv2 55 CTRL LCDIFv2 display control Register 0 32 read-write 0x80000000 0xFFFFFFFF INV_HS Invert Horizontal synchronization signal 0 1 read-write INV_HS_0 HSYNC signal not inverted (active HIGH) 0 INV_HS_1 Invert HSYNC signal (active LOW) 0x1 INV_VS Invert Vertical synchronization signal 1 1 read-write INV_VS_0 VSYNC signal not inverted (active HIGH) 0 INV_VS_1 Invert VSYNC signal (active LOW) 0x1 INV_DE Invert Data Enable polarity 2 1 read-write INV_DE_0 Data enable is active high 0 INV_DE_1 Data enable is active low 0x1 INV_PXCK Polarity change of Pixel Clock 3 1 read-write INV_PXCK_0 Display samples data on the falling edge 0 INV_PXCK_1 Display samples data on the rising edge 0x1 NEG Indicates if value at the output (pixel data output) needs to be negated 4 1 read-write NEG_0 Output is to remain same 0 NEG_1 Output to be negated 0x1 SW_RESET Software Reset 31 1 read-write SW_RESET_0 No action 0 SW_RESET_1 All LCDIFv2 internal registers are forced into their reset state. User registers are not affected 0x1 CTRL_SET LCDIFv2 display control Register 0x4 32 read-write 0x80000000 0xFFFFFFFF oneToSet INV_HS Invert Horizontal synchronization signal 0 1 read-write oneToSet INV_VS Invert Vertical synchronization signal 1 1 read-write oneToSet INV_DE Invert Data Enable polarity 2 1 read-write oneToSet INV_PXCK Polarity change of Pixel Clock 3 1 read-write oneToSet NEG Indicates if value at the output (pixel data output) needs to be negated 4 1 read-write oneToSet SW_RESET Software Reset 31 1 read-write oneToSet CTRL_CLR LCDIFv2 display control Register 0x8 32 read-write 0x80000000 0xFFFFFFFF oneToClear INV_HS Invert Horizontal synchronization signal 0 1 read-write oneToClear INV_VS Invert Vertical synchronization signal 1 1 read-write oneToClear INV_DE Invert Data Enable polarity 2 1 read-write oneToClear INV_PXCK Polarity change of Pixel Clock 3 1 read-write oneToClear NEG Indicates if value at the output (pixel data output) needs to be negated 4 1 read-write oneToClear SW_RESET Software Reset 31 1 read-write oneToClear CTRL_TOG LCDIFv2 display control Register 0xC 32 read-write 0x80000000 0xFFFFFFFF oneToToggle INV_HS Invert Horizontal synchronization signal 0 1 read-write oneToToggle INV_VS Invert Vertical synchronization signal 1 1 read-write oneToToggle INV_DE Invert Data Enable polarity 2 1 read-write oneToToggle INV_PXCK Polarity change of Pixel Clock 3 1 read-write oneToToggle NEG Indicates if value at the output (pixel data output) needs to be negated 4 1 read-write oneToToggle SW_RESET Software Reset 31 1 read-write oneToToggle DISP_PARA Display Parameter Register 0x10 32 read-write 0 0xFFFFFFFF BGND_B Blue component of the default color displayed in the sectors where no layer is active 0 8 read-write BGND_G Green component of the default color displayed in the sectors where no layer is active 8 8 read-write BGND_R Red component of the default color displayed in the sectors where no layer is active 16 8 read-write DISP_MODE LCDIFv2 operating mode 24 2 read-write DISP_MODE_0 Normal mode. Panel content controlled by layer configuration 0 DISP_MODE_1 Test Mode1(BGND Color Display) 0x1 DISP_MODE_2 Test Mode2(Column Color Bar) 0x2 DISP_MODE_3 Test Mode3(Row Color Bar) 0x3 LINE_PATTERN LCDIFv2 line output order 26 3 read-write LINE_PATTERN_0 RGB 0 LINE_PATTERN_1 RBG 0x1 LINE_PATTERN_2 GBR 0x2 LINE_PATTERN_3 GRB 0x3 LINE_PATTERN_4 BRG 0x4 LINE_PATTERN_5 BGR 0x5 DISP_ON Display panel On/Off mode 31 1 read-write DISP_ON_0 Display Off 0 DISP_ON_1 Display On 0x1 DISP_SIZE Display Size Register 0x14 32 read-write 0 0xFFFFFFFF DELTA_X Sets the display size horizontal resolution in pixels 0 12 read-write DELTA_Y Sets the display size vertical resolution in pixels 16 12 read-write HSYN_PARA Horizontal Sync Parameter Register 0x18 32 read-write 0xC01803 0xFFFFFFFF FP_H HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1 0 9 read-write PW_H HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1 11 9 read-write BP_H HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1 22 9 read-write VSYN_PARA Vertical Sync Parameter Register 0x1C 32 read-write 0xC01803 0xFFFFFFFF FP_V VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1 0 9 read-write PW_V VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1 11 9 read-write BP_V VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1 22 9 read-write INT_STATUS_D0 Interrupt Status Register for domain 0 0x20 32 read-write 0 0xFFFFFFFF oneToClear VSYNC Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame) 0 1 read-write oneToClear VSYNC_0 VSYNC has not started 0 VSYNC_1 VSYNC has started 0x1 UNDERRUN Interrupt flag to indicate the output buffer underrun condition 1 1 read-write oneToClear UNDERRUN_0 Output buffer not underrun 0 UNDERRUN_1 Output buffer underrun 0x1 VS_BLANK Interrupt flag to indicate vertical blanking period 2 1 read-write oneToClear VS_BLANK_0 Vertical blanking period has not started 0 VS_BLANK_1 Vertical blanking period has started 0x1 DMA_ERR Interrupt flag to indicate that which PLANE has Read Error on the AXI interface 8 8 read-write oneToClear DMA_DONE Interrupt flag to indicate that which PLANE has fetched the last pixel from memory 16 8 read-write oneToClear FIFO_EMPTY Interrupt flag to indicate that which FIFO in the pixel blending underflowed 24 8 read-write oneToClear INT_ENABLE_D0 Interrupt Enable Register for domain 0 0x24 32 read-write 0 0xFFFFFFFF VSYNC_EN Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame) 0 1 read-write VSYNC_EN_0 VSYNC interrupt disable 0 VSYNC_EN_1 VSYNC interrupt enable 0x1 UNDERRUN_EN Enable Interrupt flag to indicate the output buffer underrun condition 1 1 read-write UNDERRUN_EN_0 Output buffer underrun disable 0 UNDERRUN_EN_1 Output buffer underrun enable 0x1 VS_BLANK_EN Enable Interrupt flag to indicate vertical blanking period 2 1 read-write VS_BLANK_EN_0 Vertical blanking start interrupt disable 0 VS_BLANK_EN_1 Vertical blanking start interrupt enable 0x1 DMA_ERR_EN Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface 8 8 read-write DMA_DONE_EN Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory 16 8 read-write FIFO_EMPTY_EN Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed 24 8 read-write INT_STATUS_D1 Interrupt Status Register for domain 1 0x30 32 read-write 0 0xFFFFFFFF oneToClear VSYNC Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame) 0 1 read-write oneToClear UNDERRUN Interrupt flag to indicate the output buffer underrun condition 1 1 read-write oneToClear VS_BLANK Interrupt flag to indicate vertical blanking period 2 1 read-write oneToClear DMA_ERR Interrupt flag to indicate that which PLANE has Read Error on the AXI interface 8 8 read-write oneToClear DMA_DONE Interrupt flag to indicate that which PLANE has fetched the last pixel from memory 16 8 read-write oneToClear FIFO_EMPTY Interrupt flag to indicate that which FIFO in the pixel blending underflowed 24 8 read-write oneToClear INT_ENABLE_D1 Interrupt Enable Register for domain 1 0x34 32 read-write 0 0xFFFFFFFF VSYNC_EN Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame) 0 1 read-write UNDERRUN_EN Enable Interrupt flag to indicate the output buffer underrun condition 1 1 read-write VS_BLANK_EN Enable Interrupt flag to indicate vertical blanking period 2 1 read-write DMA_ERR_EN Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface 8 8 read-write DMA_DONE_EN Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory 16 8 read-write FIFO_EMPTY_EN Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed 24 8 read-write PDI_PARA Parallel Data Interface Parameter Register 0x40 32 read-write 0 0xFFFFFFFF INV_PDI_HS Polarity of PDI input HSYNC 0 1 read-write INV_PDI_HS_0 HSYNC is active HIGH 0 INV_PDI_HS_1 HSYNC is active LOW 0x1 INV_PDI_VS Polarity of PDI input VSYNC 1 1 read-write INV_PDI_VS_0 VSYNC is active HIGH 0 INV_PDI_VS_1 VSYNC is active LOW 0x1 INV_PDI_DE Polarity of PDI input Data Enable 2 1 read-write INV_PDI_DE_0 Data enable is active HIGH 0 INV_PDI_DE_1 Data enable is active LOW 0x1 INV_PDI_PXCK Polarity of PDI input Pixel Clock 3 1 read-write INV_PDI_PXCK_0 Samples data on the falling edge 0 INV_PDI_PXCK_1 Samples data on the rising edge 0x1 MODE The PDI mode for input data format 4 4 read-write MODE_0 32 bpp (ARGB8888) 0 MODE_1 24 bpp (RGB888) 0x1 MODE_2 24 bpp (RGB666) 0x2 MODE_3 16 bpp (RGB565) 0x3 MODE_4 16 bpp (RGB444) 0x4 MODE_5 16 bpp (RGB555) 0x5 MODE_6 16 bpp (YCbCr422) 0x6 PDI_SEL PDI selected on LCDIFv2 plane number 30 1 read-write PDI_SEL_0 PDI selected on LCDIFv2 plane 0 0 PDI_SEL_1 PDI selected on LCDIFv2 plane 1 0x1 PDI_EN Enable PDI input data to LCDIFv2 display 31 1 read-write PDI_EN_0 Disable PDI input data 0 PDI_EN_1 Enable PDI input data 0x1 CTRLDESCL0_1 Control Descriptor Layer 1 Register 0x200 32 read-write 0 0xFFFFFFFF WIDTH Width of the layer in pixels 0 12 read-write HEIGHT Height of the layer in pixels 16 12 read-write CTRLDESCL0_2 Control Descriptor Layer 2 Register 0x204 32 read-write 0 0xFFFFFFFF POSX The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, only positive values are to the right the left-hand column of the panel 0 12 read-write POSY The vertical position of top row of the layer, where 0 is the top row of the panel, only positive values are below the top row of the panel 16 12 read-write CTRLDESCL0_3 Control Descriptor Layer 3 Register 0x208 32 read-write 0 0xFFFFFFFF PITCH Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry 0 16 read-write CTRLDESCL0_4 Control Descriptor Layer 4 Register 0x20C 32 read-write 0 0xFFFFFFFF ADDR Address of layer data in the memory. The address programmed should be 64-bit aligned 0 32 read-write CTRLDESCL0_5 Control Descriptor Layer 5 Register 0x210 32 read-write 0 0xFFFFFFFF AB_MODE Alpha Blending Mode 0 2 read-write AB_MODE_0 No alpha Blending (The SAFETY_EN bit need set to 1) 0 AB_MODE_1 Blend with global ALPHA 0x1 AB_MODE_2 Blend with embedded ALPHA 0x2 AB_MODE_3 Blend with PoterDuff enable 0x3 PD_FACTOR_MODE PoterDuff factor mode 4 2 read-write PD_FACTOR_MODE_0 Using 1 0 PD_FACTOR_MODE_1 Using 0 0x1 PD_FACTOR_MODE_2 Using straight alpha 0x2 PD_FACTOR_MODE_3 Using inverse alpha 0x3 PD_GLOBAL_ALPHA_MODE PoterDuff global alpha mode 6 2 read-write PD_GLOBAL_ALPHA_MODE_0 Using global alpha 0 PD_GLOBAL_ALPHA_MODE_1 Using local alpha 0x1 PD_GLOBAL_ALPHA_MODE_2 Using scaled alpha 0x2 PD_GLOBAL_ALPHA_MODE_3 Using scaled alpha 0x3 PD_ALPHA_MODE PoterDuff alpha mode 8 1 read-write PD_ALPHA_MODE_0 Straight mode for Porter Duff alpha 0 PD_ALPHA_MODE_1 Inversed mode for Porter Duff alpha 0x1 PD_COLOR_MODE PoterDuff alpha mode 9 1 read-write PD_COLOR_MODE_0 Straight mode for Porter Duff color 0 PD_COLOR_MODE_1 Inversed mode for Porter Duff color 0x1 YUV_FORMAT The YUV422 input format selection 14 2 read-write YUV_FORMAT_0 The YVYU422 8bit sequence is U1,Y1,V1,Y2 0 YUV_FORMAT_1 The YVYU422 8bit sequence is V1,Y1,U1,Y2 0x1 YUV_FORMAT_2 The YVYU422 8bit sequence is Y1,U1,Y2,V1 0x2 YUV_FORMAT_3 The YVYU422 8bit sequence is Y1,V1,Y2,U1 0x3 GLOBAL_ALPHA Global Alpha 16 8 read-write BPP Layer encoding format (bit per pixel) 24 4 read-write BPP_0 1 bpp 0 BPP_1 2 bpp 0x1 BPP_2 4 bpp 0x2 BPP_3 8 bpp 0x3 BPP_4 16 bpp (RGB565) 0x4 BPP_5 16 bpp (ARGB1555) 0x5 BPP_6 16 bpp (ARGB4444) 0x6 BPP_7 YCbCr422 (Only layer 0/1 can support this format) 0x7 BPP_8 24 bpp (RGB888) 0x8 BPP_9 32 bpp (ARGB8888) 0x9 BPP_10 32 bpp (ABGR8888) 0xA SAFETY_EN Safety Mode Enable Bit 28 1 read-write SAFETY_EN_0 Safety Mode is disabled 0 SAFETY_EN_1 Safety Mode is enabled for this layer 0x1 SHADOW_LOAD_EN Shadow Load Enable 30 1 read-write EN Enable the layer for DMA 31 1 read-write EN_0 OFF 0 EN_1 ON 0x1 CTRLDESCL0_6 Control Descriptor Layer 6 Register 0x214 32 read-write 0 0xFFFFFFFF BCLR_B Background B component value 0 8 read-write BCLR_G Background G component value 8 8 read-write BCLR_R Background R component value 16 8 read-write CSC0_COEF0 Color Space Conversion Coefficient Register 0 0x218 32 read-write 0x4000000 0xFFFFFFFF Y_OFFSET Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is typically -16 (0x1F0) 0 9 read-write UV_OFFSET Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range) 9 9 read-write C0 Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) 18 11 read-write ENABLE Enable the CSC unit in the LCDIFv2 plane data path 30 1 read-write ENABLE_0 The CSC is bypassed and the input pixels are RGB data already 0 ENABLE_1 The CSC is enabled and the pixels will be converted to RGB data 0x1 YCBCR_MODE This bit changes the behavior when performing U/V converting 31 1 read-write YCBCR_MODE_0 Converting YUV to RGB data 0 YCBCR_MODE_1 Converting YCbCr to RGB data 0x1 CSC0_COEF1 Color Space Conversion Coefficient Register 1 0x21C 32 read-write 0x1230208 0xFFFFFFFF C4 Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017) 0 11 read-write C1 Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596) 16 11 read-write CSC0_COEF2 Color Space Conversion Coefficient Register 2 0x220 32 read-write 0x76B079C 0xFFFFFFFF C3 Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392) 0 11 read-write C2 Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813) 16 11 read-write CTRLDESCL1_1 Control Descriptor Layer 1 Register 0x240 32 read-write 0 0xFFFFFFFF WIDTH Width of the layer in pixels 0 12 read-write HEIGHT Height of the layer in pixels 16 12 read-write CTRLDESCL1_2 Control Descriptor Layer 2 Register 0x244 32 read-write 0 0xFFFFFFFF POSX The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, only positive values are to the right the left-hand column of the panel 0 12 read-write POSY The vertical position of top row of the layer, where 0 is the top row of the panel, only positive values are below the top row of the panel 16 12 read-write CTRLDESCL1_3 Control Descriptor Layer 3 Register 0x248 32 read-write 0 0xFFFFFFFF PITCH Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry 0 16 read-write CTRLDESCL1_4 Control Descriptor Layer 4 Register 0x24C 32 read-write 0 0xFFFFFFFF ADDR Address of layer data in the memory. The address programmed should be 64-bit aligned 0 32 read-write CTRLDESCL1_5 Control Descriptor Layer 5 Register 0x250 32 read-write 0 0xFFFFFFFF AB_MODE Alpha Blending Mode 0 2 read-write AB_MODE_0 No alpha Blending (The SAFETY_EN bit need set to 1) 0 AB_MODE_1 Blend with global ALPHA 0x1 AB_MODE_2 Blend with embedded ALPHA 0x2 AB_MODE_3 Blend with PoterDuff enable 0x3 PD_FACTOR_MODE PoterDuff factor mode 4 2 read-write PD_FACTOR_MODE_0 Using 1 0 PD_FACTOR_MODE_1 Using 0 0x1 PD_FACTOR_MODE_2 Using straight alpha 0x2 PD_FACTOR_MODE_3 Using inverse alpha 0x3 PD_GLOBAL_ALPHA_MODE PoterDuff global alpha mode 6 2 read-write PD_GLOBAL_ALPHA_MODE_0 Using global alpha 0 PD_GLOBAL_ALPHA_MODE_1 Using local alpha 0x1 PD_GLOBAL_ALPHA_MODE_2 Using scaled alpha 0x2 PD_GLOBAL_ALPHA_MODE_3 Using scaled alpha 0x3 PD_ALPHA_MODE PoterDuff alpha mode 8 1 read-write PD_ALPHA_MODE_0 Straight mode for Porter Duff alpha 0 PD_ALPHA_MODE_1 Inversed mode for Porter Duff alpha 0x1 PD_COLOR_MODE PoterDuff alpha mode 9 1 read-write PD_COLOR_MODE_0 Straight mode for Porter Duff color 0 PD_COLOR_MODE_1 Inversed mode for Porter Duff color 0x1 YUV_FORMAT The YUV422 input format selection 14 2 read-write YUV_FORMAT_0 The YVYU422 8bit sequence is U1,Y1,V1,Y2 0 YUV_FORMAT_1 The YVYU422 8bit sequence is V1,Y1,U1,Y2 0x1 YUV_FORMAT_2 The YVYU422 8bit sequence is Y1,U1,Y2,V1 0x2 YUV_FORMAT_3 The YVYU422 8bit sequence is Y1,V1,Y2,U1 0x3 GLOBAL_ALPHA Global Alpha 16 8 read-write BPP Layer encoding format (bit per pixel) 24 4 read-write BPP_0 1 bpp 0 BPP_1 2 bpp 0x1 BPP_2 4 bpp 0x2 BPP_3 8 bpp 0x3 BPP_4 16 bpp (RGB565) 0x4 BPP_5 16 bpp (ARGB1555) 0x5 BPP_6 16 bpp (ARGB4444) 0x6 BPP_7 YCbCr422 (Only layer 0/1 can support this format) 0x7 BPP_8 24 bpp (RGB888) 0x8 BPP_9 32 bpp (ARGB8888) 0x9 BPP_10 32 bpp (ABGR8888) 0xA SAFETY_EN Safety Mode Enable Bit 28 1 read-write SAFETY_EN_0 Safety Mode is disabled 0 SAFETY_EN_1 Safety Mode is enabled for this layer 0x1 SHADOW_LOAD_EN Shadow Load Enable 30 1 read-write EN Enable the layer for DMA 31 1 read-write EN_0 OFF 0 EN_1 ON 0x1 CTRLDESCL1_6 Control Descriptor Layer 6 Register 0x254 32 read-write 0 0xFFFFFFFF BCLR_B Background B component value 0 8 read-write BCLR_G Background G component value 8 8 read-write BCLR_R Background R component value 16 8 read-write CSC1_COEF0 Color Space Conversion Coefficient Register 0 0x258 32 read-write 0x4000000 0xFFFFFFFF Y_OFFSET Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is typically -16 (0x1F0) 0 9 read-write UV_OFFSET Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range) 9 9 read-write C0 Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) 18 11 read-write ENABLE Enable the CSC unit in the LCDIFv2 plane data path 30 1 read-write ENABLE_0 The CSC is bypassed and the input pixels are RGB data already 0 ENABLE_1 The CSC is enabled and the pixels will be converted to RGB data 0x1 YCBCR_MODE This bit changes the behavior when performing U/V converting 31 1 read-write YCBCR_MODE_0 Converting YUV to RGB data 0 YCBCR_MODE_1 Converting YCbCr to RGB data 0x1 CSC1_COEF1 Color Space Conversion Coefficient Register 1 0x25C 32 read-write 0x1230208 0xFFFFFFFF C4 Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017) 0 11 read-write C1 Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596) 16 11 read-write CSC1_COEF2 Color Space Conversion Coefficient Register 2 0x260 32 read-write 0x76B079C 0xFFFFFFFF C3 Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392) 0 11 read-write C2 Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813) 16 11 read-write CTRLDESCL2_1 Control Descriptor Layer 1 Register 0x280 32 read-write 0 0xFFFFFFFF WIDTH Width of the layer in pixels 0 12 read-write HEIGHT Height of the layer in pixels 16 12 read-write CTRLDESCL2_2 Control Descriptor Layer 2 Register 0x284 32 read-write 0 0xFFFFFFFF POSX The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, only positive values are to the right the left-hand column of the panel 0 12 read-write POSY The vertical position of top row of the layer, where 0 is the top row of the panel, only positive values are below the top row of the panel 16 12 read-write CTRLDESCL2_3 Control Descriptor Layer 3 Register 0x288 32 read-write 0 0xFFFFFFFF PITCH Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry 0 16 read-write CTRLDESCL2_4 Control Descriptor Layer 4 Register 0x28C 32 read-write 0 0xFFFFFFFF ADDR Address of layer data in the memory. The address programmed should be 64-bit aligned 0 32 read-write CTRLDESCL2_5 Control Descriptor Layer 5 Register 0x290 32 read-write 0 0xFFFFFFFF AB_MODE Alpha Blending Mode 0 2 read-write AB_MODE_0 No alpha Blending (The SAFETY_EN bit need set to 1) 0 AB_MODE_1 Blend with global ALPHA 0x1 AB_MODE_2 Blend with embedded ALPHA 0x2 AB_MODE_3 Blend with PoterDuff enable 0x3 PD_FACTOR_MODE PoterDuff factor mode 4 2 read-write PD_FACTOR_MODE_0 Using 1 0 PD_FACTOR_MODE_1 Using 0 0x1 PD_FACTOR_MODE_2 Using straight alpha 0x2 PD_FACTOR_MODE_3 Using inverse alpha 0x3 PD_GLOBAL_ALPHA_MODE PoterDuff global alpha mode 6 2 read-write PD_GLOBAL_ALPHA_MODE_0 Using global alpha 0 PD_GLOBAL_ALPHA_MODE_1 Using local alpha 0x1 PD_GLOBAL_ALPHA_MODE_2 Using scaled alpha 0x2 PD_GLOBAL_ALPHA_MODE_3 Using scaled alpha 0x3 PD_ALPHA_MODE PoterDuff alpha mode 8 1 read-write PD_ALPHA_MODE_0 Straight mode for Porter Duff alpha 0 PD_ALPHA_MODE_1 Inversed mode for Porter Duff alpha 0x1 PD_COLOR_MODE PoterDuff alpha mode 9 1 read-write PD_COLOR_MODE_0 Straight mode for Porter Duff color 0 PD_COLOR_MODE_1 Inversed mode for Porter Duff color 0x1 YUV_FORMAT The YUV422 input format selection 14 2 read-write YUV_FORMAT_0 The YVYU422 8bit sequence is U1,Y1,V1,Y2 0 YUV_FORMAT_1 The YVYU422 8bit sequence is V1,Y1,U1,Y2 0x1 YUV_FORMAT_2 The YVYU422 8bit sequence is Y1,U1,Y2,V1 0x2 YUV_FORMAT_3 The YVYU422 8bit sequence is Y1,V1,Y2,U1 0x3 GLOBAL_ALPHA Global Alpha 16 8 read-write BPP Layer encoding format (bit per pixel) 24 4 read-write BPP_0 1 bpp 0 BPP_1 2 bpp 0x1 BPP_2 4 bpp 0x2 BPP_3 8 bpp 0x3 BPP_4 16 bpp (RGB565) 0x4 BPP_5 16 bpp (ARGB1555) 0x5 BPP_6 16 bpp (ARGB4444) 0x6 BPP_7 YCbCr422 (Only layer 0/1 can support this format) 0x7 BPP_8 24 bpp (RGB888) 0x8 BPP_9 32 bpp (ARGB8888) 0x9 BPP_10 32 bpp (ABGR8888) 0xA SAFETY_EN Safety Mode Enable Bit 28 1 read-write SAFETY_EN_0 Safety Mode is disabled 0 SAFETY_EN_1 Safety Mode is enabled for this layer 0x1 SHADOW_LOAD_EN Shadow Load Enable 30 1 read-write EN Enable the layer for DMA 31 1 read-write EN_0 OFF 0 EN_1 ON 0x1 CTRLDESCL2_6 Control Descriptor Layer 6 Register 0x294 32 read-write 0 0xFFFFFFFF BCLR_B Background B component value 0 8 read-write BCLR_G Background G component value 8 8 read-write BCLR_R Background R component value 16 8 read-write CTRLDESCL3_1 Control Descriptor Layer 1 Register 0x2C0 32 read-write 0 0xFFFFFFFF WIDTH Width of the layer in pixels 0 12 read-write HEIGHT Height of the layer in pixels 16 12 read-write CTRLDESCL3_2 Control Descriptor Layer 2 Register 0x2C4 32 read-write 0 0xFFFFFFFF POSX The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, only positive values are to the right the left-hand column of the panel 0 12 read-write POSY The vertical position of top row of the layer, where 0 is the top row of the panel, only positive values are below the top row of the panel 16 12 read-write CTRLDESCL3_3 Control Descriptor Layer 3 Register 0x2C8 32 read-write 0 0xFFFFFFFF PITCH Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry 0 16 read-write CTRLDESCL3_4 Control Descriptor Layer 4 Register 0x2CC 32 read-write 0 0xFFFFFFFF ADDR Address of layer data in the memory. The address programmed should be 64-bit aligned 0 32 read-write CTRLDESCL3_5 Control Descriptor Layer 5 Register 0x2D0 32 read-write 0 0xFFFFFFFF AB_MODE Alpha Blending Mode 0 2 read-write AB_MODE_0 No alpha Blending (The SAFETY_EN bit need set to 1) 0 AB_MODE_1 Blend with global ALPHA 0x1 AB_MODE_2 Blend with embedded ALPHA 0x2 AB_MODE_3 Blend with PoterDuff enable 0x3 PD_FACTOR_MODE PoterDuff factor mode 4 2 read-write PD_FACTOR_MODE_0 Using 1 0 PD_FACTOR_MODE_1 Using 0 0x1 PD_FACTOR_MODE_2 Using straight alpha 0x2 PD_FACTOR_MODE_3 Using inverse alpha 0x3 PD_GLOBAL_ALPHA_MODE PoterDuff global alpha mode 6 2 read-write PD_GLOBAL_ALPHA_MODE_0 Using global alpha 0 PD_GLOBAL_ALPHA_MODE_1 Using local alpha 0x1 PD_GLOBAL_ALPHA_MODE_2 Using scaled alpha 0x2 PD_GLOBAL_ALPHA_MODE_3 Using scaled alpha 0x3 PD_ALPHA_MODE PoterDuff alpha mode 8 1 read-write PD_ALPHA_MODE_0 Straight mode for Porter Duff alpha 0 PD_ALPHA_MODE_1 Inversed mode for Porter Duff alpha 0x1 PD_COLOR_MODE PoterDuff alpha mode 9 1 read-write PD_COLOR_MODE_0 Straight mode for Porter Duff color 0 PD_COLOR_MODE_1 Inversed mode for Porter Duff color 0x1 YUV_FORMAT The YUV422 input format selection 14 2 read-write YUV_FORMAT_0 The YVYU422 8bit sequence is U1,Y1,V1,Y2 0 YUV_FORMAT_1 The YVYU422 8bit sequence is V1,Y1,U1,Y2 0x1 YUV_FORMAT_2 The YVYU422 8bit sequence is Y1,U1,Y2,V1 0x2 YUV_FORMAT_3 The YVYU422 8bit sequence is Y1,V1,Y2,U1 0x3 GLOBAL_ALPHA Global Alpha 16 8 read-write BPP Layer encoding format (bit per pixel) 24 4 read-write BPP_0 1 bpp 0 BPP_1 2 bpp 0x1 BPP_2 4 bpp 0x2 BPP_3 8 bpp 0x3 BPP_4 16 bpp (RGB565) 0x4 BPP_5 16 bpp (ARGB1555) 0x5 BPP_6 16 bpp (ARGB4444) 0x6 BPP_7 YCbCr422 (Only layer 0/1 can support this format) 0x7 BPP_8 24 bpp (RGB888) 0x8 BPP_9 32 bpp (ARGB8888) 0x9 BPP_10 32 bpp (ABGR8888) 0xA SAFETY_EN Safety Mode Enable Bit 28 1 read-write SAFETY_EN_0 Safety Mode is disabled 0 SAFETY_EN_1 Safety Mode is enabled for this layer 0x1 SHADOW_LOAD_EN Shadow Load Enable 30 1 read-write EN Enable the layer for DMA 31 1 read-write EN_0 OFF 0 EN_1 ON 0x1 CTRLDESCL3_6 Control Descriptor Layer 6 Register 0x2D4 32 read-write 0 0xFFFFFFFF BCLR_B Background B component value 0 8 read-write BCLR_G Background G component value 8 8 read-write BCLR_R Background R component value 16 8 read-write CTRLDESCL4_1 Control Descriptor Layer 1 Register 0x300 32 read-write 0 0xFFFFFFFF WIDTH Width of the layer in pixels 0 12 read-write HEIGHT Height of the layer in pixels 16 12 read-write CTRLDESCL4_2 Control Descriptor Layer 2 Register 0x304 32 read-write 0 0xFFFFFFFF POSX The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, only positive values are to the right the left-hand column of the panel 0 12 read-write POSY The vertical position of top row of the layer, where 0 is the top row of the panel, only positive values are below the top row of the panel 16 12 read-write CTRLDESCL4_3 Control Descriptor Layer 3 Register 0x308 32 read-write 0 0xFFFFFFFF PITCH Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry 0 16 read-write CTRLDESCL4_4 Control Descriptor Layer 4 Register 0x30C 32 read-write 0 0xFFFFFFFF ADDR Address of layer data in the memory. The address programmed should be 64-bit aligned 0 32 read-write CTRLDESCL4_5 Control Descriptor Layer 5 Register 0x310 32 read-write 0 0xFFFFFFFF AB_MODE Alpha Blending Mode 0 2 read-write AB_MODE_0 No alpha Blending (The SAFETY_EN bit need set to 1) 0 AB_MODE_1 Blend with global ALPHA 0x1 AB_MODE_2 Blend with embedded ALPHA 0x2 AB_MODE_3 Blend with PoterDuff enable 0x3 PD_FACTOR_MODE PoterDuff factor mode 4 2 read-write PD_FACTOR_MODE_0 Using 1 0 PD_FACTOR_MODE_1 Using 0 0x1 PD_FACTOR_MODE_2 Using straight alpha 0x2 PD_FACTOR_MODE_3 Using inverse alpha 0x3 PD_GLOBAL_ALPHA_MODE PoterDuff global alpha mode 6 2 read-write PD_GLOBAL_ALPHA_MODE_0 Using global alpha 0 PD_GLOBAL_ALPHA_MODE_1 Using local alpha 0x1 PD_GLOBAL_ALPHA_MODE_2 Using scaled alpha 0x2 PD_GLOBAL_ALPHA_MODE_3 Using scaled alpha 0x3 PD_ALPHA_MODE PoterDuff alpha mode 8 1 read-write PD_ALPHA_MODE_0 Straight mode for Porter Duff alpha 0 PD_ALPHA_MODE_1 Inversed mode for Porter Duff alpha 0x1 PD_COLOR_MODE PoterDuff alpha mode 9 1 read-write PD_COLOR_MODE_0 Straight mode for Porter Duff color 0 PD_COLOR_MODE_1 Inversed mode for Porter Duff color 0x1 YUV_FORMAT The YUV422 input format selection 14 2 read-write YUV_FORMAT_0 The YVYU422 8bit sequence is U1,Y1,V1,Y2 0 YUV_FORMAT_1 The YVYU422 8bit sequence is V1,Y1,U1,Y2 0x1 YUV_FORMAT_2 The YVYU422 8bit sequence is Y1,U1,Y2,V1 0x2 YUV_FORMAT_3 The YVYU422 8bit sequence is Y1,V1,Y2,U1 0x3 GLOBAL_ALPHA Global Alpha 16 8 read-write BPP Layer encoding format (bit per pixel) 24 4 read-write BPP_0 1 bpp 0 BPP_1 2 bpp 0x1 BPP_2 4 bpp 0x2 BPP_3 8 bpp 0x3 BPP_4 16 bpp (RGB565) 0x4 BPP_5 16 bpp (ARGB1555) 0x5 BPP_6 16 bpp (ARGB4444) 0x6 BPP_7 YCbCr422 (Only layer 0/1 can support this format) 0x7 BPP_8 24 bpp (RGB888) 0x8 BPP_9 32 bpp (ARGB8888) 0x9 BPP_10 32 bpp (ABGR8888) 0xA SAFETY_EN Safety Mode Enable Bit 28 1 read-write SAFETY_EN_0 Safety Mode is disabled 0 SAFETY_EN_1 Safety Mode is enabled for this layer 0x1 SHADOW_LOAD_EN Shadow Load Enable 30 1 read-write EN Enable the layer for DMA 31 1 read-write EN_0 OFF 0 EN_1 ON 0x1 CTRLDESCL4_6 Control Descriptor Layer 6 Register 0x314 32 read-write 0 0xFFFFFFFF BCLR_B Background B component value 0 8 read-write BCLR_G Background G component value 8 8 read-write BCLR_R Background R component value 16 8 read-write CTRLDESCL5_1 Control Descriptor Layer 1 Register 0x340 32 read-write 0 0xFFFFFFFF WIDTH Width of the layer in pixels 0 12 read-write HEIGHT Height of the layer in pixels 16 12 read-write CTRLDESCL5_2 Control Descriptor Layer 2 Register 0x344 32 read-write 0 0xFFFFFFFF POSX The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, only positive values are to the right the left-hand column of the panel 0 12 read-write POSY The vertical position of top row of the layer, where 0 is the top row of the panel, only positive values are below the top row of the panel 16 12 read-write CTRLDESCL5_3 Control Descriptor Layer 3 Register 0x348 32 read-write 0 0xFFFFFFFF PITCH Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry 0 16 read-write CTRLDESCL5_4 Control Descriptor Layer 4 Register 0x34C 32 read-write 0 0xFFFFFFFF ADDR Address of layer data in the memory. The address programmed should be 64-bit aligned 0 32 read-write CTRLDESCL5_5 Control Descriptor Layer 5 Register 0x350 32 read-write 0 0xFFFFFFFF AB_MODE Alpha Blending Mode 0 2 read-write AB_MODE_0 No alpha Blending (The SAFETY_EN bit need set to 1) 0 AB_MODE_1 Blend with global ALPHA 0x1 AB_MODE_2 Blend with embedded ALPHA 0x2 AB_MODE_3 Blend with PoterDuff enable 0x3 PD_FACTOR_MODE PoterDuff factor mode 4 2 read-write PD_FACTOR_MODE_0 Using 1 0 PD_FACTOR_MODE_1 Using 0 0x1 PD_FACTOR_MODE_2 Using straight alpha 0x2 PD_FACTOR_MODE_3 Using inverse alpha 0x3 PD_GLOBAL_ALPHA_MODE PoterDuff global alpha mode 6 2 read-write PD_GLOBAL_ALPHA_MODE_0 Using global alpha 0 PD_GLOBAL_ALPHA_MODE_1 Using local alpha 0x1 PD_GLOBAL_ALPHA_MODE_2 Using scaled alpha 0x2 PD_GLOBAL_ALPHA_MODE_3 Using scaled alpha 0x3 PD_ALPHA_MODE PoterDuff alpha mode 8 1 read-write PD_ALPHA_MODE_0 Straight mode for Porter Duff alpha 0 PD_ALPHA_MODE_1 Inversed mode for Porter Duff alpha 0x1 PD_COLOR_MODE PoterDuff alpha mode 9 1 read-write PD_COLOR_MODE_0 Straight mode for Porter Duff color 0 PD_COLOR_MODE_1 Inversed mode for Porter Duff color 0x1 YUV_FORMAT The YUV422 input format selection 14 2 read-write YUV_FORMAT_0 The YVYU422 8bit sequence is U1,Y1,V1,Y2 0 YUV_FORMAT_1 The YVYU422 8bit sequence is V1,Y1,U1,Y2 0x1 YUV_FORMAT_2 The YVYU422 8bit sequence is Y1,U1,Y2,V1 0x2 YUV_FORMAT_3 The YVYU422 8bit sequence is Y1,V1,Y2,U1 0x3 GLOBAL_ALPHA Global Alpha 16 8 read-write BPP Layer encoding format (bit per pixel) 24 4 read-write BPP_0 1 bpp 0 BPP_1 2 bpp 0x1 BPP_2 4 bpp 0x2 BPP_3 8 bpp 0x3 BPP_4 16 bpp (RGB565) 0x4 BPP_5 16 bpp (ARGB1555) 0x5 BPP_6 16 bpp (ARGB4444) 0x6 BPP_7 YCbCr422 (Only layer 0/1 can support this format) 0x7 BPP_8 24 bpp (RGB888) 0x8 BPP_9 32 bpp (ARGB8888) 0x9 BPP_10 32 bpp (ABGR8888) 0xA SAFETY_EN Safety Mode Enable Bit 28 1 read-write SAFETY_EN_0 Safety Mode is disabled 0 SAFETY_EN_1 Safety Mode is enabled for this layer 0x1 SHADOW_LOAD_EN Shadow Load Enable 30 1 read-write EN Enable the layer for DMA 31 1 read-write EN_0 OFF 0 EN_1 ON 0x1 CTRLDESCL5_6 Control Descriptor Layer 6 Register 0x354 32 read-write 0 0xFFFFFFFF BCLR_B Background B component value 0 8 read-write BCLR_G Background G component value 8 8 read-write BCLR_R Background R component value 16 8 read-write CTRLDESCL6_1 Control Descriptor Layer 1 Register 0x380 32 read-write 0 0xFFFFFFFF WIDTH Width of the layer in pixels 0 12 read-write HEIGHT Height of the layer in pixels 16 12 read-write CTRLDESCL6_2 Control Descriptor Layer 2 Register 0x384 32 read-write 0 0xFFFFFFFF POSX The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, only positive values are to the right the left-hand column of the panel 0 12 read-write POSY The vertical position of top row of the layer, where 0 is the top row of the panel, only positive values are below the top row of the panel 16 12 read-write CTRLDESCL6_3 Control Descriptor Layer 3 Register 0x388 32 read-write 0 0xFFFFFFFF PITCH Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry 0 16 read-write CTRLDESCL6_4 Control Descriptor Layer 4 Register 0x38C 32 read-write 0 0xFFFFFFFF ADDR Address of layer data in the memory. The address programmed should be 64-bit aligned 0 32 read-write CTRLDESCL6_5 Control Descriptor Layer 5 Register 0x390 32 read-write 0 0xFFFFFFFF AB_MODE Alpha Blending Mode 0 2 read-write AB_MODE_0 No alpha Blending (The SAFETY_EN bit need set to 1) 0 AB_MODE_1 Blend with global ALPHA 0x1 AB_MODE_2 Blend with embedded ALPHA 0x2 AB_MODE_3 Blend with PoterDuff enable 0x3 PD_FACTOR_MODE PoterDuff factor mode 4 2 read-write PD_FACTOR_MODE_0 Using 1 0 PD_FACTOR_MODE_1 Using 0 0x1 PD_FACTOR_MODE_2 Using straight alpha 0x2 PD_FACTOR_MODE_3 Using inverse alpha 0x3 PD_GLOBAL_ALPHA_MODE PoterDuff global alpha mode 6 2 read-write PD_GLOBAL_ALPHA_MODE_0 Using global alpha 0 PD_GLOBAL_ALPHA_MODE_1 Using local alpha 0x1 PD_GLOBAL_ALPHA_MODE_2 Using scaled alpha 0x2 PD_GLOBAL_ALPHA_MODE_3 Using scaled alpha 0x3 PD_ALPHA_MODE PoterDuff alpha mode 8 1 read-write PD_ALPHA_MODE_0 Straight mode for Porter Duff alpha 0 PD_ALPHA_MODE_1 Inversed mode for Porter Duff alpha 0x1 PD_COLOR_MODE PoterDuff alpha mode 9 1 read-write PD_COLOR_MODE_0 Straight mode for Porter Duff color 0 PD_COLOR_MODE_1 Inversed mode for Porter Duff color 0x1 YUV_FORMAT The YUV422 input format selection 14 2 read-write YUV_FORMAT_0 The YVYU422 8bit sequence is U1,Y1,V1,Y2 0 YUV_FORMAT_1 The YVYU422 8bit sequence is V1,Y1,U1,Y2 0x1 YUV_FORMAT_2 The YVYU422 8bit sequence is Y1,U1,Y2,V1 0x2 YUV_FORMAT_3 The YVYU422 8bit sequence is Y1,V1,Y2,U1 0x3 GLOBAL_ALPHA Global Alpha 16 8 read-write BPP Layer encoding format (bit per pixel) 24 4 read-write BPP_0 1 bpp 0 BPP_1 2 bpp 0x1 BPP_2 4 bpp 0x2 BPP_3 8 bpp 0x3 BPP_4 16 bpp (RGB565) 0x4 BPP_5 16 bpp (ARGB1555) 0x5 BPP_6 16 bpp (ARGB4444) 0x6 BPP_7 YCbCr422 (Only layer 0/1 can support this format) 0x7 BPP_8 24 bpp (RGB888) 0x8 BPP_9 32 bpp (ARGB8888) 0x9 BPP_10 32 bpp (ABGR8888) 0xA SAFETY_EN Safety Mode Enable Bit 28 1 read-write SAFETY_EN_0 Safety Mode is disabled 0 SAFETY_EN_1 Safety Mode is enabled for this layer 0x1 SHADOW_LOAD_EN Shadow Load Enable 30 1 read-write EN Enable the layer for DMA 31 1 read-write EN_0 OFF 0 EN_1 ON 0x1 CTRLDESCL6_6 Control Descriptor Layer 6 Register 0x394 32 read-write 0 0xFFFFFFFF BCLR_B Background B component value 0 8 read-write BCLR_G Background G component value 8 8 read-write BCLR_R Background R component value 16 8 read-write CTRLDESCL7_1 Control Descriptor Layer 1 Register 0x3C0 32 read-write 0 0xFFFFFFFF WIDTH Width of the layer in pixels 0 12 read-write HEIGHT Height of the layer in pixels 16 12 read-write CTRLDESCL7_2 Control Descriptor Layer 2 Register 0x3C4 32 read-write 0 0xFFFFFFFF POSX The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, only positive values are to the right the left-hand column of the panel 0 12 read-write POSY The vertical position of top row of the layer, where 0 is the top row of the panel, only positive values are below the top row of the panel 16 12 read-write CTRLDESCL7_3 Control Descriptor Layer 3 Register 0x3C8 32 read-write 0 0xFFFFFFFF PITCH Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry 0 16 read-write CTRLDESCL7_4 Control Descriptor Layer 4 Register 0x3CC 32 read-write 0 0xFFFFFFFF ADDR Address of layer data in the memory. The address programmed should be 64-bit aligned 0 32 read-write CTRLDESCL7_5 Control Descriptor Layer 5 Register 0x3D0 32 read-write 0 0xFFFFFFFF AB_MODE Alpha Blending Mode 0 2 read-write AB_MODE_0 No alpha Blending (The SAFETY_EN bit need set to 1) 0 AB_MODE_1 Blend with global ALPHA 0x1 AB_MODE_2 Blend with embedded ALPHA 0x2 AB_MODE_3 Blend with PoterDuff enable 0x3 PD_FACTOR_MODE PoterDuff factor mode 4 2 read-write PD_FACTOR_MODE_0 Using 1 0 PD_FACTOR_MODE_1 Using 0 0x1 PD_FACTOR_MODE_2 Using straight alpha 0x2 PD_FACTOR_MODE_3 Using inverse alpha 0x3 PD_GLOBAL_ALPHA_MODE PoterDuff global alpha mode 6 2 read-write PD_GLOBAL_ALPHA_MODE_0 Using global alpha 0 PD_GLOBAL_ALPHA_MODE_1 Using local alpha 0x1 PD_GLOBAL_ALPHA_MODE_2 Using scaled alpha 0x2 PD_GLOBAL_ALPHA_MODE_3 Using scaled alpha 0x3 PD_ALPHA_MODE PoterDuff alpha mode 8 1 read-write PD_ALPHA_MODE_0 Straight mode for Porter Duff alpha 0 PD_ALPHA_MODE_1 Inversed mode for Porter Duff alpha 0x1 PD_COLOR_MODE PoterDuff alpha mode 9 1 read-write PD_COLOR_MODE_0 Straight mode for Porter Duff color 0 PD_COLOR_MODE_1 Inversed mode for Porter Duff color 0x1 YUV_FORMAT The YUV422 input format selection 14 2 read-write YUV_FORMAT_0 The YVYU422 8bit sequence is U1,Y1,V1,Y2 0 YUV_FORMAT_1 The YVYU422 8bit sequence is V1,Y1,U1,Y2 0x1 YUV_FORMAT_2 The YVYU422 8bit sequence is Y1,U1,Y2,V1 0x2 YUV_FORMAT_3 The YVYU422 8bit sequence is Y1,V1,Y2,U1 0x3 GLOBAL_ALPHA Global Alpha 16 8 read-write BPP Layer encoding format (bit per pixel) 24 4 read-write BPP_0 1 bpp 0 BPP_1 2 bpp 0x1 BPP_2 4 bpp 0x2 BPP_3 8 bpp 0x3 BPP_4 16 bpp (RGB565) 0x4 BPP_5 16 bpp (ARGB1555) 0x5 BPP_6 16 bpp (ARGB4444) 0x6 BPP_7 YCbCr422 (Only layer 0/1 can support this format) 0x7 BPP_8 24 bpp (RGB888) 0x8 BPP_9 32 bpp (ARGB8888) 0x9 BPP_10 32 bpp (ABGR8888) 0xA SAFETY_EN Safety Mode Enable Bit 28 1 read-write SAFETY_EN_0 Safety Mode is disabled 0 SAFETY_EN_1 Safety Mode is enabled for this layer 0x1 SHADOW_LOAD_EN Shadow Load Enable 30 1 read-write EN Enable the layer for DMA 31 1 read-write EN_0 OFF 0 EN_1 ON 0x1 CTRLDESCL7_6 Control Descriptor Layer 6 Register 0x3D4 32 read-write 0 0xFFFFFFFF BCLR_B Background B component value 0 8 read-write BCLR_G Background G component value 8 8 read-write BCLR_R Background R component value 16 8 read-write CLUT_LOAD LCDIFv2 CLUT load Register 0x400 32 read-write 0 0xFFFFFFFF CLUT_UPDATE_EN CLUT Update Enable 0 1 read-write SEL_CLUT_NUM Selected CLUT Number 4 3 read-write DSI_HOST DSI HOST DSI_HOST 0x4080C000 0 0x34 registers MIPI_DSI 59 CFG_NUM_LANES CFG_NUM_LANES 0 32 read-write 0 0xFFFFFFFF NUM_LANES Sets the number of active lanes that are to be used for transmitting data. 0 2 read-write NUM_LANES_0 1 lane 0 NUM_LANES_1 2 lanes 0x1 CFG_NONCONTINUOUS_CLK CFG_NONCONTINUOUS_CLK 0x4 32 read-write 0 0xFFFFFFFF CLK_MODE Sets the Host Controller into non-continuous MIPI clock mode. When in non-continuous clock mode, the high speed clock will transition into low power mode between transmissions. 0 1 read-write CLK_MODE_0 Continuous high speed clock 0 CLK_MODE_1 Non-Continuous high speed clock 0x1 CFG_T_PRE CFG_T_PRE 0x8 32 read-write 0 0xFFFFFFFF NUM_PERIODS Sets the number of byte clock periods ('clk_byte' input) that the controller will wait after enabling the clock lane for HS operation before enabling the data lanes for HS operation. This setting represents the TCLK-PRE DPHY timing parameter. The minimum value for this port is 1. 0 8 read-write CFG_T_POST CFG_T_POST 0xC 32 read-write 0 0xFFFFFFFF NUM_PERIODS Sets the number of byte clock periods ('clk_byte' input) to wait before putting the clock lane into LP mode after the data lanes have been detected to be in Stop State. This setting represents the DPHY timing parameters TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE requirement for the clock lane before the data lane is allowed to change from LP11 to start a high speed transmission. The minimum value for this port is 1. 0 8 read-write CFG_TX_GAP CFG_TX_GAP 0x10 32 read-write 0 0xFFFFFFFF NUM_PERIODS Sets the number of byte clock periods ('clk_byte' input) that the controller will wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode again. This setting represents the THS-EXIT DPHY timing parameter. The minimum value for this port is 1. 0 8 read-write CFG_AUTOINSERT_EOTP CFG_AUTOINSERT_ETOP 0x14 32 read-write 0 0xFFFFFFFF AUTOINSERT Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode. 0 1 read-write NOT_AUTO EoTp is not automatically inserted 0 AUTO EoTp is automatically inserted 0x1 CFG_EXTRA_CMDS_AFTER_EOTP CFG_EXTRA_CMDS_AFTER_ETOP 0x18 32 read-write 0 0xFFFFFFFF EXTRA_EOTP Configures the DSI Host Controller to send extra End Of Transmission Packets after the end of a packet. The value is the number of extra EOTP packets sent. 0 8 read-write CFG_HTX_TO_COUNT CFG_HTX_TO_COUNT 0x1C 32 read-write 0 0xFFFFFFFF COUNT Sets the value of the DSI Host High Speed TX timeout count in clk_byte clock periods that once reached will initiate a timeout error and follow the recovery procedure documented in the DSI specification. 0 24 read-write CFG_LRX_H_TO_COUNT CFG_LRX_H_TO_COUNT 0x20 32 read-write 0 0xFFFFFFFF COUNT Sets the value of the DSI Host low power RX timeout count in clk_byte clock periods that once reached will initiate a timeout error and follow the recovery procedure documented in the DSI specification. 0 24 read-write CFG_BTA_H_TO_COUNT CFG_BTA_H_TO_COUNT 0x24 32 read-write 0 0xFFFFFFFF COUNT Sets the value of the DSI Host Bus Turn Around (BTA) timeout in clk_byte clock periods that once reached will initiate a timeout error. 0 24 read-write CFG_TWAKEUP CFG_TWAKEUP 0x28 32 read-write 0 0xFFFFFFFF NUM_PERIODS DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods to keep a clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a minimum of 1ms in Mark-1 state after leaving ULPS. 0 19 read-write CFG_STATUS_OUT CFG_STATUS_OUT 0x2C 32 read-only 0 0xFFFFFFFF STATUS Status Register 0 32 read-only RX_ERROR_STATUS RX_ERROR_STATUS 0x30 32 read-only 0 0xFFFFFFFF STATUS Status Register for Host receive error detection, ECC errors, CRC errors and for timeout indicators 0 11 read-only DSI_HOST_DPI_INTFC DSI Host DPI Interface DSI_HOST_DPI_INTFC 0x4080C200 0 0x40 registers PIXEL_PAYLOAD_SIZE PEXEL_PAYLOAD_SIZE 0 32 read-write 0 0xFFFFFFFF PAYLOAD_SIZE Maximum number of pixels that should be sent as one DSI packet. Recommended to be evenly divisible by the line size (in pixels). 0 16 read-write PIXEL_FIFO_SEND_LEVEL PIXEL_FIFO_SEND_LEVEL 0x4 32 read-write 0 0xFFFFFFFF FIFO_SEND_LEVEL In order to optimize DSI utility, the DPI bridge buffers a certain number of DPI pixels before initiating a DSI packet. This configuration port controls the level at which the DPI Host bridge begins sending pixels. 0 16 read-write INTERFACE_COLOR_CODING INTERFACE_COLOR_CODING 0x8 32 read-write 0 0xFFFFFFFF RGB_CONFIG Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification. 0 3 read-write RGB_CONFIG_0 16-bit Configuration 1 0 RGB_CONFIG_1 16-bit Configuration 2 0x1 RGB_CONFIG_2 16-bit Configuration 3 0x2 RGB_CONFIG_3 18-bit Configuration 1 0x3 RGB_CONFIG_4 18-bit Configuration 2 0x4 RGB_CONFIG_5 24-bit 0x5 PIXEL_FORMAT PIXEL_FORMAT 0xC 32 read-write 0 0xFFFFFFFF PIXEL_FORMAT Sets the DSI packet type of the pixels 0 2 read-write PIXEL_FORMAT_0 16 bit 0 PIXEL_FORMAT_1 18 bit 0x1 PIXEL_FORMAT_2 18 bit loosely packed 0x2 PIXEL_FORMAT_3 24 bit 0x3 VSYNC_POLARITY VSYNC_POLARITY 0x10 32 read-write 0 0xFFFFFFFF VSYNC_POLARITY Sets polarity of dpi_vsync_input 0 1 read-write VSYNC_POLARITY_0 active low 0 VSYNC_POLARITY_1 active high 0x1 HSYNC_POLARITY HSYNC_POLARITY 0x14 32 read-write 0 0xFFFFFFFF HSYNC_POLARITY Sets polarity of dpi_hsync_input 0 1 read-write HSYNC_POLARITY_0 active low 0 HSYNC_POLARITY_1 active high 0x1 VIDEO_MODE VIDEO_MODE 0x18 32 read-write 0 0xFFFFFFFF VIDEO_MODE Select DSI video mode that the host DPI module should generate packets for. 0 2 read-write VIDEO_MODE_0 Non-Burst mode with Sync Pulses 0 VIDEO_MODE_1 Non-Burst mode with Sync Events 0x1 VIDEO_MODE_2 Burst mode 0x2 HFP HFP 0x1C 32 read-write 0 0xFFFFFFFF PAYLOAD_SIZE Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet. 0 16 read-write HBP HBP 0x20 32 read-write 0 0xFFFFFFFF PAYLOAD_SIZE Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet. 0 16 read-write HSA HSA 0x24 32 read-write 0 0xFFFFFFFF PAYLOAD_SIZE Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet. 0 16 read-write ENABLE_MULT_PKTS ENABLE_MULT_PKTS 0x28 32 read-write 0 0xFFFFFFFF ENABLE_MULT_PKTS Enable Multiple packets per video line. When enabled, PIXEL_PAYLOAD_SIZE[PAYLOAD_SIZE] must be set to exactly half the size of the video line 0 1 read-write ENABLE_MULT_PKTS_0 Video Line is sent in a single packet 0 ENABLE_MULT_PKTS_1 Video Line is sent in two packets 0x1 VBP VBP 0x2C 32 read-write 0 0xFFFFFFFF NUM_LINES Sets the number of lines in the vertical back porch. 0 8 read-write VFP VFP 0x30 32 read-write 0 0xFFFFFFFF NUM_LINES Sets the number of lines in the vertical front porch. 0 8 read-write BLLP_MODE BLLP_MODE 0x34 32 read-write 0 0xFFFFFFFF LP Optimize bllp periods to Low Power mode when possible 0 1 read-write LP_0 Blanking packets are sent during BLLP periods 0 LP_1 LP mode is used for BLLP periods 0x1 USE_NULL_PKT_BLLP USE_NULL_PKT_BLLP 0x38 32 read-write 0 0xFFFFFFFF NULL Selects type of blanking packet to be sent during bllp 0 1 read-write NULL_0 Blanking packet used in bllp region 1 0 NULL_1 Null packet used in bllp region 0x1 VACTIVE VACTIVE 0x3C 32 read-write 0 0xFFFFFFFF NUM_LINES Sets the number of lines in the vertical active aread. 0 14 read-write DSI_HOST_APB_PKT_IF DSI HOST APB PKT Interface DSI_HOST_APB_PKT_IF 0x4080C280 0 0x30 registers TX_PAYLOAD TX_PAYLOAD 0 32 read-write 0 0xFFFFFFFF PAYLOAD Tx Payload data write register. Write to this register loads the payload FIFO with 32 bit values. 0 32 read-write PKT_CONTROL PKT_CONTROL 0x4 32 read-write 0 0xFFFFFFFF CTRL Tx packet control 0 27 read-write SEND_PACKET SEND_PACKET 0x8 32 read-write 0 0xFFFFFFFF TX_SEND Tx send packet, writing to this register causes the packet described in dsi_host_pkt_control to be sent. 0 1 read-write TX_SEND_0 Packet not sent 0 TX_SEND_1 Packet is sent 0x1 PKT_STATUS PKT_STATUS 0xC 32 read-only 0 0xFFFFFFFF STATUS Status of APB to packet interface. 0 9 read-only PKT_FIFO_WR_LEVEL PKT_FIFO_WR_LEVEL 0x10 32 read-only 0 0xFFFFFFFF WR Write level of APB to pkt interface FIFO 0 16 read-only PKT_FIFO_RD_LEVEL PKT_FIFO_RD_LEVEL 0x14 32 read-only 0 0xFFFFFFFF RD Read level of APB to pkt interface FIFO 0 16 read-only PKT_RX_PAYLOAD PKT_RX_PAYLOAD 0x18 32 read-only 0 0xFFFFFFFF PAYLOAD APB to pkt interface Rx payload read 0 32 read-only PKT_RX_PKT_HEADER PKT_RX_PKT_HEADER 0x1C 32 read-only 0 0xFFFFFFFF HEADER APB to pkt interface Rx packet header 0 24 read-only IRQ_STATUS IRQ_STATUS 0x20 32 read-only 0 0xFFFFFFFF STATUS Status of APB to packet interface. 0 32 read-only IRQ_STATUS2 IRQ_STATUS2 0x24 32 read-only 0 0xFFFFFFFF STATUS2 Status of APB to packet interface part 2, read part 2 first then dsi_host_irq_status. Reading dsi_host_irq_status will clear both status and status2. 0 3 read-only IRQ_MASK IRQ_MASK 0x28 32 read-write 0 0xFFFFFFFF MASK IRQ Mask 0 32 read-write IRQ_MASK2 IRQ_MASK2 0x2C 32 read-write 0 0xFFFFFFFF MASK2 IRQ mask 2 0 3 read-write DSI_HOST_DPHY_INTFC DSI HOST DPHY INTFC DSI_HOST_NXP_FDSOI28_DPHY_INTFC 0x4080C300 0 0x48 registers PD_TX PD_TX 0 32 read-write 0x1 0xFFFFFFFF PD_TX Power Down input for D-PHY 0 1 read-write PD_TX_0 Power Up 0 PD_TX_1 Power Down 0x1 M_PRG_HS_PREPARE M_PRG_HS_PREPARE 0x4 32 read-write 0 0xFFFFFFFF M_PRG_HS_PREPARE DPHY m_PRG_HS_PREPARE input 0 2 read-write MC_PRG_HS_PREPARE MC_PRG_HS_PREPARE 0x8 32 read-write 0 0xFFFFFFFF MC_PRG_HS_PREPARE DPHY mc_PRG_HS_PREPARE input 0 1 read-write M_PRG_HS_ZERO M_PRG_HS_ZERO 0xC 32 read-write 0 0xFFFFFFFF M_PRG_HS_ZERO DPHY m_PRG_HS_ZERO input 0 5 read-write MC_PRG_HS_ZERO MC_PRG_HS_ZERO 0x10 32 read-write 0 0xFFFFFFFF MC_PRG_HS_ZERO DPHY mc_PRG_HS_ZERO input 0 6 read-write M_PRG_HS_TRAIL M_PRG_HS_TRAIL 0x14 32 read-write 0 0xFFFFFFFF M_PRG_HS_TRAIL DPHY m_PRG_HS_TRAIL input 0 4 read-write MC_PRG_HS_TRAIL MC_PRG_HS_TRAIL 0x18 32 read-write 0 0xFFFFFFFF MC_PRG_HS_TRAIL DPHY mc_PRG_HS_TRAIL input 0 4 read-write PD_PLL PD_PLL 0x1C 32 read-write 0x1 0xFFFFFFFF PD_PLL Power-down signal 0 1 read-write PD_PLL_0 Power up PLL 0 PD_PLL_1 Power down PLL 0x1 TST TST 0x20 32 read-write 0x25 0xFFFFFFFF TST Test 0 6 read-write CN CN 0x24 32 read-write 0 0xFFFFFFFF CN Control N divider 0 5 read-write CM CM 0x28 32 read-write 0 0xFFFFFFFF CM Control M divider 0 8 read-write CO CO 0x2C 32 read-write 0 0xFFFFFFFF CO Control O divider 0 2 read-write CO_0 Divide by 1 0 CO_1 Divide by 2 0x1 CO_2 Divide by 4 0x2 CO_3 Divide by 8 0x3 LOCK LOCK 0x30 32 read-only 0 0xFFFFFFFF LOCK Lock Detect output 0 1 read-only LOCK_0 PLL not locked 0 LOCK_1 PLL has achieved frequency lock 0x1 LOCK_BYP LOCK_BYP 0x34 32 read-write 0 0xFFFFFFFF LOCK_BYP DPHY LOCK_BYP input 0 1 read-write GATE PLL LOCK signal will gate TxByteClkHS clock 0 NOGATE PLL LOCK signal will not gate TxByteClkHS clock, CIL based counter will be used to gate the TxByteClkHS 0x1 TX_RCAL TX_RCAL 0x38 32 read-write 0 0xFFFFFFFF TX_RCAL On-chip termination control bits for manual calibration of HS-TX 0 2 read-write TX_RCAL_0 20% higher than mid-range. Highest impedance setting 0 TX_RCAL_1 Mid-range impedance setting (default) 0x1 TX_RCAL_2 15% lower than mid-range 0x2 TX_RCAL_3 25% lower than mid-range. Lowest impedance setting 0x3 AUTO_PD_EN AUTO_PD_EN 0x3C 32 read-write 0 0xFFFFFFFF AUTO_PD_EN DPHY AUTO_PD_EN input 0 1 read-write PWR_UP Inactive lanes are powered up and driving LP11 0 PWR_DWN inactive lanes are powered down 0x1 RXLPRP RXLPRP 0x40 32 read-write 0 0xFFFFFFFF RXLPRP DPHY RXLPRP input 0 2 read-write RXCDRP RXCDRP 0x44 32 read-write 0 0xFFFFFFFF RXCDRP DPHY RXCDRP input 0 2 read-write RXCDRP_0 344mV 0 RXCDRP_1 325mV (Default) 0x1 RXCDRP_2 307mV 0x2 RXCDRP_3 Invalid 0x3 MIPI_CSI2RX no description available MIPI_CSI2RX 0x40810000 0 0x19C registers MIPI_CSI 58 CFG_NUM_LANES Lane Configuration Register 0x100 32 read-write 0 0xFFFFFFFF CFG_NUM_LANES This field is used to set the number of active lanes for receiving data. 0 2 read-write CFG_NUM_LANES_0 1 Lane 0 CFG_NUM_LANES_1 2 Lane 0x1 CFG_DISABLE_DATA_LANES Disable Data Lane Register 0x104 32 read-write 0xF 0xFFFFFFFF CFG_DISABLE_DATA_LANES This field is used to disable data lanes. 0 4 read-write BIT_ERR ECC and CRC Error Status Register 0x108 32 read-only 0 0xFFFFFFFF BIT_ERR This field shows the error status of ECC and CRC 0 10 read-only IRQ_STATUS IRQ Status Register 0x10C 32 read-only 0 0xFFFFFFFF IRQ_STATUS This field shows the IRQ status 0 9 read-only IRQ_MASK IRQ Mask Setting Register 0x110 32 read-write 0 0xFFFFFFFF IRQ_MASK This field shows the IRQ Mask setting 0 9 read-write ULPS_STATUS Ultra Low Power State (ULPS) Status Register 0x114 32 read-only 0 0xFFFFFFFF STATUS This field shows the status of Rx D-PHY ULPS state 0 10 read-only PPI_ERRSOT_HS ERRSot HS Status Register 0x118 32 read-only 0 0xFFFFFFFF STATUS This field indicates PPI ErrSotHS captured status from D-PHY 0 4 read-only PPI_ERRSOTSYNC_HS ErrSotSync HS Status Register 0x11C 32 read-only 0 0xFFFFFFFF STATUS This field indicates PPI ErrSotSync_HS captured status from D-PHY 0 4 read-only PPI_ERRESC ErrEsc Status Register 0x120 32 read-only 0 0xFFFFFFFF STATUS This field indicates PPI ErrEsc captured status from D-PHY 0 4 read-only PPI_ERRSYNCESC ErrSyncEsc Status Register 0x124 32 read-only 0 0xFFFFFFFF STATUS This field indicates PPI ErrSyncEsc captured status from D-PHY 0 4 read-only PPI_ERRCONTROL ErrControl Status Register 0x128 32 read-only 0 0xFFFFFFFF STATUS This field indicates PPI ErrControl captured status from D-PHY 0 4 read-only CFG_DISABLE_PAYLOAD_0 Disable Payload 0 Register 0x12C 32 read-write 0 0xFFFFFFFF DIS_PAYLOAD_NULL Null 0 1 read-write DIS_PAYLOAD_BLANK Blank 1 1 read-write DIS_PAYLOAD_EMBEDDED Embedded 2 1 read-write DIS_PAYLOAD_YUV420 Legacy YUV 420 8 bit 10 1 read-write DIS_PAYLOAD_YUV422_8BIT YUV422 8 bit 14 1 read-write DIS_PAYLOAD_RGB444 RGB444 16 1 read-write DIS_PAYLOAD_RGB555 RGB555 17 1 read-write DIS_PAYLOAD_RGB565 RGB565 18 1 read-write DIS_PAYLOAD_RGB666 RGB666 19 1 read-write DIS_PAYLOAD_RGB888 RGB888 20 1 read-write CFG_DISABLE_PAYLOAD_1 Disable Payload 1 Register 0x130 32 read-write 0 0xFFFFFFFF DIS_PAYLOAD_UDEF_30 User defined type 0x31 0 1 read-write DIS_PAYLOAD_UDEF_31 User defined type 0x32 1 1 read-write DIS_PAYLOAD_UDEF_32 User defined type 0x33 2 1 read-write DIS_PAYLOAD_UDEF_33 User defined type 0x34 3 1 read-write DIS_PAYLOAD_UDEF_34 User defined type 0x35 4 1 read-write DIS_PAYLOAD_UDEF_35 User defined type 0x35 5 1 read-write DIS_PAYLOAD_UDEF_36 User defined type 0x36 6 1 read-write DIS_PAYLOAD_UDEF_37 User defined type 0x37 7 1 read-write DIS_PAYLOAD_UNSUPPORTED Unsupported Data Types 16 1 read-write CFG_IGNORE_VC Ignore Virtual Channel Register 0x180 32 read-write 0 0xFFFFFFFF IGNORE_VC When set, this input causes the interface to ignore the Virtual Channel (VC) field in received packets 0 1 read-write CFG_VID_VC Virtual Channel value Register 0x184 32 read-write 0 0xFFFFFFFF VID_VC This bit field sets the Virtual Channel value the interface must match in an incoming packet for it to accept the packet 0 2 read-write CFG_VID_P_FIFO_SEND_LEVEL FIFO Send Level Configuration Register 0x188 32 read-write 0 0xFFFFFFFF SEND_LEVEL FIFO Send Level field 0 16 read-write CFG_VID_VSYNC VSYNC Configuration Register 0x18C 32 read-write 0 0xFFFFFFFF WIDTH Width of VSYNC 0 8 read-write CFG_VID_HSYNC_FP Start of HSYNC Delay control Register 0x190 32 read-write 0 0xFFFFFFFF DELAY_CTL Delay control for beginning of HSYNC pulse 0 8 read-write CFG_VID_HSYNC HSYNC Configuration Register 0x194 32 read-write 0 0xFFFFFFFF WIDTH Width of HSYNC 0 8 read-write CFG_VID_HSYNC_BP End of HSYNC Delay Control Register 0x198 32 read-write 0 0xFFFFFFFF DELAY_CTL Delay Control for end of HSYNC pulse 0 8 read-write PXP PXP v2.0 Register Reference Index PXP PXP_ 0x40814000 0 0x444 registers PXP 57 CTRL Control Register 0 0 32 read-write 0xC0000000 0xFFFFFFFF ENABLE Enables PXP operation with specified parameters 0 1 read-write Disabled PXP is disabled 0 Enabled PXP is enabled 0x1 IRQ_ENABLE Interrupt enable When using the PXP_NEXT functionality to reprogram the PXP, the new value of this bit will be used and may therefore enable or disable an interrupt unintentionally 1 1 read-write Disabled PXP interrupt is disabled 0 Enabled PXP interrupt is enabled 0x1 NEXT_IRQ_ENABLE Next command interrupt enable 2 1 read-write Disabled Disabled 0 Enabled Enabled 0x1 ENABLE_LCD_HANDSHAKE Enable handshake with LCD controller 4 1 read-write ROTATE Indicates the clockwise rotation to be applied at the output buffer 8 2 read-write ROT_0 ROT_0 0 ROT_90 ROT_90 0x1 ROT_180 ROT_180 0x2 ROT_270 ROT_270 0x3 HFLIP Indicates that the output buffer should be flipped horizontally (effect applied before rotation). 10 1 read-write Disabled Horizontal Flip is disabled 0 Enabled Horizontal Flip is enabled 0x1 VFLIP Indicates that the output buffer should be flipped vertically (effect applied before rotation). 11 1 read-write Disabled Vertical Flip is disabled 0 Enabled Vertical Flip is enabled 0x1 ROT_POS This bit controls where rotation will occur in the PXP datapath 22 1 read-write BLOCK_SIZE Select the block size to process. 23 1 read-write 8X8 Process 8x8 pixel blocks. 0 16X16 Process 16x16 pixel blocks. 0x1 EN_REPEAT Enable the PXP to run continuously 28 1 read-write Complete PXP will complete the process and enter the idle state ready to accept the next frame to be processed 0 Repeat PXP will repeat based on the current configuration register settings 0x1 CLKGATE This bit must be set to zero for normal operation 30 1 read-write Normal Normal operation 0 Gated All clocks to PXP is gated-off 0x1 SFTRST This bit can be turned on and then off to reset the PXP block to its default state. 31 1 read-write Enabled Normal PXP operation is enabled 0 Disabled Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. 0x1 CTRL_SET Control Register 0 0x4 32 read-write 0xC0000000 0xFFFFFFFF ENABLE Enables PXP operation with specified parameters 0 1 read-write Disabled PXP is disabled 0 Enabled PXP is enabled 0x1 IRQ_ENABLE Interrupt enable When using the PXP_NEXT functionality to reprogram the PXP, the new value of this bit will be used and may therefore enable or disable an interrupt unintentionally 1 1 read-write Disabled PXP interrupt is disabled 0 Enabled PXP interrupt is enabled 0x1 NEXT_IRQ_ENABLE Next command interrupt enable 2 1 read-write Disabled Disabled 0 Enabled Enabled 0x1 ENABLE_LCD_HANDSHAKE Enable handshake with LCD controller 4 1 read-write ROTATE Indicates the clockwise rotation to be applied at the output buffer 8 2 read-write ROT_0 ROT_0 0 ROT_90 ROT_90 0x1 ROT_180 ROT_180 0x2 ROT_270 ROT_270 0x3 HFLIP Indicates that the output buffer should be flipped horizontally (effect applied before rotation). 10 1 read-write Disabled Horizontal Flip is disabled 0 Enabled Horizontal Flip is enabled 0x1 VFLIP Indicates that the output buffer should be flipped vertically (effect applied before rotation). 11 1 read-write Disabled Vertical Flip is disabled 0 Enabled Vertical Flip is enabled 0x1 ROT_POS This bit controls where rotation will occur in the PXP datapath 22 1 read-write BLOCK_SIZE Select the block size to process. 23 1 read-write 8X8 Process 8x8 pixel blocks. 0 16X16 Process 16x16 pixel blocks. 0x1 EN_REPEAT Enable the PXP to run continuously 28 1 read-write Complete PXP will complete the process and enter the idle state ready to accept the next frame to be processed 0 Repeat PXP will repeat based on the current configuration register settings 0x1 CLKGATE This bit must be set to zero for normal operation 30 1 read-write Normal Normal operation 0 Gated All clocks to PXP is gated-off 0x1 SFTRST This bit can be turned on and then off to reset the PXP block to its default state. 31 1 read-write Enabled Normal PXP operation is enabled 0 Disabled Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. 0x1 CTRL_CLR Control Register 0 0x8 32 read-write 0xC0000000 0xFFFFFFFF ENABLE Enables PXP operation with specified parameters 0 1 read-write Disabled PXP is disabled 0 Enabled PXP is enabled 0x1 IRQ_ENABLE Interrupt enable When using the PXP_NEXT functionality to reprogram the PXP, the new value of this bit will be used and may therefore enable or disable an interrupt unintentionally 1 1 read-write Disabled PXP interrupt is disabled 0 Enabled PXP interrupt is enabled 0x1 NEXT_IRQ_ENABLE Next command interrupt enable 2 1 read-write Disabled Disabled 0 Enabled Enabled 0x1 ENABLE_LCD_HANDSHAKE Enable handshake with LCD controller 4 1 read-write ROTATE Indicates the clockwise rotation to be applied at the output buffer 8 2 read-write ROT_0 ROT_0 0 ROT_90 ROT_90 0x1 ROT_180 ROT_180 0x2 ROT_270 ROT_270 0x3 HFLIP Indicates that the output buffer should be flipped horizontally (effect applied before rotation). 10 1 read-write Disabled Horizontal Flip is disabled 0 Enabled Horizontal Flip is enabled 0x1 VFLIP Indicates that the output buffer should be flipped vertically (effect applied before rotation). 11 1 read-write Disabled Vertical Flip is disabled 0 Enabled Vertical Flip is enabled 0x1 ROT_POS This bit controls where rotation will occur in the PXP datapath 22 1 read-write BLOCK_SIZE Select the block size to process. 23 1 read-write 8X8 Process 8x8 pixel blocks. 0 16X16 Process 16x16 pixel blocks. 0x1 EN_REPEAT Enable the PXP to run continuously 28 1 read-write Complete PXP will complete the process and enter the idle state ready to accept the next frame to be processed 0 Repeat PXP will repeat based on the current configuration register settings 0x1 CLKGATE This bit must be set to zero for normal operation 30 1 read-write Normal Normal operation 0 Gated All clocks to PXP is gated-off 0x1 SFTRST This bit can be turned on and then off to reset the PXP block to its default state. 31 1 read-write Enabled Normal PXP operation is enabled 0 Disabled Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. 0x1 CTRL_TOG Control Register 0 0xC 32 read-write 0xC0000000 0xFFFFFFFF ENABLE Enables PXP operation with specified parameters 0 1 read-write Disabled PXP is disabled 0 Enabled PXP is enabled 0x1 IRQ_ENABLE Interrupt enable When using the PXP_NEXT functionality to reprogram the PXP, the new value of this bit will be used and may therefore enable or disable an interrupt unintentionally 1 1 read-write Disabled PXP interrupt is disabled 0 Enabled PXP interrupt is enabled 0x1 NEXT_IRQ_ENABLE Next command interrupt enable 2 1 read-write Disabled Disabled 0 Enabled Enabled 0x1 ENABLE_LCD_HANDSHAKE Enable handshake with LCD controller 4 1 read-write ROTATE Indicates the clockwise rotation to be applied at the output buffer 8 2 read-write ROT_0 ROT_0 0 ROT_90 ROT_90 0x1 ROT_180 ROT_180 0x2 ROT_270 ROT_270 0x3 HFLIP Indicates that the output buffer should be flipped horizontally (effect applied before rotation). 10 1 read-write Disabled Horizontal Flip is disabled 0 Enabled Horizontal Flip is enabled 0x1 VFLIP Indicates that the output buffer should be flipped vertically (effect applied before rotation). 11 1 read-write Disabled Vertical Flip is disabled 0 Enabled Vertical Flip is enabled 0x1 ROT_POS This bit controls where rotation will occur in the PXP datapath 22 1 read-write BLOCK_SIZE Select the block size to process. 23 1 read-write 8X8 Process 8x8 pixel blocks. 0 16X16 Process 16x16 pixel blocks. 0x1 EN_REPEAT Enable the PXP to run continuously 28 1 read-write Complete PXP will complete the process and enter the idle state ready to accept the next frame to be processed 0 Repeat PXP will repeat based on the current configuration register settings 0x1 CLKGATE This bit must be set to zero for normal operation 30 1 read-write Normal Normal operation 0 Gated All clocks to PXP is gated-off 0x1 SFTRST This bit can be turned on and then off to reset the PXP block to its default state. 31 1 read-write Enabled Normal PXP operation is enabled 0 Disabled Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. 0x1 STAT Status Register 0x10 32 read-write 0 0xFFFFFFFF IRQ Indicates current PXP interrupt status 0 1 read-write IRQ_0 No interrupt 0 IRQ_1 Interrupt generated 0x1 AXI_WRITE_ERROR Indicates PXP encountered an AXI write error and processing has been terminated. 1 1 read-write Normal AXI write is normal 0 Error AXI write error has occurred 0x1 AXI_READ_ERROR Indicates PXP encountered an AXI read error and processing has been terminated. 2 1 read-write Normal AXI read is normal 0 Error AXI read error has occurred 0x1 NEXT_IRQ Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register 3 1 read-write AXI_ERROR_ID Indicates the AXI ID of the failing bus operation. 4 4 read-only LUT_DMA_LOAD_DONE_IRQ Indicates that the LUT DMA transfer has completed. 8 1 read-write Active LUT DMA LOAD transfer is active 0 Complete LUT DMA LOAD transfer is complete 0x1 BLOCKY Indicates the X coordinate of the block currently being rendered. 16 8 read-only BLOCKX Indicates the X coordinate of the block currently being rendered. 24 8 read-only STAT_SET Status Register 0x14 32 read-write 0 0xFFFFFFFF IRQ Indicates current PXP interrupt status 0 1 read-write IRQ_0 No interrupt 0 IRQ_1 Interrupt generated 0x1 AXI_WRITE_ERROR Indicates PXP encountered an AXI write error and processing has been terminated. 1 1 read-write Normal AXI write is normal 0 Error AXI write error has occurred 0x1 AXI_READ_ERROR Indicates PXP encountered an AXI read error and processing has been terminated. 2 1 read-write Normal AXI read is normal 0 Error AXI read error has occurred 0x1 NEXT_IRQ Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register 3 1 read-write AXI_ERROR_ID Indicates the AXI ID of the failing bus operation. 4 4 read-only LUT_DMA_LOAD_DONE_IRQ Indicates that the LUT DMA transfer has completed. 8 1 read-write Active LUT DMA LOAD transfer is active 0 Complete LUT DMA LOAD transfer is complete 0x1 BLOCKY Indicates the X coordinate of the block currently being rendered. 16 8 read-only BLOCKX Indicates the X coordinate of the block currently being rendered. 24 8 read-only STAT_CLR Status Register 0x18 32 read-write 0 0xFFFFFFFF IRQ Indicates current PXP interrupt status 0 1 read-write IRQ_0 No interrupt 0 IRQ_1 Interrupt generated 0x1 AXI_WRITE_ERROR Indicates PXP encountered an AXI write error and processing has been terminated. 1 1 read-write Normal AXI write is normal 0 Error AXI write error has occurred 0x1 AXI_READ_ERROR Indicates PXP encountered an AXI read error and processing has been terminated. 2 1 read-write Normal AXI read is normal 0 Error AXI read error has occurred 0x1 NEXT_IRQ Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register 3 1 read-write AXI_ERROR_ID Indicates the AXI ID of the failing bus operation. 4 4 read-only LUT_DMA_LOAD_DONE_IRQ Indicates that the LUT DMA transfer has completed. 8 1 read-write Active LUT DMA LOAD transfer is active 0 Complete LUT DMA LOAD transfer is complete 0x1 BLOCKY Indicates the X coordinate of the block currently being rendered. 16 8 read-only BLOCKX Indicates the X coordinate of the block currently being rendered. 24 8 read-only STAT_TOG Status Register 0x1C 32 read-write 0 0xFFFFFFFF IRQ Indicates current PXP interrupt status 0 1 read-write IRQ_0 No interrupt 0 IRQ_1 Interrupt generated 0x1 AXI_WRITE_ERROR Indicates PXP encountered an AXI write error and processing has been terminated. 1 1 read-write Normal AXI write is normal 0 Error AXI write error has occurred 0x1 AXI_READ_ERROR Indicates PXP encountered an AXI read error and processing has been terminated. 2 1 read-write Normal AXI read is normal 0 Error AXI read error has occurred 0x1 NEXT_IRQ Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register 3 1 read-write AXI_ERROR_ID Indicates the AXI ID of the failing bus operation. 4 4 read-only LUT_DMA_LOAD_DONE_IRQ Indicates that the LUT DMA transfer has completed. 8 1 read-write Active LUT DMA LOAD transfer is active 0 Complete LUT DMA LOAD transfer is complete 0x1 BLOCKY Indicates the X coordinate of the block currently being rendered. 16 8 read-only BLOCKX Indicates the X coordinate of the block currently being rendered. 24 8 read-only OUT_CTRL Output Buffer Control Register 0x20 32 read-write 0 0xFFFFFFFF FORMAT Output framebuffer format 0 5 read-write ARGB8888 32-bit pixels 0 RGB888 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0x4 RGB888P 24-bit pixels (packed 24-bit format) 0x5 ARGB1555 16-bit pixels 0x8 ARGB4444 16-bit pixels 0x9 RGB555 16-bit pixels 0xC RGB444 16-bit pixels 0xD RGB565 16-bit pixels 0xE YUV1P444 32-bit pixels (1-plane XYUV unpacked) 0x10 UYVY1P422 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0x12 VYUY1P422 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0x13 Y8 8-bit monochrome pixels (1-plane Y luma output) 0x14 Y4 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0x15 YUV2P422 16-bit pixels (2-plane UV interleaved bytes) 0x18 YUV2P420 16-bit pixels (2-plane UV) 0x19 YVU2P422 16-bit pixels (2-plane VU interleaved bytes) 0x1A YVU2P420 16-bit pixels (2-plane VU) 0x1B INTERLACED_OUTPUT Determines how the PXP writes it's output data 8 2 read-write PROGRESSIVE All data written in progressive format to the OUTBUF Pointer. 0 FIELD0 Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0x1 FIELD1 Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0x2 INTERLACED Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. 0x3 ALPHA_OUTPUT Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] 23 1 read-write Retain Retain 0 Overwritten Overwritten 0x1 ALPHA When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline 24 8 read-write OUT_CTRL_SET Output Buffer Control Register 0x24 32 read-write 0 0xFFFFFFFF FORMAT Output framebuffer format 0 5 read-write ARGB8888 32-bit pixels 0 RGB888 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0x4 RGB888P 24-bit pixels (packed 24-bit format) 0x5 ARGB1555 16-bit pixels 0x8 ARGB4444 16-bit pixels 0x9 RGB555 16-bit pixels 0xC RGB444 16-bit pixels 0xD RGB565 16-bit pixels 0xE YUV1P444 32-bit pixels (1-plane XYUV unpacked) 0x10 UYVY1P422 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0x12 VYUY1P422 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0x13 Y8 8-bit monochrome pixels (1-plane Y luma output) 0x14 Y4 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0x15 YUV2P422 16-bit pixels (2-plane UV interleaved bytes) 0x18 YUV2P420 16-bit pixels (2-plane UV) 0x19 YVU2P422 16-bit pixels (2-plane VU interleaved bytes) 0x1A YVU2P420 16-bit pixels (2-plane VU) 0x1B INTERLACED_OUTPUT Determines how the PXP writes it's output data 8 2 read-write PROGRESSIVE All data written in progressive format to the OUTBUF Pointer. 0 FIELD0 Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0x1 FIELD1 Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0x2 INTERLACED Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. 0x3 ALPHA_OUTPUT Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] 23 1 read-write Retain Retain 0 Overwritten Overwritten 0x1 ALPHA When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline 24 8 read-write OUT_CTRL_CLR Output Buffer Control Register 0x28 32 read-write 0 0xFFFFFFFF FORMAT Output framebuffer format 0 5 read-write ARGB8888 32-bit pixels 0 RGB888 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0x4 RGB888P 24-bit pixels (packed 24-bit format) 0x5 ARGB1555 16-bit pixels 0x8 ARGB4444 16-bit pixels 0x9 RGB555 16-bit pixels 0xC RGB444 16-bit pixels 0xD RGB565 16-bit pixels 0xE YUV1P444 32-bit pixels (1-plane XYUV unpacked) 0x10 UYVY1P422 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0x12 VYUY1P422 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0x13 Y8 8-bit monochrome pixels (1-plane Y luma output) 0x14 Y4 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0x15 YUV2P422 16-bit pixels (2-plane UV interleaved bytes) 0x18 YUV2P420 16-bit pixels (2-plane UV) 0x19 YVU2P422 16-bit pixels (2-plane VU interleaved bytes) 0x1A YVU2P420 16-bit pixels (2-plane VU) 0x1B INTERLACED_OUTPUT Determines how the PXP writes it's output data 8 2 read-write PROGRESSIVE All data written in progressive format to the OUTBUF Pointer. 0 FIELD0 Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0x1 FIELD1 Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0x2 INTERLACED Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. 0x3 ALPHA_OUTPUT Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] 23 1 read-write Retain Retain 0 Overwritten Overwritten 0x1 ALPHA When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline 24 8 read-write OUT_CTRL_TOG Output Buffer Control Register 0x2C 32 read-write 0 0xFFFFFFFF FORMAT Output framebuffer format 0 5 read-write ARGB8888 32-bit pixels 0 RGB888 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0x4 RGB888P 24-bit pixels (packed 24-bit format) 0x5 ARGB1555 16-bit pixels 0x8 ARGB4444 16-bit pixels 0x9 RGB555 16-bit pixels 0xC RGB444 16-bit pixels 0xD RGB565 16-bit pixels 0xE YUV1P444 32-bit pixels (1-plane XYUV unpacked) 0x10 UYVY1P422 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0x12 VYUY1P422 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0x13 Y8 8-bit monochrome pixels (1-plane Y luma output) 0x14 Y4 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0x15 YUV2P422 16-bit pixels (2-plane UV interleaved bytes) 0x18 YUV2P420 16-bit pixels (2-plane UV) 0x19 YVU2P422 16-bit pixels (2-plane VU interleaved bytes) 0x1A YVU2P420 16-bit pixels (2-plane VU) 0x1B INTERLACED_OUTPUT Determines how the PXP writes it's output data 8 2 read-write PROGRESSIVE All data written in progressive format to the OUTBUF Pointer. 0 FIELD0 Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0x1 FIELD1 Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0x2 INTERLACED Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. 0x3 ALPHA_OUTPUT Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] 23 1 read-write Retain Retain 0 Overwritten Overwritten 0x1 ALPHA When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline 24 8 read-write OUT_BUF Output Frame Buffer Pointer 0x30 32 read-write 0 0xFFFFFFFF ADDR Current address pointer for the output frame buffer 0 32 read-write OUT_BUF2 Output Frame Buffer Pointer #2 0x40 32 read-write 0 0xFFFFFFFF ADDR Current address pointer for the output frame buffer 0 32 read-write OUT_PITCH Output Buffer Pitch 0x50 32 read-write 0 0xFFFFFFFF PITCH Indicates the number of bytes in memory between two vertically adjacent pixels. 0 16 read-write OUT_LRC Output Surface Lower Right Coordinate 0x60 32 read-write 0 0xFFFFFFFF Y Indicates the number of vertical PIXELS in the output surface (non-rotated) 0 14 read-write X Indicates number of horizontal PIXELS in the output surface (non-rotated) 16 14 read-write OUT_PS_ULC Processed Surface Upper Left Coordinate 0x70 32 read-write 0 0xFFFFFFFF Y This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output buffer 0 14 read-write X This field indicates the upper left X-coordinate (in pixels) of the processed surface (PS) in the output buffer 16 14 read-write OUT_PS_LRC Processed Surface Lower Right Coordinate 0x80 32 read-write 0 0xFFFFFFFF Y This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer 0 14 read-write X This field indicates the lower right X-coordinate (in pixels) of the processed surface (PS) in the output frame buffer 16 14 read-write OUT_AS_ULC Alpha Surface Upper Left Coordinate 0x90 32 read-write 0 0xFFFFFFFF Y This field indicates the upper left Y-coordinate (in pixels) of the alpha surface in the output frame buffer 0 14 read-write X This field indicates the upper left X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer 16 14 read-write OUT_AS_LRC Alpha Surface Lower Right Coordinate 0xA0 32 read-write 0 0xFFFFFFFF Y This field indicates the lower right Y-coordinate (in pixels) of the alpha surface in the output frame buffer 0 14 read-write X This field indicates the lower right X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer 16 14 read-write PS_CTRL Processed Surface (PS) Control Register 0xB0 32 read-write 0 0xFFFFFFFF FORMAT PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. 0 6 read-write RGB888_ARGB8888 32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0x4 RGB555_ARGB1555 16-bit pixels with/without alpha at high 1bit 0xC RGB444_ARGB4444 16-bit pixels with/without alpha at high 4 bits 0xD RGB565 16-bit pixels 0xE YUV1P444 32-bit pixels (1-plane XYUV unpacked) 0x10 UYVY1P422 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0x12 VYUY1P422 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0x13 Y8 8-bit monochrome pixels (1-plane Y luma output) 0x14 Y4 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0x15 YUV2P422 16-bit pixels (2-plane UV interleaved bytes) 0x18 YUV2P420 16-bit pixels (2-plane UV) 0x19 YVU2P422 16-bit pixels (2-plane VU interleaved bytes) 0x1A YVU2P420 16-bit pixels (2-plane VU) 0x1B YUV422 16-bit pixels (3-plane format) 0x1E YUV420 16-bit pixels (3-plane format) 0x1F RGBA8888 2-bit pixels with alpha at the low 8 bits 0x24 RGBA5551 16-bit pixels with alpha at the low 1bits 0x2C RGBA4444 16-bit pixels with alpha at the low 4 bits 0x2D WB_SWAP Swap bytes in words. For each 16 bit word, the two bytes will be swapped. 6 1 read-write Disabled Byte swap is disabled 0 Enabled Byte swap is enabled 0x1 DECY Verticle pre decimation filter control. 8 2 read-write DISABLE Disable pre-decimation filter. 0 DECY2 Decimate PS by 2. 0x1 DECY4 Decimate PS by 4. 0x2 DECY8 Decimate PS by 8. 0x3 DECX Horizontal pre decimation filter control. 10 2 read-write DISABLE Disable pre-decimation filter. 0 DECX2 Decimate PS by 2. 0x1 DECX4 Decimate PS by 4. 0x2 DECX8 Decimate PS by 8. 0x3 PS_CTRL_SET Processed Surface (PS) Control Register 0xB4 32 read-write 0 0xFFFFFFFF FORMAT PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. 0 6 read-write RGB888_ARGB8888 32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0x4 RGB555_ARGB1555 16-bit pixels with/without alpha at high 1bit 0xC RGB444_ARGB4444 16-bit pixels with/without alpha at high 4 bits 0xD RGB565 16-bit pixels 0xE YUV1P444 32-bit pixels (1-plane XYUV unpacked) 0x10 UYVY1P422 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0x12 VYUY1P422 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0x13 Y8 8-bit monochrome pixels (1-plane Y luma output) 0x14 Y4 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0x15 YUV2P422 16-bit pixels (2-plane UV interleaved bytes) 0x18 YUV2P420 16-bit pixels (2-plane UV) 0x19 YVU2P422 16-bit pixels (2-plane VU interleaved bytes) 0x1A YVU2P420 16-bit pixels (2-plane VU) 0x1B YUV422 16-bit pixels (3-plane format) 0x1E YUV420 16-bit pixels (3-plane format) 0x1F RGBA8888 2-bit pixels with alpha at the low 8 bits 0x24 RGBA5551 16-bit pixels with alpha at the low 1bits 0x2C RGBA4444 16-bit pixels with alpha at the low 4 bits 0x2D WB_SWAP Swap bytes in words. For each 16 bit word, the two bytes will be swapped. 6 1 read-write Disabled Byte swap is disabled 0 Enabled Byte swap is enabled 0x1 DECY Verticle pre decimation filter control. 8 2 read-write DISABLE Disable pre-decimation filter. 0 DECY2 Decimate PS by 2. 0x1 DECY4 Decimate PS by 4. 0x2 DECY8 Decimate PS by 8. 0x3 DECX Horizontal pre decimation filter control. 10 2 read-write DISABLE Disable pre-decimation filter. 0 DECX2 Decimate PS by 2. 0x1 DECX4 Decimate PS by 4. 0x2 DECX8 Decimate PS by 8. 0x3 PS_CTRL_CLR Processed Surface (PS) Control Register 0xB8 32 read-write 0 0xFFFFFFFF FORMAT PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. 0 6 read-write RGB888_ARGB8888 32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0x4 RGB555_ARGB1555 16-bit pixels with/without alpha at high 1bit 0xC RGB444_ARGB4444 16-bit pixels with/without alpha at high 4 bits 0xD RGB565 16-bit pixels 0xE YUV1P444 32-bit pixels (1-plane XYUV unpacked) 0x10 UYVY1P422 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0x12 VYUY1P422 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0x13 Y8 8-bit monochrome pixels (1-plane Y luma output) 0x14 Y4 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0x15 YUV2P422 16-bit pixels (2-plane UV interleaved bytes) 0x18 YUV2P420 16-bit pixels (2-plane UV) 0x19 YVU2P422 16-bit pixels (2-plane VU interleaved bytes) 0x1A YVU2P420 16-bit pixels (2-plane VU) 0x1B YUV422 16-bit pixels (3-plane format) 0x1E YUV420 16-bit pixels (3-plane format) 0x1F RGBA8888 2-bit pixels with alpha at the low 8 bits 0x24 RGBA5551 16-bit pixels with alpha at the low 1bits 0x2C RGBA4444 16-bit pixels with alpha at the low 4 bits 0x2D WB_SWAP Swap bytes in words. For each 16 bit word, the two bytes will be swapped. 6 1 read-write Disabled Byte swap is disabled 0 Enabled Byte swap is enabled 0x1 DECY Verticle pre decimation filter control. 8 2 read-write DISABLE Disable pre-decimation filter. 0 DECY2 Decimate PS by 2. 0x1 DECY4 Decimate PS by 4. 0x2 DECY8 Decimate PS by 8. 0x3 DECX Horizontal pre decimation filter control. 10 2 read-write DISABLE Disable pre-decimation filter. 0 DECX2 Decimate PS by 2. 0x1 DECX4 Decimate PS by 4. 0x2 DECX8 Decimate PS by 8. 0x3 PS_CTRL_TOG Processed Surface (PS) Control Register 0xBC 32 read-write 0 0xFFFFFFFF FORMAT PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. 0 6 read-write RGB888_ARGB8888 32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0x4 RGB555_ARGB1555 16-bit pixels with/without alpha at high 1bit 0xC RGB444_ARGB4444 16-bit pixels with/without alpha at high 4 bits 0xD RGB565 16-bit pixels 0xE YUV1P444 32-bit pixels (1-plane XYUV unpacked) 0x10 UYVY1P422 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0x12 VYUY1P422 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0x13 Y8 8-bit monochrome pixels (1-plane Y luma output) 0x14 Y4 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0x15 YUV2P422 16-bit pixels (2-plane UV interleaved bytes) 0x18 YUV2P420 16-bit pixels (2-plane UV) 0x19 YVU2P422 16-bit pixels (2-plane VU interleaved bytes) 0x1A YVU2P420 16-bit pixels (2-plane VU) 0x1B YUV422 16-bit pixels (3-plane format) 0x1E YUV420 16-bit pixels (3-plane format) 0x1F RGBA8888 2-bit pixels with alpha at the low 8 bits 0x24 RGBA5551 16-bit pixels with alpha at the low 1bits 0x2C RGBA4444 16-bit pixels with alpha at the low 4 bits 0x2D WB_SWAP Swap bytes in words. For each 16 bit word, the two bytes will be swapped. 6 1 read-write Disabled Byte swap is disabled 0 Enabled Byte swap is enabled 0x1 DECY Verticle pre decimation filter control. 8 2 read-write DISABLE Disable pre-decimation filter. 0 DECY2 Decimate PS by 2. 0x1 DECY4 Decimate PS by 4. 0x2 DECY8 Decimate PS by 8. 0x3 DECX Horizontal pre decimation filter control. 10 2 read-write DISABLE Disable pre-decimation filter. 0 DECX2 Decimate PS by 2. 0x1 DECX4 Decimate PS by 4. 0x2 DECX8 Decimate PS by 8. 0x3 PS_BUF PS Input Buffer Address 0xC0 32 read-write 0 0xFFFFFFFF ADDR Address pointer for the PS RGB or Y (luma) input buffer. 0 32 read-write PS_UBUF PS U/Cb or 2 Plane UV Input Buffer Address 0xD0 32 read-write 0 0xFFFFFFFF ADDR Address pointer for the PS U/Cb or 2 plane UV Chroma input buffer. 0 32 read-write PS_VBUF PS V/Cr Input Buffer Address 0xE0 32 read-write 0 0xFFFFFFFF ADDR Address pointer for the PS V/Cr Chroma input buffer. 0 32 read-write PS_PITCH Processed Surface Pitch 0xF0 32 read-write 0 0xFFFFFFFF PITCH Indicates the number of bytes in memory between two vertically adjacent pixels. 0 16 read-write PS_BACKGROUND PS Background Color 0x100 32 read-write 0 0xFFFFFFFF COLOR Background color (in 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC 0 24 read-write PS_SCALE PS Scale Factor Register 0x110 32 read-write 0x10001000 0xFFFFFFFF XSCALE This is a two bit integer and 12 bit fractional representation (## 0 15 read-write YSCALE This is a two bit integer and 12 bit fractional representation (## 16 15 read-write PS_OFFSET PS Scale Offset Register 0x120 32 read-write 0 0xFFFFFFFF XOFFSET This is a 12 bit fractional representation (0 0 12 read-write YOFFSET This is a 12 bit fractional representation (0 16 12 read-write PS_CLRKEYLOW PS Color Key Low 0x130 32 read-write 0xFFFFFF 0xFFFFFFFF PIXEL Low range of color key applied to PS buffer 0 24 read-write PS_CLRKEYHIGH PS Color Key High 0x140 32 read-write 0 0xFFFFFFFF PIXEL High range of color key applied to PS buffer 0 24 read-write AS_CTRL Alpha Surface Control 0x150 32 read-write 0 0xFFFFFFFF ALPHA_CTRL Determines how the alpha value is constructed for this alpha surface 1 2 read-write Embedded Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored. 0 Override Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. 0x1 Multiply Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. 0x2 ROPs Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels. 0x3 ENABLE_COLORKEY Indicates that colorkey functionality is enabled for this alpha surface 3 1 read-write Disabled Disabled 0 Enabled Enabled 0x1 FORMAT Indicates the input buffer format for AS. 4 4 read-write ARGB8888 32-bit pixels with alpha 0 RGBA888 2-bit pixel with alpha at low 8 bits 0x1 RGB888 32-bit pixels without alpha (unpacked 24-bit format) 0x4 ARGB1555 16-bit pixels with alpha 0x8 ARGB4444 16-bit pixels with alpha 0x9 RGBA5551 16-bit pixel with alpha at low 1 bit 0xA RGBA4444 16-bit pixel with alpha at low 4 bits 0xB RGB555 16-bit pixels without alpha 0xC RGB444 16-bit pixels without alpha 0xD RGB565 16-bit pixels without alpha 0xE ALPHA Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in PXP_AS_CTRL[ALPHA_CTRL] 8 8 read-write ROP Indicates a raster operation to perform when enabled 16 4 read-write MASKAS AS AND PS 0 MASKNOTAS nAS AND PS 0x1 MASKASNOT AS AND nPS 0x2 MERGEAS AS OR PS 0x3 MERGENOTAS nAS OR PS 0x4 MERGEASNOT AS OR nPS 0x5 NOTCOPYAS nAS 0x6 NOT nPS 0x7 NOTMASKAS AS NAND PS 0x8 NOTMERGEAS AS NOR PS 0x9 XORAS AS XOR PS 0xA NOTXORAS AS XNOR PS 0xB ALPHA_INVERT Setting this bit to logic 0 will not alter the alpha value 20 1 read-write ALPHA_INVERT_0 Not inverted 0 Inverted Inverted 0x1 AS_BUF Alpha Surface Buffer Pointer 0x160 32 read-write 0 0xFFFFFFFF ADDR Address pointer for the alpha surface 0 buffer. 0 32 read-write AS_PITCH Alpha Surface Pitch 0x170 32 read-write 0 0xFFFFFFFF PITCH Indicates the number of bytes in memory between two vertically adjacent pixels. 0 16 read-write AS_CLRKEYLOW Overlay Color Key Low 0x180 32 read-write 0xFFFFFF 0xFFFFFFFF PIXEL Low range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. 0 24 read-write AS_CLRKEYHIGH Overlay Color Key High 0x190 32 read-write 0 0xFFFFFFFF PIXEL High range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. 0 24 read-write CSC1_COEF0 Color Space Conversion Coefficient Register 0 0x1A0 32 read-write 0x4000000 0xFFFFFFFF Y_OFFSET Two's compliment amplitude offset implicit in the Y data 0 9 read-write UV_OFFSET Two's compliment phase offset implicit for CbCr data 9 9 read-write C0 Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) 18 11 read-write BYPASS Bypass the CSC unit in the scaling engine 30 1 read-write YCBCR_MODE Set to 1 when performing YCbCr conversion to RGB 31 1 read-write YCBCR_MODE_0 YUV to RGB 0 YCBCR_MODE_1 YCbCr to RGB 0x1 CSC1_COEF1 Color Space Conversion Coefficient Register 1 0x1B0 32 read-write 0x1230208 0xFFFFFFFF C4 Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017) 0 11 read-write C1 Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596) 16 11 read-write CSC1_COEF2 Color Space Conversion Coefficient Register 2 0x1C0 32 read-write 0x79B076C 0xFFFFFFFF C3 Two's complement Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392) 0 11 read-write C2 Two's complement Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813) 16 11 read-write POWER PXP Power Control Register 0x320 32 read-write 0 0xFFFFFFFF ROT_MEM_LP_STATE Select the low power state of the Rotation (ROT) memory. 9 3 read-write NONE Memory is not in low power state. 0 LS Light Sleep Mode. Low leakage mode, maintain memory contents. 0x1 DS Deep Sleep Mode. Low leakage mode, maintain memory contents. 0x2 SD Shut Down Mode. Shut Down periphery and core, no memory retention. 0x4 NEXT Next Frame Pointer 0x400 32 read-write 0 0xFFFFFFFF ENABLED Indicates that the "next frame" functionality has been enabled 0 1 read-only POINTER A pointer to a data structure containing register values to be used when processing the next frame 2 30 read-write PORTER_DUFF_CTRL PXP Alpha Engine A Control Register. 0x440 32 read-write 0 0xFFFFFFFF PORTER_DUFF_ENABLE Porter-Duff Enable 0 1 read-write Disabled Disabled 0 Enabled Enabled 0x1 S0_S1_FACTOR_MODE s0 to s1 factor mode 1 2 read-write S0_S1_FACTOR_MODE_0 1 0 S0_S1_FACTOR_MODE_1 0 0x1 S0_S1_FACTOR_MODE_2 Straight alpha 0x2 S0_S1_FACTOR_MODE_3 Inverse alpha 0x3 S0_GLOBAL_ALPHA_MODE s0 global alpha mode 3 2 read-write S0_GLOBAL_ALPHA_MODE_0 Global alpha 0 S0_GLOBAL_ALPHA_MODE_1 Local alpha 0x1 S0_GLOBAL_ALPHA_MODE_2 Scaled alpha 0x2 S0_GLOBAL_ALPHA_MODE_3 Scaled alpha 0x3 S0_ALPHA_MODE s0 alpha mode (Porter-Duff alpha mode) 5 1 read-write S0_ALPHA_MODE_0 Straight mode 0 S0_ALPHA_MODE_1 Inverted mode 0x1 S0_COLOR_MODE s0 color mode (Porter-Duff color mode) 6 1 read-write S0_COLOR_MODE_0 Original pixel 0 S0_COLOR_MODE_1 Scaled pixel 0x1 S1_S0_FACTOR_MODE s1 to s0 factor mode (Porter-Duff factor mode) 8 2 read-write S1_S0_FACTOR_MODE_0 1 0 S1_S0_FACTOR_MODE_1 0 0x1 S1_S0_FACTOR_MODE_2 Straight alpha 0x2 S1_S0_FACTOR_MODE_3 Inverse alpha 0x3 S1_GLOBAL_ALPHA_MODE s1 global alpha mode (Porter-Duff Global Alpha mode) 10 2 read-write S1_GLOBAL_ALPHA_MODE_0 Global alpha 0 S1_GLOBAL_ALPHA_MODE_1 Local alpha 0x1 S1_GLOBAL_ALPHA_MODE_2 Scaled alpha 0x2 S1_GLOBAL_ALPHA_MODE_3 Scaled alpha 0x3 S1_ALPHA_MODE s1 alpha mode (Porter-Duff Alpha mode) 12 1 read-write S1_ALPHA_MODE_0 Straight mode 0 S1_ALPHA_MODE_1 Inverted mode 0x1 S1_COLOR_MODE s1 color mode 13 1 read-write S1_COLOR_MODE_0 Original pixel 0 S1_COLOR_MODE_1 Scaled pixel 0x1 S0_GLOBAL_ALPHA s0 global alpha 16 8 read-write S1_GLOBAL_ALPHA s1 global alpha 24 8 read-write VIDEO_MUX VIDEO_MUX VIDEO_MUX 0x40818000 0 0x80 registers VID_MUX_CTRL Video mux Control Register 0 32 read-write 0 0xFFFFFFFF CSI_SEL CSI sensor data input mux selector 0 1 read-write PARALLEL_CSI CSI sensor data is from Parallel CSI 0 MIPI_CSI CSI sensor data is from MIPI CSI 0x1 LCDIF2_SEL LCDIF2 sensor data input mux selector 1 1 read-write PARALLEL_CSI LCDIFv2 sensor data is from Parallel CSI 0 MIPI_CSI LCDIFv2 sensor data is from MIPI CSI 0x1 MIPI_DSI_SEL MIPI DSI video data input mux selector 2 1 read-write PARALLEL_CSI MIPI DSI video data is from eLCDIF 0 MIPI_CSI MIPI DSI video data is from LCDIFv2 0x1 PARA_LCD_SEL Parallel LCDIF video data input mux selector 3 1 read-write PARALLEL_CSI Parallel LCDIF video data is from eLCDIF 0 MIPI_CSI Parallel LCDIF video data is from LCDIFv2 0x1 VID_MUX_CTRL_SET Video mux Control Register 0x4 32 read-write 0 0xFFFFFFFF oneToSet CSI_SEL CSI sensor data input mux selector 0 1 read-write oneToSet LCDIF2_SEL LCDIF2 sensor data input mux selector 1 1 read-write oneToSet MIPI_DSI_SEL MIPI DSI video data input mux selector 2 1 read-write oneToSet PARA_LCD_SEL Parallel LCDIF video data input mux selector 3 1 read-write oneToSet VID_MUX_CTRL_CLR Video mux Control Register 0x8 32 read-write 0 0xFFFFFFFF oneToClear CSI_SEL CSI sensor data input mux selector 0 1 read-write oneToClear LCDIF2_SEL LCDIF2 sensor data input mux selector 1 1 read-write oneToClear MIPI_DSI_SEL MIPI DSI video data input mux selector 2 1 read-write oneToClear PARA_LCD_SEL Parallel LCDIF video data input mux selector 3 1 read-write oneToClear VID_MUX_CTRL_TOG Video mux Control Register 0xC 32 read-write 0 0xFFFFFFFF oneToToggle CSI_SEL CSI sensor data input mux selector 0 1 read-write oneToToggle LCDIF2_SEL LCDIF2 sensor data input mux selector 1 1 read-write oneToToggle MIPI_DSI_SEL MIPI DSI video data input mux selector 2 1 read-write oneToToggle PARA_LCD_SEL Parallel LCDIF video data input mux selector 3 1 read-write oneToToggle PLM_CTRL Pixel Link Master(PLM) Control Register 0x20 32 read-write 0 0xFFFFFFFF ENABLE Enable the output of HYSNC and VSYNC 0 1 read-write NO_ACTIVE No active HSYNC and VSYNC output 0 ACTIVE Active HSYNC and VSYNC output 0x1 VSYNC_OVERRIDE VSYNC override 1 1 read-write DEASSERT VSYNC is not asserted 0 ASSERT VSYNC is asserted 0x1 HSYNC_OVERRIDE HSYNC override 2 1 read-write DEASSERT HSYNC is not asserted 0 ASSERT HSYNC is asserted 0x1 VALID_OVERRIDE Valid override 3 1 read-write ASSERT HSYNC and VSYNC is asserted 0 DEASSERT HSYNC and VSYNC is not asserted 0x1 POLARITY Polarity of HYSNC/VSYNC 4 1 read-write KEEP Keep the current polarity of HSYNC and VSYNC 0 INVERT Invert the polarity of HSYNC and VSYNC 0x1 PLM_CTRL_SET Pixel Link Master(PLM) Control Register 0x24 32 read-write 0 0xFFFFFFFF oneToSet ENABLE Enable the output of HYSNC and VSYNC 0 1 read-write oneToSet VSYNC_OVERRIDE VSYNC override 1 1 read-write oneToSet HSYNC_OVERRIDE HSYNC override 2 1 read-write oneToSet VALID_OVERRIDE Valid override 3 1 read-write oneToSet POLARITY Polarity of HYSNC/VSYNC 4 1 read-write oneToSet PLM_CTRL_CLR Pixel Link Master(PLM) Control Register 0x28 32 read-write 0 0xFFFFFFFF oneToClear ENABLE Enable the output of HYSNC and VSYNC 0 1 read-write oneToClear VSYNC_OVERRIDE VSYNC override 1 1 read-write oneToClear HSYNC_OVERRIDE HSYNC override 2 1 read-write oneToClear VALID_OVERRIDE Valid override 3 1 read-write oneToClear POLARITY Polarity of HYSNC/VSYNC 4 1 read-write oneToClear PLM_CTRL_TOG Pixel Link Master(PLM) Control Register 0x2C 32 read-write 0 0xFFFFFFFF oneToToggle ENABLE Enable the output of HYSNC and VSYNC 0 1 read-write oneToToggle VSYNC_OVERRIDE VSYNC override 1 1 read-write oneToToggle HSYNC_OVERRIDE HSYNC override 2 1 read-write oneToToggle VALID_OVERRIDE Valid override 3 1 read-write oneToToggle POLARITY Polarity of HYSNC/VSYNC 4 1 read-write oneToToggle YUV420_CTRL YUV420 Control Register 0x30 32 read-write 0 0xFFFFFFFF FST_LN_DATA_TYPE Data type of First Line 0 1 read-write ODD Odd (default) 0 EVEN Even 0x1 YUV420_CTRL_SET YUV420 Control Register 0x34 32 read-write 0 0xFFFFFFFF oneToSet FST_LN_DATA_TYPE Data type of First Line 0 1 read-write oneToSet YUV420_CTRL_CLR YUV420 Control Register 0x38 32 read-write 0 0xFFFFFFFF oneToClear FST_LN_DATA_TYPE Data type of First Line 0 1 read-write oneToClear YUV420_CTRL_TOG YUV420 Control Register 0x3C 32 read-write 0 0xFFFFFFFF oneToToggle FST_LN_DATA_TYPE Data type of First Line 0 1 read-write oneToToggle CFG_DT_DISABLE Data Disable Register 0x50 32 read-write 0 0xFFFFFFFF CFG_DT_DISABLE Data Type Disable 0 24 read-write CFG_DT_DISABLE_SET Data Disable Register 0x54 32 read-write 0 0xFFFFFFFF oneToSet CFG_DT_DISABLE Data Type Disable 0 24 read-write oneToSet CFG_DT_DISABLE_CLR Data Disable Register 0x58 32 read-write 0 0xFFFFFFFF oneToClear CFG_DT_DISABLE Data Type Disable 0 24 read-write oneToClear CFG_DT_DISABLE_TOG Data Disable Register 0x5C 32 read-write 0 0xFFFFFFFF oneToToggle CFG_DT_DISABLE Data Type Disable 0 24 read-write oneToToggle MIPI_DSI_CTRL MIPI DSI Control Register 0x70 32 read-write 0 0xFFFFFFFF DPI_SD Shut Down - Control to shutdown display (type 4 only) 0 1 read-write NO No effect 0 SENDCMD Send shutdown command 0x1 DPI_CM Color Mode control 1 1 read-write NORMAL Normal Mode 0 LOWCLR Low-color mode 0x1 MIPI_DSI_CTRL_SET MIPI DSI Control Register 0x74 32 read-write 0 0xFFFFFFFF oneToSet DPI_SD Shut Down - Control to shutdown display (type 4 only) 0 1 read-write oneToSet DPI_CM Color Mode control 1 1 read-write oneToSet MIPI_DSI_CTRL_CLR MIPI DSI Control Register 0x78 32 read-write 0 0xFFFFFFFF oneToClear DPI_SD Shut Down - Control to shutdown display (type 4 only) 0 1 read-write oneToClear DPI_CM Color Mode control 1 1 read-write oneToClear MIPI_DSI_CTRL_TOG MIPI DSI Control Register 0x7C 32 read-write 0 0xFFFFFFFF oneToToggle DPI_SD Shut Down - Control to shutdown display (type 4 only) 0 1 read-write oneToToggle DPI_CM Color Mode control 1 1 read-write oneToToggle DCIC1 DCIC DCIC DCIC1_ DCIC 0x40819000 0 0x110 registers DCIC1 95 DCICC DCIC Control Register 0 32 read-write 0x70 0xFFFFFFFF IC_EN Integrity Check enable. Main enable switch. 0 1 read-write IC_EN_0 Disabled 0 IC_EN_1 Enabled 0x1 DE_POL DATA_EN_IN signal polarity. 4 1 read-write DE_POL_0 Active High. 0 DE_POL_1 Active Low. 0x1 HSYNC_POL HSYNC_IN signal polarity. 5 1 read-write HSYNC_POL_0 Active High. 0 HSYNC_POL_1 Active Low. 0x1 VSYNC_POL VSYNC_IN signal polarity. 6 1 read-write VSYNC_POL_0 Active High. 0 VSYNC_POL_1 Active Low. 0x1 CLK_POL DISP_CLK signal polarity. 7 1 read-write CLK_POL_0 Not inverted (default). 0 CLK_POL_1 Inverted. 0x1 DCICIC DCIC Interrupt Control Register 0x4 32 read-write 0x3 0xFFFFFFFF EI_MASK Error Interrupt mask. Can be changed only while FREEZE_MASK = 0. 0 1 read-write EI_MASK_0 Mask disabled - Interrupt assertion enabled 0 EI_MASK_1 Mask enabled - Interrupt assertion disabled 0x1 FI_MASK Functional Interrupt mask. Can be changed only while FREEZE_MASK = 0. 1 1 read-write FI_MASK_0 Mask disabled - Interrupt assertion enabled 0 FI_MASK_1 Mask enabled - Interrupt assertion disabled 0x1 FREEZE_MASK Disable change of interrupt masks. "Sticky" bit which can be set once and cleared by reset only. 3 1 read-write FREEZE_MASK_0 Masks change allowed 0 FREEZE_MASK_1 Masks are frozen 0x1 EXT_SIG_EN External controller mismatch indication signal. 16 1 read-write EXT_SIG_EN_0 Disabled 0 EXT_SIG_EN_1 Enabled 0x1 DCICS DCIC Status Register 0x8 32 read-write 0 0xFFFFFFFF ROI_MATCH_STAT Each set bit of this field indicates there was a mismatch at the appropriate ROIs signature during the last frame 0 16 read-write oneToClear ROI_MATCH_STAT_0 ROI calculated CRC matches expected signature 0 ROI_MATCH_STAT_1 Mismatch at ROI calculated CRC 0x1 EI_STAT Error Interrupt status 16 1 read-only EI_STAT_0 No pending Interrupt 0 EI_STAT_1 Pending Interrupt 0x1 FI_STAT Functional Interrupt status. Write "1" to clear. 17 1 read-write oneToClear FI_STAT_0 No pending Interrupt 0 FI_STAT_1 Pending Interrupt 0x1 16 0x10 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 DCICRC%s DCIC ROI Config Register 0x10 32 read-write 0 0xFFFFFFFF START_OFFSET_X Column number of ROIs upper-left corner (X coordinate) Range: 0 to 2^13-1 0 13 read-write START_OFFSET_Y Row number of ROIs upper-left corner (Y coordinate) Range: 0 to 2^12-1 16 12 read-write ROI_FREEZE When set, the only parameter of the ROI that can be changed is the reference signature 30 1 read-write ROI_FREEZE_0 ROI configuration can be changed 0 ROI_FREEZE_1 ROI configuration is frozen 0x1 ROI_EN ROI tracking enable 31 1 read-write ROI_EN_0 Disabled 0 ROI_EN_1 Enabled 0x1 16 0x10 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 DCICRS%s DCIC ROI Size Register 0x14 32 read-write 0 0xFFFFFFFF END_OFFSET_X Column number of ROIs lower-right corner (X coordinate) Range: 1 to 2^13-1 0 13 read-write END_OFFSET_Y Row number of ROIs lower-right corner (Y coordinate) Range: 1 to 2^12-1 16 12 read-write 16 0x10 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 DCICRRS%s DCIC ROI Reference Signature Register 0x18 32 read-write 0 0xFFFFFFFF REFERENCE_SIGNATURE 32-bit expected signature (CRC calculation result) for the ROI 0 32 read-write 16 0x10 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 DCICRCS%s DCIC ROI Calculated Signature Register 0x1C 32 read-only 0 0xFFFFFFFF CALCULATED_SIGNATURE 32-bit actual signature (CRC calculation result) for the ROI during the last frame 0 32 read-only DCIC2 DCIC DCIC DCIC2_ 0x4081A000 0 0x110 registers DCIC2 96 GPC_CPU_MODE_CTRL_0 GPC_CPU GPC_CPU_MODE_CTRL GPC_CPU_MODE_CTRL 0x40C00000 0 0x800 registers CM_AUTHEN_CTRL CM Authentication Control 0x4 32 read-write 0xF00 0xFFFFFFFF USER Allow user mode access 0 1 read-write b0 Allow only privilege mode to access CPU mode control registers 0 b1 Allow both privilege and user mode to access CPU mode control registers 0x1 NONSECURE Allow non-secure mode access 1 1 read-write b0 Allow only secure mode to access CPU mode control registers 0 b1 Allow both secure and non-secure mode to access CPU mode control registers 0x1 LOCK_SETTING Lock NONSECURE and USER 4 1 read-write WHITE_LIST Domain ID white list 8 4 read-write LOCK_LIST White list lock 12 1 read-write LOCK_CFG Configuration lock 20 1 read-write CM_INT_CTRL CM Interrupt Control 0x8 32 read-write 0x7 0xFFFFFFFF SP_REQ_NOT_ALLOWED_SLEEP_INT_EN sp_req_not_allowed_for_sleep interrupt enable 0 1 read-write b0 Interrupt disable 0 b1 Interrupt enable 0x1 SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN sp_req_not_allowed_for_wakeup interrupt enable 1 1 read-write b0 Interrupt disable 0 b1 Interrupt enable 0x1 SP_REQ_NOT_ALLOWED_SOFT_INT_EN sp_req_not_allowed_for_soft interrupt enable 2 1 read-write b0 Interrupt disable 0 b1 Interrupt enable 0x1 SP_REQ_NOT_ALLOWED_SLEEP_INT sp_req_not_allowed_for_sleep interrupt status and clear register 16 1 read-write oneToClear SP_REQ_NOT_ALLOWED_WAKEUP_INT sp_req_not_allowed_for_wakeup interrupt status and clear register 17 1 read-write oneToClear SP_REQ_NOT_ALLOWED_SOFT_INT sp_req_not_allowed_for_soft interrupt status and clear register 18 1 read-write oneToClear CM_MISC Miscellaneous 0xC 32 read-write 0x6 0xFFFFFFFF NMI_STAT Non-masked interrupt status 0 1 read-only b0 NMI is not asserting 0 b1 NMI is asserting 0x1 SLEEP_HOLD_EN Allow cpu_sleep_hold_req assert during CPU low power status 1 1 read-write b0 Disable cpu_sleep_hold_req 0 b1 Allow cpu_sleep_hold_req assert during CPU low power status 0x1 SLEEP_HOLD_STAT Status of cpu_sleep_hold_ack_b 2 1 read-only MASTER_CPU Master CPU 4 1 read-write CM_MODE_CTRL CPU mode control 0x10 32 read-write 0 0xFFFFFFFF CPU_MODE_TARGET The CPU mode the CPU platform should transit to on next sleep event 0 2 read-write b0 Stay in RUN mode 0 b1 Transit to WAIT mode 0x1 b2 Transit to STOP mode 0x2 b3 Transit to SUSPEND mode 0x3 WFE_EN WFE assertion can be sleep event 4 1 read-write b0 WFE assertion can not trigger low power 0 b1 WFE assertion can trigger low power 0x1 CM_MODE_STAT CM CPU mode Status 0x14 32 read-only 0 0xFFFFFFFF CPU_MODE_CURRENT Current CPU mode 0 2 read-only RUN CPU is currently in RUN mode 0 WAIT CPU is currently in WAIT mode 0x1 STOP CPU is currently in STOP mode 0x2 SUSPEND CPU is currently in SUSPEND mode 0x3 CPU_MODE_PREVIOUS Previous CPU mode 2 2 read-only RUN CPU was previously in RUN mode 0 WAIT CPU was previously in WAIT mode 0x1 STOP CPU was previously in STOP mode 0x2 SUSPEND CPU was previously in SUSPEND mode 0x3 CM_IRQ_WAKEUP_MASK_0 CM IRQ0~31 wakeup mask 0x100 32 read-write 0 0xFFFFFFFF IRQ_WAKEUP_MASK_0_31 "1" means the IRQ cannot wakeup CPU platform 0 32 read-write CM_IRQ_WAKEUP_MASK_1 CM IRQ32~63 wakeup mask 0x104 32 read-write 0 0xFFFFFFFF IRQ_WAKEUP_MASK_32_63 "1" means the IRQ cannot wakeup CPU platform 0 32 read-write CM_IRQ_WAKEUP_MASK_2 CM IRQ64~95 wakeup mask 0x108 32 read-write 0 0xFFFFFFFF IRQ_WAKEUP_MASK_64_95 "1" means the IRQ cannot wakeup CPU platform 0 32 read-write CM_IRQ_WAKEUP_MASK_3 CM IRQ96~127 wakeup mask 0x10C 32 read-write 0 0xFFFFFFFF IRQ_WAKEUP_MASK_96_127 "1" means the IRQ cannot wakeup CPU platform 0 32 read-write CM_IRQ_WAKEUP_MASK_4 CM IRQ128~159 wakeup mask 0x110 32 read-write 0 0xFFFFFFFF IRQ_WAKEUP_MASK_128_159 "1" means the IRQ cannot wakeup CPU platform 0 32 read-write CM_IRQ_WAKEUP_MASK_5 CM IRQ160~191 wakeup mask 0x114 32 read-write 0 0xFFFFFFFF IRQ_WAKEUP_MASK_160_191 "1" means the IRQ cannot wakeup CPU platform 0 32 read-write CM_IRQ_WAKEUP_MASK_6 CM IRQ192~223 wakeup mask 0x118 32 read-write 0 0xFFFFFFFF IRQ_WAKEUP_MASK_192_223 "1" means the IRQ cannot wakeup CPU platform 0 32 read-write CM_IRQ_WAKEUP_MASK_7 CM IRQ224~255 wakeup mask 0x11C 32 read-write 0 0xFFFFFFFF IRQ_WAKEUP_MASK_224_255 "1" means the IRQ cannot wakeup CPU platform 0 32 read-write CM_NON_IRQ_WAKEUP_MASK CM non-irq wakeup mask 0x140 32 read-write 0x1 0xFFFFFFFF EVENT_WAKEUP_MASK There are 256 interrupts and 1 event as a wakeup source for GPC. This field masks the 1 event wakeup source. 0 1 read-write b1 The event cannot wakeup CPU platform 0x1 DEBUG_WAKEUP_MASK "1" means the debug_wakeup_request cannot wakeup CPU platform 1 1 read-write CM_IRQ_WAKEUP_STAT_0 CM IRQ0~31 wakeup status 0x150 32 read-only 0 0xFFFFFFFF IRQ_WAKEUP_STAT_0_31 IRQ status 0 32 read-only b0 None 0 b1 Valid 0x1 CM_IRQ_WAKEUP_STAT_1 CM IRQ32~63 wakeup status 0x154 32 read-only 0 0xFFFFFFFF IRQ_WAKEUP_STAT_32_63 IRQ status 0 32 read-only b0 None 0 b1 Valid 0x1 CM_IRQ_WAKEUP_STAT_2 CM IRQ64~95 wakeup status 0x158 32 read-only 0 0xFFFFFFFF IRQ_WAKEUP_STAT_64_95 IRQ status 0 32 read-only b0 None 0 b1 Valid 0x1 CM_IRQ_WAKEUP_STAT_3 CM IRQ96~127 wakeup status 0x15C 32 read-only 0 0xFFFFFFFF IRQ_WAKEUP_STAT_96_127 IRQ status 0 32 read-only b0 None 0 b1 Valid 0x1 CM_IRQ_WAKEUP_STAT_4 CM IRQ128~159 wakeup status 0x160 32 read-only 0 0xFFFFFFFF IRQ_WAKEUP_STAT_128_159 IRQ status 0 32 read-only b0 None 0 b1 Valid 0x1 CM_IRQ_WAKEUP_STAT_5 CM IRQ160~191 wakeup status 0x164 32 read-only 0 0xFFFFFFFF IRQ_WAKEUP_STAT_160_191 IRQ status 0 32 read-only b0 None 0 b1 Valid 0x1 CM_IRQ_WAKEUP_STAT_6 CM IRQ192~223 wakeup status 0x168 32 read-only 0 0xFFFFFFFF IRQ_WAKEUP_STAT_192_223 IRQ status 0 32 read-only b0 None 0 b1 Valid 0x1 CM_IRQ_WAKEUP_STAT_7 CM IRQ224~255 wakeup status 0x16C 32 read-only 0 0xFFFFFFFF IRQ_WAKEUP_MASK_224_255 IRQ status 0 32 read-only b0 None 0 b1 Valid 0x1 CM_NON_IRQ_WAKEUP_STAT CM non-irq wakeup status 0x190 32 read-only 0 0xFFFFFFFF EVENT_WAKEUP_STAT Event wakeup status 0 1 read-only b1 Interrupt is asserting (pending) 0x1 DEBUG_WAKEUP_STAT Debug wakeup status 1 1 read-only CM_SLEEP_SSAR_CTRL CM sleep SSAR control 0x200 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE. 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_SLEEP_LPCG_CTRL CM sleep LPCG control 0x208 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_SLEEP_PLL_CTRL CM sleep PLL control 0x210 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_SLEEP_ISO_CTRL CM sleep isolation control 0x218 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_SLEEP_RESET_CTRL CM sleep reset control 0x220 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_SLEEP_POWER_CTRL CM sleep power control 0x228 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_WAKEUP_POWER_CTRL CM wakeup power control 0x290 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_WAKEUP_RESET_CTRL CM wakeup reset control 0x298 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_WAKEUP_ISO_CTRL CM wakeup isolation control 0x2A0 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_WAKEUP_PLL_CTRL CM wakeup PLL control 0x2A8 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_WAKEUP_LPCG_CTRL CM wakeup LPCG control 0x2B0 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_WAKEUP_SSAR_CTRL CM wakeup SSAR control 0x2B8 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write CM_SP_CTRL CM Setpoint Control 0x300 32 read-write 0 0xFFFFFFFF CPU_SP_RUN_EN Request a Setpoint transition when this bit is set 0 1 read-write CPU_SP_RUN The Setpoint that CPU want the system to transit to when CPU_SP_RUN_EN is set 1 4 read-write CPU_SP_SLEEP_EN 1 means enable Setpoint transition on next CPU platform sleep sequence 5 1 read-write CPU_SP_SLEEP The Setpoint that CPU want the system to transit to on next CPU platform sleep sequence 6 4 read-write CPU_SP_WAKEUP_EN 1 means enable Setpoint transition on next CPU platform wakeup sequence 10 1 read-write CPU_SP_WAKEUP The Setpoint that CPU want the system to transit to on next CPU platform wakeup sequence 11 4 read-write CPU_SP_WAKEUP_SEL Select the Setpoint transiton on the next CPU platform wakeup sequence 15 1 read-write b0 Request SP transition to CPU_SP_WAKEUP 0 b1 Request SP transition to the Setpoint when the sleep event happens, which is captured in CPU_SP_PREVIOUS 0x1 CM_SP_STAT CM Setpoint Status 0x304 32 read-only 0 0xFFFFFFFF CPU_SP_CURRENT The current Setpoint of the system 0 4 read-only CPU_SP_PREVIOUS The previous Setpoint of the system 4 4 read-only CPU_SP_TARGET The requested Setpoint from the CPU platform 8 4 read-only CM_RUN_MODE_MAPPING CM Run Mode Setpoint Allowed 0x310 32 read-write 0xFFFF 0xFFFFFFFF CPU_RUN_MODE_MAPPING Defines which Setpoint is allowed when CPU enters RUN mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG field 0 16 read-write CM_WAIT_MODE_MAPPING CM Wait Mode Setpoint Allowed 0x314 32 read-write 0xFFFF 0xFFFFFFFF CPU_WAIT_MODE_MAPPING Defines which Setpoint is allowed when CPU enters WAIT mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG 0 16 read-write CM_STOP_MODE_MAPPING CM Stop Mode Setpoint Allowed 0x318 32 read-write 0xFFFF 0xFFFFFFFF CPU_STOP_MODE_MAPPING Defines which Setpoint is allowed when CPU enters STOP mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG 0 16 read-write CM_SUSPEND_MODE_MAPPING CM Suspend Mode Setpoint Allowed 0x31C 32 read-write 0xFFFF 0xFFFFFFFF CPU_SUSPEND_MODE_MAPPING Defines which Setpoint is allowed when CPU enters SUSPEND mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG 0 16 read-write CM_SP0_MAPPING CM Setpoint 0 Mapping 0x320 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP0_MAPPING Defines when SP0 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP1_MAPPING CM Setpoint 1 Mapping 0x324 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP1_MAPPING Defines when SP1 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP2_MAPPING CM Setpoint 2 Mapping 0x328 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP2_MAPPING Defines when SP2 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP3_MAPPING CM Setpoint 3 Mapping 0x32C 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP3_MAPPING Defines when SP3 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP4_MAPPING CM Setpoint 4 Mapping 0x330 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP4_MAPPING Defines when SP4 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP5_MAPPING CM Setpoint 5 Mapping 0x334 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP5_MAPPING Defines when SP5 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP6_MAPPING CM Setpoint 6 Mapping 0x338 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP6_MAPPING Defines when SP6 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP7_MAPPING CM Setpoint 7 Mapping 0x33C 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP7_MAPPING Defines when SP7 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP8_MAPPING CM Setpoint 8 Mapping 0x340 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP8_MAPPING Defines when SP8 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP9_MAPPING CM Setpoint 9 Mapping 0x344 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP9_MAPPING Defines when SP9 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP10_MAPPING CM Setpoint 10 Mapping 0x348 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP10_MAPPING Defines when SP10 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP11_MAPPING CM Setpoint 11 Mapping 0x34C 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP11_MAPPING Defines when SP11 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP12_MAPPING CM Setpoint 12 Mapping 0x350 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP12_MAPPING Defines when SP12 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP13_MAPPING CM Setpoint 13 Mapping 0x354 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP13_MAPPING Defines when SP13 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP14_MAPPING CM Setpoint 14 Mapping 0x358 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP14_MAPPING Defines when SP14 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_SP15_MAPPING CM Setpoint 15 Mapping 0x35C 32 read-write 0xFFFF 0xFFFFFFFF CPU_SP15_MAPPING Defines when SP15 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field 0 16 read-write CM_STBY_CTRL CM standby control 0x380 32 read-write 0 0xFFFFFFFF STBY_WAIT 0x1: Request the chip into standby mode when CPU entering WAIT mode, locked by LOCK_CFG field. 0 1 read-write STBY_STOP 0x1: Request the chip into standby mode when CPU entering STOP mode, locked by LOCK_CFG field. 1 1 read-write STBY_SUSPEND 0x1: Request the chip into standby mode when CPU entering SUSPEND mode, locked by LOCK_CFG field. 2 1 read-write STBY_SLEEP_BUSY Indicate the CPU is busy entering standby mode. 16 1 read-only STBY_WAKEUP_BUSY Indicate the CPU is busy exiting standby mode. 17 1 read-only GPC_CPU_MODE_CTRL_1 GPC_CPU GPC_CPU_MODE_CTRL 0x40C00800 0 0x800 registers GPC_SET_POINT_CTRL GPC_SP GPC_SET_POINT_CTRL 0x40C02000 0 0x800 registers SP_AUTHEN_CTRL SP Authentication Control 0x4 32 read-write 0xF00 0xFFFFFFFF USER Allow user mode access 0 1 read-write b0 Allow only privilege mode to access setpoint control registers 0 b1 Allow both privilege and user mode to access setpoint control registers 0x1 NONSECURE Allow non-secure mode access 1 1 read-write b0 Allow only secure mode to access setpoint control registers 0 b1 Allow both secure and non-secure mode to access setpoint control registers 0x1 LOCK_SETTING Lock NONSECURE and USER 4 1 read-write WHITE_LIST Domain ID white list 8 4 read-write LOCK_LIST White list lock 12 1 read-write LOCK_CFG Configuration lock 20 1 read-write SP_INT_CTRL SP Interrupt Control 0x8 32 read-write 0x1 0xFFFFFFFF NO_ALLOWED_SP_INT_EN no_allowed_set_point interrupt enable 0 1 read-write NO_ALLOWED_SP_INT no_allowed_set_point interrupt 1 1 read-write oneToClear SP_CPU_REQ CPU SP Request 0x10 32 read-only 0 0xFFFFFFFF SP_REQ_CPU0 Setpoint requested by CPU0 0 4 read-only SP_REQ_CPU1 Setpoint requested by CPU1 4 4 read-only SP_REQ_CPU2 Setpoint requested by CPU2 8 4 read-only SP_REQ_CPU3 Setpoint requested by CPU3 12 4 read-only SP_ACCEPTED_CPU0 CPU0 Setpoint accepted by SP controller 16 4 read-only SP_ACCEPTED_CPU1 CPU1 Setpoint accepted by SP controller 20 4 read-only SP_ACCEPTED_CPU2 CPU2 Setpoint accepted by SP controller 24 4 read-only SP_ACCEPTED_CPU3 CPU3 Setpoint accepted by SP controller 28 4 read-only SP_SYS_STAT SP System Status 0x14 32 read-only 0xFFFF 0xFFFFFFFF SYS_SP_ALLOWED Allowed Setpoints by all current CPU Setpoint requests 0 16 read-only SYS_SP_TARGET The Setpoint chosen as the target setpoint 16 4 read-only SYS_SP_CURRENT Current Setpoint, only valid when not SP trans busy 20 4 read-only SYS_SP_PREVIOUS Previous Setpoint, only valid when not SP trans busy 24 4 read-only SP_ROSC_CTRL SP ROSC Control 0x1C 32 read-write 0 0xFFFFFFFF SP_ALLOW_ROSC_OFF Allow shutting off the ROSC 0 16 read-write SP_PRIORITY_0_7 SP0~7 Priority 0x40 32 read-write 0x76543210 0xFFFFFFFF SYS_SP0_PRIORITY priority of Setpoint 0 0 4 read-write SYS_SP1_PRIORITY priority of Setpoint 1 4 4 read-write SYS_SP2_PRIORITY priority of Setpoint 2 8 4 read-write SYS_SP3_PRIORITY priority of Setpoint 3 12 4 read-write SYS_SP4_PRIORITY priority of Setpoint 4 16 4 read-write SYS_SP5_PRIORITY priority of Setpoint 5 20 4 read-write SYS_SP6_PRIORITY priority of Setpoint 6 24 4 read-write SYS_SP7_PRIORITY priority of Setpoint 7 28 4 read-write SP_PRIORITY_8_15 SP8~15 Priority 0x44 32 read-write 0xFEDCBA98 0xFFFFFFFF SYS_SP8_PRIORITY priority of Setpoint 8 0 4 read-write SYS_SP9_PRIORITY priority of Setpoint 9 4 4 read-write SYS_SP10_PRIORITY priority of Setpoint 10 8 4 read-write SYS_SP11_PRIORITY priority of Setpoint 11 12 4 read-write SYS_SP12_PRIORITY priority of Setpoint 12 16 4 read-write SYS_SP13_PRIORITY priority of Setpoint 13 20 4 read-write SYS_SP14_PRIORITY priority of Setpoint 14 24 4 read-write SYS_SP15_PRIORITY priority of Setpoint 15 28 4 read-write SP_SSAR_SAVE_CTRL SP SSAR save control 0x100 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_LPCG_OFF_CTRL SP LPCG off control 0x110 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_GROUP_DOWN_CTRL SP group down control 0x120 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_ROOT_DOWN_CTRL SP root down control 0x130 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_PLL_OFF_CTRL SP PLL off control 0x140 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_ISO_ON_CTRL SP ISO on control 0x150 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_RESET_EARLY_CTRL SP reset early control 0x160 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_POWER_OFF_CTRL SP power off control 0x170 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_BIAS_OFF_CTRL SP bias off control 0x180 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_BG_PLDO_OFF_CTRL SP bandgap and PLL_LDO off control 0x190 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_LDO_PRE_CTRL SP LDO pre control 0x1A0 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_DCDC_DOWN_CTRL SP DCDC down control 0x1B0 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_DCDC_UP_CTRL SP DCDC up control 0x200 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_LDO_POST_CTRL SP LDO post control 0x210 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_BG_PLDO_ON_CTRL SP bandgap and PLL_LDO on control 0x220 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_BIAS_ON_CTRL SP bias on control 0x230 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_POWER_ON_CTRL SP power on control 0x240 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_RESET_LATE_CTRL SP reset late control 0x250 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_ISO_OFF_CTRL SP ISO off control 0x260 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_PLL_ON_CTRL SP PLL on control 0x270 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_ROOT_UP_CTRL SP root up control 0x280 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_GROUP_UP_CTRL SP group up control 0x290 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_LPCG_ON_CTRL SP LPCG on control 0x2A0 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SP_SSAR_RESTORE_CTRL SP SSAR restore control 0x2B0 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write GPC_STBY_CTRL GPC_STBY GPC_STBY_CTRL 0x40C02800 0 0x800 registers STBY_AUTHEN_CTRL Standby Authentication Control 0x4 32 read-write 0 0xFFFFFFFF LOCK_CFG Configuration lock 20 1 read-write STBY_MISC STBY Misc 0xC 32 read-write 0 0xFFFFFFFF FORCE_CPU0_STBY Force CPU0 requesting standby mode 0 1 read-write FORCE_CPU1_STBY Force CPU0 requesting standby mode 1 1 read-write FORCE_CPU2_STBY Force CPU2 requesting standby mode 2 1 read-write FORCE_CPU3_STBY Force CPU3 requesting standby mode 3 1 read-write STBY_LPCG_IN_CTRL STBY lpcg_in control 0xF0 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_PLL_IN_CTRL STBY pll_in control 0x100 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_BIAS_IN_CTRL STBY bias_in control 0x110 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_PLDO_IN_CTRL STBY pldo_in control 0x120 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_BANDGAP_IN_CTRL STBY bandgap_in control 0x128 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_LDO_IN_CTRL STBY ldo_in control 0x130 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_DCDC_IN_CTRL STBY dcdc_in control 0x140 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_PMIC_IN_CTRL STBY PMIC in control 0x150 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_PMIC_OUT_CTRL STBY PMIC out control 0x200 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_DCDC_OUT_CTRL STBY DCDC out control 0x210 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_LDO_OUT_CTRL STBY LDO out control 0x220 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_BANDGAP_OUT_CTRL STBY bandgap out control 0x230 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_PLDO_OUT_CTRL STBY pldo out control 0x238 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_BIAS_OUT_CTRL STBY bias out control 0x240 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_PLL_OUT_CTRL STBY PLL out control 0x250 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write STBY_LPCG_OUT_CTRL STBY LPCG out control 0x260 32 read-write 0x4 0xFFFFFFFF STEP_CNT Step count, useage is depending on CNT_MODE 0 16 read-write CNT_MODE Count mode 28 2 read-write b0 Counter disable mode: not use step counter, step completes once receiving step_done 0 b1 Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT 0x1 b2 Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes 0x2 b3 Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value 0x3 DISABLE Disable this step 31 1 read-write SRC SRC SRC 0x40C04000 0 0x334 registers SCR SRC Control Register 0 32 read-write 0 0xFFFFFFFF BT_RELEASE_M4 cm4 core reset will be held until boot core write this bit to 1 to release it. 0 1 read-write BT_RELEASE_M4_0 cm4 core reset is asserted 0 BT_RELEASE_M4_1 cm4 core reset is released 0x1 BT_RELEASE_M7 cm7 core reset will be held until boot core write this bit to 1 to release it. 1 1 read-write BT_RELEASE_M7_0 cm7 core reset is asserted 0 BT_RELEASE_M7_1 cm7 core reset is released 0x1 SRMR SRC Reset Mode Register 0x4 32 read-write 0 0xFFFFFFFF WDOG_RESET_MODE Wdog reset mode configuration 0 2 read-write WDOG_RESET_MODE_0 reset system 0 WDOG_RESET_MODE_3 do not reset anything 0x3 WDOG3_RESET_MODE Wdog3 reset mode configuration 2 2 read-write WDOG3_RESET_MODE_0 reset system 0 WDOG3_RESET_MODE_3 do not reset anything 0x3 WDOG4_RESET_MODE Wdog4 reset mode configuration 4 2 read-write WDOG4_RESET_MODE_0 reset system 0 WDOG4_RESET_MODE_3 do not reset anything 0x3 M4LOCKUP_RESET_MODE M4 core lockup reset mode configuration 6 2 read-write M4LOCKUP_RESET_MODE_0 reset system 0 M4LOCKUP_RESET_MODE_3 do not reset anything 0x3 M7LOCKUP_RESET_MODE M7 core lockup reset mode configuration 8 2 read-write M7LOCKUP_RESET_MODE_0 reset system 0 M7LOCKUP_RESET_MODE_3 do not reset anything 0x3 M4REQ_RESET_MODE M4 request reset configuration 10 2 read-write M4REQ_RESET_MODE_0 reset system 0 M4REQ_RESET_MODE_3 do not reset anything 0x3 M7REQ_RESET_MODE M7 request reset configuration 12 2 read-write M7REQ_RESET_MODE_0 reset system 0 M7REQ_RESET_MODE_3 do not reset anything 0x3 TEMPSENSE_RESET_MODE Tempsense reset mode configuration 14 2 read-write TEMPSENSE_RESET_MODE_0 reset system 0 TEMPSENSE_RESET_MODE_3 do not reset anything 0x3 CSU_RESET_MODE CSU reset mode configuration 16 2 read-write CSU_RESET_MODE_0 reset system 0 CSU_RESET_MODE_3 do not reset anything 0x3 JTAGSW_RESET_MODE Jtag SW reset mode configuration 18 2 read-write JTAGSW_RESET_MODE_0 reset system 0 JTAGSW_RESET_MODE_3 do not reset anything 0x3 OVERVOLT_RESET_MODE Jtag SW reset mode configuration 20 2 read-write OVERVOLT_RESET_MODE_0 reset system 0 OVERVOLT_RESET_MODE_3 do not reset anything 0x3 SBMR1 SRC Boot Mode Register 1 0x8 32 read-only 0 0xFFFFFFFF BOOT_CFG1 Please see fusemap. 0 8 read-only BOOT_CFG2 Please see fusemap. 8 8 read-only BOOT_CFG3 Please see fusemap. 16 8 read-only BOOT_CFG4 Please see fusemap. 24 8 read-only SBMR2 SRC Boot Mode Register 2 0xC 32 read-only 0 0xFFFFFFFF SEC_CONFIG SECONFIG[1] shows the state of the SECONFIG[1] fuse 0 2 read-only BT_FUSE_SEL BT_FUSE_SEL shows the state of the BT_FUSE_SEL fuse 4 1 read-only BMOD BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B 24 2 read-only SRSR SRC Reset Status Register 0x10 32 read-write 0 0xFFFFFFFF oneToClear IPP_RESET_B_M7 Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence) 0 1 read-write oneToClear IPP_RESET_B_M7_0 Reset is not a result of ipp_reset_b pin. 0 IPP_RESET_B_M7_1 Reset is a result of ipp_reset_b pin. 0x1 M7_REQUEST_M7 Indicates whether reset was the result of m7 reset request 1 1 read-write oneToClear M7_REQUEST_M7_0 Reset is not a result of m7 reset request. 0 M7_REQUEST_M7_1 Reset is a result of m7 reset request. 0x1 M7_LOCKUP_M7 Indicates a reset has been caused by M7 CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core 2 1 read-write oneToClear M7_LOCKUP_M7_0 Reset is not a result of the mentioned case. 0 M7_LOCKUP_M7_1 Reset is a result of the mentioned case. 0x1 CSU_RESET_B_M7 Indicates whether the reset was the result of the csu_reset_b input. 3 1 read-write oneToClear CSU_RESET_B_M7_0 Reset is not a result of the csu_reset_b event. 0 CSU_RESET_B_M7_1 Reset is a result of the csu_reset_b event. 0x1 IPP_USER_RESET_B_M7 Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. 4 1 read-write oneToClear IPP_USER_RESET_B_M7_0 Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. 0 IPP_USER_RESET_B_M7_1 Reset is a result of the ipp_user_reset_b qualified as COLD reset event. 0x1 WDOG_RST_B_M7 IC Watchdog Time-out reset 5 1 read-write oneToClear WDOG_RST_B_M7_0 Reset is not a result of the watchdog time-out event. 0 WDOG_RST_B_M7_1 Reset is a result of the watchdog time-out event. 0x1 JTAG_RST_B_M7 HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG. 6 1 read-write oneToClear JTAG_RST_B_M7_0 Reset is not a result of HIGH-Z reset from JTAG. 0 JTAG_RST_B_M7_1 Reset is a result of HIGH-Z reset from JTAG. 0x1 JTAG_SW_RST_M7 JTAG software reset. Indicates whether the reset was the result of software reset from JTAG. 7 1 read-write oneToClear JTAG_SW_RST_M7_0 Reset is not a result of software reset from JTAG. 0 JTAG_SW_RST_M7_1 Reset is a result of software reset from JTAG. 0x1 WDOG3_RST_B_M7 IC Watchdog3 Time-out reset 8 1 read-write oneToClear WDOG3_RST_B_M7_0 Reset is not a result of the watchdog3 time-out event. 0 WDOG3_RST_B_M7_1 Reset is a result of the watchdog3 time-out event. 0x1 WDOG4_RST_B_M7 IC Watchdog4 Time-out reset 9 1 read-write oneToClear WDOG4_RST_B_M7_0 Reset is not a result of the watchdog4 time-out event. 0 WDOG4_RST_B_M7_1 Reset is a result of the watchdog4 time-out event. 0x1 TEMPSENSE_RST_B_M7 Temper Sensor software reset 10 1 read-write oneToClear TEMPSENSE_RST_B_M7_0 Reset is not a result of software reset from Temperature Sensor. 0 TEMPSENSE_RST_B_M7_1 Reset is a result of software reset from Temperature Sensor. 0x1 M4_REQUEST_M7 Indicates whether reset was the result of m4 reset request. 11 1 read-write oneToClear M4_REQUEST_M7_0 Reset is not a result of m4 reset request. 0 M4_REQUEST_M7_1 Reset is a result of m4 reset request. 0x1 M4_LOCKUP_M7 Indicates a reset has been caused by M4 CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core 12 1 read-write oneToClear M4_LOCKUP_M7_0 Reset is not a result of the mentioned case. 0 M4_LOCKUP_M7_1 Reset is a result of the mentioned case. 0x1 OVERVOLT_RST_M7 Indicates a reset has been caused by power suppy voltage over the highest permitted level. 13 1 read-write oneToClear OVERVOLT_RST_M7_0 Reset is not a result of the mentioned case. 0 OVERVOLT_RST_M7_1 Reset is a result of the mentioned case. 0x1 CDOG_RST_M7 Indicates a reset has been caused by CDOG reset. 14 1 read-write oneToClear CDOG_RST_M7_0 Reset is not a result of the mentioned case. 0 CDOG_RST_M7_1 Reset is a result of the mentioned case. 0x1 IPP_RESET_B_M4 Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence) 16 1 read-write oneToClear IPP_RESET_B_M4_0 Reset is not a result of ipp_reset_b pin. 0 IPP_RESET_B_M4_1 Reset is a result of ipp_reset_b pin. 0x1 M4_REQUEST_M4 Indicates whether reset was the result of m4 reset request 17 1 read-write oneToClear M4_REQUEST_M4_0 Reset is not a result of m4 reset request. 0 M4_REQUEST_M4_1 Reset is a result of m4 reset request. 0x1 M4_LOCKUP_M4 Indicates a reset has been caused by M4 CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core 18 1 read-write oneToClear M4_LOCKUP_M4_0 Reset is not a result of the mentioned case. 0 M4_LOCKUP_M4_1 Reset is a result of the mentioned case. 0x1 CSU_RESET_B_M4 Indicates whether the reset was the result of the csu_reset_b input. 19 1 read-write oneToClear CSU_RESET_B_M4_0 Reset is not a result of the csu_reset_b event. 0 CSU_RESET_B_M4_1 Reset is a result of the csu_reset_b event. 0x1 IPP_USER_RESET_B_M4 Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. 20 1 read-write oneToClear IPP_USER_RESET_B_M4_0 Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. 0 IPP_USER_RESET_B_M4_1 Reset is a result of the ipp_user_reset_b qualified as COLD reset event. 0x1 WDOG_RST_B_M4 IC Watchdog Time-out reset 21 1 read-write oneToClear WDOG_RST_B_M4_0 Reset is not a result of the watchdog time-out event. 0 WDOG_RST_B_M4_1 Reset is a result of the watchdog time-out event. 0x1 JTAG_RST_B_M4 HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG. 22 1 read-write oneToClear JTAG_RST_B_M4_0 Reset is not a result of HIGH-Z reset from JTAG. 0 JTAG_RST_B_M4_1 Reset is a result of HIGH-Z reset from JTAG. 0x1 JTAG_SW_RST_M4 JTAG software reset. Indicates whether the reset was the result of software reset from JTAG. 23 1 read-write oneToClear JTAG_SW_RST_M4_0 Reset is not a result of software reset from JTAG. 0 JTAG_SW_RST_M4_1 Reset is a result of software reset from JTAG. 0x1 WDOG3_RST_B_M4 IC Watchdog3 Time-out reset 24 1 read-write oneToClear WDOG3_RST_B_M4_0 Reset is not a result of the watchdog3 time-out event. 0 WDOG3_RST_B_M4_1 Reset is a result of the watchdog3 time-out event. 0x1 WDOG4_RST_B_M4 IC Watchdog4 Time-out reset 25 1 read-write oneToClear WDOG4_RST_B_M4_0 Reset is not a result of the watchdog4 time-out event. 0 WDOG4_RST_B_M4_1 Reset is a result of the watchdog4 time-out event. 0x1 TEMPSENSE_RST_B_M4 Temper Sensor software reset 26 1 read-write oneToClear TEMPSENSE_RST_B_M4_0 Reset is not a result of software reset from Temperature Sensor. 0 TEMPSENSE_RST_B_M4_1 Reset is a result of software reset from Temperature Sensor. 0x1 M7_REQUEST_M4 Indicates whether reset was the result of m7 reset request. 27 1 read-write oneToClear M7_REQUEST_M4_0 Reset is not a result of m7 reset request. 0 M7_REQUEST_M4_1 Reset is a result of m7 reset request. 0x1 M7_LOCKUP_M4 Indicates a reset has been caused by M7 CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core 28 1 read-write oneToClear M7_LOCKUP_M4_0 Reset is not a result of the mentioned case. 0 M7_LOCKUP_M4_1 Reset is a result of the mentioned case. 0x1 OVERVOLT_RST_M4 Indicates a reset has been caused by power suppy voltage over the highest permitted level. 29 1 read-write oneToClear OVERVOLT_RST_M4_0 Reset is not a result of the mentioned case. 0 OVERVOLT_RST_M4_1 Reset is a result of the mentioned case. 0x1 CDOG_RST_M4 Indicates a reset has been caused by CDOG reset. 30 1 read-write oneToClear CDOG_RST_M4_0 Reset is not a result of the mentioned case. 0 CDOG_RST_M4_1 Reset is a result of the mentioned case. 0x1 20 0x4 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20 GPR%s SRC General Purpose Register 0x14 32 read-write 0 0xFFFFFFFF GPR General Purpose Register. 0 32 read-write AUTHEN_MEGA Slice Authentication Register 0x200 32 read-write 0 0xFFFFFFFF DOMAIN_MODE Control whether reset slice is in domain mode 0 1 read-write DOMAIN_MODE_0 slice hardware reset will NOT be triggered by CPU power mode transition 0 DOMAIN_MODE_1 slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. 0x1 SETPOINT_MODE Control whether reset slice is in Setpoint mode 1 1 read-write SETPOINT_MODE_0 slice hardware reset will NOT be triggered by Setpoint transition 0 SETPOINT_MODE_1 slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. 0x1 LOCK_MODE Domain/Setpoint mode lock 7 1 read-write ASSIGN_LIST when this bitfield set to 1, reset of slice would be subject to corresponding core status transition 8 4 read-write LOCK_ASSIGN Assign list lock 15 1 read-write WHITE_LIST Domain ID white list 16 4 read-write LOCK_LIST White list lock 23 1 read-write USER Allow user mode access 24 1 read-write NONSECURE Allow non-secure mode access 25 1 read-write LOCK_SETTING Lock NONSECURE and USER 31 1 read-write CTRL_MEGA Slice Control Register 0x204 32 read-write 0 0xFFFFFFFF SW_RESET This is a self clearing bit 0 1 read-write SW_RESET_0 do not assert slice software reset 0 SW_RESET_1 assert slice software reset 0x1 SETPOINT_MEGA Slice Setpoint Config Register 0x208 32 read-write 0 0xFFFFFFFF SETPOINT0 SETPOINT0 0 1 read-write SETPOINT0_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT0_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT1 SETPOINT1 1 1 read-write SETPOINT1_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT1_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT2 SETPOINT2 2 1 read-write SETPOINT2_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT2_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT3 SETPOINT3 3 1 read-write SETPOINT3_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT3_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT4 SETPOINT4 4 1 read-write SETPOINT4_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT4_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT5 SETPOINT5 5 1 read-write SETPOINT5_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT5_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT6 SETPOINT6 6 1 read-write SETPOINT6_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT6_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT7 SETPOINT7 7 1 read-write SETPOINT7_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT7_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT8 SETPOINT8 8 1 read-write SETPOINT8_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT8_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT9 SETPOINT9 9 1 read-write SETPOINT9_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT9_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT10 SETPOINT10 10 1 read-write SETPOINT10_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT10_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT11 SETPOINT11 11 1 read-write SETPOINT11_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT11_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT12 SETPOINT12 12 1 read-write SETPOINT12_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT12_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT13 SETPOINT13 13 1 read-write SETPOINT13_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT13_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT14 SETPOINT14 14 1 read-write SETPOINT14_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT14_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT15 SETPOINT15 15 1 read-write SETPOINT15_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT15_1 Slice reset will be asserted when system in Setpoint n 0x1 DOMAIN_MEGA Slice Domain Config Register 0x20C 32 read-write 0 0xFFFFFFFF CPU0_RUN CPU mode setting for RUN 0 1 read-write CPU0_RUN_0 Slice reset will be de-asserted when CPU0 in RUN mode 0 CPU0_RUN_1 Slice reset will be asserted when CPU0 in RUN mode 0x1 CPU0_WAIT CPU mode setting for WAIT 1 1 read-write CPU0_WAIT_0 Slice reset will be de-asserted when CPU0 in WAIT mode 0 CPU0_WAIT_1 Slice reset will be asserted when CPU0 in WAIT mode 0x1 CPU0_STOP CPU mode setting for STOP 2 1 read-write CPU0_STOP_0 Slice reset will be de-asserted when CPU0 in STOP mode 0 CPU0_STOP_1 Slice reset will be asserted when CPU0 in STOP mode 0x1 CPU0_SUSP CPU mode setting for SUSPEND 3 1 read-write CPU0_SUSP_0 Slice reset will be de-asserted when CPU0 in SUSPEND mode 0 CPU0_SUSP_1 Slice reset will be asserted when CPU0 in SUSPEND mode 0x1 CPU1_RUN CPU mode setting for RUN 4 1 read-write CPU1_RUN_0 Slice reset will be de-asserted when CPU1 in RUN mode 0 CPU1_RUN_1 Slice reset will be asserted when CPU1 in RUN mode 0x1 CPU1_WAIT CPU mode setting for WAIT 5 1 read-write CPU1_WAIT_0 Slice reset will be de-asserted when CPU1 in WAIT mode 0 CPU1_WAIT_1 Slice reset will be asserted when CPU1 in WAIT mode 0x1 CPU1_STOP CPU mode setting for STOP 6 1 read-write CPU1_STOP_0 Slice reset will be de-asserted when CPU1 in STOP mode 0 CPU1_STOP_1 Slice reset will be asserted when CPU1 in STOP mode 0x1 CPU1_SUSP CPU mode setting for SUSPEND 7 1 read-write CPU1_SUSP_0 Slice reset will be de-asserted when CPU1 in SUSPEND mode 0 CPU1_SUSP_1 Slice reset will be asserted when CPU1 in SUSPEND mode 0x1 STAT_MEGA Slice Status Register 0x210 32 read-write 0 0xFFFFFFFF UNDER_RST This is a Read Only bit. It indicate if the reset is in process. 0 1 read-only UNDER_RST_0 the reset is finished 0 UNDER_RST_1 the reset is in process 0x1 RST_BY_HW This bit indicate if the reset is caused by the power mode transfer. 2 1 read-write oneToClear RST_BY_HW_0 the reset is not caused by the power mode transfer 0 RST_BY_HW_1 the reset is caused by the power mode transfer 0x1 RST_BY_SW This bit indicate if the reset is caused by setting SW_RESET bit. 3 1 read-write oneToClear RST_BY_SW_0 the reset is not caused by software setting 0 RST_BY_SW_1 the reset is caused by software setting 0x1 AUTHEN_DISPLAY Slice Authentication Register 0x220 32 read-write 0 0xFFFFFFFF DOMAIN_MODE Control whether reset slice is in domain mode 0 1 read-write DOMAIN_MODE_0 slice hardware reset will NOT be triggered by CPU power mode transition 0 DOMAIN_MODE_1 slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. 0x1 SETPOINT_MODE Control whether reset slice is in Setpoint mode 1 1 read-write SETPOINT_MODE_0 slice hardware reset will NOT be triggered by Setpoint transition 0 SETPOINT_MODE_1 slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. 0x1 LOCK_MODE Domain/Setpoint mode lock 7 1 read-write ASSIGN_LIST when this bitfield set to 1, reset of slice would be subject to corresponding core status transition 8 4 read-write LOCK_ASSIGN Assign list lock 15 1 read-write WHITE_LIST Domain ID white list 16 4 read-write LOCK_LIST White list lock 23 1 read-write USER Allow user mode access 24 1 read-write NONSECURE Allow non-secure mode access 25 1 read-write LOCK_SETTING Lock NONSECURE and USER 31 1 read-write CTRL_DISPLAY Slice Control Register 0x224 32 read-write 0 0xFFFFFFFF SW_RESET This is a self clearing bit 0 1 read-write SW_RESET_0 do not assert slice software reset 0 SW_RESET_1 assert slice software reset 0x1 SETPOINT_DISPLAY Slice Setpoint Config Register 0x228 32 read-write 0 0xFFFFFFFF SETPOINT0 SETPOINT0 0 1 read-write SETPOINT0_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT0_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT1 SETPOINT1 1 1 read-write SETPOINT1_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT1_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT2 SETPOINT2 2 1 read-write SETPOINT2_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT2_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT3 SETPOINT3 3 1 read-write SETPOINT3_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT3_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT4 SETPOINT4 4 1 read-write SETPOINT4_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT4_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT5 SETPOINT5 5 1 read-write SETPOINT5_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT5_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT6 SETPOINT6 6 1 read-write SETPOINT6_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT6_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT7 SETPOINT7 7 1 read-write SETPOINT7_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT7_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT8 SETPOINT8 8 1 read-write SETPOINT8_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT8_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT9 SETPOINT9 9 1 read-write SETPOINT9_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT9_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT10 SETPOINT10 10 1 read-write SETPOINT10_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT10_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT11 SETPOINT11 11 1 read-write SETPOINT11_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT11_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT12 SETPOINT12 12 1 read-write SETPOINT12_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT12_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT13 SETPOINT13 13 1 read-write SETPOINT13_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT13_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT14 SETPOINT14 14 1 read-write SETPOINT14_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT14_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT15 SETPOINT15 15 1 read-write SETPOINT15_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT15_1 Slice reset will be asserted when system in Setpoint n 0x1 DOMAIN_DISPLAY Slice Domain Config Register 0x22C 32 read-write 0 0xFFFFFFFF CPU0_RUN CPU mode setting for RUN 0 1 read-write CPU0_RUN_0 Slice reset will be de-asserted when CPU0 in RUN mode 0 CPU0_RUN_1 Slice reset will be asserted when CPU0 in RUN mode 0x1 CPU0_WAIT CPU mode setting for WAIT 1 1 read-write CPU0_WAIT_0 Slice reset will be de-asserted when CPU0 in WAIT mode 0 CPU0_WAIT_1 Slice reset will be asserted when CPU0 in WAIT mode 0x1 CPU0_STOP CPU mode setting for STOP 2 1 read-write CPU0_STOP_0 Slice reset will be de-asserted when CPU0 in STOP mode 0 CPU0_STOP_1 Slice reset will be asserted when CPU0 in STOP mode 0x1 CPU0_SUSP CPU mode setting for SUSPEND 3 1 read-write CPU0_SUSP_0 Slice reset will be de-asserted when CPU0 in SUSPEND mode 0 CPU0_SUSP_1 Slice reset will be asserted when CPU0 in SUSPEND mode 0x1 CPU1_RUN CPU mode setting for RUN 4 1 read-write CPU1_RUN_0 Slice reset will be de-asserted when CPU1 in RUN mode 0 CPU1_RUN_1 Slice reset will be asserted when CPU1 in RUN mode 0x1 CPU1_WAIT CPU mode setting for WAIT 5 1 read-write CPU1_WAIT_0 Slice reset will be de-asserted when CPU1 in WAIT mode 0 CPU1_WAIT_1 Slice reset will be asserted when CPU1 in WAIT mode 0x1 CPU1_STOP CPU mode setting for STOP 6 1 read-write CPU1_STOP_0 Slice reset will be de-asserted when CPU1 in STOP mode 0 CPU1_STOP_1 Slice reset will be asserted when CPU1 in STOP mode 0x1 CPU1_SUSP CPU mode setting for SUSPEND 7 1 read-write CPU1_SUSP_0 Slice reset will be de-asserted when CPU1 in SUSPEND mode 0 CPU1_SUSP_1 Slice reset will be asserted when CPU1 in SUSPEND mode 0x1 STAT_DISPLAY Slice Status Register 0x230 32 read-write 0 0xFFFFFFFF UNDER_RST This is a Read Only bit. It indicate if the reset is in process. 0 1 read-only UNDER_RST_0 the reset is finished 0 UNDER_RST_1 the reset is in process 0x1 RST_BY_HW This bit indicate if the reset is caused by the power mode transfer. 2 1 read-write oneToClear RST_BY_HW_0 the reset is not caused by the power mode transfer 0 RST_BY_HW_1 the reset is caused by the power mode transfer 0x1 RST_BY_SW This bit indicate if the reset is caused by setting SW_RESET bit. 3 1 read-write oneToClear RST_BY_SW_0 the reset is not caused by software setting 0 RST_BY_SW_1 the reset is caused by software setting 0x1 AUTHEN_WAKEUP Slice Authentication Register 0x240 32 read-write 0 0xFFFFFFFF DOMAIN_MODE Control whether reset slice is in domain mode 0 1 read-write DOMAIN_MODE_0 slice hardware reset will NOT be triggered by CPU power mode transition 0 DOMAIN_MODE_1 slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. 0x1 SETPOINT_MODE Control whether reset slice is in Setpoint mode 1 1 read-write SETPOINT_MODE_0 slice hardware reset will NOT be triggered by Setpoint transition 0 SETPOINT_MODE_1 slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. 0x1 LOCK_MODE Domain/Setpoint mode lock 7 1 read-write ASSIGN_LIST when this bitfield set to 1, reset of slice would be subject to corresponding core status transition 8 4 read-write LOCK_ASSIGN Assign list lock 15 1 read-write WHITE_LIST Domain ID white list 16 4 read-write LOCK_LIST White list lock 23 1 read-write USER Allow user mode access 24 1 read-write NONSECURE Allow non-secure mode access 25 1 read-write LOCK_SETTING Lock NONSECURE and USER 31 1 read-write CTRL_WAKEUP Slice Control Register 0x244 32 read-write 0 0xFFFFFFFF SW_RESET This is a self clearing bit 0 1 read-write SW_RESET_0 do not assert slice software reset 0 SW_RESET_1 assert slice software reset 0x1 SETPOINT_WAKEUP Slice Setpoint Config Register 0x248 32 read-write 0 0xFFFFFFFF SETPOINT0 SETPOINT0 0 1 read-write SETPOINT0_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT0_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT1 SETPOINT1 1 1 read-write SETPOINT1_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT1_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT2 SETPOINT2 2 1 read-write SETPOINT2_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT2_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT3 SETPOINT3 3 1 read-write SETPOINT3_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT3_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT4 SETPOINT4 4 1 read-write SETPOINT4_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT4_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT5 SETPOINT5 5 1 read-write SETPOINT5_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT5_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT6 SETPOINT6 6 1 read-write SETPOINT6_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT6_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT7 SETPOINT7 7 1 read-write SETPOINT7_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT7_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT8 SETPOINT8 8 1 read-write SETPOINT8_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT8_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT9 SETPOINT9 9 1 read-write SETPOINT9_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT9_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT10 SETPOINT10 10 1 read-write SETPOINT10_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT10_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT11 SETPOINT11 11 1 read-write SETPOINT11_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT11_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT12 SETPOINT12 12 1 read-write SETPOINT12_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT12_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT13 SETPOINT13 13 1 read-write SETPOINT13_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT13_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT14 SETPOINT14 14 1 read-write SETPOINT14_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT14_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT15 SETPOINT15 15 1 read-write SETPOINT15_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT15_1 Slice reset will be asserted when system in Setpoint n 0x1 DOMAIN_WAKEUP Slice Domain Config Register 0x24C 32 read-write 0 0xFFFFFFFF CPU0_RUN CPU mode setting for RUN 0 1 read-write CPU0_RUN_0 Slice reset will be de-asserted when CPU0 in RUN mode 0 CPU0_RUN_1 Slice reset will be asserted when CPU0 in RUN mode 0x1 CPU0_WAIT CPU mode setting for WAIT 1 1 read-write CPU0_WAIT_0 Slice reset will be de-asserted when CPU0 in WAIT mode 0 CPU0_WAIT_1 Slice reset will be asserted when CPU0 in WAIT mode 0x1 CPU0_STOP CPU mode setting for STOP 2 1 read-write CPU0_STOP_0 Slice reset will be de-asserted when CPU0 in STOP mode 0 CPU0_STOP_1 Slice reset will be asserted when CPU0 in STOP mode 0x1 CPU0_SUSP CPU mode setting for SUSPEND 3 1 read-write CPU0_SUSP_0 Slice reset will be de-asserted when CPU0 in SUSPEND mode 0 CPU0_SUSP_1 Slice reset will be asserted when CPU0 in SUSPEND mode 0x1 CPU1_RUN CPU mode setting for RUN 4 1 read-write CPU1_RUN_0 Slice reset will be de-asserted when CPU1 in RUN mode 0 CPU1_RUN_1 Slice reset will be asserted when CPU1 in RUN mode 0x1 CPU1_WAIT CPU mode setting for WAIT 5 1 read-write CPU1_WAIT_0 Slice reset will be de-asserted when CPU1 in WAIT mode 0 CPU1_WAIT_1 Slice reset will be asserted when CPU1 in WAIT mode 0x1 CPU1_STOP CPU mode setting for STOP 6 1 read-write CPU1_STOP_0 Slice reset will be de-asserted when CPU1 in STOP mode 0 CPU1_STOP_1 Slice reset will be asserted when CPU1 in STOP mode 0x1 CPU1_SUSP CPU mode setting for SUSPEND 7 1 read-write CPU1_SUSP_0 Slice reset will be de-asserted when CPU1 in SUSPEND mode 0 CPU1_SUSP_1 Slice reset will be asserted when CPU1 in SUSPEND mode 0x1 STAT_WAKEUP Slice Status Register 0x250 32 read-write 0 0xFFFFFFFF UNDER_RST This is a Read Only bit. It indicate if the reset is in process. 0 1 read-only UNDER_RST_0 the reset is finished 0 UNDER_RST_1 the reset is in process 0x1 RST_BY_HW This bit indicate if the reset is caused by the power mode transfer. 2 1 read-write oneToClear RST_BY_HW_0 the reset is not caused by the power mode transfer 0 RST_BY_HW_1 the reset is caused by the power mode transfer 0x1 RST_BY_SW This bit indicate if the reset is caused by setting SW_RESET bit. 3 1 read-write oneToClear RST_BY_SW_0 the reset is not caused by software setting 0 RST_BY_SW_1 the reset is caused by software setting 0x1 AUTHEN_M4CORE Slice Authentication Register 0x280 32 read-write 0 0xFFFFFFFF DOMAIN_MODE Control whether reset slice is in domain mode 0 1 read-write DOMAIN_MODE_0 slice hardware reset will NOT be triggered by CPU power mode transition 0 DOMAIN_MODE_1 slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. 0x1 SETPOINT_MODE Control whether reset slice is in Setpoint mode 1 1 read-write SETPOINT_MODE_0 slice hardware reset will NOT be triggered by Setpoint transition 0 SETPOINT_MODE_1 slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. 0x1 LOCK_MODE Domain/Setpoint mode lock 7 1 read-write ASSIGN_LIST when this bitfield set to 1, reset of slice would be subject to corresponding core status transition 8 4 read-write LOCK_ASSIGN Assign list lock 15 1 read-write WHITE_LIST Domain ID white list 16 4 read-write LOCK_LIST White list lock 23 1 read-write USER Allow user mode access 24 1 read-write NONSECURE Allow non-secure mode access 25 1 read-write LOCK_SETTING Lock NONSECURE and USER 31 1 read-write CTRL_M4CORE Slice Control Register 0x284 32 read-write 0 0xFFFFFFFF SW_RESET This is a self clearing bit 0 1 read-write SW_RESET_0 do not assert slice software reset 0 SW_RESET_1 assert slice software reset 0x1 SETPOINT_M4CORE Slice Setpoint Config Register 0x288 32 read-write 0 0xFFFFFFFF SETPOINT0 SETPOINT0 0 1 read-write SETPOINT0_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT0_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT1 SETPOINT1 1 1 read-write SETPOINT1_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT1_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT2 SETPOINT2 2 1 read-write SETPOINT2_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT2_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT3 SETPOINT3 3 1 read-write SETPOINT3_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT3_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT4 SETPOINT4 4 1 read-write SETPOINT4_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT4_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT5 SETPOINT5 5 1 read-write SETPOINT5_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT5_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT6 SETPOINT6 6 1 read-write SETPOINT6_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT6_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT7 SETPOINT7 7 1 read-write SETPOINT7_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT7_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT8 SETPOINT8 8 1 read-write SETPOINT8_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT8_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT9 SETPOINT9 9 1 read-write SETPOINT9_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT9_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT10 SETPOINT10 10 1 read-write SETPOINT10_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT10_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT11 SETPOINT11 11 1 read-write SETPOINT11_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT11_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT12 SETPOINT12 12 1 read-write SETPOINT12_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT12_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT13 SETPOINT13 13 1 read-write SETPOINT13_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT13_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT14 SETPOINT14 14 1 read-write SETPOINT14_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT14_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT15 SETPOINT15 15 1 read-write SETPOINT15_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT15_1 Slice reset will be asserted when system in Setpoint n 0x1 DOMAIN_M4CORE Slice Domain Config Register 0x28C 32 read-write 0 0xFFFFFFFF CPU0_RUN CPU mode setting for RUN 0 1 read-write CPU0_RUN_0 Slice reset will be de-asserted when CPU0 in RUN mode 0 CPU0_RUN_1 Slice reset will be asserted when CPU0 in RUN mode 0x1 CPU0_WAIT CPU mode setting for WAIT 1 1 read-write CPU0_WAIT_0 Slice reset will be de-asserted when CPU0 in WAIT mode 0 CPU0_WAIT_1 Slice reset will be asserted when CPU0 in WAIT mode 0x1 CPU0_STOP CPU mode setting for STOP 2 1 read-write CPU0_STOP_0 Slice reset will be de-asserted when CPU0 in STOP mode 0 CPU0_STOP_1 Slice reset will be asserted when CPU0 in STOP mode 0x1 CPU0_SUSP CPU mode setting for SUSPEND 3 1 read-write CPU0_SUSP_0 Slice reset will be de-asserted when CPU0 in SUSPEND mode 0 CPU0_SUSP_1 Slice reset will be asserted when CPU0 in SUSPEND mode 0x1 CPU1_RUN CPU mode setting for RUN 4 1 read-write CPU1_RUN_0 Slice reset will be de-asserted when CPU1 in RUN mode 0 CPU1_RUN_1 Slice reset will be asserted when CPU1 in RUN mode 0x1 CPU1_WAIT CPU mode setting for WAIT 5 1 read-write CPU1_WAIT_0 Slice reset will be de-asserted when CPU1 in WAIT mode 0 CPU1_WAIT_1 Slice reset will be asserted when CPU1 in WAIT mode 0x1 CPU1_STOP CPU mode setting for STOP 6 1 read-write CPU1_STOP_0 Slice reset will be de-asserted when CPU1 in STOP mode 0 CPU1_STOP_1 Slice reset will be asserted when CPU1 in STOP mode 0x1 CPU1_SUSP CPU mode setting for SUSPEND 7 1 read-write CPU1_SUSP_0 Slice reset will be de-asserted when CPU1 in SUSPEND mode 0 CPU1_SUSP_1 Slice reset will be asserted when CPU1 in SUSPEND mode 0x1 STAT_M4CORE Slice Status Register 0x290 32 read-write 0 0xFFFFFFFF UNDER_RST This is a Read Only bit. It indicate if the reset is in process. 0 1 read-only UNDER_RST_0 the reset is finished 0 UNDER_RST_1 the reset is in process 0x1 RST_BY_HW This bit indicate if the reset is caused by the power mode transfer. 2 1 read-write oneToClear RST_BY_HW_0 the reset is not caused by the power mode transfer 0 RST_BY_HW_1 the reset is caused by the power mode transfer 0x1 RST_BY_SW This bit indicate if the reset is caused by setting SW_RESET bit. 3 1 read-write oneToClear RST_BY_SW_0 the reset is not caused by software setting 0 RST_BY_SW_1 the reset is caused by software setting 0x1 AUTHEN_M7CORE Slice Authentication Register 0x2A0 32 read-write 0 0xFFFFFFFF DOMAIN_MODE Control whether reset slice is in domain mode 0 1 read-write DOMAIN_MODE_0 slice hardware reset will NOT be triggered by CPU power mode transition 0 DOMAIN_MODE_1 slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. 0x1 SETPOINT_MODE Control whether reset slice is in Setpoint mode 1 1 read-write SETPOINT_MODE_0 slice hardware reset will NOT be triggered by Setpoint transition 0 SETPOINT_MODE_1 slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. 0x1 LOCK_MODE Domain/Setpoint mode lock 7 1 read-write ASSIGN_LIST when this bitfield set to 1, reset of slice would be subject to corresponding core status transition 8 4 read-write LOCK_ASSIGN Assign list lock 15 1 read-write WHITE_LIST Domain ID white list 16 4 read-write LOCK_LIST White list lock 23 1 read-write USER Allow user mode access 24 1 read-write NONSECURE Allow non-secure mode access 25 1 read-write LOCK_SETTING Lock NONSECURE and USER 31 1 read-write CTRL_M7CORE Slice Control Register 0x2A4 32 read-write 0 0xFFFFFFFF SW_RESET This is a self clearing bit 0 1 read-write SW_RESET_0 do not assert slice software reset 0 SW_RESET_1 assert slice software reset 0x1 SETPOINT_M7CORE Slice Setpoint Config Register 0x2A8 32 read-write 0 0xFFFFFFFF SETPOINT0 SETPOINT0 0 1 read-write SETPOINT0_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT0_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT1 SETPOINT1 1 1 read-write SETPOINT1_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT1_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT2 SETPOINT2 2 1 read-write SETPOINT2_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT2_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT3 SETPOINT3 3 1 read-write SETPOINT3_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT3_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT4 SETPOINT4 4 1 read-write SETPOINT4_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT4_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT5 SETPOINT5 5 1 read-write SETPOINT5_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT5_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT6 SETPOINT6 6 1 read-write SETPOINT6_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT6_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT7 SETPOINT7 7 1 read-write SETPOINT7_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT7_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT8 SETPOINT8 8 1 read-write SETPOINT8_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT8_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT9 SETPOINT9 9 1 read-write SETPOINT9_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT9_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT10 SETPOINT10 10 1 read-write SETPOINT10_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT10_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT11 SETPOINT11 11 1 read-write SETPOINT11_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT11_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT12 SETPOINT12 12 1 read-write SETPOINT12_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT12_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT13 SETPOINT13 13 1 read-write SETPOINT13_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT13_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT14 SETPOINT14 14 1 read-write SETPOINT14_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT14_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT15 SETPOINT15 15 1 read-write SETPOINT15_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT15_1 Slice reset will be asserted when system in Setpoint n 0x1 DOMAIN_M7CORE Slice Domain Config Register 0x2AC 32 read-write 0 0xFFFFFFFF CPU0_RUN CPU mode setting for RUN 0 1 read-write CPU0_RUN_0 Slice reset will be de-asserted when CPU0 in RUN mode 0 CPU0_RUN_1 Slice reset will be asserted when CPU0 in RUN mode 0x1 CPU0_WAIT CPU mode setting for WAIT 1 1 read-write CPU0_WAIT_0 Slice reset will be de-asserted when CPU0 in WAIT mode 0 CPU0_WAIT_1 Slice reset will be asserted when CPU0 in WAIT mode 0x1 CPU0_STOP CPU mode setting for STOP 2 1 read-write CPU0_STOP_0 Slice reset will be de-asserted when CPU0 in STOP mode 0 CPU0_STOP_1 Slice reset will be asserted when CPU0 in STOP mode 0x1 CPU0_SUSP CPU mode setting for SUSPEND 3 1 read-write CPU0_SUSP_0 Slice reset will be de-asserted when CPU0 in SUSPEND mode 0 CPU0_SUSP_1 Slice reset will be asserted when CPU0 in SUSPEND mode 0x1 CPU1_RUN CPU mode setting for RUN 4 1 read-write CPU1_RUN_0 Slice reset will be de-asserted when CPU1 in RUN mode 0 CPU1_RUN_1 Slice reset will be asserted when CPU1 in RUN mode 0x1 CPU1_WAIT CPU mode setting for WAIT 5 1 read-write CPU1_WAIT_0 Slice reset will be de-asserted when CPU1 in WAIT mode 0 CPU1_WAIT_1 Slice reset will be asserted when CPU1 in WAIT mode 0x1 CPU1_STOP CPU mode setting for STOP 6 1 read-write CPU1_STOP_0 Slice reset will be de-asserted when CPU1 in STOP mode 0 CPU1_STOP_1 Slice reset will be asserted when CPU1 in STOP mode 0x1 CPU1_SUSP CPU mode setting for SUSPEND 7 1 read-write CPU1_SUSP_0 Slice reset will be de-asserted when CPU1 in SUSPEND mode 0 CPU1_SUSP_1 Slice reset will be asserted when CPU1 in SUSPEND mode 0x1 STAT_M7CORE Slice Status Register 0x2B0 32 read-write 0 0xFFFFFFFF UNDER_RST This is a Read Only bit. It indicate if the reset is in process. 0 1 read-only UNDER_RST_0 the reset is finished 0 UNDER_RST_1 the reset is in process 0x1 RST_BY_HW This bit indicate if the reset is caused by the power mode transfer. 2 1 read-write oneToClear RST_BY_HW_0 the reset is not caused by the power mode transfer 0 RST_BY_HW_1 the reset is caused by the power mode transfer 0x1 RST_BY_SW This bit indicate if the reset is caused by setting SW_RESET bit. 3 1 read-write oneToClear RST_BY_SW_0 the reset is not caused by software setting 0 RST_BY_SW_1 the reset is caused by software setting 0x1 AUTHEN_M4DEBUG Slice Authentication Register 0x2C0 32 read-write 0 0xFFFFFFFF DOMAIN_MODE Control whether reset slice is in domain mode 0 1 read-write DOMAIN_MODE_0 slice hardware reset will NOT be triggered by CPU power mode transition 0 DOMAIN_MODE_1 slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. 0x1 SETPOINT_MODE Control whether reset slice is in Setpoint mode 1 1 read-write SETPOINT_MODE_0 slice hardware reset will NOT be triggered by Setpoint transition 0 SETPOINT_MODE_1 slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. 0x1 LOCK_MODE Domain/Setpoint mode lock 7 1 read-write ASSIGN_LIST when this bitfield set to 1, reset of slice would be subject to corresponding core status transition 8 4 read-write LOCK_ASSIGN Assign list lock 15 1 read-write WHITE_LIST Domain ID white list 16 4 read-write LOCK_LIST White list lock 23 1 read-write USER Allow user mode access 24 1 read-write NONSECURE Allow non-secure mode access 25 1 read-write LOCK_SETTING Lock NONSECURE and USER 31 1 read-write CTRL_M4DEBUG Slice Control Register 0x2C4 32 read-write 0 0xFFFFFFFF SW_RESET This is a self clearing bit 0 1 read-write SW_RESET_0 do not assert slice software reset 0 SW_RESET_1 assert slice software reset 0x1 SETPOINT_M4DEBUG Slice Setpoint Config Register 0x2C8 32 read-write 0 0xFFFFFFFF SETPOINT0 SETPOINT0 0 1 read-write SETPOINT0_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT0_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT1 SETPOINT1 1 1 read-write SETPOINT1_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT1_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT2 SETPOINT2 2 1 read-write SETPOINT2_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT2_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT3 SETPOINT3 3 1 read-write SETPOINT3_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT3_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT4 SETPOINT4 4 1 read-write SETPOINT4_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT4_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT5 SETPOINT5 5 1 read-write SETPOINT5_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT5_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT6 SETPOINT6 6 1 read-write SETPOINT6_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT6_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT7 SETPOINT7 7 1 read-write SETPOINT7_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT7_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT8 SETPOINT8 8 1 read-write SETPOINT8_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT8_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT9 SETPOINT9 9 1 read-write SETPOINT9_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT9_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT10 SETPOINT10 10 1 read-write SETPOINT10_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT10_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT11 SETPOINT11 11 1 read-write SETPOINT11_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT11_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT12 SETPOINT12 12 1 read-write SETPOINT12_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT12_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT13 SETPOINT13 13 1 read-write SETPOINT13_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT13_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT14 SETPOINT14 14 1 read-write SETPOINT14_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT14_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT15 SETPOINT15 15 1 read-write SETPOINT15_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT15_1 Slice reset will be asserted when system in Setpoint n 0x1 DOMAIN_M4DEBUG Slice Domain Config Register 0x2CC 32 read-write 0 0xFFFFFFFF CPU0_RUN CPU mode setting for RUN 0 1 read-write CPU0_RUN_0 Slice reset will be de-asserted when CPU0 in RUN mode 0 CPU0_RUN_1 Slice reset will be asserted when CPU0 in RUN mode 0x1 CPU0_WAIT CPU mode setting for WAIT 1 1 read-write CPU0_WAIT_0 Slice reset will be de-asserted when CPU0 in WAIT mode 0 CPU0_WAIT_1 Slice reset will be asserted when CPU0 in WAIT mode 0x1 CPU0_STOP CPU mode setting for STOP 2 1 read-write CPU0_STOP_0 Slice reset will be de-asserted when CPU0 in STOP mode 0 CPU0_STOP_1 Slice reset will be asserted when CPU0 in STOP mode 0x1 CPU0_SUSP CPU mode setting for SUSPEND 3 1 read-write CPU0_SUSP_0 Slice reset will be de-asserted when CPU0 in SUSPEND mode 0 CPU0_SUSP_1 Slice reset will be asserted when CPU0 in SUSPEND mode 0x1 CPU1_RUN CPU mode setting for RUN 4 1 read-write CPU1_RUN_0 Slice reset will be de-asserted when CPU1 in RUN mode 0 CPU1_RUN_1 Slice reset will be asserted when CPU1 in RUN mode 0x1 CPU1_WAIT CPU mode setting for WAIT 5 1 read-write CPU1_WAIT_0 Slice reset will be de-asserted when CPU1 in WAIT mode 0 CPU1_WAIT_1 Slice reset will be asserted when CPU1 in WAIT mode 0x1 CPU1_STOP CPU mode setting for STOP 6 1 read-write CPU1_STOP_0 Slice reset will be de-asserted when CPU1 in STOP mode 0 CPU1_STOP_1 Slice reset will be asserted when CPU1 in STOP mode 0x1 CPU1_SUSP CPU mode setting for SUSPEND 7 1 read-write CPU1_SUSP_0 Slice reset will be de-asserted when CPU1 in SUSPEND mode 0 CPU1_SUSP_1 Slice reset will be asserted when CPU1 in SUSPEND mode 0x1 STAT_M4DEBUG Slice Status Register 0x2D0 32 read-write 0 0xFFFFFFFF UNDER_RST This is a Read Only bit. It indicate if the reset is in process. 0 1 read-only UNDER_RST_0 the reset is finished 0 UNDER_RST_1 the reset is in process 0x1 RST_BY_HW This bit indicate if the reset is caused by the power mode transfer. 2 1 read-write oneToClear RST_BY_HW_0 the reset is not caused by the power mode transfer 0 RST_BY_HW_1 the reset is caused by the power mode transfer 0x1 RST_BY_SW This bit indicate if the reset is caused by setting SW_RESET bit. 3 1 read-write oneToClear RST_BY_SW_0 the reset is not caused by software setting 0 RST_BY_SW_1 the reset is caused by software setting 0x1 AUTHEN_M7DEBUG Slice Authentication Register 0x2E0 32 read-write 0 0xFFFFFFFF DOMAIN_MODE Control whether reset slice is in domain mode 0 1 read-write DOMAIN_MODE_0 slice hardware reset will NOT be triggered by CPU power mode transition 0 DOMAIN_MODE_1 slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. 0x1 SETPOINT_MODE Control whether reset slice is in Setpoint mode 1 1 read-write SETPOINT_MODE_0 slice hardware reset will NOT be triggered by Setpoint transition 0 SETPOINT_MODE_1 slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. 0x1 LOCK_MODE Domain/Setpoint mode lock 7 1 read-write ASSIGN_LIST when this bitfield set to 1, reset of slice would be subject to corresponding core status transition 8 4 read-write LOCK_ASSIGN Assign list lock 15 1 read-write WHITE_LIST Domain ID white list 16 4 read-write LOCK_LIST White list lock 23 1 read-write USER Allow user mode access 24 1 read-write NONSECURE Allow non-secure mode access 25 1 read-write LOCK_SETTING Lock NONSECURE and USER 31 1 read-write CTRL_M7DEBUG Slice Control Register 0x2E4 32 read-write 0 0xFFFFFFFF SW_RESET This is a self clearing bit 0 1 read-write SW_RESET_0 do not assert slice software reset 0 SW_RESET_1 assert slice software reset 0x1 SETPOINT_M7DEBUG Slice Setpoint Config Register 0x2E8 32 read-write 0 0xFFFFFFFF SETPOINT0 SETPOINT0 0 1 read-write SETPOINT0_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT0_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT1 SETPOINT1 1 1 read-write SETPOINT1_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT1_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT2 SETPOINT2 2 1 read-write SETPOINT2_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT2_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT3 SETPOINT3 3 1 read-write SETPOINT3_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT3_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT4 SETPOINT4 4 1 read-write SETPOINT4_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT4_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT5 SETPOINT5 5 1 read-write SETPOINT5_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT5_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT6 SETPOINT6 6 1 read-write SETPOINT6_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT6_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT7 SETPOINT7 7 1 read-write SETPOINT7_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT7_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT8 SETPOINT8 8 1 read-write SETPOINT8_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT8_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT9 SETPOINT9 9 1 read-write SETPOINT9_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT9_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT10 SETPOINT10 10 1 read-write SETPOINT10_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT10_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT11 SETPOINT11 11 1 read-write SETPOINT11_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT11_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT12 SETPOINT12 12 1 read-write SETPOINT12_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT12_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT13 SETPOINT13 13 1 read-write SETPOINT13_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT13_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT14 SETPOINT14 14 1 read-write SETPOINT14_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT14_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT15 SETPOINT15 15 1 read-write SETPOINT15_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT15_1 Slice reset will be asserted when system in Setpoint n 0x1 DOMAIN_M7DEBUG Slice Domain Config Register 0x2EC 32 read-write 0 0xFFFFFFFF CPU0_RUN CPU mode setting for RUN 0 1 read-write CPU0_RUN_0 Slice reset will be de-asserted when CPU0 in RUN mode 0 CPU0_RUN_1 Slice reset will be asserted when CPU0 in RUN mode 0x1 CPU0_WAIT CPU mode setting for WAIT 1 1 read-write CPU0_WAIT_0 Slice reset will be de-asserted when CPU0 in WAIT mode 0 CPU0_WAIT_1 Slice reset will be asserted when CPU0 in WAIT mode 0x1 CPU0_STOP CPU mode setting for STOP 2 1 read-write CPU0_STOP_0 Slice reset will be de-asserted when CPU0 in STOP mode 0 CPU0_STOP_1 Slice reset will be asserted when CPU0 in STOP mode 0x1 CPU0_SUSP CPU mode setting for SUSPEND 3 1 read-write CPU0_SUSP_0 Slice reset will be de-asserted when CPU0 in SUSPEND mode 0 CPU0_SUSP_1 Slice reset will be asserted when CPU0 in SUSPEND mode 0x1 CPU1_RUN CPU mode setting for RUN 4 1 read-write CPU1_RUN_0 Slice reset will be de-asserted when CPU1 in RUN mode 0 CPU1_RUN_1 Slice reset will be asserted when CPU1 in RUN mode 0x1 CPU1_WAIT CPU mode setting for WAIT 5 1 read-write CPU1_WAIT_0 Slice reset will be de-asserted when CPU1 in WAIT mode 0 CPU1_WAIT_1 Slice reset will be asserted when CPU1 in WAIT mode 0x1 CPU1_STOP CPU mode setting for STOP 6 1 read-write CPU1_STOP_0 Slice reset will be de-asserted when CPU1 in STOP mode 0 CPU1_STOP_1 Slice reset will be asserted when CPU1 in STOP mode 0x1 CPU1_SUSP CPU mode setting for SUSPEND 7 1 read-write CPU1_SUSP_0 Slice reset will be de-asserted when CPU1 in SUSPEND mode 0 CPU1_SUSP_1 Slice reset will be asserted when CPU1 in SUSPEND mode 0x1 STAT_M7DEBUG Slice Status Register 0x2F0 32 read-write 0 0xFFFFFFFF UNDER_RST This is a Read Only bit. It indicate if the reset is in process. 0 1 read-only UNDER_RST_0 the reset is finished 0 UNDER_RST_1 the reset is in process 0x1 RST_BY_HW This bit indicate if the reset is caused by the power mode transfer. 2 1 read-write oneToClear RST_BY_HW_0 the reset is not caused by the power mode transfer 0 RST_BY_HW_1 the reset is caused by the power mode transfer 0x1 RST_BY_SW This bit indicate if the reset is caused by setting SW_RESET bit. 3 1 read-write oneToClear RST_BY_SW_0 the reset is not caused by software setting 0 RST_BY_SW_1 the reset is caused by software setting 0x1 AUTHEN_USBPHY1 Slice Authentication Register 0x300 32 read-write 0 0xFFFFFFFF DOMAIN_MODE Control whether reset slice is in domain mode 0 1 read-write DOMAIN_MODE_0 slice hardware reset will NOT be triggered by CPU power mode transition 0 DOMAIN_MODE_1 slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. 0x1 SETPOINT_MODE Control whether reset slice is in Setpoint mode 1 1 read-write SETPOINT_MODE_0 slice hardware reset will NOT be triggered by Setpoint transition 0 SETPOINT_MODE_1 slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. 0x1 LOCK_MODE Domain/Setpoint mode lock 7 1 read-write ASSIGN_LIST when this bitfield set to 1, reset of slice would be subject to corresponding core status transition 8 4 read-write LOCK_ASSIGN Assign list lock 15 1 read-write WHITE_LIST Domain ID white list 16 4 read-write LOCK_LIST White list lock 23 1 read-write USER Allow user mode access 24 1 read-write NONSECURE Allow non-secure mode access 25 1 read-write LOCK_SETTING Lock NONSECURE and USER 31 1 read-write CTRL_USBPHY1 Slice Control Register 0x304 32 read-write 0 0xFFFFFFFF SW_RESET This is a self clearing bit 0 1 read-write SW_RESET_0 do not assert slice software reset 0 SW_RESET_1 assert slice software reset 0x1 SETPOINT_USBPHY1 Slice Setpoint Config Register 0x308 32 read-write 0 0xFFFFFFFF SETPOINT0 SETPOINT0 0 1 read-write SETPOINT0_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT0_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT1 SETPOINT1 1 1 read-write SETPOINT1_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT1_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT2 SETPOINT2 2 1 read-write SETPOINT2_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT2_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT3 SETPOINT3 3 1 read-write SETPOINT3_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT3_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT4 SETPOINT4 4 1 read-write SETPOINT4_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT4_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT5 SETPOINT5 5 1 read-write SETPOINT5_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT5_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT6 SETPOINT6 6 1 read-write SETPOINT6_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT6_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT7 SETPOINT7 7 1 read-write SETPOINT7_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT7_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT8 SETPOINT8 8 1 read-write SETPOINT8_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT8_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT9 SETPOINT9 9 1 read-write SETPOINT9_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT9_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT10 SETPOINT10 10 1 read-write SETPOINT10_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT10_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT11 SETPOINT11 11 1 read-write SETPOINT11_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT11_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT12 SETPOINT12 12 1 read-write SETPOINT12_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT12_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT13 SETPOINT13 13 1 read-write SETPOINT13_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT13_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT14 SETPOINT14 14 1 read-write SETPOINT14_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT14_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT15 SETPOINT15 15 1 read-write SETPOINT15_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT15_1 Slice reset will be asserted when system in Setpoint n 0x1 DOMAIN_USBPHY1 Slice Domain Config Register 0x30C 32 read-write 0 0xFFFFFFFF CPU0_RUN CPU mode setting for RUN 0 1 read-write CPU0_RUN_0 Slice reset will be de-asserted when CPU0 in RUN mode 0 CPU0_RUN_1 Slice reset will be asserted when CPU0 in RUN mode 0x1 CPU0_WAIT CPU mode setting for WAIT 1 1 read-write CPU0_WAIT_0 Slice reset will be de-asserted when CPU0 in WAIT mode 0 CPU0_WAIT_1 Slice reset will be asserted when CPU0 in WAIT mode 0x1 CPU0_STOP CPU mode setting for STOP 2 1 read-write CPU0_STOP_0 Slice reset will be de-asserted when CPU0 in STOP mode 0 CPU0_STOP_1 Slice reset will be asserted when CPU0 in STOP mode 0x1 CPU0_SUSP CPU mode setting for SUSPEND 3 1 read-write CPU0_SUSP_0 Slice reset will be de-asserted when CPU0 in SUSPEND mode 0 CPU0_SUSP_1 Slice reset will be asserted when CPU0 in SUSPEND mode 0x1 CPU1_RUN CPU mode setting for RUN 4 1 read-write CPU1_RUN_0 Slice reset will be de-asserted when CPU1 in RUN mode 0 CPU1_RUN_1 Slice reset will be asserted when CPU1 in RUN mode 0x1 CPU1_WAIT CPU mode setting for WAIT 5 1 read-write CPU1_WAIT_0 Slice reset will be de-asserted when CPU1 in WAIT mode 0 CPU1_WAIT_1 Slice reset will be asserted when CPU1 in WAIT mode 0x1 CPU1_STOP CPU mode setting for STOP 6 1 read-write CPU1_STOP_0 Slice reset will be de-asserted when CPU1 in STOP mode 0 CPU1_STOP_1 Slice reset will be asserted when CPU1 in STOP mode 0x1 CPU1_SUSP CPU mode setting for SUSPEND 7 1 read-write CPU1_SUSP_0 Slice reset will be de-asserted when CPU1 in SUSPEND mode 0 CPU1_SUSP_1 Slice reset will be asserted when CPU1 in SUSPEND mode 0x1 STAT_USBPHY1 Slice Status Register 0x310 32 read-write 0 0xFFFFFFFF UNDER_RST This is a Read Only bit. It indicate if the reset is in process. 0 1 read-only UNDER_RST_0 the reset is finished 0 UNDER_RST_1 the reset is in process 0x1 RST_BY_HW This bit indicate if the reset is caused by the power mode transfer. 2 1 read-write oneToClear RST_BY_HW_0 the reset is not caused by the power mode transfer 0 RST_BY_HW_1 the reset is caused by the power mode transfer 0x1 RST_BY_SW This bit indicate if the reset is caused by setting SW_RESET bit. 3 1 read-write oneToClear RST_BY_SW_0 the reset is not caused by software setting 0 RST_BY_SW_1 the reset is caused by software setting 0x1 AUTHEN_USBPHY2 Slice Authentication Register 0x320 32 read-write 0 0xFFFFFFFF DOMAIN_MODE Control whether reset slice is in domain mode 0 1 read-write DOMAIN_MODE_0 slice hardware reset will NOT be triggered by CPU power mode transition 0 DOMAIN_MODE_1 slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. 0x1 SETPOINT_MODE Control whether reset slice is in Setpoint mode 1 1 read-write SETPOINT_MODE_0 slice hardware reset will NOT be triggered by Setpoint transition 0 SETPOINT_MODE_1 slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. 0x1 LOCK_MODE Domain/Setpoint mode lock 7 1 read-write ASSIGN_LIST when this bitfield set to 1, reset of slice would be subject to corresponding core status transition 8 4 read-write LOCK_ASSIGN Assign list lock 15 1 read-write WHITE_LIST Domain ID white list 16 4 read-write LOCK_LIST White list lock 23 1 read-write USER Allow user mode access 24 1 read-write NONSECURE Allow non-secure mode access 25 1 read-write LOCK_SETTING Lock NONSECURE and USER 31 1 read-write CTRL_USBPHY2 Slice Control Register 0x324 32 read-write 0 0xFFFFFFFF SW_RESET This is a self clearing bit 0 1 read-write SW_RESET_0 do not assert slice software reset 0 SW_RESET_1 assert slice software reset 0x1 SETPOINT_USBPHY2 Slice Setpoint Config Register 0x328 32 read-write 0 0xFFFFFFFF SETPOINT0 SETPOINT0 0 1 read-write SETPOINT0_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT0_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT1 SETPOINT1 1 1 read-write SETPOINT1_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT1_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT2 SETPOINT2 2 1 read-write SETPOINT2_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT2_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT3 SETPOINT3 3 1 read-write SETPOINT3_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT3_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT4 SETPOINT4 4 1 read-write SETPOINT4_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT4_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT5 SETPOINT5 5 1 read-write SETPOINT5_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT5_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT6 SETPOINT6 6 1 read-write SETPOINT6_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT6_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT7 SETPOINT7 7 1 read-write SETPOINT7_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT7_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT8 SETPOINT8 8 1 read-write SETPOINT8_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT8_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT9 SETPOINT9 9 1 read-write SETPOINT9_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT9_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT10 SETPOINT10 10 1 read-write SETPOINT10_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT10_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT11 SETPOINT11 11 1 read-write SETPOINT11_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT11_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT12 SETPOINT12 12 1 read-write SETPOINT12_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT12_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT13 SETPOINT13 13 1 read-write SETPOINT13_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT13_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT14 SETPOINT14 14 1 read-write SETPOINT14_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT14_1 Slice reset will be asserted when system in Setpoint n 0x1 SETPOINT15 SETPOINT15 15 1 read-write SETPOINT15_0 Slice reset will be de-asserted when system in Setpoint n 0 SETPOINT15_1 Slice reset will be asserted when system in Setpoint n 0x1 DOMAIN_USBPHY2 Slice Domain Config Register 0x32C 32 read-write 0 0xFFFFFFFF CPU0_RUN CPU mode setting for RUN 0 1 read-write CPU0_RUN_0 Slice reset will be de-asserted when CPU0 in RUN mode 0 CPU0_RUN_1 Slice reset will be asserted when CPU0 in RUN mode 0x1 CPU0_WAIT CPU mode setting for WAIT 1 1 read-write CPU0_WAIT_0 Slice reset will be de-asserted when CPU0 in WAIT mode 0 CPU0_WAIT_1 Slice reset will be asserted when CPU0 in WAIT mode 0x1 CPU0_STOP CPU mode setting for STOP 2 1 read-write CPU0_STOP_0 Slice reset will be de-asserted when CPU0 in STOP mode 0 CPU0_STOP_1 Slice reset will be asserted when CPU0 in STOP mode 0x1 CPU0_SUSP CPU mode setting for SUSPEND 3 1 read-write CPU0_SUSP_0 Slice reset will be de-asserted when CPU0 in SUSPEND mode 0 CPU0_SUSP_1 Slice reset will be asserted when CPU0 in SUSPEND mode 0x1 CPU1_RUN CPU mode setting for RUN 4 1 read-write CPU1_RUN_0 Slice reset will be de-asserted when CPU1 in RUN mode 0 CPU1_RUN_1 Slice reset will be asserted when CPU1 in RUN mode 0x1 CPU1_WAIT CPU mode setting for WAIT 5 1 read-write CPU1_WAIT_0 Slice reset will be de-asserted when CPU1 in WAIT mode 0 CPU1_WAIT_1 Slice reset will be asserted when CPU1 in WAIT mode 0x1 CPU1_STOP CPU mode setting for STOP 6 1 read-write CPU1_STOP_0 Slice reset will be de-asserted when CPU1 in STOP mode 0 CPU1_STOP_1 Slice reset will be asserted when CPU1 in STOP mode 0x1 CPU1_SUSP CPU mode setting for SUSPEND 7 1 read-write CPU1_SUSP_0 Slice reset will be de-asserted when CPU1 in SUSPEND mode 0 CPU1_SUSP_1 Slice reset will be asserted when CPU1 in SUSPEND mode 0x1 STAT_USBPHY2 Slice Status Register 0x330 32 read-write 0 0xFFFFFFFF UNDER_RST This is a Read Only bit. It indicate if the reset is in process. 0 1 read-only UNDER_RST_0 the reset is finished 0 UNDER_RST_1 the reset is in process 0x1 RST_BY_HW This bit indicate if the reset is caused by the power mode transfer. 2 1 read-write oneToClear RST_BY_HW_0 the reset is not caused by the power mode transfer 0 RST_BY_HW_1 the reset is caused by the power mode transfer 0x1 RST_BY_SW This bit indicate if the reset is caused by setting SW_RESET bit. 3 1 read-write oneToClear RST_BY_SW_0 the reset is not caused by software setting 0 RST_BY_SW_1 the reset is caused by software setting 0x1 IOMUXC_LPSR IOMUXC LPSR IOMUXC_LPSR 0x40C08000 0 0xE0 registers SW_MUX_CTL_PAD_GPIO_LPSR_00 SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register 0 32 read-write 0xA 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_can3_TX Select mux mode: ALT0 mux port: FLEXCAN3_TX of instance: FLEXCAN3 0 ALT1_mic_CLK Select mux mode: ALT1 mux port: MIC_CLK of instance: MIC 0x1 ALT2_mqs_RIGHT Select mux mode: ALT2 mux port: MQS_RIGHT of instance: MQS 0x2 ALT3_ARM_CM4_EVENTO Select mux mode: ALT3 mux port: ARM_CM4_EVENTO of instance: CM4 0x3 ALT5_gpio_mux6_IO0 Select mux mode: ALT5 mux port: GPIO_MUX6_IO00 of instance: GPIO_MUX6 0x5 ALT6_lpuart12_TX Select mux mode: ALT6 mux port: LPUART12_TXD of instance: LPUART12 0x6 ALT7_sai4_MCLK Select mux mode: ALT7 mux port: SAI4_MCLK of instance: SAI4 0x7 ALT10_gpio12_IO0 Select mux mode: ALT10 mux port: GPIO12_IO00 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_00 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_01 SW_MUX_CTL_PAD_GPIO_LPSR_01 SW MUX Control Register 0x4 32 read-write 0xA 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_can3_RX Select mux mode: ALT0 mux port: FLEXCAN3_RX of instance: FLEXCAN3 0 ALT1_mic_BITSTREAM0 Select mux mode: ALT1 mux port: MIC_BITSTREAM0 of instance: MIC 0x1 ALT2_mqs_LEFT Select mux mode: ALT2 mux port: MQS_LEFT of instance: MQS 0x2 ALT3_ARM_CM4_EVENTI Select mux mode: ALT3 mux port: ARM_CM4_EVENTI of instance: CM4 0x3 ALT5_gpio_mux6_IO1 Select mux mode: ALT5 mux port: GPIO_MUX6_IO01 of instance: GPIO_MUX6 0x5 ALT6_lpuart12_RX Select mux mode: ALT6 mux port: LPUART12_RXD of instance: LPUART12 0x6 ALT10_gpio12_IO1 Select mux mode: ALT10 mux port: GPIO12_IO01 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_01 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_02 SW_MUX_CTL_PAD_GPIO_LPSR_02 SW MUX Control Register 0x8 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_src_BOOT_MODE0 Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: SRC 0 ALT1_lpspi5_SCK Select mux mode: ALT1 mux port: LPSPI5_SCK of instance: LPSPI5 0x1 ALT2_sai4_TX_DATA Select mux mode: ALT2 mux port: SAI4_TX_DATA of instance: SAI4 0x2 ALT3_mqs_RIGHT Select mux mode: ALT3 mux port: MQS_RIGHT of instance: MQS 0x3 ALT5_gpio_mux6_IO2 Select mux mode: ALT5 mux port: GPIO_MUX6_IO02 of instance: GPIO_MUX6 0x5 ALT10_gpio12_IO2 Select mux mode: ALT10 mux port: GPIO12_IO02 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_02 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_03 SW_MUX_CTL_PAD_GPIO_LPSR_03 SW MUX Control Register 0xC 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_src_BOOT_MODE1 Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: SRC 0 ALT1_lpspi5_PCS0 Select mux mode: ALT1 mux port: LPSPI5_PCS0 of instance: LPSPI5 0x1 ALT2_sai4_TX_SYNC Select mux mode: ALT2 mux port: SAI4_TX_SYNC of instance: SAI4 0x2 ALT3_mqs_LEFT Select mux mode: ALT3 mux port: MQS_LEFT of instance: MQS 0x3 ALT5_gpio_mux6_IO3 Select mux mode: ALT5 mux port: GPIO_MUX6_IO03 of instance: GPIO_MUX6 0x5 ALT10_gpio12_IO3 Select mux mode: ALT10 mux port: GPIO12_IO03 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_03 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_04 SW_MUX_CTL_PAD_GPIO_LPSR_04 SW MUX Control Register 0x10 32 read-write 0xA 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpi2c5_SDA Select mux mode: ALT0 mux port: LPI2C5_SDA of instance: LPI2C5 0 ALT1_lpspi5_SDO Select mux mode: ALT1 mux port: LPSPI5_SOUT of instance: LPSPI5 0x1 ALT2_sai4_TX_BCLK Select mux mode: ALT2 mux port: SAI4_TX_BCLK of instance: SAI4 0x2 ALT3_lpuart12_RTS_B Select mux mode: ALT3 mux port: LPUART12_RTS_B of instance: LPUART12 0x3 ALT5_gpio_mux6_IO4 Select mux mode: ALT5 mux port: GPIO_MUX6_IO04 of instance: GPIO_MUX6 0x5 ALT6_lpuart11_TX Select mux mode: ALT6 mux port: LPUART11_TXD of instance: LPUART11 0x6 ALT10_gpio12_IO4 Select mux mode: ALT10 mux port: GPIO12_IO04 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_04 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_05 SW_MUX_CTL_PAD_GPIO_LPSR_05 SW MUX Control Register 0x14 32 read-write 0xA 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpi2c5_SCL Select mux mode: ALT0 mux port: LPI2C5_SCL of instance: LPI2C5 0 ALT1_lpspi5_SDI Select mux mode: ALT1 mux port: LPSPI5_SIN of instance: LPSPI5 0x1 ALT2_sai4_MCLK Select mux mode: ALT2 mux port: SAI4_MCLK of instance: SAI4 0x2 ALT3_lpuart12_CTS_B Select mux mode: ALT3 mux port: LPUART12_CTS_B of instance: LPUART12 0x3 ALT5_gpio_mux6_IO5 Select mux mode: ALT5 mux port: GPIO_MUX6_IO05 of instance: GPIO_MUX6 0x5 ALT6_lpuart11_RX Select mux mode: ALT6 mux port: LPUART11_RXD of instance: LPUART11 0x6 ALT7_nmi_glue_NMI Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue 0x7 ALT10_gpio12_IO5 Select mux mode: ALT10 mux port: GPIO12_IO05 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_05 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_06 SW_MUX_CTL_PAD_GPIO_LPSR_06 SW MUX Control Register 0x18 32 read-write 0xA 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpi2c6_SDA Select mux mode: ALT0 mux port: LPI2C6_SDA of instance: LPI2C6 0 ALT2_sai4_RX_DATA Select mux mode: ALT2 mux port: SAI4_RX_DATA of instance: SAI4 0x2 ALT3_lpuart12_TX Select mux mode: ALT3 mux port: LPUART12_TXD of instance: LPUART12 0x3 ALT4_lpspi6_PCS3 Select mux mode: ALT4 mux port: LPSPI6_PCS3 of instance: LPSPI6 0x4 ALT5_gpio_mux6_IO6 Select mux mode: ALT5 mux port: GPIO_MUX6_IO06 of instance: GPIO_MUX6 0x5 ALT6_can3_TX Select mux mode: ALT6 mux port: FLEXCAN3_TX of instance: FLEXCAN3 0x6 ALT7_pit2_TRIGGER3 Select mux mode: ALT7 mux port: PIT2_TRIGGER3 of instance: PIT2 0x7 ALT8_lpspi5_PCS1 Select mux mode: ALT8 mux port: LPSPI5_PCS1 of instance: LPSPI5 0x8 ALT10_gpio12_IO6 Select mux mode: ALT10 mux port: GPIO12_IO06 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_06 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_07 SW_MUX_CTL_PAD_GPIO_LPSR_07 SW MUX Control Register 0x1C 32 read-write 0xA 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpi2c6_SCL Select mux mode: ALT0 mux port: LPI2C6_SCL of instance: LPI2C6 0 ALT2_sai4_RX_BCLK Select mux mode: ALT2 mux port: SAI4_RX_BCLK of instance: SAI4 0x2 ALT3_lpuart12_RX Select mux mode: ALT3 mux port: LPUART12_RXD of instance: LPUART12 0x3 ALT4_lpspi6_PCS2 Select mux mode: ALT4 mux port: LPSPI6_PCS2 of instance: LPSPI6 0x4 ALT5_gpio_mux6_IO7 Select mux mode: ALT5 mux port: GPIO_MUX6_IO07 of instance: GPIO_MUX6 0x5 ALT6_can3_RX Select mux mode: ALT6 mux port: FLEXCAN3_RX of instance: FLEXCAN3 0x6 ALT7_pit2_TRIGGER2 Select mux mode: ALT7 mux port: PIT2_TRIGGER2 of instance: PIT2 0x7 ALT8_lpspi5_PCS2 Select mux mode: ALT8 mux port: LPSPI5_PCS2 of instance: LPSPI5 0x8 ALT10_gpio12_IO7 Select mux mode: ALT10 mux port: GPIO12_IO07 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_07 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_08 SW_MUX_CTL_PAD_GPIO_LPSR_08 SW MUX Control Register 0x20 32 read-write 0xA 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpuart11_TX Select mux mode: ALT0 mux port: LPUART11_TXD of instance: LPUART11 0 ALT1_can3_TX Select mux mode: ALT1 mux port: FLEXCAN3_TX of instance: FLEXCAN3 0x1 ALT2_sai4_RX_SYNC Select mux mode: ALT2 mux port: SAI4_RX_SYNC of instance: SAI4 0x2 ALT3_mic_CLK Select mux mode: ALT3 mux port: MIC_CLK of instance: MIC 0x3 ALT4_lpspi6_PCS1 Select mux mode: ALT4 mux port: LPSPI6_PCS1 of instance: LPSPI6 0x4 ALT5_gpio_mux6_IO8 Select mux mode: ALT5 mux port: GPIO_MUX6_IO08 of instance: GPIO_MUX6 0x5 ALT6_lpi2c5_SDA Select mux mode: ALT6 mux port: LPI2C5_SDA of instance: LPI2C5 0x6 ALT7_pit2_TRIGGER1 Select mux mode: ALT7 mux port: PIT2_TRIGGER1 of instance: PIT2 0x7 ALT8_lpspi5_PCS3 Select mux mode: ALT8 mux port: LPSPI5_PCS3 of instance: LPSPI5 0x8 ALT10_gpio12_IO8 Select mux mode: ALT10 mux port: GPIO12_IO08 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_08 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_09 SW_MUX_CTL_PAD_GPIO_LPSR_09 SW MUX Control Register 0x24 32 read-write 0xA 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_lpuart11_RX Select mux mode: ALT0 mux port: LPUART11_RXD of instance: LPUART11 0 ALT1_can3_RX Select mux mode: ALT1 mux port: FLEXCAN3_RX of instance: FLEXCAN3 0x1 ALT2_pit2_TRIGGER0 Select mux mode: ALT2 mux port: PIT2_TRIGGER0 of instance: PIT2 0x2 ALT3_mic_BITSTREAM0 Select mux mode: ALT3 mux port: MIC_BITSTREAM0 of instance: MIC 0x3 ALT4_lpspi6_PCS0 Select mux mode: ALT4 mux port: LPSPI6_PCS0 of instance: LPSPI6 0x4 ALT5_gpio_mux6_IO9 Select mux mode: ALT5 mux port: GPIO_MUX6_IO09 of instance: GPIO_MUX6 0x5 ALT6_lpi2c5_SCL Select mux mode: ALT6 mux port: LPI2C5_SCL of instance: LPI2C5 0x6 ALT7_sai4_TX_DATA Select mux mode: ALT7 mux port: SAI4_TX_DATA of instance: SAI4 0x7 ALT10_gpio12_IO9 Select mux mode: ALT10 mux port: GPIO12_IO09 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_09 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_10 SW_MUX_CTL_PAD_GPIO_LPSR_10 SW MUX Control Register 0x28 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_jtag_mux_TRSTB Select mux mode: ALT0 mux port: JTAG_MUX_TRSTB of instance: JTAG_MUX 0 ALT1_lpuart11_CTS_B Select mux mode: ALT1 mux port: LPUART11_CTS_B of instance: LPUART11 0x1 ALT2_lpi2c6_SDA Select mux mode: ALT2 mux port: LPI2C6_SDA of instance: LPI2C6 0x2 ALT3_mic_BITSTREAM1 Select mux mode: ALT3 mux port: MIC_BITSTREAM1 of instance: MIC 0x3 ALT4_lpspi6_SCK Select mux mode: ALT4 mux port: LPSPI6_SCK of instance: LPSPI6 0x4 ALT5_gpio_mux6_IO10 Select mux mode: ALT5 mux port: GPIO_MUX6_IO10 of instance: GPIO_MUX6 0x5 ALT6_lpi2c5_SCLS Select mux mode: ALT6 mux port: LPI2C5_SCLS of instance: LPI2C5 0x6 ALT7_sai4_TX_SYNC Select mux mode: ALT7 mux port: SAI4_TX_SYNC of instance: SAI4 0x7 ALT8_lpuart12_TX Select mux mode: ALT8 mux port: LPUART12_TXD of instance: LPUART12 0x8 ALT10_gpio12_IO10 Select mux mode: ALT10 mux port: GPIO12_IO10 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_10 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_11 SW_MUX_CTL_PAD_GPIO_LPSR_11 SW MUX Control Register 0x2C 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_jtag_mux_TDO Select mux mode: ALT0 mux port: JTAG_MUX_TDO of instance: JTAG_MUX 0 ALT1_lpuart11_RTS_B Select mux mode: ALT1 mux port: LPUART11_RTS_B of instance: LPUART11 0x1 ALT2_lpi2c6_SCL Select mux mode: ALT2 mux port: LPI2C6_SCL of instance: LPI2C6 0x2 ALT3_mic_BITSTREAM2 Select mux mode: ALT3 mux port: MIC_BITSTREAM2 of instance: MIC 0x3 ALT4_lpspi6_SDO Select mux mode: ALT4 mux port: LPSPI6_SOUT of instance: LPSPI6 0x4 ALT5_gpio_mux6_IO11 Select mux mode: ALT5 mux port: GPIO_MUX6_IO11 of instance: GPIO_MUX6 0x5 ALT6_lpi2c5_SDAS Select mux mode: ALT6 mux port: LPI2C5_SDAS of instance: LPI2C5 0x6 ALT7_ARM_TRACE_SWO Select mux mode: ALT7 mux port: ARM_TRACE_SWO of instance: ARM 0x7 ALT8_lpuart12_RX Select mux mode: ALT8 mux port: LPUART12_RXD of instance: LPUART12 0x8 ALT10_gpio12_IO11 Select mux mode: ALT10 mux port: GPIO12_IO11 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_11 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_12 SW_MUX_CTL_PAD_GPIO_LPSR_12 SW MUX Control Register 0x30 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_jtag_mux_TDI Select mux mode: ALT0 mux port: JTAG_MUX_TDI of instance: JTAG_MUX 0 ALT1_pit2_TRIGGER0 Select mux mode: ALT1 mux port: PIT2_TRIGGER0 of instance: PIT2 0x1 ALT3_mic_BITSTREAM3 Select mux mode: ALT3 mux port: MIC_BITSTREAM3 of instance: MIC 0x3 ALT4_lpspi6_SDI Select mux mode: ALT4 mux port: LPSPI6_SIN of instance: LPSPI6 0x4 ALT5_gpio_mux6_IO12 Select mux mode: ALT5 mux port: GPIO_MUX6_IO12 of instance: GPIO_MUX6 0x5 ALT6_lpi2c5_HREQ Select mux mode: ALT6 mux port: LPI2C5_HREQ of instance: LPI2C5 0x6 ALT7_sai4_TX_BCLK Select mux mode: ALT7 mux port: SAI4_TX_BCLK of instance: SAI4 0x7 ALT8_lpspi5_SCK Select mux mode: ALT8 mux port: LPSPI5_SCK of instance: LPSPI5 0x8 ALT10_gpio12_IO12 Select mux mode: ALT10 mux port: GPIO12_IO12 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_12 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_13 SW_MUX_CTL_PAD_GPIO_LPSR_13 SW MUX Control Register 0x34 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_jtag_mux_MOD Select mux mode: ALT0 mux port: JTAG_MUX_MOD of instance: JTAG_MUX 0 ALT1_mic_BITSTREAM1 Select mux mode: ALT1 mux port: MIC_BITSTREAM1 of instance: MIC 0x1 ALT2_pit2_TRIGGER1 Select mux mode: ALT2 mux port: PIT2_TRIGGER1 of instance: PIT2 0x2 ALT5_gpio_mux6_IO13 Select mux mode: ALT5 mux port: GPIO_MUX6_IO13 of instance: GPIO_MUX6 0x5 ALT7_sai4_RX_DATA Select mux mode: ALT7 mux port: SAI4_RX_DATA of instance: SAI4 0x7 ALT8_lpspi5_PCS0 Select mux mode: ALT8 mux port: LPSPI5_PCS0 of instance: LPSPI5 0x8 ALT10_gpio12_IO13 Select mux mode: ALT10 mux port: GPIO12_IO13 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_13 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_14 SW_MUX_CTL_PAD_GPIO_LPSR_14 SW MUX Control Register 0x38 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_jtag_mux_TCK Select mux mode: ALT0 mux port: JTAG_MUX_TCK of instance: JTAG_MUX/SWD_CLK 0 ALT1_mic_BITSTREAM2 Select mux mode: ALT1 mux port: MIC_BITSTREAM2 of instance: MIC 0x1 ALT2_pit2_TRIGGER2 Select mux mode: ALT2 mux port: PIT2_TRIGGER2 of instance: PIT2 0x2 ALT5_gpio_mux6_IO14 Select mux mode: ALT5 mux port: GPIO_MUX6_IO14 of instance: GPIO_MUX6 0x5 ALT7_sai4_RX_BCLK Select mux mode: ALT7 mux port: SAI4_RX_BCLK of instance: SAI4 0x7 ALT8_lpspi5_SDO Select mux mode: ALT8 mux port: LPSPI5_SOUT of instance: LPSPI5 0x8 ALT10_gpio12_IO14 Select mux mode: ALT10 mux port: GPIO12_IO14 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_14 0x1 SW_MUX_CTL_PAD_GPIO_LPSR_15 SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register 0x3C 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 4 read-write ALT0_jtag_mux_TMS Select mux mode: ALT0 mux port: JTAG_MUX_TMS of instance: JTAG_MUX/SWD_DIO 0 ALT1_mic_BITSTREAM3 Select mux mode: ALT1 mux port: MIC_BITSTREAM3 of instance: MIC 0x1 ALT2_pit2_TRIGGER3 Select mux mode: ALT2 mux port: PIT2_TRIGGER3 of instance: PIT2 0x2 ALT5_gpio_mux6_IO15 Select mux mode: ALT5 mux port: GPIO_MUX6_IO15 of instance: GPIO_MUX6 0x5 ALT7_sai4_RX_SYNC Select mux mode: ALT7 mux port: SAI4_RX_SYNC of instance: SAI4 0x7 ALT8_lpspi5_SDI Select mux mode: ALT8 mux port: LPSPI5_SIN of instance: LPSPI5 0x8 ALT10_gpio12_IO15 Select mux mode: ALT10 mux port: GPIO12_IO15 of instance: GPIO12 0xA SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_LPSR_15 0x1 SW_PAD_CTL_PAD_GPIO_LPSR_00 SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register 0x40 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_01 SW_PAD_CTL_PAD_GPIO_LPSR_01 SW PAD Control Register 0x44 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_02 SW_PAD_CTL_PAD_GPIO_LPSR_02 SW PAD Control Register 0x48 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_03 SW_PAD_CTL_PAD_GPIO_LPSR_03 SW PAD Control Register 0x4C 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_04 SW_PAD_CTL_PAD_GPIO_LPSR_04 SW PAD Control Register 0x50 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_05 SW_PAD_CTL_PAD_GPIO_LPSR_05 SW PAD Control Register 0x54 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_06 SW_PAD_CTL_PAD_GPIO_LPSR_06 SW PAD Control Register 0x58 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_07 SW_PAD_CTL_PAD_GPIO_LPSR_07 SW PAD Control Register 0x5C 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_08 SW_PAD_CTL_PAD_GPIO_LPSR_08 SW PAD Control Register 0x60 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_09 SW_PAD_CTL_PAD_GPIO_LPSR_09 SW PAD Control Register 0x64 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_10 SW_PAD_CTL_PAD_GPIO_LPSR_10 SW PAD Control Register 0x68 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_11 SW_PAD_CTL_PAD_GPIO_LPSR_11 SW PAD Control Register 0x6C 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_12 SW_PAD_CTL_PAD_GPIO_LPSR_12 SW PAD Control Register 0x70 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_13 SW_PAD_CTL_PAD_GPIO_LPSR_13 SW PAD Control Register 0x74 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_14 SW_PAD_CTL_PAD_GPIO_LPSR_14 SW PAD Control Register 0x78 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_LPSR_15 SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register 0x7C 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_LPSR Open Drain LPSR Field 5 1 read-write ODE_LPSR_0_Disabled Disabled 0 ODE_LPSR_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 CAN3_IPP_IND_CANRX_SELECT_INPUT CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register 0x80 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_LPSR_01_ALT0 Selecting Pad: GPIO_LPSR_01 for Mode: ALT0 0 SELECT_GPIO_LPSR_07_ALT6 Selecting Pad: GPIO_LPSR_07 for Mode: ALT6 0x1 SELECT_GPIO_LPSR_09_ALT1 Selecting Pad: GPIO_LPSR_09 for Mode: ALT1 0x2 LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register 0x84 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_05_ALT0 Selecting Pad: GPIO_LPSR_05 for Mode: ALT0 0 SELECT_GPIO_LPSR_09_ALT6 Selecting Pad: GPIO_LPSR_09 for Mode: ALT6 0x1 LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register 0x88 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_04_ALT0 Selecting Pad: GPIO_LPSR_04 for Mode: ALT0 0 SELECT_GPIO_LPSR_08_ALT6 Selecting Pad: GPIO_LPSR_08 for Mode: ALT6 0x1 LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register 0x8C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_07_ALT0 Selecting Pad: GPIO_LPSR_07 for Mode: ALT0 0 SELECT_GPIO_LPSR_11_ALT2 Selecting Pad: GPIO_LPSR_11 for Mode: ALT2 0x1 LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register 0x90 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_06_ALT0 Selecting Pad: GPIO_LPSR_06 for Mode: ALT0 0 SELECT_GPIO_LPSR_10_ALT2 Selecting Pad: GPIO_LPSR_10 for Mode: ALT2 0x1 LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 DAISY Register 0x94 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_03_ALT1 Selecting Pad: GPIO_LPSR_03 for Mode: ALT1 0 SELECT_GPIO_LPSR_13_ALT8 Selecting Pad: GPIO_LPSR_13 for Mode: ALT8 0x1 LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT DAISY Register 0x98 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_02_ALT1 Selecting Pad: GPIO_LPSR_02 for Mode: ALT1 0 SELECT_GPIO_LPSR_12_ALT8 Selecting Pad: GPIO_LPSR_12 for Mode: ALT8 0x1 LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT DAISY Register 0x9C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_05_ALT1 Selecting Pad: GPIO_LPSR_05 for Mode: ALT1 0 SELECT_GPIO_LPSR_15_ALT8 Selecting Pad: GPIO_LPSR_15 for Mode: ALT8 0x1 LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT DAISY Register 0xA0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_04_ALT1 Selecting Pad: GPIO_LPSR_04 for Mode: ALT1 0 SELECT_GPIO_LPSR_14_ALT8 Selecting Pad: GPIO_LPSR_14 for Mode: ALT8 0x1 LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register 0xA4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_05_ALT6 Selecting Pad: GPIO_LPSR_05 for Mode: ALT6 0 SELECT_GPIO_LPSR_09_ALT0 Selecting Pad: GPIO_LPSR_09 for Mode: ALT0 0x1 LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register 0xA8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_04_ALT6 Selecting Pad: GPIO_LPSR_04 for Mode: ALT6 0 SELECT_GPIO_LPSR_08_ALT0 Selecting Pad: GPIO_LPSR_08 for Mode: ALT0 0x1 LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register 0xAC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_LPSR_01_ALT6 Selecting Pad: GPIO_LPSR_01 for Mode: ALT6 0 SELECT_GPIO_LPSR_07_ALT3 Selecting Pad: GPIO_LPSR_07 for Mode: ALT3 0x1 SELECT_GPIO_LPSR_11_ALT8 Selecting Pad: GPIO_LPSR_11 for Mode: ALT8 0x2 LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register 0xB0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write SELECT_GPIO_LPSR_00_ALT6 Selecting Pad: GPIO_LPSR_00 for Mode: ALT6 0 SELECT_GPIO_LPSR_06_ALT3 Selecting Pad: GPIO_LPSR_06 for Mode: ALT3 0x1 SELECT_GPIO_LPSR_10_ALT8 Selecting Pad: GPIO_LPSR_10 for Mode: ALT8 0x2 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 DAISY Register 0xB4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_01_ALT1 Selecting Pad: GPIO_LPSR_01 for Mode: ALT1 0 SELECT_GPIO_LPSR_09_ALT3 Selecting Pad: GPIO_LPSR_09 for Mode: ALT3 0x1 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 DAISY Register 0xB8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_10_ALT3 Selecting Pad: GPIO_LPSR_10 for Mode: ALT3 0 SELECT_GPIO_LPSR_13_ALT1 Selecting Pad: GPIO_LPSR_13 for Mode: ALT1 0x1 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 DAISY Register 0xBC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_11_ALT3 Selecting Pad: GPIO_LPSR_11 for Mode: ALT3 0 SELECT_GPIO_LPSR_14_ALT1 Selecting Pad: GPIO_LPSR_14 for Mode: ALT1 0x1 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 DAISY Register 0xC0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_12_ALT3 Selecting Pad: GPIO_LPSR_12 for Mode: ALT3 0 SELECT_GPIO_LPSR_15_ALT1 Selecting Pad: GPIO_LPSR_15 for Mode: ALT1 0x1 NMI_GLUE_IPP_IND_NMI_SELECT_INPUT NMI_GLUE_IPP_IND_NMI_SELECT_INPUT DAISY Register 0xC4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_05_ALT7 Selecting Pad: GPIO_LPSR_05 for Mode: ALT7 0 SELECT_WAKEUP_DIG_ALT7 Selecting Pad: WAKEUP_DIG for Mode: ALT7 0x1 SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT DAISY Register 0xC8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_00_ALT7 Selecting Pad: GPIO_LPSR_00 for Mode: ALT7 0 SELECT_GPIO_LPSR_05_ALT2 Selecting Pad: GPIO_LPSR_05 for Mode: ALT2 0x1 SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register 0xCC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_07_ALT2 Selecting Pad: GPIO_LPSR_07 for Mode: ALT2 0 SELECT_GPIO_LPSR_14_ALT7 Selecting Pad: GPIO_LPSR_14 for Mode: ALT7 0x1 SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register 0xD0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_06_ALT2 Selecting Pad: GPIO_LPSR_06 for Mode: ALT2 0 SELECT_GPIO_LPSR_13_ALT7 Selecting Pad: GPIO_LPSR_13 for Mode: ALT7 0x1 SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register 0xD4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_08_ALT2 Selecting Pad: GPIO_LPSR_08 for Mode: ALT2 0 SELECT_GPIO_LPSR_15_ALT7 Selecting Pad: GPIO_LPSR_15 for Mode: ALT7 0x1 SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register 0xD8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_04_ALT2 Selecting Pad: GPIO_LPSR_04 for Mode: ALT2 0 SELECT_GPIO_LPSR_12_ALT7 Selecting Pad: GPIO_LPSR_12 for Mode: ALT7 0x1 SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register 0xDC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write SELECT_GPIO_LPSR_03_ALT2 Selecting Pad: GPIO_LPSR_03 for Mode: ALT2 0 SELECT_GPIO_LPSR_10_ALT7 Selecting Pad: GPIO_LPSR_10 for Mode: ALT7 0x1 IOMUXC_LPSR_GPR IOMUXC LPSR GPR IOMUXC_LPSR_GPR 0x40C0C000 0 0xA8 registers GPR0 GPR0 General Purpose Register 0 32 read-write 0x400 0xFFFFFFFF CM4_INIT_VTOR_LOW CM4 Vector table offset value lower bits out of reset 3 13 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR1 GPR1 General Purpose Register 0x4 32 read-write 0x20 0xFFFFFFFF CM4_INIT_VTOR_HIGH CM4 Vector table offset value higher bits out of reset 0 16 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR2 GPR2 General Purpose Register 0x8 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R0_BOT APC start address of memory region-0 3 29 read-write GPR3 GPR3 General Purpose Register 0xC 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R0_TOP APC end address of memory region-0 3 29 read-write GPR4 GPR4 General Purpose Register 0x10 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R1_BOT APC start address of memory region-1 3 29 read-write GPR5 GPR5 General Purpose Register 0x14 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R1_TOP APC end address of memory region-1 3 29 read-write GPR6 GPR6 General Purpose Register 0x18 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R2_BOT APC start address of memory region-2 3 29 read-write GPR7 GPR7 General Purpose Register 0x1C 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R2_TOP APC end address of memory region-2 3 29 read-write GPR8 GPR8 General Purpose Register 0x20 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R3_BOT APC start address of memory region-3 3 29 read-write GPR9 GPR9 General Purpose Register 0x24 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R3_TOP APC end address of memory region-3 3 29 read-write GPR10 GPR10 General Purpose Register 0x28 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R4_BOT APC start address of memory region-4 3 29 read-write GPR11 GPR11 General Purpose Register 0x2C 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R4_TOP APC end address of memory region-4 3 29 read-write GPR12 GPR12 General Purpose Register 0x30 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R5_BOT APC start address of memory region-5 3 29 read-write GPR13 GPR13 General Purpose Register 0x34 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R5_TOP APC end address of memory region-5 3 29 read-write GPR14 GPR14 General Purpose Register 0x38 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R6_BOT APC start address of memory region-6 3 29 read-write GPR15 GPR15 General Purpose Register 0x3C 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R6_TOP APC end address of memory region-6 3 29 read-write GPR16 GPR16 General Purpose Register 0x40 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R7_BOT APC start address of memory region-7 3 29 read-write GPR17 GPR17 General Purpose Register 0x44 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce NO Write access to bit 31:1 is not blocked 0 BLOCK Write access to bit 31:1 is blocked 0x1 APC_AC_R7_TOP APC end address of memory region-7 3 29 read-write GPR18 GPR18 General Purpose Register 0x48 32 read-write 0 0xFFFFFFFF APC_R0_ENCRYPT_ENABLE APC memory region-0 encryption enable 4 1 read-write DIS No effect 0 ENABLE Encryption enabled 0x1 LOCK Lock the write to bit 15:0 16 16 read-writeOnce GPR19 GPR19 General Purpose Register 0x4C 32 read-write 0 0xFFFFFFFF APC_R1_ENCRYPT_ENABLE APC memory region-1 encryption enable 4 1 read-write DIS No effect 0 ENABLE Encryption enabled 0x1 LOCK Lock the write to bit 15:0 16 16 read-writeOnce GPR20 GPR20 General Purpose Register 0x50 32 read-write 0 0xFFFFFFFF APC_R2_ENCRYPT_ENABLE APC memory region-2 encryption enable 4 1 read-write DIS No effect 0 ENABLE Encryption enabled 0x1 LOCK Lock the write to bit 15:0 16 16 read-writeOnce GPR21 GPR21 General Purpose Register 0x54 32 read-write 0 0xFFFFFFFF APC_R3_ENCRYPT_ENABLE APC memory region-3 encryption enable 4 1 read-write DIS No effect 0 ENABLE Encryption enabled 0x1 LOCK Lock the write to bit 15:0 16 16 read-writeOnce GPR22 GPR22 General Purpose Register 0x58 32 read-write 0 0xFFFFFFFF APC_R4_ENCRYPT_ENABLE APC memory region-4 encryption enable 4 1 read-write DIS No effect 0 ENABLE Encryption enabled 0x1 LOCK Lock the write to bit 15:0 16 16 read-writeOnce GPR23 GPR23 General Purpose Register 0x5C 32 read-write 0 0xFFFFFFFF APC_R5_ENCRYPT_ENABLE APC memory region-5 encryption enable 4 1 read-write DIS No effect 0 ENABLE Encryption enabled 0x1 LOCK Lock the write to bit 15:0 16 16 read-writeOnce GPR24 GPR24 General Purpose Register 0x60 32 read-write 0 0xFFFFFFFF APC_R6_ENCRYPT_ENABLE APC memory region-6 encryption enable 4 1 read-write DIS No effect 0 ENABLE Encryption enabled 0x1 LOCK Lock the write to bit 15:0 16 16 read-writeOnce GPR25 GPR25 General Purpose Register 0x64 32 read-write 0 0xFFFFFFFF APC_R7_ENCRYPT_ENABLE APC memory region-7 encryption enable 4 1 read-write DIS No effect 0 ENABLE Encryption enabled 0x1 APC_VALID APC global enable bit 5 1 read-write DIS No effect 0 ENABLE Enable encryption for GPRx[APC_x_ENCRYPT_ENABLE] (valid for GPR2-GPR25) 0x1 LOCK Lock the write to bit 15:0 16 16 read-writeOnce GPR26 GPR26 General Purpose Register 0x68 32 read-write 0x4000 0xFFFFFFFF CM7_INIT_VTOR Vector table offset register out of reset. See the ARM v7-M Architecture Reference Manual for more information about the vector table offset register (VTOR). 0 25 read-write FIELD_0 General purpose bits 25 3 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR33 GPR33 General Purpose Register 0x84 32 read-write 0 0xFFFFFFFF M4_NMI_CLEAR Clear CM4 NMI holding register 0 1 read-write USBPHY1_WAKEUP_IRQ_CLEAR Clear USBPHY1 wakeup interrupt holding register 8 1 read-write USBPHY2_WAKEUP_IRQ_CLEAR Clear USBPHY1 wakeup interrupt holding register 9 1 read-write DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR34 GPR34 General Purpose Register 0x88 32 read-write 0xE00 0xFFFFFFFF GPIO_LPSR_HIGH_RANGE GPIO_LPSR IO bank supply voltage range selection 1 1 read-write GPIO_LPSR_LOW_RANGE GPIO_LPSR IO bank supply voltage range selection 2 1 read-write M7_NMI_MASK Mask CM7 NMI pin input 3 1 read-write DISABLE NMI input from IO to CM7 is not blocked 0 ENABLE NMI input from IO to CM7 is blocked 0x1 M4_NMI_MASK Mask CM4 NMI pin input 4 1 read-write DISABLE NMI input from IO to CM4 is not blocked 0 ENABLE NMI input from IO to CM4 is blocked 0x1 M4_GPC_SLEEP_SEL CM4 sleep request selection 5 1 read-write DISABLE CM4 SLEEPDEEP is sent to GPC 0 NABLE CM4 SLEEPING is sent to GPC 0x1 SEC_ERR_RESP Security error response enable 11 1 read-write DISABLE OKEY response 0 ENABLE SLVError (default) 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR35 GPR35 General Purpose Register 0x8C 32 read-write 0 0xFFFFFFFF ADC1_IPG_DOZE ADC1 doze mode 0 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 ADC1_STOP_REQ ADC1 stop request 1 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 ADC1_IPG_STOP_MODE ADC1 stop mode selection. This bitfield cannot change when ADC1_STOP_REQ is asserted. 2 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 ADC2_IPG_DOZE ADC2 doze mode 3 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 ADC2_STOP_REQ ADC2 stop request 4 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 ADC2_IPG_STOP_MODE ADC2 stop mode selection. This bitfield cannot change when ADC2_STOP_REQ is asserted. 5 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 CAAM_IPG_DOZE CAN3 doze mode 6 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 CAAM_STOP_REQ CAAM stop request 7 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 CAN1_IPG_DOZE CAN1 doze mode 8 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 CAN1_STOP_REQ CAN1 stop request 9 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 CAN2_IPG_DOZE CAN2 doze mode 10 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 CAN2_STOP_REQ CAN2 stop request 11 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 CAN3_IPG_DOZE CAN3 doze mode 12 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 CAN3_STOP_REQ CAN3 stop request 13 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 EDMA_STOP_REQ EDMA stop request 15 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 EDMA_LPSR_STOP_REQ EDMA_LPSR stop request 16 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 ENET_IPG_DOZE ENET doze mode 17 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 ENET_STOP_REQ ENET stop request 18 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 ENET1G_IPG_DOZE ENET1G doze mode 19 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 ENET1G_STOP_REQ ENET1G stop request 20 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 FLEXIO1_IPG_DOZE FLEXIO2 doze mode 21 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 FLEXIO2_IPG_DOZE FLEXIO2 doze mode 22 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 FLEXSPI1_IPG_DOZE FLEXSPI1 doze mode 23 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 FLEXSPI1_STOP_REQ FLEXSPI1 stop request 24 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 FLEXSPI2_IPG_DOZE FLEXSPI2 doze mode 25 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 FLEXSPI2_STOP_REQ FLEXSPI2 stop request 26 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR36 GPR36 General Purpose Register 0x90 32 read-write 0 0xFFFFFFFF GPT1_IPG_DOZE GPT1 doze mode 0 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 GPT2_IPG_DOZE GPT2 doze mode 1 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 GPT3_IPG_DOZE GPT3 doze mode 2 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 GPT4_IPG_DOZE GPT4 doze mode 3 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 GPT5_IPG_DOZE GPT5 doze mode 4 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 GPT6_IPG_DOZE GPT6 doze mode 5 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPI2C1_IPG_DOZE LPI2C1 doze mode 6 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPI2C1_STOP_REQ LPI2C1 stop request 7 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPI2C1_IPG_STOP_MODE LPI2C1 stop mode selection. This bitfield cannot change when LPI2C1_STOP_REQ is asserted. 8 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPI2C2_IPG_DOZE LPI2C2 doze mode 9 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPI2C2_STOP_REQ LPI2C2 stop request 10 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPI2C2_IPG_STOP_MODE LPI2C2 stop mode selection. This bitfield cannot change when LPI2C2_STOP_REQ is asserted. 11 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPI2C3_IPG_DOZE LPI2C3 doze mode 12 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPI2C3_STOP_REQ LPI2C3 stop request 13 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPI2C3_IPG_STOP_MODE LPI2C3 stop mode selection. This bitfield cannot change when LPI2C3_STOP_REQ is asserted. 14 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPI2C4_IPG_DOZE LPI2C4 doze mode 15 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPI2C4_STOP_REQ LPI2C4 stop request 16 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPI2C4_IPG_STOP_MODE LPI2C4 stop mode selection. This bitfield cannot change when LPI2C4_STOP_REQ is asserted. 17 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPI2C5_IPG_DOZE LPI2C5 doze mode 18 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPI2C5_STOP_REQ LPI2C5 stop request 19 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPI2C5_IPG_STOP_MODE LPI2C5 stop mode selection. This bitfield cannot change when LPI2C5_STOP_REQ is asserted. 20 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPI2C6_IPG_DOZE LPI2C6 doze mode 21 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPI2C6_STOP_REQ LPI2C6 stop request 22 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPI2C6_IPG_STOP_MODE LPI2C6 stop mode selection. This bitfield cannot change when LPI2C6_STOP_REQ is asserted. 23 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPSPI1_IPG_DOZE LPSPI1 doze mode 24 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPSPI1_STOP_REQ LPSPI1 stop request 25 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPSPI1_IPG_STOP_MODE LPSPI1 stop mode selection. This bitfield cannot change when LPSPI1_STOP_REQ is asserted. 26 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR37 GPR37 General Purpose Register 0x94 32 read-write 0 0xFFFFFFFF LPSPI2_IPG_DOZE LPSPI2 doze mode 0 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPSPI2_STOP_REQ LPSPI2 stop request 1 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPSPI2_IPG_STOP_MODE LPSPI2 stop mode selection. This bitfield cannot change when LPSPI2_STOP_REQ is asserted. 2 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPSPI3_IPG_DOZE LPSPI3 doze mode 3 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPSPI3_STOP_REQ LPSPI3 stop request 4 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPSPI3_IPG_STOP_MODE LPSPI3 stop mode selection. This bitfield cannot change when LPSPI3_STOP_REQ is asserted. 5 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPSPI4_IPG_DOZE LPSPI4 doze mode 6 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPSPI4_STOP_REQ LPSPI4 stop request 7 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPSPI4_IPG_STOP_MODE LPSPI4 stop mode selection. This bitfield cannot change when LPSPI4_STOP_REQ is asserted. 8 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPSPI5_IPG_DOZE LPSPI5 doze mode 9 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPSPI5_STOP_REQ LPSPI5 stop request 10 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPSPI5_IPG_STOP_MODE LPSPI5 stop mode selection. This bitfield cannot change when LPSPI5_STOP_REQ is asserted. 11 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPSPI6_IPG_DOZE LPSPI6 doze mode 12 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPSPI6_STOP_REQ LPSPI6 stop request 13 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPSPI6_IPG_STOP_MODE LPSPI6 stop mode selection. This bitfield cannot change when LPSPI6_STOP_REQ is asserted. 14 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART1_IPG_DOZE LPUART1 doze mode 15 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART1_STOP_REQ LPUART1 stop request 16 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART1_IPG_STOP_MODE LPUART1 stop mode selection. This bitfield cannot change when LPUART1_STOP_REQ is asserted. 17 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART2_IPG_DOZE LPUART2 doze mode 18 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART2_STOP_REQ LPUART2 stop request 19 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART2_IPG_STOP_MODE LPUART2 stop mode selection. This bitfield cannot change when LPUART2_STOP_REQ is asserted. 20 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART3_IPG_DOZE LPUART3 doze mode 21 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART3_STOP_REQ LPUART3 stop request 22 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART3_IPG_STOP_MODE LPUART3 stop mode selection. This bitfield cannot change when LPUART3_STOP_REQ is asserted. 23 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART4_IPG_DOZE LPUART4 doze mode 24 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART4_STOP_REQ LPUART4 stop request 25 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART4_IPG_STOP_MODE LPUART4 stop mode selection. This bitfield cannot change when LPUART4_STOP_REQ is asserted. 26 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR38 GPR38 General Purpose Register 0x98 32 read-write 0 0xFFFFFFFF LPUART5_IPG_DOZE LPUART5 doze mode 0 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART5_STOP_REQ LPUART5 stop request 1 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART5_IPG_STOP_MODE LPUART5 stop mode selection. This bitfield cannot change when LPUART5_STOP_REQ is asserted. 2 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART6_IPG_DOZE LPUART6 doze mode 3 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART6_STOP_REQ LPUART6 stop request 4 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART6_IPG_STOP_MODE LPUART6 stop mode selection. This bitfield cannot change when LPUART6_STOP_REQ is asserted. 5 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART7_IPG_DOZE LPUART7 doze mode 6 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART7_STOP_REQ LPUART7 stop request 7 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART7_IPG_STOP_MODE LPUART7 stop mode selection. This bitfield cannot change when LPUART7_STOP_REQ is asserted. 8 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART8_IPG_DOZE LPUART8 doze mode 9 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART8_STOP_REQ LPUART8 stop request 10 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART8_IPG_STOP_MODE LPUART8 stop mode selection. This bitfield cannot change when LPUART8_STOP_REQ is asserted. 11 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART9_IPG_DOZE LPUART9 doze mode 12 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART9_STOP_REQ LPUART9 stop request 13 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART9_IPG_STOP_MODE LPUART9 stop mode selection. This bitfield cannot change when LPUART9_STOP_REQ is asserted. 14 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART10_IPG_DOZE LPUART10 doze mode 15 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART10_STOP_REQ LPUART10 stop request 16 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART10_IPG_STOP_MODE LPUART10 stop mode selection. This bitfield cannot change when LPUART10_STOP_REQ is asserted. 17 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART11_IPG_DOZE LPUART11 doze mode 18 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART11_STOP_REQ LPUART11 stop request 19 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART11_IPG_STOP_MODE LPUART11 stop mode selection. This bitfield cannot change when LPUART11_STOP_REQ is asserted. 20 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 LPUART12_IPG_DOZE LPUART12 doze mode 21 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 LPUART12_STOP_REQ LPUART12 stop request 22 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 LPUART12_IPG_STOP_MODE LPUART12 stop mode selection. This bitfield cannot change when LPUART12_STOP_REQ is asserted. 23 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 MIC_IPG_DOZE MIC doze mode 24 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 MIC_STOP_REQ MIC stop request 25 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 MIC_IPG_STOP_MODE MIC stop mode selection. This bitfield cannot change when MIC_STOP_REQ is asserted. 26 1 read-write FUNC This module is functional in Stop Mode 0 NONFUNC This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR39 GPR39 General Purpose Register 0x9C 32 read-write 0 0xFFFFFFFF PIT1_STOP_REQ PIT1 stop request 1 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 PIT2_STOP_REQ PIT2 stop request 2 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 SEMC_STOP_REQ SEMC stop request 3 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 SIM1_IPG_DOZE SIM1 doze mode 4 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 SIM2_IPG_DOZE SIM2 doze mode 5 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 SNVS_HP_IPG_DOZE SNVS_HP doze mode 6 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 SNVS_HP_STOP_REQ SNVS_HP stop request 7 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 WDOG1_IPG_DOZE WDOG1 doze mode 8 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 WDOG2_IPG_DOZE WDOG2 doze mode 9 1 read-write DISABLE Not in doze mode 0 ENABLE In doze mode 0x1 SAI1_STOP_REQ SAI1 stop request 10 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 SAI2_STOP_REQ SAI2 stop request 11 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 SAI3_STOP_REQ SAI3 stop request 12 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 SAI4_STOP_REQ SAI4 stop request 13 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 FLEXIO1_STOP_REQ_BUS FLEXIO1 bus clock domain stop request 14 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 FLEXIO1_STOP_REQ_PER FLEXIO1 peripheral clock domain stop request 15 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 FLEXIO2_STOP_REQ_BUS FLEXIO2 bus clock domain stop request 16 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 FLEXIO2_STOP_REQ_PER FLEXIO2 peripheral clock domain stop request 17 1 read-write DISABLE Stop request off 0 ENABLE Stop request on 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 GPR40 GPR40 General Purpose Register 0xA0 32 read-only 0 0xFFFFFFFF ADC1_STOP_ACK ADC1 stop acknowledge 0 1 read-only ADC2_STOP_ACK ADC2 stop acknowledge 1 1 read-only CAAM_STOP_ACK CAAM stop acknowledge 2 1 read-only CAN1_STOP_ACK CAN1 stop acknowledge 3 1 read-only CAN2_STOP_ACK CAN2 stop acknowledge 4 1 read-only CAN3_STOP_ACK CAN3 stop acknowledge 5 1 read-only EDMA_STOP_ACK EDMA stop acknowledge 6 1 read-only EDMA_LPSR_STOP_ACK EDMA_LPSR stop acknowledge 7 1 read-only ENET_STOP_ACK ENET stop acknowledge 8 1 read-only ENET1G_STOP_ACK ENET1G stop acknowledge 9 1 read-only FLEXSPI1_STOP_ACK FLEXSPI1 stop acknowledge 10 1 read-only FLEXSPI2_STOP_ACK FLEXSPI2 stop acknowledge 11 1 read-only LPI2C1_STOP_ACK LPI2C1 stop acknowledge 12 1 read-only LPI2C2_STOP_ACK LPI2C2 stop acknowledge 13 1 read-only LPI2C3_STOP_ACK LPI2C3 stop acknowledge 14 1 read-only LPI2C4_STOP_ACK LPI2C4 stop acknowledge 15 1 read-only LPI2C5_STOP_ACK LPI2C5 stop acknowledge 16 1 read-only LPI2C6_STOP_ACK LPI2C6 stop acknowledge 17 1 read-only LPSPI1_STOP_ACK LPSPI1 stop acknowledge 18 1 read-only LPSPI2_STOP_ACK LPSPI2 stop acknowledge 19 1 read-only LPSPI3_STOP_ACK LPSPI3 stop acknowledge 20 1 read-only LPSPI4_STOP_ACK LPSPI4 stop acknowledge 21 1 read-only LPSPI5_STOP_ACK LPSPI5 stop acknowledge 22 1 read-only LPSPI6_STOP_ACK LPSPI6 stop acknowledge 23 1 read-only LPUART1_STOP_ACK LPUART1 stop acknowledge 24 1 read-only LPUART2_STOP_ACK LPUART2 stop acknowledge 25 1 read-only LPUART3_STOP_ACK LPUART3 stop acknowledge 26 1 read-only LPUART4_STOP_ACK LPUART4 stop acknowledge 27 1 read-only LPUART5_STOP_ACK LPUART5 stop acknowledge 28 1 read-only LPUART6_STOP_ACK LPUART6 stop acknowledge 29 1 read-only LPUART7_STOP_ACK LPUART7 stop acknowledge 30 1 read-only LPUART8_STOP_ACK LPUART8 stop acknowledge 31 1 read-only GPR41 GPR41 General Purpose Register 0xA4 32 read-only 0 0xFFFFFFFF LPUART9_STOP_ACK LPUART9 stop acknowledge 0 1 read-only LPUART10_STOP_ACK LPUART10 stop acknowledge 1 1 read-only LPUART11_STOP_ACK LPUART11 stop acknowledge 2 1 read-only LPUART12_STOP_ACK LPUART12 stop acknowledge 3 1 read-only MIC_STOP_ACK MIC stop acknowledge 4 1 read-only PIT1_STOP_ACK PIT1 stop acknowledge 5 1 read-only PIT2_STOP_ACK PIT2 stop acknowledge 6 1 read-only SEMC_STOP_ACK SEMC stop acknowledge 7 1 read-only SNVS_HP_STOP_ACK SNVS_HP stop acknowledge 8 1 read-only SAI1_STOP_ACK SAI1 stop acknowledge 9 1 read-only SAI2_STOP_ACK SAI2 stop acknowledge 10 1 read-only SAI3_STOP_ACK SAI3 stop acknowledge 11 1 read-only SAI4_STOP_ACK SAI4 stop acknowledge 12 1 read-only FLEXIO1_STOP_ACK_BUS FLEXIO1 stop acknowledge of bus clock domain 13 1 read-only FLEXIO1_STOP_ACK_PER FLEXIO1 stop acknowledge of peripheral clock domain 14 1 read-only FLEXIO2_STOP_ACK_BUS FLEXIO2 stop acknowledge of bus clock domain 15 1 read-only FLEXIO2_STOP_ACK_PER FLEXIO2 stop acknowledge of peripheral clock domain 16 1 read-only ROM_READ_LOCKED ROM read lock status bit 24 1 read-only PDM PDM PDM 0x40C20000 0 0xAC registers PDM_HWVAD_EVENT 200 PDM_HWVAD_ERROR 201 PDM_EVENT 202 PDM_ERROR 203 CTRL_1 PDM Control register 1 0 32 read-write 0 0xFFFFFFFF CH0EN Channel 0 Enable 0 1 read-write CH1EN Channel 1 Enable 1 1 read-write CH2EN Channel 2 Enable 2 1 read-write CH3EN Channel 3 Enable 3 1 read-write CH4EN Channel 4 Enable 4 1 read-write CH5EN Channel 5 Enable 5 1 read-write CH6EN Channel 6 Enable 6 1 read-write CH7EN Channel 7 Enable 7 1 read-write ERREN Error Interruption Enable 23 1 read-write disabled Error Interrupts disabled 0 enabled Error Interrupts enabled 0x1 DISEL DMA Interrupt Selection 24 2 read-write all_disabled DMA and interrupt requests disabled 0 dmareq_enabled DMA requests enabled 0x1 intreq_enabled Interrupt requests enabled 0x2 DBGE Module Enable in Debug 26 1 read-write disabled Disabled after completing the current frame 0 enabled Enabled 0x1 SRES Software-reset bit 27 1 read-write no_action No action 0 sw_reset Software reset 0x1 DBG Debug Mode 28 1 read-write normal Normal Mode 0 debug Debug Mode 0x1 PDMIEN PDM Enable 29 1 read-write stopped PDM stopped 0 started PDM operation started 0x1 DOZEN DOZE enable 30 1 read-write MDIS Module Disable 31 1 read-write normal Normal Mode 0 low_leakage Disable/Low Leakage Mode 0x1 CTRL_2 PDM Control register 2 0x4 32 read-write 0 0xFFFFFFFF CLKDIV Clock Divider 0 8 read-write CICOSR CIC Decimation Rate 16 4 read-write QSEL Quality Mode 25 3 read-write mq_mode Medium quality mode 0 hq_mode High quality mode 0x1 vlq2_mode Very low quality 2 mode 0x4 vlq1_mode Very low quality 1 mode 0x5 vlq0_mode Very low quality 0 mode 0x6 lq_mode Low quality mode 0x7 STAT PDM Status register 0x8 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Output Data Flag 0 1 read-write oneToClear wm_notreached Channel's FIFO did not reach the number of elements configured in watermark bit-field 0 wm_reached Channel's FIFO reached the number of elements configured in watermark bit-field 0x1 CH1F Channel 1 Output Data Flag 1 1 read-write oneToClear wm_notreached Channel's FIFO did not reach the number of elements configured in watermark bit-field 0 wm_reached Channel's FIFO reached the number of elements configured in watermark bit-field 0x1 CH2F Channel 2 Output Data Flag 2 1 read-write oneToClear wm_notreached Channel's FIFO did not reach the number of elements configured in watermark bit-field 0 wm_reached Channel's FIFO reached the number of elements configured in watermark bit-field 0x1 CH3F Channel 3 Output Data Flag 3 1 read-write oneToClear wm_notreached Channel's FIFO did not reach the number of elements configured in watermark bit-field 0 wm_reached Channel's FIFO reached the number of elements configured in watermark bit-field 0x1 CH4F Channel 4 Output Data Flag 4 1 read-write oneToClear wm_notreached Channel's FIFO did not reach the number of elements configured in watermark bit-field 0 wm_reached Channel's FIFO reached the number of elements configured in watermark bit-field 0x1 CH5F Channel 5 Output Data Flag 5 1 read-write oneToClear wm_notreached Channel's FIFO did not reach the number of elements configured in watermark bit-field 0 wm_reached Channel's FIFO reached the number of elements configured in watermark bit-field 0x1 CH6F Channel 6 Output Data Flag 6 1 read-write oneToClear wm_notreached Channel's FIFO did not reach the number of elements configured in watermark bit-field 0 wm_reached Channel's FIFO reached the number of elements configured in watermark bit-field 0x1 CH7F Channel 7 Output Data Flag 7 1 read-write oneToClear wm_notreached Channel's FIFO did not reach the number of elements configured in watermark bit-field 0 wm_reached Channel's FIFO reached the number of elements configured in watermark bit-field 0x1 LOWFREQF Low Frequency Flag 29 1 read-write oneToClear clkdiv_ok CLKDIV value is OK 0 clkdiv_low CLKDIV value is too low 0x1 FIR_RDY Filter Data Ready 30 1 read-only not_reliable Filter data is not reliable 0 reliable Filter data is reliable 0x1 BSY_FIL Busy Flag 31 1 read-only stopped PDM is stopped 0 running PDM is running 0x1 FIFO_CTRL PDM FIFO Control register 0x10 32 read-write 0x7 0xFFFFFFFF FIFOWMK FIFO Watermark Control 0 3 read-write FIFO_STAT PDM FIFO Status register 0x14 32 read-write 0 0xFFFFFFFF oneToClear FIFOOVF0 FIFO Overflow Exception flag for Channel 0 0 1 read-write oneToClear no_exception No exception by FIFO overflow 0 exception Exception by FIFO overflow 0x1 FIFOOVF1 FIFO Overflow Exception flag for Channel 1 1 1 read-write oneToClear no_exception No exception by FIFO overflow 0 exception Exception by FIFO overflow 0x1 FIFOOVF2 FIFO Overflow Exception flag for Channel 2 2 1 read-write oneToClear no_exception No exception by FIFO overflow 0 exception Exception by FIFO overflow 0x1 FIFOOVF3 FIFO Overflow Exception flag for Channel 3 3 1 read-write oneToClear no_exception No exception by FIFO overflow 0 exception Exception by FIFO overflow 0x1 FIFOOVF4 FIFO Overflow Exception flag for Channel 4 4 1 read-write oneToClear no_exception No exception by FIFO overflow 0 exception Exception by FIFO overflow 0x1 FIFOOVF5 FIFO Overflow Exception flag for Channel 5 5 1 read-write oneToClear no_exception No exception by FIFO overflow 0 exception Exception by FIFO overflow 0x1 FIFOOVF6 FIFO Overflow Exception flag for Channel 6 6 1 read-write oneToClear no_exception No exception by FIFO overflow 0 exception Exception by FIFO overflow 0x1 FIFOOVF7 FIFO Overflow Exception flag for Channel 7 7 1 read-write oneToClear no_exception No exception by FIFO overflow 0 exception Exception by FIFO overflow 0x1 FIFOUND0 FIFO Underflow Exception flag for Channel 0 8 1 read-write oneToClear no_exception No exception by FIFO Underflow 0 exception Exception by FIFO underflow 0x1 FIFOUND1 FIFO Underflow Exception flag for Channel 1 9 1 read-write oneToClear no_exception No exception by FIFO Underflow 0 exception Exception by FIFO underflow 0x1 FIFOUND2 FIFO Underflow Exception flag for Channel 2 10 1 read-write oneToClear no_exception No exception by FIFO Underflow 0 exception Exception by FIFO underflow 0x1 FIFOUND3 FIFO Underflow Exception flag for Channel 3 11 1 read-write oneToClear no_exception No exception by FIFO Underflow 0 exception Exception by FIFO underflow 0x1 FIFOUND4 FIFO Underflow Exception flag for Channel 4 12 1 read-write oneToClear no_exception No exception by FIFO Underflow 0 exception Exception by FIFO underflow 0x1 FIFOUND5 FIFO Underflow Exception flag for Channel 5 13 1 read-write oneToClear no_exception No exception by FIFO Underflow 0 exception Exception by FIFO underflow 0x1 FIFOUND6 FIFO Underflow Exception flag for Channel 6 14 1 read-write oneToClear no_exception No exception by FIFO Underflow 0 exception Exception by FIFO underflow 0x1 FIFOUND7 FIFO Underflow Exception flag for Channel 7 15 1 read-write oneToClear no_exception No exception by FIFO Underflow 0 exception Exception by FIFO underflow 0x1 8 0x4 DATACH[%s] PDM Output Result Register 0x24 32 read-only 0 0xFFFFFFFF DATA Channel n Data 0 32 read-only DC_CTRL PDM DC Remover Control register 0x64 32 read-write 0 0xFFFFFFFF DCCONFIG0 Channel 0 DC Remover Configuration 0 2 read-write dc_rem_21Hz DC Remover cut-off at 21Hz 0 dc_rem_83Hz DC Remover cut-off at 83Hz 0x1 dc_rem_152Hz DC Remover cut-off at 152Hz 0x2 dc_rem_bypass DC Remover is bypassed 0x3 DCCONFIG1 Channel 1 DC Remover Configuration 2 2 read-write dc_rem_21Hz DC Remover cut-off at 21Hz 0 dc_rem_83Hz DC Remover cut-off at 83Hz 0x1 dc_rem_152Hz DC Remover cut-off at 152Hz 0x2 dc_rem_bypass DC Remover is bypassed 0x3 DCCONFIG2 Channel 2 DC Remover Configuration 4 2 read-write dc_rem_21Hz DC Remover cut-off at 21Hz 0 dc_rem_83Hz DC Remover cut-off at 83Hz 0x1 dc_rem_152Hz DC Remover cut-off at 152Hz 0x2 dc_rem_bypass DC Remover is bypassed 0x3 DCCONFIG3 Channel 3 DC Remover Configuration 6 2 read-write dc_rem_21Hz DC Remover cut-off at 21Hz 0 dc_rem_83Hz DC Remover cut-off at 83Hz 0x1 dc_rem_152Hz DC Remover cut-off at 152Hz 0x2 dc_rem_bypass DC Remover is bypassed 0x3 DCCONFIG4 Channel 4 DC Remover Configuration 8 2 read-write dc_rem_21Hz DC Remover cut-off at 21Hz 0 dc_rem_83Hz DC Remover cut-off at 83Hz 0x1 dc_rem_152Hz DC Remover cut-off at 152Hz 0x2 dc_rem_bypass DC Remover is bypassed 0x3 DCCONFIG5 Channel 5 DC Remover Configuration 10 2 read-write dc_rem_21Hz DC Remover cut-off at 21Hz 0 dc_rem_83Hz DC Remover cut-off at 83Hz 0x1 dc_rem_152Hz DC Remover cut-off at 152Hz 0x2 dc_rem_bypass DC Remover is bypassed 0x3 DCCONFIG6 Channel 6 DC Remover Configuration 12 2 read-write dc_rem_21Hz DC Remover cut-off at 21Hz 0 dc_rem_83Hz DC Remover cut-off at 83Hz 0x1 dc_rem_152Hz DC Remover cut-off at 152Hz 0x2 dc_rem_bypass DC Remover is bypassed 0x3 DCCONFIG7 Channel 7 DC Remover Configuration 14 2 read-write dc_rem_21Hz DC Remover cut-off at 21Hz 0 dc_rem_83Hz DC Remover cut-off at 83Hz 0x1 dc_rem_152Hz DC Remover cut-off at 152Hz 0x2 dc_rem_bypass DC Remover is bypassed 0x3 RANGE_CTRL PDM Range Control register 0x74 32 read-write 0 0xFFFFFFFF RANGEADJ0 Channel 0 Range Adjustment 0 4 read-write RANGEADJ1 Channel 1 Range Adjustment 4 4 read-write RANGEADJ2 Channel 2 Range Adjustment 8 4 read-write RANGEADJ3 Channel 3 Range Adjustment 12 4 read-write RANGEADJ4 Channel 4 Range Adjustment 16 4 read-write RANGEADJ5 Channel 5 Range Adjustment 20 4 read-write RANGEADJ6 Channel 6 Range Adjustment 24 4 read-write RANGEADJ7 Channel 7 Range Adjustment 28 4 read-write RANGE_STAT PDM Range Status register 0x7C 32 read-write 0 0xFFFFFFFF oneToClear RANGEOVF0 Channel 0 Range Overflow Error Flag 0 1 read-write oneToClear no_exception No exception by range overflow 0 exception Exception by range overflow 0x1 RANGEOVF1 Channel 1 Range Overflow Error Flag 1 1 read-write oneToClear no_exception No exception by range overflow 0 exception Exception by range overflow 0x1 RANGEOVF2 Channel 2 Range Overflow Error Flag 2 1 read-write oneToClear no_exception No exception by range overflow 0 exception Exception by range overflow 0x1 RANGEOVF3 Channel 3 Range Overflow Error Flag 3 1 read-write oneToClear no_exception No exception by range overflow 0 exception Exception by range overflow 0x1 RANGEOVF4 Channel 4 Range Overflow Error Flag 4 1 read-write oneToClear no_exception No exception by range overflow 0 exception Exception by range overflow 0x1 RANGEOVF5 Channel 5 Range Overflow Error Flag 5 1 read-write oneToClear no_exception No exception by range overflow 0 exception Exception by range overflow 0x1 RANGEOVF6 Channel 6 Range Overflow Error Flag 6 1 read-write oneToClear no_exception No exception by range overflow 0 exception Exception by range overflow 0x1 RANGEOVF7 Channel 7 Range Overflow Error Flag 7 1 read-write oneToClear no_exception No exception by range overflow 0 exception Exception by range overflow 0x1 RANGEUNF0 Channel 0 Range Underflow Error Flag 16 1 read-write oneToClear no_exception No exception by range underflow 0 exception Exception by range underflow 0x1 RANGEUNF1 Channel 1 Range Underflow Error Flag 17 1 read-write oneToClear no_exception No exception by range underflow 0 exception Exception by range underflow 0x1 RANGEUNF2 Channel 2 Range Underflow Error Flag 18 1 read-write oneToClear no_exception No exception by range underflow 0 exception Exception by range underflow 0x1 RANGEUNF3 Channel 3 Range Underflow Error Flag 19 1 read-write oneToClear no_exception No exception by range underflow 0 exception Exception by range underflow 0x1 RANGEUNF4 Channel 4 Range Underflow Error Flag 20 1 read-write oneToClear no_exception No exception by range underflow 0 exception Exception by range underflow 0x1 RANGEUNF5 Channel 5 Range Underflow Error Flag 21 1 read-write oneToClear no_exception No exception by range underflow 0 exception Exception by range underflow 0x1 RANGEUNF6 Channel 6 Range Underflow Error Flag 22 1 read-write oneToClear no_exception No exception by range underflow 0 exception Exception by range underflow 0x1 RANGEUNF7 Channel 7 Range Underflow Error Flag 23 1 read-write oneToClear no_exception No exception by range underflow 0 exception Exception by range underflow 0x1 VAD0_CTRL_1 Voice Activity Detector 0 Control register 0x90 32 read-write 0 0xFFFFFFFF VADEN Voice Activity Detector Enable 0 1 read-write disabled The HWVAD is disabled 0 enabled The HWVAD is enabled 0x1 VADRST Voice Activity Detector Reset 1 1 read-write VADIE Voice Activity Detector Interruption Enable 2 1 read-write disabled HWVAD Interrupts disabled 0 enabled HWVAD Interrupts enabled 0x1 VADERIE Voice Activity Detector Error Interruption Enable 3 1 read-write disabled HWVAD Error Interrupts disabled 0 enabled HWVAD Error Interrupts enabled 0x1 VADST10 Voice Activity Detector Internal Filters Initialization 4 1 read-write normal_op Normal operation. 0 filt_init Filters are initialized. 0x1 VADINITT Voice Activity Detector Initialization Time 8 5 read-write VADCICOSR Voice Activity Detector CIC Oversampling Rate 16 4 read-write VADCHSEL Voice Activity Detector Channel Selector 24 3 read-write VAD0_CTRL_2 Voice Activity Detector 0 Control register 0x94 32 read-write 0xA0000 0xFFFFFFFF VADHPF Voice Activity Detector High-Pass Filter 0 2 read-write filt_bypass Filter bypassed. 0 cutoff_1750Hz Cut-off frequency at 1750Hz. 0x1 cutoff_215Hz Cut-off frequency at 215Hz. 0x2 cutoff_102Hz Cut-off frequency at 102Hz. 0x3 VADINPGAIN Voice Activity Detector Input Gain 8 4 read-write VADFRAMET Voice Activity Detector Frame Time 16 6 read-write VADFOUTDIS Voice Activity Detector Force Output Disable 28 1 read-write out_enabled Output is enabled. 0 out_disabled Output is disabled. 0x1 VADPREFEN Voice Activity Detector Pre Filter Enable 30 1 read-write bypassed Pre-filter is bypassed. 0 enabled Pre-filter is enabled. 0x1 VADFRENDIS Voice Activity Detector Frame Energy Disable 31 1 read-write enabled Frame energy calculus enabled. 0 disabled Frame energy calculus disabled. 0x1 VAD0_STAT Voice Activity Detector 0 Status register 0x98 32 read-write 0x80000000 0xFFFFFFFF VADIF Voice Activity Detector Interrupt Flag 0 1 read-write oneToClear no_detect Voice activity not detected 0 detect Voice activity detected 0x1 VADEF Voice Activity Detector Event Flag 15 1 read-only no_detect Voice activity not detected 0 detect Voice activity detected 0x1 VADINSATF Voice Activity Detector Input Saturation Flag 16 1 read-write oneToClear no_exception No exception 0 exception Exception 0x1 VADINITF Voice Activity Detector Initialization Flag 31 1 read-only not_init HWVAD is not being initialized. 0 init HWVAD is being initialized. 0x1 VAD0_SCONFIG Voice Activity Detector 0 Signal Configuration 0x9C 32 read-write 0 0xFFFFFFFF VADSGAIN Voice Activity Detector Signal Gain 0 4 read-write VADSMAXEN Voice Activity Detector Signal Maximum Enable 30 1 read-write bypassed Maximum block is bypassed. 0 enabled Maximum block is enabled. 0x1 VADSFILEN Voice Activity Detector Signal Filter Enable 31 1 read-write disabled Signal filter is disabled. 0 enabled Signal filter is enabled. 0x1 VAD0_NCONFIG Voice Activity Detector 0 Noise Configuration 0xA0 32 read-write 0x80000000 0xFFFFFFFF VADNGAIN Voice Activity Detector Noise Gain 0 4 read-write VADNFILADJ Voice Activity Detector Noise Filter Adjustment 8 5 read-write VADNOREN Voice Activity Detector Noise OR Enable 28 1 read-write not_decimated Noise input is not decimated. 0 decimated Noise input is decimated. 0x1 VADNDECEN Voice Activity Detector Noise Decimation Enable 29 1 read-write not_decimated Noise input is not decimated. 0 decimated Noise input is decimated. 0x1 VADNMINEN Voice Activity Detector Noise Minimum Enable 30 1 read-write bypassed Minimum block is bypassed. 0 enabled Minimum block is enabled. 0x1 VADNFILAUTO Voice Activity Detector Noise Filter Auto 31 1 read-write nf_always_en Noise filter is always enabled. 0 nf_cond_en Noise filter is enabled/disabled based on voice activity information. 0x1 VAD0_NDATA Voice Activity Detector 0 Noise Data 0xA4 32 read-only 0 0xFFFFFFFF VADNDATA Voice Activity Detector Noise Data 0 16 read-only VAD0_ZCD Voice Activity Detector 0 Zero-Crossing Detector 0xA8 32 read-write 0x4 0xFFFFFFFF VADZCDEN Zero-Crossing Detector Enable 0 1 read-write disabled The ZCD is disabled 0 enabled The ZCD is enabled 0x1 VADZCDAUTO Zero-Crossing Detector Automatic Threshold 2 1 read-write not_estimated The ZCD threshold is not estimated automatically 0 estimated The ZCD threshold is estimated automatically 0x1 VADZCDAND Zero-Crossing Detector AND Behavior 4 1 read-write ored The ZCD result is OR'ed with the energy-based detection. 0 anded The ZCD result is AND'ed with the energy-based detection. 0x1 VADZCDADJ Zero-Crossing Detector Adjustment 8 4 read-write VADZCDTH Zero-Crossing Detector Threshold 16 10 read-write RDC_SEMAPHORE1 SEMA42 RDC_SEMAPHORE RDC_SEMAPHORE1_ RDC_SEMAPHORE 0x40C44000 0 0x44 registers 64 0x1 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 GATE%s Gate Register 0 8 read-write 0 0xFF GTFSM Gate Finite State Machine. 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor with master_index = 0. 0x1 GTFSM_2 The gate has been locked by processor with master_index = 1. 0x2 GTFSM_3 The gate has been locked by processor with master_index = 2. 0x3 GTFSM_4 The gate has been locked by processor with master_index = 3. 0x4 GTFSM_5 The gate has been locked by processor with master_index = 4. 0x5 GTFSM_6 The gate has been locked by processor with master_index = 5. 0x6 GTFSM_7 The gate has been locked by processor with master_index = 6. 0x7 GTFSM_8 The gate has been locked by processor with master_index = 7. 0x8 GTFSM_9 The gate has been locked by processor with master_index = 8. 0x9 GTFSM_10 The gate has been locked by processor with master_index = 9. 0xA GTFSM_11 The gate has been locked by processor with master_index = 10. 0xB GTFSM_12 The gate has been locked by processor with master_index = 11. 0xC GTFSM_13 The gate has been locked by processor with master_index = 12. 0xD GTFSM_14 The gate has been locked by processor with master_index = 13. 0xE GTFSM_15 The gate has been locked by processor with master_index = 14. 0xF LDOM Read-only bits. They indicate which domain had currently locked the gate. 4 2 read-only LDOM_0 The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.) 0 LDOM_1 The gate has been locked by domain 1. 0x1 RSTGT_R Reset Gate Read RSTGT_R_RSTGT_W 0x42 16 read-write 0 0xFFFF RSTGMS Reset Gate Bus Master 0 4 read-only RSTGSM Reset Gate Finite State Machine 4 2 read-only RSTGSM_0 Idle, waiting for the first data pattern write. 0 RSTGSM_1 Waiting for the second data pattern write. 0x1 RSTGSM_2 The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists for only one clock cycle. Software will never be able to observe this state. 0x2 RSTGSM_3 This state encoding is never used and therefore reserved. 0x3 RSTGTN Reset Gate Number 8 8 read-write RSTGT_W Reset Gate Write RSTGT_R_RSTGT_W 0x42 16 read-write 0 0xFFFF RSTGDP Reset Gate Data Pattern 0 8 read-write RSTGTN Reset Gate Number 8 8 read-write RDC_SEMAPHORE2 SEMA42 RDC_SEMAPHORE RDC_SEMAPHORE2_ 0x40CCC000 0 0x44 registers MUA MUA MU 0x40C48000 0 0x28 registers MUA 118 TR0 Processor A Transmit Register 0 0 32 read-write 0 0xFFFFFFFF DATA TR0 0 32 read-write TR1 Processor A Transmit Register 1 0x4 32 read-write 0 0xFFFFFFFF DATA TR1 0 32 read-write TR2 Processor A Transmit Register 2 0x8 32 read-write 0 0xFFFFFFFF DATA TR2 0 32 read-write TR3 Processor A Transmit Register 3 0xC 32 read-write 0 0xFFFFFFFF DATA TR3 0 32 read-write RR0 Processor A Receive Register 0 0x10 32 read-only 0 0xFFFFFFFF DATA RR0 0 32 read-only RR1 Processor A Receive Register 1 0x14 32 read-only 0 0xFFFFFFFF DATA RR1 0 32 read-only RR2 Processor A Receive Register 2 0x18 32 read-only 0 0xFFFFFFFF DATA RR2 0 32 read-only RR3 Processor A Receive Register 3 0x1C 32 read-only 0 0xFFFFFFFF DATA RR3 0 32 read-only SR Processor A Status Register 0x20 32 read-write 0xF00080 0xFFFFFFFF Fn Fn 0 3 read-only zero BAFn bit in MUB.CR register is written 0 (default). 0 one BAFn bit in MUB.CR register is written 1. 0x1 EP EP 4 1 read-only not_pending The Processor A-side event is not pending (default). 0 pending The Processor A-side event is pending. 0x1 RS RS 7 1 read-only not_reset The Processor B-side of the MU is not in reset. 0 reset The Processor B-side of the MU is in reset. 0x1 FUP FUP 8 1 read-only no_update No flags updated, initiated by the Processor A, in progress (default) 0 update Processor A initiated flags update, processing 0x1 TEn TEn 20 4 read-only not_empty MUA.TRn register is not empty. 0 empty MUA.TRn register is empty (default). 0x1 RFn RFn 24 4 read-only not_full MUA.RRn register is not full (default). 0 full MUA.RRn register has received data from MUB.TRn register and is ready to be read by the Processor A. 0x1 GIPn GIPn 28 4 read-write oneToClear not_pending Processor A general purpose interrupt n is not pending. (default) 0 pending Processor A general purpose interrupt n is pending. 0x1 CR Processor A Control Register 0x24 32 read-write 0 0xFFFFFFFF Fn Fn 0 3 read-write not_appl N/A. Self clearing bit (default). 0 assert_reset Asserts the Processor A MU reset. 0x1 MUR MUR 5 1 read-write not_appl N/A. Self clearing bit (default). 0 assert_reset Asserts the Processor A MU reset. 0x1 GIRn GIRn 16 4 read-write not_requested Processor A General Interrupt n is not requested to the Processor B (default). 0 requested Processor A General Interrupt n is requested to the Processor B. 0x1 TIEn TIEn 20 4 read-write disable Disables Processor A Transmit Interrupt n. (default) 0 enable Enables Processor A Transmit Interrupt n. 0x1 RIEn RIEn 24 4 read-write disable Disables Processor A Receive Interrupt n. (default) 0 enable Enables Processor A Receive Interrupt n. 0x1 GIEn GIEn 28 4 read-write disable Disables Processor A General Interrupt n. (default) 0 enable Enables Processor A General Interrupt n. 0x1 RDC RDC RDC RDC_ 0x40C78000 0 0xBB0 registers RDC 92 VIR Version Information 0 32 read-only 0x3B800C2 0xFFFFFFFF NDID Number of Domains 0 4 read-only NMSTR Number of Masters 4 8 read-only NPER Number of Peripherals 12 8 read-only NRGN Number of Memory Regions 20 8 read-only STAT Status 0x24 32 read-write 0x100 0xFFFFFFFF DID Domain ID 0 4 read-write PDS Power Domain Status 8 1 read-write PDS_0 Power Down Domain is OFF 0 PDS_1 Power Down Domain is ON 0x1 INTCTRL Interrupt and Control 0x28 32 read-write 0 0xFFFFFFFF RCI_EN Restoration Complete Interrupt 0 1 read-write RCI_EN_0 Interrupt Disabled 0 RCI_EN_1 Interrupt Enabled 0x1 INTSTAT Interrupt Status 0x2C 32 read-write 0 0xFFFFFFFF oneToClear INT Interrupt Status 0 1 read-write oneToClear INT_0 No Interrupt Pending 0 INT_1 Interrupt Pending 0x1 12 0x4 0,1,2,3,4,5,6,7,8,9,10,11 MDA%s Master Domain Assignment 0x200 32 read-write 0 0xFFFFFFFF DID Domain ID 0 2 read-write DID_0 Master assigned to Processing Domain 0 0 DID_1 Master assigned to Processing Domain 1 0x1 LCK Assignment Lock 31 1 read-write LCK_0 Not Locked 0 LCK_1 Locked 0x1 128 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127 PDAP%s Peripheral Domain Access Permissions 0x400 32 read-write 0xF 0xFFFFFFFF D0W Domain 0 Write Access 0 1 read-write D0W_0 No Write Access 0 D0W_1 Write Access Allowed 0x1 D0R Domain 0 Read Access 1 1 read-write D0R_0 No Read Access 0 D0R_1 Read Access Allowed 0x1 D1W Domain 1 Write Access 2 1 read-write D1W_0 No Write Access 0 D1W_1 Write Access Allowed 0x1 D1R Domain 1 Read Access 3 1 read-write D1R_0 No Read Access 0 D1R_1 Read Access Allowed 0x1 SREQ Semaphore Required 30 1 read-write SREQ_0 Semaphores have no effect 0 SREQ_1 Semaphores are enforced 0x1 LCK Peripheral Permissions Lock 31 1 read-write LCK_0 Not Locked 0 LCK_1 Locked 0x1 59 0x10 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58 MRSA%s Memory Region Start Address 0x800 32 read-write 0 0 SADR Start address for memory region 7 25 read-write 59 0x10 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58 MREA%s Memory Region End Address 0x804 32 read-write 0 0 EADR Upper bound for memory region 7 25 read-write 59 0x10 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58 MRC%s Memory Region Control 0x808 32 read-write 0xFF 0xFFFFFFFF D0W Domain 0 Write Access to Region 0 1 read-write D0W_0 Processing Domain 0 does not have Write access to the memory region 0 D0W_1 Processing Domain 0 has Write access to the memory region 0x1 D0R Domain 0 Read Access to Region 1 1 read-write D0R_0 Processing Domain 0 does not have Read access to the memory region 0 D0R_1 Processing Domain 0 has Read access to the memory region 0x1 D1W Domain 1 Write Access to Region 2 1 read-write D1W_0 Processing Domain 1 does not have Write access to the memory region 0 D1W_1 Processing Domain 1 has Write access to the memory region 0x1 D1R Domain 1 Read Access to Region 3 1 read-write D1R_0 Processing Domain 1 does not have Read access to the memory region 0 D1R_1 Processing Domain 1 has Read access to the memory region 0x1 ENA Region Enable 30 1 read-write ENA_0 Memory region is not defined or restricted. 0 ENA_1 Memory boundaries, domain permissions and controls are in effect. 0x1 LCK Region Lock 31 1 read-write LCK_0 No Lock. All fields in this register may be modified. 0 LCK_1 Locked. No fields in this register may be modified except ENA, which may be set but not cleared. 0x1 59 0x10 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58 MRVS%s Memory Region Violation Status 0x80C 32 read-write 0 0xFFFFFFFF VDID Violating Domain ID 0 2 read-only VDID_0 Processing Domain 0 0 VDID_1 Processing Domain 1 0x1 AD Access Denied 4 1 read-write oneToClear VADR Violating Address 5 27 read-only KEY_MANAGER KEYMGR KEY_MANAGER 0x40C80000 0 0xC00 registers KEY_MANAGER 64 MASTER_KEY_CTRL CSR Master Key Control Register 0 32 read-write 0 0 modify SELECT Key select for SNVS OTPMK. Default value comes from FUSE_MASTER_KEY_SEL. 0 1 read-write modify SELECT_FROM_UDF select key from UDF 0 SELECT_FROM_PUF If LOCK = 1, select key from PUF, otherwise select key from fuse (bypass the fuse OTPMK to SNVS) 0x1 LOCK lock this register, prevent from writing. Default value comes from FUSE_MASTER_KEY_SEL_LOCK. 16 1 read-write modify UNLOCK not locked 0 LOCK locked 0x1 OTFAD1_KEY_CTRL CSR OTFAD-1 Key Control 0x10 32 read-write 0 0xFFFFFFFF modify SELECT key select for OTFAD-1. Default value comes from FUSE_OTFAD1_KEY_SEL. 0 1 read-write modify SELECT_FROM_USER_KEY5 Select key from OCOTP USER_KEY5 0 SELECT_FROM_PUF If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5 0x1 LOCK lock this register, prevent from writing. Default value comes from FUSE_OTFAD1_KEY_SEL_LOCK. 16 1 read-write modify UNLOCK not locked 0 LOCK locked 0x1 OTFAD2_KEY_CTRL CSR OTFAD-2 Key Control 0x18 32 read-write 0 0xFFFFFFFF modify SELECT key select for OTFAD-2. Default value comes from FUSE_OTFAD1_KEY_SEL. 0 1 read-write modify SELECT_FROM_USER_KEY5 select key from OCOTP USER_KEY5 0 SELECT_FROM_PUF If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5 0x1 LOCK lock this register, prevent from writing. Default value comes from FUSE_OTFAD2_KEY_SEL_LOCK. 16 1 read-write modify UNLOCK not locked 0 LOCK locked 0x1 IEE_KEY_CTRL CSR IEE Key Control 0x20 32 read-write 0 0xFFFFFFFF oneToSet RELOAD Restart load key signal for IEE 0 1 read-write oneToSet IDLE Do nothing 0 RESTART Restart IEE key load flow 0x1 PUF_KEY_CTRL CSR PUF Key Control 0x30 32 read-write 0 0xFFFFFFFF modify LOCK Lock signal for key select 0 1 read-write modify UNLOCK Do not lock the key select 0 LOCK Lock the key select to select key from PUF, otherwise bypass key from OCOPT and do not lock. Once it has been set to 1, it cannot be reset manually. It will be set to 0 when the IEE key reload operation is done. 0x1 SLOT0_CTRL Slot 0 Control 0x400 32 read-write 0xF 0xFFFFFFFF WHITE_LIST Whitelist 0 4 read-write modify LOCK_LIST Lock whitelist 15 1 read-write oneToSet UNLOCK Whitelist is not locked 0 LOCK Whitelist is locked 0x1 TZ_NS Allow non-secure write access to this register and the slot it controls 16 1 read-write modify PREVENT Do not allow non-secure write access 0 ALLOW Allow non-secure write access 0x1 TZ_USER Allow user write access to this register and the slot it controls 17 1 read-write modify PREVENT Do not allow user write access 0 ALLOW Allow user write access 0x1 LOCK_CONTROL Lock control of this slot 31 1 read-write modify UNLOCK Do not lock the control register of this slot 0 LOCK Lock the control register of this slot 0x1 SLOT1_CTRL Slot1 Control 0x404 32 read-write 0xF 0xFFFFFFFF WHITE_LIST Whitelist 0 4 read-write modify LOCK_LIST Lock whitelist 15 1 read-write oneToSet UNLOCK Whitelist is not locked 0 LOCK Whitelist is locked 0x1 TZ_NS Allow non-secure write access to this register and the slot it controls 16 1 read-write modify PREVENT Do not allow non-secure write access 0 ALLOW Allow non-secure write access 0x1 TZ_USER Allow user write access to this register and the slot it controls 17 1 read-write modify PREVENT Do not allow user write access 0 ALLOW Allow user write access 0x1 LOCK_CONTROL Lock control of this slot 31 1 read-write modify UNLOCK Do not lock the control register of this slot 0 LOCK Lock the control register of this slot 0x1 SLOT2_CTRL Slot2 Control 0x408 32 read-write 0xF 0xFFFFFFFF WHITE_LIST Whitelist 0 4 read-write modify LOCK_LIST Lock whitelist 15 1 read-write oneToSet UNLOCK Whitelist is not locked 0 LOCK Whitelist is locked 0x1 TZ_NS Allow non-secure write access to this register and the slot it controls 16 1 read-write modify PREVENT Do not allow non-secure write access 0 ALLOW Allow non-secure write access 0x1 TZ_USER Allow user write access to this register and the slot it controls 17 1 read-write modify PREVENT Do not allow user write access 0 ALLOW Allow user write access 0x1 LOCK_CONTROL Lock control of this slot 31 1 read-write modify UNLOCK Do not lock the control register of this slot 0 LOCK Lock the control register of this slot 0x1 SLOT3_CTRL Slot3 Control 0x40C 32 read-write 0xF 0xFFFFFFFF WHITE_LIST Whitelist 0 4 read-write modify LOCK_LIST Lock whitelist 15 1 read-write oneToSet UNLOCK Whitelist is not locked 0 LOCK Whitelist is locked 0x1 TZ_NS Allow non-secure write access to this register and the slot it controls 16 1 read-write modify PREVENT Do not allow non-secure write access 0 ALLOW Allow non-secure write access 0x1 TZ_USER Allow user write access to this register and the slot it controls 17 1 read-write modify PREVENT Do not allow user write access 0 ALLOW Allow user write access 0x1 LOCK_CONTROL Lock control of this slot 31 1 read-write modify UNLOCK Do not lock the control register of this slot 0 LOCK Lock the control register of this slot 0x1 SLOT4_CTRL Slot 4 Control 0x410 32 read-write 0xF 0xFFFFFFFF WHITE_LIST Whitelist 0 4 read-write modify LOCK_LIST Lock whitelist 15 1 read-write oneToSet UNLOCK Whitelist is not locked 0 LOCK Whitelist is locked 0x1 TZ_NS Allow non-secure write access to this register and the slot it controls 16 1 read-write modify PREVENT Do not allow non-secure write access 0 ALLOW Allow non-secure write access 0x1 TZ_USER Allow user write access to this register and the slot it controls 17 1 read-write modify PREVENT Do not allow user write access 0 ALLOW Allow user write access 0x1 LOCK_CONTROL Lock control of this slot 31 1 read-write modify UNLOCK Do not lock the control register of this slot 0 LOCK Lock the control register of this slot 0x1 KEY_MANAGER__PUF PUF PUF 0x40C82000 0 0x2000 registers CTRL PUF Control Register 0 32 read-write 0 0xFFFFFFFF modify ZEROIZE Begin Zeroize operation for PUF and go to Error state 0 1 read-write modify UNSET No Zeroize operation in progress 0 SET Zeroize operation in progress 0x1 ENROLL Begin Enroll operation 1 1 read-write modify UNSET No Enroll operation in progress 0 SET Enroll operation in progress 0x1 START Begin Start operation 2 1 read-write modify UNSET No Start operation in progress 0 SET Start operation in progress 0x1 GENERATEKEY Begin Set Intrinsic Key operation 3 1 read-write modify UNSET No Set Intrinsic Key operation in progress 0 SET Set Intrinsic Key operation in progress 0x1 SETKEY Begin Set User Key operation 4 1 read-write modify UNSET No Set Key operation in progress 0 SET Set Key operation in progress 0x1 GETKEY Begin Get Key operation 6 1 read-write modify UNSET No Get Key operation in progress 0 SET Get Key operation in progress 0x1 KEYINDEX PUF Key Index Register 0x4 32 read-write 0 0xFFFFFFFF modify KEYIDX PUF Key Index 0 4 read-write modify INDEX0 USE INDEX0 0 INDEX1 USE INDEX1 0x1 INDEX2 USE INDEX2 0x2 INDEX3 USE INDEX3 0x3 INDEX4 USE INDEX4 0x4 INDEX5 USE INDEX5 0x5 INDEX6 USE INDEX6 0x6 INDEX7 USE INDEX7 0x7 INDEX8 USE INDEX8 0x8 INDEX9 USE INDEX9 0x9 INDEX10 USE INDEX10 0xA INDEX11 USE INDEX11 0xB INDEX12 USE INDEX12 0xC INDEX13 USE INDEX13 0xD INDEX14 USE INDEX14 0xE INDEX15 USE INDEX15 0xF KEYSIZE PUF Key Size Register 0x8 32 read-write 0 0xFFFFFFFF modify KEYSIZE PUF Key Size 0 6 read-write modify SIZE64 Key Size is 512 Bytes and KC Size is 532 Bytes 0 SIZE1 Key Size is 8 Bytes and KC Size is 52 Bytes 0x1 SIZE2 Key Size is 16 Bytes and KC Size is 52 Bytes 0x2 SIZE3 Key Size is 24 Bytes and KC Size is 52 Bytes 0x3 SIZE4 Key Size is 32 Bytes and KC Size is 52 Bytes 0x4 SIZE5 Key Size is 40 Bytes and KC Size is 84 Bytes 0x5 SIZE6 Key Size is 48 Bytes and KC Size is 84 Bytes 0x6 SIZE7 Key Size is 56 Bytes and KC Size is 84 Bytes 0x7 SIZE8 Key Size is 64 Bytes and KC Size is 84 Bytes 0x8 SIZE9 Key Size is 72 Bytes and KC Size is 116 Bytes 0x9 SIZE10 Key Size is 80 Bytes and KC Size is 116 Bytes 0xA SIZE11 Key Size is 88 Bytes and KC Size is 116 Bytes 0xB SIZE12 Key Size is 96 Bytes and KC Size is 116 Bytes 0xC SIZE13 Key Size is 104 Bytes and KC Size is 148 Bytes 0xD SIZE14 Key Size is 112 Bytes and KC Size is 148 Bytes 0xE SIZE15 Key Size is 120 Bytes and KC Size is 148 Bytes 0xF SIZE16 Key Size is 128 Bytes and KC Size is 148 Bytes 0x10 SIZE17 Key Size is 136 Bytes and KC Size is 180 Bytes 0x11 SIZE18 Key Size is 144 Bytes and KC Size is 180 Bytes 0x12 SIZE19 Key Size is 152 Bytes and KC Size is 180 Bytes 0x13 SIZE20 Key Size is 160 Bytes and KC Size is 180 Bytes 0x14 SIZE21 Key Size is 168 Bytes and KC Size is 212 Bytes 0x15 SIZE22 Key Size is 176 Bytes and KC Size is 212 Bytes 0x16 SIZE23 Key Size is 184 Bytes and KC Size is 212 Bytes 0x17 SIZE24 Key Size is 192 Bytes and KC Size is 212 Bytes 0x18 SIZE25 Key Size is 200 Bytes and KC Size is 244 Bytes 0x19 SIZE26 Key Size is 208 Bytes and KC Size is 244 Bytes 0x1A SIZE27 Key Size is 216 Bytes and KC Size is 244 Bytes 0x1B SIZE28 Key Size is 224 Bytes and KC Size is 244 Bytes 0x1C SIZE29 Key Size is 232 Bytes and KC Size is 276 Bytes 0x1D SIZE30 Key Size is 240 Bytes and KC Size is 276 Bytes 0x1E SIZE31 Key Size is 248 Bytes and KC Size is 276 Bytes 0x1F SIZE32 Key Size is 256 Bytes and KC Size is 276 Bytes 0x20 SIZE33 Key Size is 264 Bytes and KC Size is 308 Bytes 0x21 SIZE34 Key Size is 272 Bytes and KC Size is 308 Bytes 0x22 SIZE35 Key Size is 280 Bytes and KC Size is 308 Bytes 0x23 SIZE36 Key Size is 288 Bytes and KC Size is 308 Bytes 0x24 SIZE37 Key Size is 296 Bytes and KC Size is 340 Bytes 0x25 SIZE38 Key Size is 304 Bytes and KC Size is 340 Bytes 0x26 SIZE39 Key Size is 312 Bytes and KC Size is 340 Bytes 0x27 SIZE40 Key Size is 320 Bytes and KC Size is 340 Bytes 0x28 SIZE41 Key Size is 328 Bytes and KC Size is 372 Bytes 0x29 SIZE42 Key Size is 336 Bytes and KC Size is 372 Bytes 0x2A SIZE43 Key Size is 344 Bytes and KC Size is 372 Bytes 0x2B SIZE44 Key Size is 352 Bytes and KC Size is 372 Bytes 0x2C SIZE45 Key Size is 360 Bytes and KC Size is 404 Bytes 0x2D SIZE46 Key Size is 368 Bytes and KC Size is 404 Bytes 0x2E SIZE47 Key Size is 376 Bytes and KC Size is 404 Bytes 0x2F SIZE48 Key Size is 384 Bytes and KC Size is 404 Bytes 0x30 SIZE49 Key Size is 392 Bytes and KC Size is 436 Bytes 0x31 SIZE50 Key Size is 400 Bytes and KC Size is 436 Bytes 0x32 SIZE51 Key Size is 408 Bytes and KC Size is 436 Bytes 0x33 SIZE52 Key Size is 416 Bytes and KC Size is 436 Bytes 0x34 SIZE53 Key Size is 424 Bytes and KC Size is 468 Bytes 0x35 SIZE54 Key Size is 432 Bytes and KC Size is 468 Bytes 0x36 SIZE55 Key Size is 440 Bytes and KC Size is 468 Bytes 0x37 SIZE56 Key Size is 448 Bytes and KC Size is 468 Bytes 0x38 SIZE57 Key Size is 456 Bytes and KC Size is 500 Bytes 0x39 SIZE58 Key Size is 464 Bytes and KC Size is 500 Bytes 0x3A SIZE59 Key Size is 472 Bytes and KC Size is 500 Bytes 0x3B SIZE60 Key Size is 480 Bytes and KC Size is 500 Bytes 0x3C SIZE61 Key Size is 488 Bytes and KC Size is 532 Bytes 0x3D SIZE62 Key Size is 496 Bytes and KC Size is 532 Bytes 0x3E SIZE63 Key Size is 504 Bytes and KC Size is 532 Bytes 0x3F STAT PUF Status Register 0x20 32 read-only 0x1 0xFFFFFFFF modify BUSY puf_busy 0 1 read-only modify IDLE IDLE 0 BUSY BUSY 0x1 SUCCESS puf_ok 1 1 read-only modify NO Last operation was unsuccessful 0 SUCCESSFUL Last operation was successful 0x1 ERROR puf_error 2 1 read-only modify NO_IN_ERROR PUF is not in the Error state 0 IN_ERROR PUF is in the Error state 0x1 KEYINREQ KI_ir 4 1 read-only modify NOREQUEST No request for next part of key 0 REQUEST Request for next part of key in KEYINPUT register 0x1 KEYOUTAVAIL KO_or 5 1 read-only modify NOAVAILABLE Next part of key is not available 0 AVAILABLE Next part of key is available in KEYOUTPUT register 0x1 CODEINREQ CI_ir 6 1 read-only modify NOREQUEST No request for next part of Activation Code/Key Code 0 REQUEST request for next part of Activation Code/Key Code in CODEINPUT register 0x1 CODEOUTAVAIL CO_or 7 1 read-only modify NOAVAILABLE Next part of Activation Code/Key Code is not available 0 AVAILABLE Next part of Activation Code/Key Code is available in CODEOUTPUT register 0x1 ALLOW PUF Allow Register 0x28 32 read-only 0 0xFFFFFFFF modify ALLOWENROLL Allow Enroll operation 0 1 read-only modify NOALLOW Specified operation is not currently allowed 0 ALLOW Specified operation is allowed 0x1 ALLOWSTART Allow Start operation 1 1 read-only modify NOALLOW Specified operation is not currently allowed 0 ALLOW Specified operation is allowed 0x1 ALLOWSETKEY Allow Set Key operations 2 1 read-only modify NOALLOW Specified operation is not currently allowed 0 ALLOW Specified operation is allowed 0x1 ALLOWGETKEY Allow Get Key operation 3 1 read-only modify NOALLOW Specified operation is not currently allowed 0 ALLOW Specified operation is allowed 0x1 KEYINPUT PUF Key Input Register 0x40 32 write-only 0 0xFFFFFFFF modify KEYIN Key input data 0 32 write-only modify CODEINPUT PUF Code Input Register 0x44 32 write-only 0 0xFFFFFFFF modify CODEIN AC/KC input data 0 32 write-only modify CODEOUTPUT PUF Code Output Register 0x48 32 read-only 0 0xFFFFFFFF modify CODEOUT AC/KC output data 0 32 read-only modify KEYOUTINDEX PUF Key Output Index Register 0x60 32 read-only 0 0xFFFFFFFF modify KEYOUTIDX Output Key index 0 32 read-only modify KEYOUTPUT PUF Key Output Register 0x64 32 read-only 0 0xFFFFFFFF modify KEYOUT Key output data from a Get Key operation 0 32 read-only modify IFSTAT PUF Interface Status Register 0xDC 32 read-write 0 0xFFFFFFFF oneToClear ERROR APB error has occurred 0 1 read-write oneToClear NOERROR NOERROR 0 ERROR ERROR 0x1 VERSION PUF Version Register 0xFC 32 read-only 0 0xFFFFFFFF modify VERSION Version of PUF 0 32 read-only modify INTEN PUF Interrupt Enable 0x100 32 read-write 0 0xFFFFFFFF modify READYEN PUF Ready Interrupt Enable 0 1 read-write modify DISABLE PUF ready interrupt disabled 0 ENABLE PUF ready interrupt enabled 0x1 SUCCESSEN PUF_OK Interrupt Enable 1 1 read-write modify DISABLE PUF successful interrupt disabled 0 ENABLE PUF successful interrupt enabled 0x1 ERROREN PUF Error Interrupt Enable 2 1 read-write modify DISABLE PUF error interrupt disabled 0 ENABLE PUF error interrupt enabled 0x1 KEYINREQEN PUF Key Input Register Interrupt Enable 4 1 read-write modify DISABLE Key interrupt request disabled 0 ENABLE Key interrupt request enabled 0x1 KEYOUTAVAILEN PUF Key Output Register Interrupt Enable 5 1 read-write modify DISABLE Key available interrupt disabled 0 ENABLE Key available interrupt enabled 0x1 CODEINREQEN PUF Code Input Register Interrupt Enable 6 1 read-write modify DISABLE AC/KC interrupt request disabled 0 ENABLE AC/KC interrupt request enabled 0x1 CODEOUTAVAILEN PUF Code Output Register Interrupt Enable 7 1 read-write modify DISABLE AC/KC available interrupt disabled 0 ENABLE AC/KC available interrupt enabled 0x1 INTSTAT PUF Interrupt Status 0x104 32 read-write 0 0xFFFFFFFF READY PUF_FINISH Interrupt Status 0 1 read-write oneToClear NOT_FINISHED Indicates that last operation not finished 0 FINISHED Indicates that last operation is finished 0x1 SUCCESS PUF_OK Interrupt Status 1 1 read-only modify UNSUCCESSFUL Indicates that last operation was not successful 0 SUCCESSFUL Indicates that last operation was successful 0x1 ERROR PUF_ERROR Interrupt Status 2 1 read-only modify NO_ERROR PUF is not in the Error state and operations can be performed 0 ERROR PUF is in the Error state and no operations can be performed 0x1 KEYINREQ PUF Key Input Register Interrupt Status 4 1 read-only modify NO_REQUEST No request for next part of key 0 REQUEST Request for next part of key 0x1 KEYOUTAVAIL PUF Key Output Register Interrupt Status 5 1 read-only modify NOT_AVAILABLE Next part of key is not available 0 AVAILABLE Next part of key is available 0x1 CODEINREQ PUF Code Input Register Interrupt Status 6 1 read-only modify NO_REQUEST No request for next part of AC/KC 0 REQUEST Request for next part of AC/KC 0x1 CODEOUTAVAIL PUF Code Output Register Interrupt Status 7 1 read-only modify NOT_AVAILABLE Next part of AC/KC is not available 0 AVAILABLE Next part of AC/KC is available 0x1 PWRCTRL PUF Power Control Of RAM 0x108 32 read-write 0x1 0xFFFFFFFF modify RAM_ON PUF RAM on 0 1 read-write modify SLEEP PUF RAM is in sleep mode (PUF operation disabled) 0 WAKE PUF RAM is awake (normal PUF operation enabled) 0x1 CK_DIS Clock disable 2 1 read-write modify ENABLE PUF RAM is clocked (normal PUF operation enabled) 0 DISABLE PUF RAM clock is gated/disabled (PUF operation disabled) 0x1 RAM_INITN RAM initialization 3 1 read-write modify RESET Reset the PUF RAM (PUF operation disabled) 0 DO_NOT_RESET Do not reset the PUF RAM (normal PUF operation enabled) 0x1 RAM_PSW PUF RAM power switches 4 4 read-write modify CFG PUF Configuration Register 0x10C 32 read-writeOnce 0 0xFFFFFFFF modify PUF_BLOCK_SET_KEY PUF Block Set Key Disable 0 1 read-writeOnce modify ENABLE Enable the Set Key state 0 DISABLE Disable the Set Key state 0x1 PUF_BLOCK_ENROLL PUF Block Enroll Disable 1 1 read-writeOnce modify ENABLE Enable the Enrollment state 0 DISABLE Disable the Enrollment state 0x1 KEYLOCK PUF Key Manager Lock 0x200 32 read-writeOnce 0xA 0xFFFFFFFF modify LOCK0 Lock Block 0 0 2 read-writeOnce modify LOCKED_00 SNVS Key block locked 0 LOCKED_01 SNVS Key block locked 0x1 UNLOCKED SNVS Key block unlocked 0x2 LOCKED_11 SNVS Key block locked 0x3 LOCK1 Lock Block 1 2 2 read-writeOnce modify LOCKED_00 OTFAD Key block locked 0 LOCKED_01 OTFAD Key block locked 0x1 UNLOCKED OTFAD Key block unlocked 0x2 LOCKED_11 OTFAD Key block locked 0x3 KEYENABLE PUF Key Manager Enable 0x204 32 read-write 0x5 0xFFFFFFFF modify ENABLE0 Enable Block 0 0 2 read-write modify DISABLED_00 Key block 0 disabled 0 DISABLED_01 Key block 0 disabled 0x1 ENABLED Key block 0 enabled 0x2 DISABLED_11 Key block 0 disabled 0x3 ENABLE1 Enable Block 1 2 2 read-write modify DISABLED_00 Key block 1 disabled 0 DISABLED_01 Key block 1 disabled 0x1 ENABLED Key block 1 enabled 0x2 DISABLED_11 Key block 1 disabled 0x3 KEYRESET PUF Key Manager Reset 0x208 32 read-write 0 0xFFFFFFFF modify RESET0 Reset Block 0 0 2 read-write modify NORESET_00 Do not reset key block 0 0 NORESET_01 Do not reset key block 0 0x1 RESET Reset key block 0 0x2 NORESET_11 Do not reset key block 0 0x3 RESET1 Reset Block 1 2 2 read-write modify NORESET_00 Do not reset key block 1 0 NORESET_01 Do not reset key block 1 0x1 RESET Reset key block 1 0x2 NORESET_11 Do not reset key block 1 0x3 IDXBLK PUF Index Block Key Output 0x20C 32 read-write 0xAAAAAAAA 0xFFFFFFFF modify IDXBLK0 idxblk0 0 2 read-write modify IDXBLK1 idxblk1 2 2 read-write modify IDXBLK2 idxblk2 4 2 read-write modify IDXBLK3 idxblk3 6 2 read-write modify IDXBLK4 idxblk4 8 2 read-write modify IDXBLK5 idxblk5 10 2 read-write modify IDXBLK6 idxblk6 12 2 read-write modify IDXBLK7 idxblk7 14 2 read-write modify IDXBLK8 idxblk8 16 2 read-write modify IDXBLK9 idxblk9 18 2 read-write modify IDXBLK10 idxblk10 20 2 read-write modify IDXBLK11 idxblk11 22 2 read-write modify IDXBLK12 idxblk12 24 2 read-write modify IDXBLK13 idxblk13 26 2 read-write modify IDXBLK14 idxblk14 28 2 read-write modify IDXBLK15 idxblk15 30 2 read-write modify IDXBLK_DP PUF Index Block Key Output 0x210 32 read-write 0xAAAAAAAA 0xFFFFFFFF modify IDXBLK_DP0 idxblk_dp0 0 2 read-write modify IDXBLK_DP1 idxblk_dp1 2 2 read-write modify IDXBLK_DP2 idxblk_dp2 4 2 read-write modify IDXBLK_DP3 idxblk_dp3 6 2 read-write modify IDXBLK_DP4 idxblk_dp4 8 2 read-write modify IDXBLK_DP5 idxblk_dp5 10 2 read-write modify IDXBLK_DP6 idxblk_dp6 12 2 read-write modify IDXBLK_DP7 idxblk_dp7 14 2 read-write modify IDXBLK_DP8 idxblk_dp8 16 2 read-write modify IDXBLK_DP9 idxblk_dp9 18 2 read-write modify IDXBLK_DP10 idxblk_dp10 20 2 read-write modify IDXBLK_DP11 idxblk_dp11 22 2 read-write modify IDXBLK_DP12 idxblk_dp12 24 2 read-write modify IDXBLK_DP13 idxblk_dp13 26 2 read-write modify IDXBLK_DP14 idxblk_dp14 28 2 read-write modify IDXBLK_DP15 idxblk_dp15 30 2 read-write modify KEYMASK0 PUF Key Block 0 Mask Enable 0x214 32 read-write 0 0xFFFFFFFF modify KEYMASK KEYMASK0 0 32 read-write modify KEYMASK1 PUF Key Block 1 Mask Enable 0x218 32 read-write 0 0xFFFFFFFF modify KEYMASK KEYMASK1 0 32 read-write modify IDXBLK_STATUS PUF Index Block Setting Status Register 0x254 32 read-only 0xAAAAAAAA 0xFFFFFFFF modify IDXBLK_STATUS0 idxblk_status0 0 2 read-only modify IDXBLK_STATUS1 idxblk_status1 2 2 read-only modify IDXBLK_STATUS2 idxblk_status2 4 2 read-only modify IDXBLK_STATUS3 idxblk_status3 6 2 read-only modify IDXBLK_STATUS4 idxblk_status4 8 2 read-only modify IDXBLK_STATUS5 idxblk_status5 10 2 read-only modify IDXBLK_STATUS6 idxblk_status6 12 2 read-only modify IDXBLK_STATUS7 idxblk_status7 14 2 read-only modify IDXBLK_STATUS8 idxblk_status8 16 2 read-only modify IDXBLK_STATUS9 idxblk_status9 18 2 read-only modify IDXBLK_STATUS10 idxblk_status10 20 2 read-only modify IDXBLK_STATUS11 idxblk_status11 22 2 read-only modify IDXBLK_STATUS12 idxblk_status12 24 2 read-only modify IDXBLK_STATUS13 idxblk_status13 26 2 read-only modify IDXBLK_STATUS14 idxblk_status14 28 2 read-only modify IDXBLK_STATUS15 idxblk_status15 30 2 read-only modify IDXBLK_SHIFT PUF Key Manager Shift Status 0x258 32 read-only 0 0xFFFFFFFF modify IND_KEY0 Index of key space in block 0 0 4 read-only modify IND_KEY1 Index of key space in block 1 4 4 read-only modify ANADIG_LDO_SNVS MX6RT_ANADIG_REGISTER ANADIG 0x40C84000 0 0x534 registers PMU_LDO_LPSR_ANA PMU_LDO_LPSR_ANA_REGISTER 0x510 32 read-write 0x108 0xFFFFFFFF REG_LP_EN reg_lp_en 0 1 read-write REG_DISABLE reg_disable 2 1 read-write PULL_DOWN_2MA_EN pull_down_2ma_en 3 1 read-write LPSR_ANA_CONTROL_MODE LPSR_ANA_CONTROL_MODE 4 1 read-write sw SW Control 0 hw HW Control 0x1 BYPASS_MODE_EN bypass_mode_en 5 1 read-write STANDBY_EN standby_en 6 1 read-write ALWAYS_4MA_PULLDOWN_EN always_4ma_pulldown_en 8 1 read-write TRACK_MODE_EN Track Mode Enable 19 1 read-write NORMAL Normal use 0 SWITCH Switch preparation 0x1 PULL_DOWN_20UA_EN pull_down_20ua_en 20 1 read-write PMU_LDO_LPSR_DIG_2 PMU_LDO_LPSR_DIG_2_REGISTER 0x520 32 read-write 0x2 0xFFFFFFFF VOLTAGE_STEP_INC voltage_step_inc 0 2 read-write PMU_LDO_LPSR_DIG PMU_LDO_LPSR_DIG_REGISTER 0x530 32 read-write 0x1301C05 0xFFFFFFFF REG_EN ENABLE_ILIMIT 2 1 read-write LPSR_DIG_CONTROL_MODE LPSR_DIG_CONTROL_MODE 5 1 read-write sw SW Control 0 hw HW Control 0x1 STANDBY_EN standby_en 6 1 read-write TRACKING_MODE tracking_mode 17 1 read-write BYPASS_MODE bypass_mode 18 1 read-write VOLTAGE_SELECT VOLTAGE_SELECT 20 5 read-write bitval0 Stable Voltage (range) 0 bitval1 Stable Voltage (range) 0x1 bitval2 Stable Voltage (range) 0x2 bitval3 Stable Voltage (range) 0x3 bitval4 Stable Voltage (range) 0x4 bitval5 Stable Voltage (range) 0x5 bitval6 Stable Voltage (range) 0x6 bitval7 Stable Voltage (range) 0x7 bitval8 Stable Voltage (range) 0x8 bitval9 Stable Voltage (range) 0x9 bitval10 Stable Voltage (range) 0xA bitval11 Stable Voltage (range) 0xB bitval12 Stable Voltage (range) 0xC bitval13 Stable Voltage (range) 0xD bitval14 Stable Voltage (range) 0xE bitval15 Stable Voltage (range) 0xF bitval16 Stable Voltage (range) 0x10 bitval17 Stable Voltage (range) 0x11 bitval18 Stable Voltage (range) 0x12 bitval19 Stable Voltage (range) 0x13 bitval20 Stable Voltage (range) 0x14 bitval21 Stable Voltage (range) 0x15 bitval22 Stable Voltage (range) 0x16 bitval23 Stable Voltage (range) 0x17 bitval24 Stable Voltage (range) 0x18 bitval25 Stable Voltage (range) 0x19 bitval26 Stable Voltage (range) 0x1A bitval27 Stable Voltage (range) 0x1B bitval28 Stable Voltage (range) 0x1C bitval29 Stable Voltage (range) 0x1D bitval30 Stable Voltage (range) 0x1E bitval31 Stable Voltage (range) 0x1F ANADIG_LDO_SNVS_DIG MX6RT_ANADIG_REGISTER ANADIG_LDO_SNVS ANADIG 0x40C84000 0 0x544 registers PMU_LDO_SNVS_DIG PMU_LDO_SNVS_DIG_REGISTER 0x540 32 read-write 0x1 0xFFFFFFFF REG_LP_EN REG_LP_EN 0 1 read-write TEST_OVERRIDE test_override 1 1 read-write REG_EN REG_EN 2 1 read-write ANADIG_MISC MX6RT_ANADIG_REGISTER ANADIG_LDO_SNVS ANADIG 0x40C84000 0 0x944 registers MISC_DIFPROG Chip Silicon Version Register 0x800 32 read-only 0x1170B0 0xFFFFFFFF CHIPID Chip ID 0 32 read-only VDDSOC_AI_CTRL VDDSOC_AI_CTRL_REGISTER 0x820 32 read-write 0 0xFFFFFFFF VDDSOC_AI_ADDR VDDSOC_AI_ADDR 0 8 read-write VDDSOC_AIRWB VDDSOC_AIRWB 16 1 read-write VDDSOC_AI_WDATA VDDSOC_AI_WDATA_REGISTER 0x830 32 read-write 0 0xFFFFFFFF VDDSOC_AI_WDATA VDDSOC_AI_WDATA 0 32 read-write VDDSOC_AI_RDATA VDDSOC_AI_RDATA_REGISTER 0x840 32 read-only 0 0xFFFFFFFF VDDSOC_AI_RDATA VDDSOC_AI_RDATA 0 32 read-only VDDSOC2PLL_AI_CTRL_1G VDDSOC2PLL_AI_CTRL_1G_REGISTER 0x850 32 read-write 0 0xFFFFFFFF VDDSOC2PLL_AIADDR_1G VDDSOC2PLL_AIADDR_1G 0 8 read-write VDDSOC2PLL_AITOGGLE_1G VDDSOC2PLL_AITOGGLE_1G 8 1 read-write VDDSOC2PLL_AITOGGLE_DONE_1G VDDSOC2PLL_AITOGGLE_DONE_1G 9 1 read-only VDDSOC2PLL_AIRWB_1G VDDSOC2PLL_AIRWB_1G 16 1 read-write VDDSOC2PLL_AI_WDATA_1G VDDSOC2PLL_AI_WDATA_1G_REGISTER 0x860 32 read-write 0 0xFFFFFFFF VDDSOC2PLL_AI_WDATA_1G VDDSOC2PLL_AI_WDATA_1G 0 32 read-write VDDSOC2PLL_AI_RDATA_1G VDDSOC2PLL_AI_RDATA_1G_REGISTER 0x870 32 read-only 0 0xFFFFFFFF VDDSOC2PLL_AI_RDATA_1G VDDSOC2PLL_AI_RDATA_1G 0 32 read-only VDDSOC2PLL_AI_CTRL_AUDIO VDDSOC_AI_CTRL_AUDIO_REGISTER 0x880 32 read-write 0 0xFFFFFFFF VDDSOC2PLL_AI_ADDR_AUDIO VDDSOC2PLL_AI_ADDR_AUDIO 0 8 read-write VDDSOC2PLL_AITOGGLE_AUDIO VDDSOC2PLL_AITOGGLE_AUDIO 8 1 read-write VDDSOC2PLL_AITOGGLE_DONE_AUDIO VDDSOC2PLL_AITOGGLE_DONE_AUDIO 9 1 read-only VDDSOC2PLL_AIRWB_AUDIO VDDSOC_AIRWB 16 1 read-write VDDSOC2PLL_AI_WDATA_AUDIO VDDSOC_AI_WDATA_AUDIO_REGISTER 0x890 32 read-write 0 0xFFFFFFFF VDDSOC2PLL_AI_WDATA_AUDIO VDDSOC2PLL_AI_WDATA_AUDIO 0 32 read-write VDDSOC2PLL_AI_RDATA_AUDIO VDDSOC2PLL_AI_RDATA_REGISTER 0x8A0 32 read-only 0 0xFFFFFFFF VDDSOC2PLL_AI_RDATA_AUDIO VDDSOC2PLL_AI_RDATA_AUDIO 0 32 read-only VDDSOC2PLL_AI_CTRL_VIDEO VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER 0x8B0 32 read-write 0 0xFFFFFFFF VDDSOC2PLL_AIADDR_VIDEO VDDSOC2PLL_AIADDR_VIDEO 0 8 read-write VDDSOC2PLL_AITOGGLE_VIDEO VDDSOC2PLL_AITOGGLE_VIDEO 8 1 read-write VDDSOC2PLL_AITOGGLE_DONE_VIDEO VDDSOC2PLL_AITOGGLE_DONE_VIDEO 9 1 read-only VDDSOC2PLL_AIRWB_VIDEO VDDSOC2PLL_AIRWB_VIDEO 16 1 read-write VDDSOC2PLL_AI_WDATA_VIDEO VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER 0x8C0 32 read-write 0 0xFFFFFFFF VDDSOC2PLL_AI_WDATA_VIDEO VDDSOC2PLL_AI_WDATA_VIDEO 0 32 read-write VDDSOC2PLL_AI_RDATA_VIDEO VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER 0x8D0 32 read-only 0 0xFFFFFFFF VDDSOC2PLL_AI_RDATA_VIDEO VDDSOC2PLL_AI_RDATA_VIDEO 0 32 read-only VDDLPSR_AI_CTRL VDDSOC_AI_CTRL_REGISTER 0x8E0 32 read-write 0 0xFFFFFFFF VDDLPSR_AI_ADDR VDDLPSR_AI_ADDR 0 8 read-write VDDLPSR_AIRWB VDDLPSR_AIRWB 16 1 read-write VDDLPSR_AI_WDATA VDDLPSR_AI_WDATA_REGISTER 0x8F0 32 read-write 0 0xFFFFFFFF VDDLPSR_AI_WDATA VDD_LPSR_AI_WDATA 0 32 read-write VDDLPSR_AI_RDATA_REFTOP VDDLPSR_AI_RDATA_REFTOP_REGISTER 0x900 32 read-only 0 0xFFFFFFFF VDDLPSR_AI_RDATA_REFTOP VDDLPSR_AI_RDATA_REFTOP 0 32 read-only VDDLPSR_AI_RDATA_TMPSNS VDDLPSR_AI_RDATA_TMPSNS_REGISTER 0x910 32 read-only 0 0xFFFFFFFF VDDLPSR_AI_RDATA_TMPSNS VDDLPSR_AI_RDATA_TMPSNS 0 32 read-only VDDLPSR_AI400M_CTRL VDDLPSR_AI400M_CTRL_REGISTER 0x920 32 read-write 0 0xFFFFFFFF VDDLPSR_AI400M_ADDR VDDLPSR_AI400M_ADDR 0 8 read-write VDDLPSR_AITOGGLE_400M VDDLPSR_AITOGGLE_400M 8 1 read-write VDDLPSR_AITOGGLE_DONE_400M VDDLPSR_AITOGGLE_DONE_400M 9 1 read-only VDDLPSR_AI400M_RWB VDDLPSR_AI400M_RWB 16 1 read-write VDDLPSR_AI400M_WDATA VDDLPSR_AI400M_WDATA_REGISTER 0x930 32 read-write 0 0xFFFFFFFF VDDLPSR_AI400M_WDATA VDDLPSR_AI400M_WDATA 0 32 read-write VDDLPSR_AI400M_RDATA VDDLPSR_AI400M_RDATA_REGISTER 0x940 32 read-only 0 0xFFFFFFFF VDDLPSR_AI400M_RDATA VDDLPSR_AI400M_RDATA 0 32 read-only ANADIG_OSC MX6RT_ANADIG_REGISTER ANADIG_LDO_SNVS ANADIG 0x40C84000 0 0xC4 registers OSC_48M_CTRL 48MHz RCOSC Control Register 0x10 32 read-write 0x17901F2 0xFFFFFFFF TEN 48MHz RCOSC Enable 1 1 read-write PD Power down 0 PU Power up 0x1 RC_48M_DIV2_EN RCOSC_48M_DIV2 Enable 24 1 read-write PD Disable 0 PU Enable 0x1 RC_48M_DIV2_CONTROL_MODE RCOSC_48M_DIV2 Control Mode 30 1 read-write SW Software mode (default) 0 GPC GPC mode (Setpoint) 0x1 RC_48M_CONTROL_MODE 48MHz RCOSC Control Mode 31 1 read-write SW Software mode (default) 0 GPC GPC mode (Setpoint) 0x1 OSC_24M_CTRL 24MHz OSC Control Register 0x20 32 read-write 0x80 0xFFFFFFFF BYPASS_CLK 24MHz OSC Bypass Clock 0 1 read-write BYPASS_EN 24MHz OSC Bypass Enable 1 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 LP_EN 24MHz OSC Low-Power Mode Enable 2 1 read-write HP High Gain mode (HP) 0 LP Low-power mode (LP) 0x1 OSC_COMP_MODE 24MHz OSC Comparator Mode 3 1 read-write SINGLE Single-ended mode (default) 0 DIFF Differential mode (test mode) 0x1 OSC_EN 24MHz OSC Enable 4 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 OSC_24M_GATE 24MHz OSC Gate Control 7 1 read-write NG Not Gated 0 GATE Gated 0x1 OSC_24M_STABLE 24MHz OSC Stable 30 1 read-only NS Not Stable 0 STABLE Stable 0x1 OSC_24M_CONTROL_MODE 24MHz OSC Control Mode 31 1 read-write SW Software mode (default) 0 GPC GPC mode (Setpoint) 0x1 OSC_400M_CTRL0 400MHz RCOSC Control0 Register 0x40 32 read-write 0 0xFFFFFFFF OSC400M_AI_BUSY 400MHz OSC AI BUSY 31 1 read-only OSC_400M_CTRL1 400MHz RCOSC Control1 Register 0x50 32 read-write 0x1 0xFFFFFFFF PWD Power down control for 400MHz RCOSC 0 1 read-write PD No Power down 0 PU Power down 0x1 CLKGATE_400MEG Clock gate control for 400MHz RCOSC 1 1 read-write NG Not Gated 0 GATE Gated 0x1 RC_400M_CONTROL_MODE 400MHz RCOSC Control mode 31 1 read-write SW Software mode (default) 0 GPC GPC mode (Setpoint) 0x1 OSC_400M_CTRL2 400MHz RCOSC Control2 Register 0x60 32 read-write 0 0xFFFFFFFF ENABLE_CLK Clock enable 0 1 read-write DISABLE Clock is disabled before entering GPC mode 0 ENABLE Clock is enabled before entering GPC mode 0x1 TUNE_BYP Bypass tuning logic 10 1 read-write RUN Use the output of tuning logic to run the oscillator 0 BYPASS Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator 0x1 OSC_TUNE_VAL Oscillator Tune Value 24 8 read-write OSC_16M_CTRL 16MHz RCOSC Control Register 0xC0 32 read-write 0x7 0xFFFFFFFF EN_IRC4M16M Enable Clock Output 1 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 EN_POWER_SAVE Power Save Enable 3 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 SOURCE_SEL_16M Source select 8 1 read-write Mhz_16 16MHz Oscillator 0 Mhz_24 24MHz Oscillator 0x1 RC_16M_CONTROL_MODE Control Mode for 16MHz Oscillator 31 1 read-write SW Software mode (default) 0 GPC GPC mode (Setpoint) 0x1 ANADIG_PLL MX6RT_ANADIG_REGISTER ANADIG_LDO_SNVS ANADIG 0x40C84000 0 0x394 registers ARM_PLL_CTRL ARM_PLL_CTRL_REGISTER 0x200 32 read-write 0x400000A6 0xFFFFFFFF DIV_SELECT DIV_SELECT 0 8 read-write HOLD_RING_OFF PLL Start up initialization 12 1 read-write NORMAL Normal operation 0 ENABLE Initialize PLL start up 0x1 POWERUP Powers up the PLL. 13 1 read-write PDOWN Power down the PLL 0 PUP Power Up the PLL 0x1 ENABLE_CLK Enable the clock output. 14 1 read-write DISABLE Disable the clock 0 ENABLE Enable the clock 0x1 POST_DIV_SEL POST_DIV_SEL 15 2 read-write DIV2 Divide by 2 0 DIV4 Divide by 4 0x1 DIV8 Divide by 8 0x2 DIV1 Divide by 1 0x3 BYPASS Bypass the pll. 17 1 read-write FUNC Function mode 0 BYPASS Bypass Mode 0x1 ARM_PLL_STABLE ARM_PLL_STABLE 29 1 read-only DISABLE ARM PLL is not stable 0 ENABLE ARM PLL is stable 0x1 ARM_PLL_GATE ARM_PLL_GATE 30 1 read-write DISABLE Clock is not gated 0 ENABLE Clock is gated 0x1 ARM_PLL_CONTROL_MODE pll_arm_control_mode 31 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 SYS_PLL3_CTRL SYS_PLL3_CTRL_REGISTER 0x210 32 read-write 0x40000003 0xFFFFFFFF SYS_PLL3_DIV2 SYS PLL3 DIV2 gate 3 1 read-write PLL_REG_EN Enable Internal PLL Regulator 4 1 read-write HOLD_RING_OFF PLL Start up initialization 11 1 read-write NORMAL Normal operation 0 ENABLE Initialize PLL start up 0x1 ENABLE_CLK Enable the clock output. 13 1 read-write DISABLE Disable the clock 0 ENABLE Enable the clock 0x1 BYPASS BYPASS 16 1 read-write FUNC Function mode 0 BYPASS Bypass Mode 0x1 POWERUP Powers up the PLL. 21 1 read-write PDOWN Power down the PLL 0 PUP Power Up the PLL 0x1 SYS_PLL3_DIV2_CONTROL_MODE SYS_PLL3_DIV2_CONTROL_MODE 28 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 SYS_PLL3_STABLE SYS_PLL3_STABLE 29 1 read-only SYS_PLL3_GATE SYS_PLL3_GATE 30 1 read-write DISABLE Clock is not gated 0 ENABLE Clock is gated 0x1 SYS_PLL3_CONTROL_MODE SYS_PLL3_control_mode 31 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 SYS_PLL3_UPDATE SYS_PLL3_UPDATE_REGISTER 0x220 32 read-write 0 0xFFFFFFFF PFD0_UPDATE PFD0_OVERRIDE 1 1 read-write PFD1_UPDATE PFD1_OVERRIDE 2 1 read-write PFD2_UPDATE PFD2_OVERRIDE 3 1 read-write PFD3_UPDATE PFD3_UPDATE 4 1 read-write PFD0_CONTROL_MODE pfd0_control_mode 5 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 PFD1_CONTROL_MODE pfd1_control_mode 6 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 PDF2_CONTROL_MODE pdf2_control_mode 7 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 PFD3_CONTROL_MODE pfd3_control_mode 8 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 SYS_PLL3_PFD SYS_PLL3_PFD_REGISTER 0x230 32 read-write 0x8CA0918D 0xFFFFFFFF PFD0_FRAC PFD0_FRAC 0 6 read-write PFD0_STABLE PFD0_STABLE 6 1 read-only PFD0_DIV1_CLKGATE PFD0_DIV1_CLKGATE 7 1 read-write ON ref_pfd0 fractional divider clock is enabled 0 OFF Fractional divider clock (reference ref_pfd0) is off (power savings 0x1 PFD1_FRAC PFD1_FRAC 8 6 read-write PFD1_STABLE PFD1_STABLE 14 1 read-only PFD1_DIV1_CLKGATE PFD1_DIV1_CLKGATE 15 1 read-write ON ref_pfd1 fractional divider clock is enabled 0 OFF Fractional divider clock (reference ref_pfd1) is off (power savings) 0x1 PFD2_FRAC PFD2_FRAC 16 6 read-write PFD2_STABLE PFD2_STABLE 22 1 read-only PFD2_DIV1_CLKGATE PFD2_DIV1_CLKGATE 23 1 read-write ON ref_pfd2 fractional divider clock is enabled 0 OFF Fractional divider clock (reference ref_pfd2) is off (power savings) 0x1 PFD3_FRAC PFD3_FRAC 24 6 read-write PFD3_STABLE PFD3_STABLE 30 1 read-only PFD3_DIV1_CLKGATE PFD3_DIV1_CLKGATE 31 1 read-write ON ref_pfd3 fractional divider clock is enabled 0 OFF Fractional divider clock (reference ref_pfd3) is off (power savings) 0x1 SYS_PLL2_CTRL SYS_PLL2_CTRL_REGISTER 0x240 32 read-write 0x40000000 0xFFFFFFFF PLL_REG_EN Enable Internal PLL Regulator 3 1 read-write HOLD_RING_OFF PLL Start up initialization 11 1 read-write NORMAL Normal operation 0 ENABLE Initialize PLL start up 0x1 ENABLE_CLK Enable the clock output. 13 1 read-write DISABLE Disable the clock 0 ENABLE Enable the clock 0x1 BYPASS Bypass the pll. 16 1 read-write FUNC Function mode 0 BYPASS Bypass Mode 0x1 DITHER_ENABLE DITHER_ENABLE 17 1 read-write DISABLE Disable Dither 0 ENABLE Enable Dither 0x1 PFD_OFFSET_EN PFD_OFFSET_EN 18 1 read-write PLL_DDR_OVERRIDE PLL_DDR_OVERRIDE 19 1 read-write POWERUP Powers up the PLL. 23 1 read-write PDOWN Power down the PLL 0 PUP Power Up the PLL 0x1 SYS_PLL2_STABLE SYS_PLL2_STABLE 29 1 read-only SYS_PLL2_GATE SYS_PLL2_GATE 30 1 read-write DISABLE Clock is not gated 0 ENABLE Clock is gated 0x1 SYS_PLL2_CONTROL_MODE SYS_PLL2_control_mode 31 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 SYS_PLL2_UPDATE SYS_PLL2_UPDATE_REGISTER 0x250 32 read-write 0 0xFFFFFFFF PFD0_UPDATE PFD0_UPDATE 1 1 read-write PFD1_UPDATE PFD1_UPDATE 2 1 read-write PFD2_UPDATE PFD2_UPDATE 3 1 read-write PFD3_UPDATE PFD3_UPDATE 4 1 read-write PFD0_CONTROL_MODE pfd0_control_mode 5 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 PFD1_CONTROL_MODE pfd1_control_mode 6 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 PFD2_CONTROL_MODE pfd2_control_mode 7 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 PFD3_CONTROL_MODE pfd3_control_mode 8 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 SYS_PLL2_SS SYS_PLL2_SS_REGISTER 0x260 32 read-write 0 0xFFFFFFFF STEP STEP 0 15 read-write ENABLE ENABLE 15 1 read-write DISABLE Disable Spread Spectrum 0 ENABLE Enable Spread Spectrum 0x1 STOP STOP 16 16 read-write SYS_PLL2_PFD SYS_PLL2_PFD_REGISTER 0x270 32 read-write 0xA098909B 0xFFFFFFFF PFD0_FRAC PFD0_FRAC 0 6 read-write PFD0_STABLE PFD0_STABLE 6 1 read-only PFD0_DIV1_CLKGATE PFD0_DIV1_CLKGATE 7 1 read-write PFD1_FRAC PFD1_FRAC 8 6 read-write PFD1_STABLE PFD1_STABLE 14 1 read-only PFD1_DIV1_CLKGATE PFD1_DIV1_CLKGATE 15 1 read-write PFD2_FRAC PFD2_FRAC 16 6 read-write PFD2_STABLE PFD2_STABLE 22 1 read-only PFD2_DIV1_CLKGATE PFD2_DIV1_CLKGATE 23 1 read-write PFD3_FRAC PFD3_FRAC 24 6 read-write PFD3_STABLE PFD3_STABLE 30 1 read-only PFD3_DIV1_CLKGATE PFD3_DIV1_CLKGATE 31 1 read-write SYS_PLL2_MFD SYS_PLL2_MFD_REGISTER 0x2A0 32 read-write 0xFFFFFFF 0xFFFFFFFF MFD Denominator 0 30 read-write SYS_PLL1_SS SYS_PLL1_SS_REGISTER 0x2B0 32 read-write 0 0xFFFFFFFF STEP STEP 0 15 read-write ENABLE ENABLE 15 1 read-write DISABLE Disable Spread Spectrum 0 ENABLE Enable Spread Spectrum 0x1 STOP STOP 16 16 read-write SYS_PLL1_CTRL SYS_PLL1_CTRL_REGISTER 0x2C0 32 read-write 0x4000 0xFFFFFFFF ENABLE_CLK ENABLE_CLK 13 1 read-write SYS_PLL1_GATE SYS_PLL1_GATE 14 1 read-write NOGATE No gate 0 GATED Gate the output 0x1 SYS_PLL1_DIV2 SYS_PLL1_DIV2 25 1 read-write SYS_PLL1_DIV5 SYS_PLL1_DIV5 26 1 read-write SYS_PLL1_DIV5_CONTROL_MODE SYS_PLL1_DIV5_CONTROL_MODE 27 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 SYS_PLL1_DIV2_CONTROL_MODE SYS_PLL1_DIV2_CONTROL_MODE 28 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 SYS_PLL1_STABLE SYS_PLL1_STABLE 29 1 read-only SYS_PLL1_AI_BUSY SYS_PLL1_AI_BUSY 30 1 read-only SYS_PLL1_CONTROL_MODE SYS_PLL1_CONTROL_MODE 31 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 SYS_PLL1_DENOMINATOR SYS_PLL1_DENOMINATOR_REGISTER 0x2D0 32 read-write 0x2FFFFFFE 0xFFFFFFFF DENOM DENOM 0 30 read-write SYS_PLL1_NUMERATOR SYS_PLL1_NUMERATOR_REGISTER 0x2E0 32 read-write 0x1FFFFFFF 0xFFFFFFFF NUM NUM 0 30 read-write SYS_PLL1_DIV_SELECT SYS_PLL1_DIV_SELECT_REGISTER 0x2F0 32 read-write 0x1D 0xFFFFFFFF DIV_SELECT DIV_SELECT 0 7 read-write PLL_AUDIO_CTRL PLL_AUDIO_CTRL_REGISTER 0x300 32 read-write 0x4000 0xFFFFFFFF ENABLE_CLK ENABLE_CLK 13 1 read-write PLL_AUDIO_GATE PLL_AUDIO_GATE 14 1 read-write NOGATE No gate 0 GATED Gate the output 0x1 PLL_AUDIO_STABLE PLL_AUDIO_STABLE 29 1 read-only PLL_AUDIO_AI_BUSY pll_audio_ai_busy 30 1 read-only PLL_AUDIO_CONTROL_MODE pll_audio_control_mode 31 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 PLL_AUDIO_SS PLL_AUDIO_SS_REGISTER 0x310 32 read-write 0 0xFFFFFFFF STEP STEP 0 15 read-write ENABLE ENABLE 15 1 read-write DISABLE Disable Spread Spectrum 0 ENABLE Enable Spread Spectrum 0x1 STOP STOP 16 16 read-write PLL_AUDIO_DENOMINATOR PLL_AUDIO_DENOMINATOR_REGISTER 0x320 32 read-write 0x2FFFFFFE 0xFFFFFFFF DENOM DENOM 0 30 read-write PLL_AUDIO_NUMERATOR PLL_AUDIO_NUMERATOR_REGISTER 0x330 32 read-write 0x1FFFFFFF 0xFFFFFFFF NUM NUM 0 30 read-write PLL_AUDIO_DIV_SELECT PLL_AUDIO_DIV_SELECT_REGISTER 0x340 32 read-write 0x29 0xFFFFFFFF PLL_AUDIO_DIV_SELECT PLL_AUDIO_DIV_SELECT 0 7 read-write PLL_VIDEO_CTRL PLL_VIDEO_CTRL_REGISTER 0x350 32 read-write 0x4000 0xFFFFFFFF ENABLE_CLK ENABLE_CLK 13 1 read-write PLL_VIDEO_GATE PLL_VIDEO_GATE 14 1 read-write NOGATE No gate 0 GATED Gate the output 0x1 PLL_VIDEO_COUNTER_CLR pll_video_counter_clr 24 1 read-write PLL_VIDEO_STABLE PLL_VIDEO_STABLE 29 1 read-only PLL_VIDEO_AI_BUSY pll_video_ai_busy 30 1 read-only PLL_VIDEO_CONTROL_MODE pll_video_control_mode 31 1 read-write SW Software Mode (Default) 0 GPC GPC Mode 0x1 PLL_VIDEO_SS PLL_VIDEO_SS_REGISTER 0x360 32 read-write 0 0xFFFFFFFF STEP STEP 0 15 read-write ENABLE ENABLE 15 1 read-write DISABLE Disable Spread Spectrum 0 ENABLE Enable Spread Spectrum 0x1 STOP STOP 16 16 read-write PLL_VIDEO_DENOMINATOR PLL_VIDEO_DENOMINATOR_REGISTER 0x370 32 read-write 0x2FFFFFFE 0xFFFFFFFF DENOM DENOM 0 30 read-write PLL_VIDEO_NUMERATOR PLL_VIDEO_NUMERATOR_REGISTER 0x380 32 read-write 0x1FFFFFFF 0xFFFFFFFF NUM NUM 0 30 read-write PLL_VIDEO_DIV_SELECT PLL_VIDEO_DIV_SELECT_REGISTER 0x390 32 read-write 0x29 0xFFFFFFFF DIV_SELECT DIV_SELECT 0 7 read-write ANADIG_PMU MX6RT_ANADIG_REGISTER ANADIG_LDO_SNVS ANADIG 0x40C84000 0 0x7D4 registers LPSR_LP8_BROWNOUT 86 LPSR_LP0_BROWNOUT 87 PMU_LDO_PLL PMU_LDO_PLL_REGISTER 0x500 32 read-write 0x1 0xFFFFFFFF LDO_PLL_ENABLE LDO_PLL_ENABLE 0 1 read-write LDO_PLL_CONTROL_MODE LDO_PLL_CONTROL_MODE 1 1 read-write sw SW Control 0 hw HW Control 0x1 LDO_PLL_AI_TOGGLE ldo_pll_ai_toggle 16 1 read-write LDO_PLL_AI_BUSY ldo_pll_busy 30 1 read-only PMU_BIAS_CTRL PMU_BIAS_CTRL_REGISTER 0x550 32 read-write 0 0xFFFFFFFF WB_CFG_1P8 wb_cfg_1p8 0 13 read-write WB_VDD_SEL_1P8 wb_vdd_sel_1p8 14 1 read-write lv1 VDD_LV1 0 lv2 VDD_LV2 0x1 PMU_BIAS_CTRL2 PMU_BIAS_CTRL2_REGISTER 0x560 32 read-write 0 0xFFFFFFFF WB_TST_MD TMOD_wb_tst_md_1p8 1 9 read-write WB_PWR_SW_EN_1P8 MODSEL_wb_tst_md_1p8 10 3 read-write bb0 No BB 0x1 bb1 BB 0x2 bb2 BB 0x4 WB_ADJ_1P8 wb_adj_1p8 13 8 read-write wb00000000 Cref= 0fF Cspl= 0fF DeltaC= 0fF 0 wb00000001 Cref= 0fF Cspl= 30fF DeltaC= -30fF 0x1 wb00000010 Cref= 0fF Cspl= 43fF DeltaC= -43fF 0x2 wb00000011 Cref= 0fF Cspl= 62fF DeltaC=-62fF 0x3 wb00000100 Cref= 0fF Cspl=105fF DeltaC=-105fF 0x4 wb00000101 Cref= 30fF Cspl= 0fF DeltaC= 30fF 0x5 wb00000110 Cref= 30fF Cspl= 43fF DeltaC= -12fF 0x6 wb00000111 Cref= 30fF Cspl=105fF DeltaC= -75fF 0x7 wb00001000 Cref= 43fF Cspl= 0fF DeltaC= 43fF 0x8 wb00001001 Cref= 43fF Cspl= 30fF DeltaC= 13fF 0x9 wb00001010 Cref= 43fF Cspl= 62fF DeltaC= -19fF 0xA wb00001011 Cref= 62fF Cspl= 0fF DeltaC= 62fF 0xB wb00001100 Cref= 62fF Cspl= 43fF DeltaC= 19fF 0xC wb00001101 Cref=105fF Cspl= 0fF DeltaC= 105fF 0xD wb00001110 Cref=105fF Cspl=30fF DeltaC= 75fF 0xE wb00001111 Cref=0fF Cspl=0fF DeltaC= 0fF 0xF FBB_M7_CONTROL_MODE FBB_M7_CONTROL_MODE 21 1 read-write sw SW Control 0 hw HW Control 0x1 RBB_SOC_CONTROL_MODE RBB_SOC_CONTROL_MODE 22 1 read-write sw SW Control 0 hw HW Control 0x1 RBB_LPSR_CONTROL_MODE RBB_LPSR_CONTROL_MODE 23 1 read-write sw SW Control 0 hw HW Control 0x1 WB_EN wb_en 24 1 read-write WB_TST_DIG_OUT Digital output 25 1 read-only WB_OK Digital Output pin. 26 1 read-only PMU_REF_CTRL PMU_REF_CTRL_REGISTER 0x570 32 read-write 0 0xFFFFFFFF REF_AI_TOGGLE ref_ai_toggle 0 1 read-write REF_AI_BUSY ref_ai_busy 1 1 read-only REF_ENABLE REF_ENABLE 2 1 read-write REF_CONTROL_MODE REF_CONTROL_MODE 3 1 read-write sw SW Control 0 hw HW Control 0x1 EN_PLL_VOL_REF_BUFFER en_pll_vol_ref_buffer 4 1 read-write PMU_POWER_DETECT_CTRL PMU_POWER_DETECT_CTRL_REGISTER 0x580 32 read-write 0 0xFFFFFFFF CKGB_LPSR1P0 ckgb_lpsr1p0 8 1 read-write LDO_PLL_ENABLE_SP LDO_PLL_ENABLE_SP_REGISTER 0x600 32 read-write 0 0xFFFFFFFF ON_OFF_SETPOINT0 ON_OFF_SETPOINT0 0 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT1 ON_OFF_SETPOINT1 1 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT2 ON_OFF_SETPOINT2 2 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT3 ON_OFF_SETPOINT3 3 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT4 ON_OFF_SETPOINT4 4 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT5 ON_OFF_SETPOINT5 5 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT6 ON_OFF_SETPOINT6 6 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT7 ON_OFF_SETPOINT7 7 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT8 ON_OFF_SETPOINT8 8 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT9 ON_OFF_SETPOINT9 9 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT10 ON_OFF_SETPOINT10 10 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT11 ON_OFF_SETPOINT11 11 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT12 ON_OFF_SETPOINT12 12 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT13 ON_OFF_SETPOINT13 13 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT14 ON_OFF_SETPOINT14 14 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT15 ON_OFF_SETPOINT15 15 1 read-write s0 ON 0 s1 OFF 0x1 LDO_LPSR_ANA_ENABLE_SP LDO_LPSR_ANA_ENABLE_SP_REGISTER 0x610 32 read-write 0 0xFFFFFFFF ON_OFF_SETPOINT0 ON_OFF_SETPOINT0 0 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT1 ON_OFF_SETPOINT1 1 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT2 ON_OFF_SETPOINT2 2 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT3 ON_OFF_SETPOINT3 3 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT4 ON_OFF_SETPOINT4 4 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT5 ON_OFF_SETPOINT5 5 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT6 ON_OFF_SETPOINT6 6 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT7 ON_OFF_SETPOINT7 7 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT8 ON_OFF_SETPOINT8 8 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT9 ON_OFF_SETPOINT9 9 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT10 ON_OFF_SETPOINT10 10 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT11 ON_OFF_SETPOINT11 11 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT12 ON_OFF_SETPOINT12 12 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT13 ON_OFF_SETPOINT13 13 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT14 ON_OFF_SETPOINT14 14 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT15 ON_OFF_SETPOINT15 15 1 read-write s0 ON 0 s1 OFF 0x1 LDO_LPSR_ANA_LP_MODE_SP LDO_LPSR_ANA_LP_MODE_SP_REGISTER 0x620 32 read-write 0 0xFFFFFFFF LP_MODE_SETPOINT0 LP_MODE_SETPOINT0 0 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT1 LP_MODE_SETPOINT1 1 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT2 LP_MODE_SETPOINT2 2 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT3 LP_MODE_SETPOINT3 3 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT4 LP_MODE_SETPOINT4 4 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT5 LP_MODE_SETPOINT5 5 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT6 LP_MODE_SETPOINT6 6 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT7 LP_MODE_SETPOINT7 7 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT8 LP_MODE_SETPOINT8 8 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT9 LP_MODE_SETPOINT9 9 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT10 LP_MODE_SETPOINT10 10 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT11 LP_MODE_SETPOINT11 11 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT12 LP_MODE_SETPOINT12 12 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT13 LP_MODE_SETPOINT13 13 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT14 LP_MODE_SETPOINT14 14 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPONIT15 LP_MODE_SETPOINT15 15 1 read-write lp0 LP 0 hp1 HP 0x1 LDO_LPSR_ANA_TRACKING_EN_SP LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER 0x630 32 read-write 0 0xFFFFFFFF TRACKING_EN_SETPOINT0 TRACKING_EN_SETPOINT0 0 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT1 TRACKING_EN_SETPOINT1 1 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT2 TRACKING_EN_SETPOINT2 2 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT3 TRACKING_EN_SETPOINT3 3 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT4 TRACKING_EN_SETPOINT4 4 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT5 TRACKING_EN_SETPOINT5 5 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT6 TRACKING_EN_SETPOINT6 6 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT7 TRACKING_EN_SETPOINT7 7 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT8 TRACKING_EN_SETPOINT8 8 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT9 TRACKING_EN_SETPOINT9 9 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT10 TRACKING_EN_SETPOINT10 10 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT11 TRACKING_EN_SETPOINT11 11 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT12 TRACKING_EN_SETPOINT12 12 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT13 TRACKING_EN_SETPOINT13 13 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT14 TRACKING_EN_SETPOINT14 14 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT15 TRACKING_EN_SETPOINT15 15 1 read-write track0 Disabled 0 track1 Enabled 0x1 LDO_LPSR_ANA_BYPASS_EN_SP LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER 0x640 32 read-write 0 0xFFFFFFFF BYPASS_EN_SETPOINT0 BYPASS_EN_SETPOINT0 0 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT1 BYPASS_EN_SETPOINT1 1 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT2 BYPASS_EN_SETPOINT2 2 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT3 BYPASS_EN_SETPOINT3 3 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT4 BYPASS_EN_SETPOINT4 4 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT5 BYPASS_EN_SETPOINT5 5 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT6 BYPASS_EN_SETPOINT6 6 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT7 BYPASS_EN_SETPOINT7 7 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT8 BYPASS_EN_SETPOINT 8 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT9 BYPASS_EN_SETPOINT9 9 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT10 BYPASS_EN_SETPOINT10 10 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT11 BYPASS_EN_SETPOINT11 11 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT12 BYPASS_EN_SETPOINT12 12 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT13 BYPASS_EN_SETPOINT13 13 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT14 BYPASS_EN_SETPOINT14 14 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT15 BYPASS_EN_SETPOINT15 15 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 LDO_LPSR_ANA_STBY_EN_SP LDO_LPSR_ANA_STBY_EN_SP_REGISTER 0x650 32 read-write 0 0xFFFFFFFF STBY_EN_SETPOINT0 STBY_EN_SETPOINT0 0 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT1 STBY_EN_SETPOINT1 1 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT2 STBY_EN_SETPOINT2 2 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT3 STBY_EN_SETPOINT3 3 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT4 STBY_EN_SETPOINT4 4 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT5 STBY_EN_SETPOINT5 5 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT6 STBY_EN_SETPOINT6 6 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT7 STBY_EN_SETPOINT7 7 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT8 STBY_EN_SETPOINT8 8 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT9 STBY_EN_SETPOINT9 9 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT10 STBY_EN_SETPOINT10 10 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT11 STBY_EN_SETPOINT11 11 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT12 STBY_EN_SETPOINT12 12 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT13 STBY_EN_SETPOINT13 13 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT14 STBY_EN_SETPOINT14 14 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT15 STBY_EN_SETPOINT15 15 1 read-write b0 Disabled 0 b1 Enabled 0x1 LDO_LPSR_DIG_ENABLE_SP LDO_LPSR_DIG_ENABLE_SP_REGISTER 0x660 32 read-write 0 0xFFFFFFFF ON_OFF_SETPOINT0 ON_OFF_SETPOINT0 0 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT1 ON_OFF_SETPOINT1 1 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT2 ON_OFF_SETPOINT2 2 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT3 ON_OFF_SETPOINT3 3 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT4 ON_OFF_SETPOINT4 4 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT5 ON_OFF_SETPOINT5 5 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT6 ON_OFF_SETPOINT6 6 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT7 ON_OFF_SETPOINT7 7 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT8 ON_OFF_SETPOINT8 8 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT9 ON_OFF_SETPOINT9 9 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT10 ON_OFF_SETPOINT10 10 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT11 ON_OFF_SETPOINT11 11 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT12 ON_OFF_SETPOINT12 12 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT13 ON_OFF_SETPOINT13 13 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT14 ON_OFF_SETPOINT14 14 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT15 ON_OFF_SETPOINT15 15 1 read-write s0 ON 0 s1 OFF 0x1 LDO_LPSR_DIG_TRG_SP0 LDO_LPSR_DIG_TRG_SP0_REGISTER 0x670 32 read-write 0 0xFFFFFFFF VOLTAGE_SETPOINT0 VOLTAGE_SETPOINT0 0 8 read-write VOLTAGE_SETPOINT1 VOLTAGE_SETPOINT1 8 8 read-write VOLTAGE_SETPOINT2 VOLTAGE_SETPOINT2 16 8 read-write VOLTAGE_SETPOINT3 VOLTAGE_SETPOINT3 24 8 read-write LDO_LPSR_DIG_TRG_SP1 LDO_LPSR_DIG_TRG_SP1_REGISTER 0x680 32 read-write 0 0xFFFFFFFF VOLTAGE_SETPOINT4 VOLTAGE_SETPOINT4 0 8 read-write VOLTAGE_SETPOINT5 VOLTAGE_SETPOINT5 8 8 read-write VOLTAGE_SETPOINT6 VOLTAGE_SETPOINT6 16 8 read-write VOLTAGE_SETPOINT7 VOLTAGE_SETPOINT7 24 8 read-write LDO_LPSR_DIG_TRG_SP2 LDO_LPSR_DIG_TRG_SP2_REGISTER 0x690 32 read-write 0 0xFFFFFFFF VOLTAGE_SETPOINT8 VOLTAGE_SETPOINT8 0 8 read-write VOLTAGE_SETPOINT9 VOLTAGE_SETPOINT9 8 8 read-write VOLTAGE_SETPOINT10 VOLTAGE_SETPOINT10 16 8 read-write VOLTAGE_SETPOINT11 VOLTAGE_SETPOINT11 24 8 read-write LDO_LPSR_DIG_TRG_SP3 LDO_LPSR_DIG_TRG_SP3_REGISTER 0x6A0 32 read-write 0 0xFFFFFFFF VOLTAGE_SETPOINT12 VOLTAGE_SETPOINT12 0 8 read-write VOLTAGE_SETPOINT13 VOLTAGE_SETPOINT13 8 8 read-write VOLTAGE_SETPOINT14 VOLTAGE_SETPOINT14 16 8 read-write VOLTAGE_SETPOINT15 VOLTAGE_SETPOINT15 24 8 read-write LDO_LPSR_DIG_LP_MODE_SP LDO_LPSR_DIG_LP_MODE_SP_REGISTER 0x6B0 32 read-write 0 0xFFFFFFFF LP_MODE_SETPOINT0 LP_MODE_SETPOINT0 0 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT1 LP_MODE_SETPOINT1 1 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT2 LP_MODE_SETPOINT2 2 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT3 LP_MODE_SETPOINT3 3 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT4 LP_MODE_SETPOINT4 4 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT5 LP_MODE_SETPOINT5 5 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT6 LP_MODE_SETPOINT6 6 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT7 LP_MODE_SETPOINT7 7 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT8 LP_MODE_SETPOINT8 8 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT9 LP_MODE_SETPOINT9 9 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT10 LP_MODE_SETPOINT10 10 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT11 LP_MODE_SETPOINT11 11 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT12 LP_MODE_SETPOINT12 12 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT13 LP_MODE_SETPOINT13 13 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT14 LP_MODE_SETPOINT14 14 1 read-write lp0 LP 0 hp1 HP 0x1 LP_MODE_SETPOINT15 LP_MODE_SETPOINT15 15 1 read-write lp0 LP 0 hp1 HP 0x1 LDO_LPSR_DIG_TRACKING_EN_SP LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER 0x6C0 32 read-write 0 0xFFFFFFFF TRACKING_EN_SETPOINT0 TRACKING_EN_SETPOINT0 0 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT1 TRACKING_EN_SETPOINT1 1 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT2 TRACKING_EN_SETPOINT2 2 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT3 TRACKING_EN_SETPOINT3 3 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT4 TRACKING_EN_SETPOINT4 4 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT5 TRACKING_EN_SETPOINT5 5 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT6 TRACKING_EN_SETPOINT6 6 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT7 TRACKING_EN_SETPOINT7 7 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT8 TRACKING_EN_SETPOINT8 8 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT9 TRACKING_EN_SETPOINT9 9 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT10 TRACKING_EN_SETPOINT10 10 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT11 TRACKING_EN_SETPOINT11 11 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT12 TRACKING_EN_SETPOINT12 12 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT13 TRACKING_EN_SETPOINT13 13 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT14 TRACKING_EN_SETPOINT14 14 1 read-write track0 Disabled 0 track1 Enabled 0x1 TRACKING_EN_SETPOINT15 TRACKING_EN_SETPOINT15 15 1 read-write track0 Disabled 0 track1 Enabled 0x1 LDO_LPSR_DIG_BYPASS_EN_SP LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER 0x6D0 32 read-write 0 0xFFFFFFFF BYPASS_EN_SETPOINT0 BYPASS_EN_SETPOINT0 0 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT1 BYPASS_EN_SETPOINT1 1 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT2 BYPASS_EN_SETPOINT2 2 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT3 BYPASS_EN_SETPOINT3 3 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT4 BYPASS_EN_SETPOINT4 4 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT5 BYPASS_EN_SETPOINT5 5 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT6 BYPASS_EN_SETPOINT6 6 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT7 BYPASS_EN_SETPOINT7 7 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT8 BYPASS_EN_SETPOINT8 8 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT9 BYPASS_EN_SETPOINT9 9 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT10 BYPASS_EN_SETPOINT10 10 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT11 BYPASS_EN_SETPOINT11 11 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT12 BYPASS_EN_SETPOINT12 12 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT13 BYPASS_EN_SETPOINT13 13 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT14 BYPASS_EN_SETPOINT14 14 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 BYPASS_EN_SETPOINT15 BYPASS_EN_SETPOINT15 15 1 read-write byp0 Disabled 0 byp1 Enabled 0x1 LDO_LPSR_DIG_STBY_EN_SP LDO_LPSR_DIG_STBY_EN_SP_REGISTER 0x6E0 32 read-write 0 0xFFFFFFFF STBY_EN_SETPOINT0 STBY_EN_SETPOINT0 0 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT1 STBY_EN_SETPOINT1 1 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT2 STBY_EN_SETPOINT2 2 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT3 STBY_EN_SETPOINT3 3 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT4 STBY_EN_SETPOINT4 4 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT5 STBY_EN_SETPOINT5 5 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT6 STBY_EN_SETPOINT6 6 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT7 STBY_EN_SETPOINT7 7 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT8 STBY_EN_SETPOINT8 8 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT9 STBY_EN_SETPOINT9 9 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT10 STBY_EN_SETPOINT10 10 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT11 STBY_EN_SETPOINT11 11 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT12 STBY_EN_SETPOINT12 12 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT13 STBY_EN_SETPOINT13 13 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT14 STBY_EN_SETPOINT14 14 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT15 STBY_EN_SETPOINT15 15 1 read-write b0 Disabled 0 b1 Enabled 0x1 BANDGAP_ENABLE_SP BANDGAP_ENABLE_SP_REGISTER 0x6F0 32 read-write 0 0xFFFFFFFF ON_OFF_SETPOINT0 ON_OFF_SETPOINT0 0 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT1 ON_OFF_SETPOINT1 1 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT2 ON_OFF_SETPOINT2 2 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT3 ON_OFF_SETPOINT3 3 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT4 ON_OFF_SETPOINT4 4 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT5 ON_OFF_SETPOINT5 5 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT6 ON_OFF_SETPOINT5 6 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT7 ON_OFF_SETPOINT7 7 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT8 ON_OFF_SETPOINT8 8 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT9 ON_OFF_SETPOINT9 9 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT10 ON_OFF_SETPOINT10 10 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT11 ON_OFF_SETPOINT11 11 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT12 ON_OFF_SETPOINT12 12 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT13 ON_OFF_SETPOINT13 13 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT14 ON_OFF_SETPOINT14 14 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT15 ON_OFF_SETPOINT15 15 1 read-write s0 ON 0 s1 OFF 0x1 FBB_M7_ENABLE_SP FBB_M7_ENABLE_SP_REGISTER 0x700 32 read-write 0 0xFFFFFFFF ON_OFF_SETPOINT0 ON_OFF_SETPOINT0 0 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT1 ON_OFF_SETPOINT1 1 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT2 ON_OFF_SETPOINT2 2 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT3 ON_OFF_SETPOINT3 3 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT4 ON_OFF_SETPOINT4 4 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT5 ON_OFF_SETPOINT5 5 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT6 ON_OFF_SETPOINT6 6 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT7 ON_OFF_SETPOINT7 7 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT8 ON_OFF_SETPOINT8 8 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT9 ON_OFF_SETPOINT9 9 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT10 ON_OFF_SETPOINT10 10 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT11 ON_OFF_SETPOINT11 11 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT12 ON_OFF_SETPOINT12 12 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT13 ON_OFF_SETPOINT13 13 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT14 ON_OFF_SETPOINT14 14 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT15 ON_OFF_SETPOINT15 15 1 read-write s0 ON 0 s1 OFF 0x1 RBB_SOC_ENABLE_SP RBB_SOC_ENABLE_SP_REGISTER 0x710 32 read-write 0 0xFFFFFFFF ON_OFF_SETPOINT0 ON_OFF_SETPOINT0 0 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT1 ON_OFF_SETPOINT1 1 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT2 ON_OFF_SETPOINT2 2 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT3 ON_OFF_SETPOINT3 3 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT4 ON_OFF_SETPOINT4 4 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT5 ON_OFF_SETPOINT5 5 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT6 ON_OFF_SETPOINT6 6 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT7 ON_OFF_SETPOINT7 7 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT8 ON_OFF_SETPOINT8 8 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT9 ON_OFF_SETPOINT9 9 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT10 ON_OFF_SETPOINT10 10 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT11 ON_OFF_SETPOINT11 11 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT12 ON_OFF_SETPOINT12 12 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT13 ON_OFF_SETPOINT13 13 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT14 ON_OFF_SETPOINT14 14 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT15 ON_OFF_SETPOINT15 15 1 read-write s0 ON 0 s1 OFF 0x1 RBB_LPSR_ENABLE_SP RBB_LPSR_ENABLE_SP_REGISTER 0x720 32 read-write 0 0xFFFFFFFF ON_OFF_SETPOINT0 ON_OFF_SETPOINT0 0 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT1 ON_OFF_SETPOINT1 1 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT2 ON_OFF_SETPOINT2 2 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT3 ON_OFF_SETPOINT3 3 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT4 ON_OFF_SETPOINT4 4 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT5 ON_OFF_SETPOINT5 5 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT6 ON_OFF_SETPOINT6 6 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT7 ON_OFF_SETPOINT7 7 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT8 ON_OFF_SETPOINT8 8 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT9 ON_OFF_SETPOINT9 9 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT10 ON_OFF_SETPOINT10 10 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT11 ON_OFF_SETPOINT11 11 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT12 ON_OFF_SETPOINT12 12 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT13 ON_OFF_SETPOINT13 13 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT14 ON_OFF_SETPOINT14 14 1 read-write s0 ON 0 s1 OFF 0x1 ON_OFF_SETPOINT15 ON_OFF_SETPOINT15 15 1 read-write s0 ON 0 s1 OFF 0x1 BANDGAP_STBY_EN_SP BANDGAP_STBY_EN_SP_REGISTER 0x730 32 read-write 0 0xFFFFFFFF STBY_EN_SETPOINT0 STBY_EN_SETPOINT 0 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT1 STBY_EN_SETPOINT 1 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT2 STBY_EN_SETPOINT 2 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT3 STBY_EN_SETPOINT 3 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT4 STBY_EN_SETPOINT 4 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT5 STBY_EN_SETPOINT 5 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT6 STBY_EN_SETPOINT 6 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT7 STBY_EN_SETPOINT 7 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT8 STBY_EN_SETPOINT 8 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT9 STBY_EN_SETPOINT 9 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT10 STBY_EN_SETPOINT 10 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT11 STBY_EN_SETPOINT 11 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT12 STBY_EN_SETPOINT 12 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT13 STBY_EN_SETPOINT 13 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT14 STBY_EN_SETPOINT 14 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT15 STBY_EN_SETPOINT 15 1 read-write b0 Disabled 0 b1 Enabled 0x1 PLL_LDO_STBY_EN_SP PLL_LDO_STBY_EN_SP_REGISTER 0x740 32 read-write 0 0xFFFFFFFF STBY_EN_SETPOINT0 Standby mode 0 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT1 Standby mode 1 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT2 Standby mode 2 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT3 Standby mode 3 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT4 Standby mode 4 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT5 Standby mode 5 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT6 Standby mode 6 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT7 Standby mode 7 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT8 Standby mode 8 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT9 Standby mode 9 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT10 Standby mode 10 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT11 Standby mode 11 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT12 Standby mode 12 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT13 Standby mode 13 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT14 Standby mode 14 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT15 Standby mode 15 1 read-write b0 Disabled 0 b1 Enabled 0x1 FBB_M7_STBY_EN_SP FBB_M7_STBY_EN_SP_REGISTER 0x750 32 read-write 0 0xFFFFFFFF STBY_EN_SETPOINT0 Standby mode 0 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT1 Standby mode 1 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT2 Standby mode 2 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT3 Standby mode 3 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT4 Standby mode 4 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT5 Standby mode 5 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT6 Standby mode 6 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT7 Standby mode 7 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT8 Standby mode 8 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT9 Standby mode 9 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT10 Standby mode 10 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT11 Standby mode 11 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT12 Standby mode 12 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT13 Standby mode 13 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT14 Standby mode 14 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT15 Standby mode 15 1 read-write b0 Disabled 0 b1 Enabled 0x1 RBB_SOC_STBY_EN_SP RBB_SOC_STBY_EN_SP_REGISTER 0x760 32 read-write 0 0xFFFFFFFF STBY_EN_SETPOINT0 Standby mode 0 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT1 Standby mode 1 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT2 Standby mode 2 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT3 Standby mode 3 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT4 Standby mode 4 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT5 Standby mode 5 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT6 Standby mode 6 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT7 Standby mode 7 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT8 Standby mode 8 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT9 Standby mode 9 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT10 Standby mode 10 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT11 Standby mode 11 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT12 Standby mode 12 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT13 Standby mode 13 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT14 Standby mode 14 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT15 Standby mode 15 1 read-write b0 Disabled 0 b1 Enabled 0x1 RBB_LPSR_STBY_EN_SP RBB_LPSR_STBY_EN_SP_REGISTER 0x770 32 read-write 0 0xFFFFFFFF STBY_EN_SETPOINT0 Standby mode 0 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT1 Standby mode 1 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT2 Standby mode 2 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT3 Standby mode 3 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT4 Standby mode 4 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT5 Standby mode 5 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT6 Standby mode 6 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT7 Standby mode 7 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT8 Standby mode 8 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT9 Standby mode 9 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT10 Standby mode 10 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT11 Standby mode 11 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT12 Standby mode 12 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT13 Standby mode 13 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT14 Standby mode 14 1 read-write b0 Disabled 0 b1 Enabled 0x1 STBY_EN_SETPOINT15 Standby mode 15 1 read-write b0 Disabled 0 b1 Enabled 0x1 FBB_M7_CONFIGURE FBB_M7_CONFIGURE_REGISTER 0x780 32 read-write 0x2F11 0xFFFFFFFF WB_CFG_PW wb_cfg_pw 0 4 read-write WB_CFG_NW wb_cfg_nw 4 4 read-write OSCILLATOR_BITS oscillator_bits 8 3 read-write REGULATOR_STRENGTH regulator_strength 11 3 read-write RBB_LPSR_CONFIGURE RBB_LPSR_CONFIGURE_REGISTER 0x790 32 read-write 0x3022 0xFFFFFFFF WB_CFG_PW wb_cfg_pw 0 4 read-write WB_CFG_NW wb_cfg_nw 4 4 read-write OSCILLATOR_BITS oscillator_bits 8 3 read-write REGULATOR_STRENGTH regulator_strength 11 3 read-write RBB_SOC_CONFIGURE RBB_SOC_CONFIGURE_REGISTER 0x7A0 32 read-write 0x44 0xFFFFFFFF WB_CFG_PW wb_cfg_pw 0 4 read-write WB_CFG_NW wb_cfg_nw 4 4 read-write OSCILLATOR_BITS oscillator_bits 8 3 read-write REGULATOR_STRENGTH regulator_strength 11 3 read-write REFTOP_OTP_TRIM_VALUE REFTOP_OTP_TRIM_VALUE_REGISTER 0x7B0 32 read-only 0 0xFFFFFFFF REFTOP_IBZTCADJ REFTOP_IBZTCADJ 0 3 read-only REFTOP_VBGADJ REFTOP_VBGADJ 3 3 read-only REFTOP_TRIM_EN REFTOP_TRIM_EN 6 1 read-only LPSR_1P8_LDO_OTP_TRIM_VALUE LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER 0x7D0 32 read-only 0 0xFFFFFFFF LPSR_LDO_1P8_TRIM LPSR_LDO_1P8_TRIM 0 2 read-only LPSR_LDO_1P8_TRIM_EN LPSR_LDO_1P8_TRIM_EN 2 1 read-only ANADIG_TEMPSENSOR MX6RT_ANADIG_REGISTER ANADIG_LDO_SNVS ANADIG 0x40C84000 0 0x434 registers TEMPSENSOR Tempsensor Register 0x400 32 read-write 0 0xFFFFFFFF TEMPSNS_AI_TOGGLE AI toggle 15 1 read-write TEMPSNS_AI_BUSY AI Busy monitor 16 1 read-only TEMPSNS_OTP_TRIM_VALUE TEMPSNS_OTP_TRIM_VALUE_REGISTER 0x430 32 read-only 0 0xFFFFFFFF TEMPSNS_TEMP_VAL Temperature Value at 25C 10 12 read-only IPS_DOMAIN IPS Domain IPS_DOMAIN 0x40C87C00 0 0x254 registers 38 0x10 SLOT_CTRL[%s] The slot assignments are given below: 0 SLOT_CTRL Slot Control Register 0 32 read-write 0xF 0xFFFFFFFF LOCKED_DOMAIN_ID Domain ID of the slot to be locked 0 4 read-write modify DOMAIN_LOCK Lock domain ID of this slot 15 1 read-write oneToSet UNLOCK Do not lock the domain ID 0 LOCK Lock the domain ID 0x1 ALLOW_NONSECURE Allow non-secure write access to this domain control register or domain register 16 1 read-write modify PREVENT Do not allow non-secure write access 0 ALLOW Allow non-secure write access 0x1 ALLOW_USER Allow user write access to this domain control register or domain register 17 1 read-write modify PREVENT Do not allow user write access 0 ALLOW Allow user write access 0x1 LOCK_CONTROL Lock control of this slot 31 1 read-write modify UNLOCK Do not lock the control register of this slot 0 LOCK Lock the control register of this slot 0x1 PGMC_BPC0 PGMC_BPC PGMC_BPC PGMC_BPC 0x40C88000 0 0x100 registers BPC_AUTHEN_CTRL BPC Authentication Control 0x4 32 read-write 0xF00 0xFFFFFFFF USER Allow user mode access 0 1 read-write USER_0 Allow only privilege mode to access basic power control registers 0 USER_1 Allow both privilege and user mode to access basic power control registers 0x1 NONSECURE Allow non-secure mode access 1 1 read-write NONSECURE_0 Allow only secure mode to access basic power control registers 0 NONSECURE_1 Allow both secure and non-secure mode to access basic power control registers 0x1 LOCK_SETTING Lock NONSECURE and USER 4 1 read-write WHITE_LIST Domain ID white list 8 4 read-write LOCK_LIST White list lock 12 1 read-write LOCK_CFG Configuration lock 20 1 read-write BPC_MODE BPC Mode 0x10 32 read-write 0 0xFFFFFFFF CTRL_MODE Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0 2 read-write CTRL_MODE_0 Not affected by any low power mode 0 CTRL_MODE_1 Controlled by CPU power mode of the domain 0x1 CTRL_MODE_2 Controlled by Setpoint 0x2 DOMAIN_ASSIGN Domain assignment of the BPC 4 2 read-write d0 Domain 0 0 d1 Domain 1 0x1 d2 Domain 2 0x2 d3 Domain 3 0x3 BPC_POWER_CTRL BPC power control 0x14 32 read-write 0 0xFFFFFFFF PWR_OFF_AT_WAIT 0x1: Power off when domain enters WAIT mode 1 1 read-write PWR_OFF_AT_STOP 0x1: Power off when domain enters STOP mode 2 1 read-write PWR_OFF_AT_SUSPEND 0x1: Power off when domain enters SUSPEND mode 3 1 read-write ISO_ON_SOFT Software isolation on trigger 8 1 read-write PSW_OFF_SOFT Software power off trigger 9 1 read-write PSW_ON_SOFT Software power on trigger 10 1 read-write ISO_OFF_SOFT Software isolation off trigger 11 1 read-write PWR_OFF_AT_SP Power off when system enters Setpoint number 16 16 read-write BPC_FLAG BPC flag 0x2C 32 read-write 0 0xFFFFFFFF oneToClear PDN_FLAG set to 1 after power switch off, cleared by writing 1 0 1 read-write oneToClear BPC_SSAR_SAVE_CTRL BPC SSAR save control 0x40 32 read-write 0 0xFFFFFFFF SAVE_AT_RUN Save data at RUN mode, software writting 0x1 to trigger SSARC to execute save process 0 1 read-write SAVE_AT_WAIT Save data when domain enters WAIT mode 1 1 read-write SAVE_AT_STOP Save data when domain enters STOP mode 2 1 read-write SAVE_AT_SUSPEND Save data when domain enters SUSPEND mode 3 1 read-write SAVE_AT_SP Save data when system enters a Setpoint. 16 16 read-write BPC_SSAR_RESTORE_CTRL BPC SSAR restore control 0x44 32 read-write 0 0xFFFFFFFF RESTORE_AT_RUN Restore data at RUN mode 0 1 read-write RESTORE_AT_SP Restore data when system enters a Setpoint. 16 16 read-write PGMC_BPC1 PGMC_BPC PGMC_BPC 0x40C88200 0 0x100 registers PGMC_BPC2 PGMC_BPC PGMC_BPC 0x40C88400 0 0x100 registers PGMC_BPC3 PGMC_BPC PGMC_BPC 0x40C88600 0 0x100 registers PGMC_BPC4 PGMC_BPC PGMC_BPC 0x40C88800 0 0x100 registers PGMC_BPC5 PGMC_BPC PGMC_BPC 0x40C88A00 0 0x100 registers PGMC_BPC6 PGMC_BPC PGMC_BPC 0x40C88C00 0 0x100 registers PGMC_BPC7 PGMC_BPC PGMC_BPC 0x40C88E00 0 0x100 registers PGMC_CPC0 PGMC_CPC PGMC_CPC PGMC_CPC 0x40C89000 0 0x100 registers CPC_AUTHEN_CTRL CPC Authentication Control 0x4 32 read-write 0xF00 0xFFFFFFFF USER Allow user mode access 0 1 read-write NONSECURE Allow non-secure mode access 1 1 read-write LOCK_SETTING Lock NONSECURE and USER 4 1 read-write WHITE_LIST Domain ID white list 8 4 read-write LOCK_LIST White list lock 12 1 read-write LOCK_CFG Configuration lock 20 1 read-write CPC_CORE_MODE CPC Core Mode 0x10 32 read-write 0 0xFFFFFFFF CTRL_MODE Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0 2 read-write CTRL_MODE_0 Not affected by any low power mode 0 CTRL_MODE_1 Controlled by CPU power mode of the domain 0x1 CPC_CORE_POWER_CTRL CPC core power control 0x14 32 read-write 0 0xFFFFFFFF PWR_OFF_AT_WAIT Power off when domain enters WAIT mode 1 1 read-write PWR_OFF_AT_STOP Power off when domain enters STOP mode 2 1 read-write PWR_OFF_AT_SUSPEND Power off when domain enters SUSPEND mode 3 1 read-write ISO_ON_SOFT Software isolation on trigger 8 1 read-write PSW_OFF_SOFT Software power off trigger 9 1 read-write PSW_ON_SOFT Software power on trigger 10 1 read-write ISO_OFF_SOFT Software isolation off trigger 11 1 read-write CPC_FLAG CPC flag 0x2C 32 read-write 0 0xFFFFFFFF oneToClear CORE_PDN_FLAG set to 1 after core power switch off, cleared by writing 1 0 1 read-write oneToClear CPC_CACHE_MODE CPC Cache Mode 0x40 32 read-write 0 0xFFFFFFFF CTRL_MODE Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0 2 read-write CTRL_MODE_0 Not affected by any low power mode 0 CTRL_MODE_1 Controlled by CPU power mode of the domain 0x1 CTRL_MODE_2 Controlled by Setpoint 0x2 CPC_CACHE_CM_CTRL CPC cache CPU mode control 0x44 32 read-write 0x3330 0xFFFFFFFF MLPL_AT_RUN Memory Low Power Level (MLPL) at RUN mode 0 4 read-write MLPL_AT_WAIT Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 4 4 read-write MLPL_AT_STOP Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 8 4 read-write MLPL_AT_SUSPEND Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 12 4 read-write MLPL_SOFT Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete 16 1 read-write CPC_CACHE_SP_CTRL_0 CPC cache Setpoint control 0 0x48 32 read-write 0x33333333 0xFFFFFFFF MLPL_AT_SP0 Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0 4 read-write MLPL_AT_SP1 Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 4 4 read-write MLPL_AT_SP2 Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 8 4 read-write MLPL_AT_SP3 Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 12 4 read-write MLPL_AT_SP4 Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 16 4 read-write MLPL_AT_SP5 Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 20 4 read-write MLPL_AT_SP6 Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 24 4 read-write MLPL_AT_SP7 Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 28 4 read-write CPC_CACHE_SP_CTRL_1 CPC cache Setpoint control 1 0x4C 32 read-write 0x33333333 0xFFFFFFFF MLPL_AT_SP8 Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0 4 read-write MLPL_AT_SP9 Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 4 4 read-write MLPL_AT_SP10 Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 8 4 read-write MLPL_AT_SP11 Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 12 4 read-write MLPL_AT_SP12 Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 16 4 read-write MLPL_AT_SP13 Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 20 4 read-write MLPL_AT_SP14 Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 24 4 read-write MLPL_AT_SP15 Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 28 4 read-write CPC_LMEM_MODE CPC local memory Mode 0xC0 32 read-write 0 0xFFFFFFFF CTRL_MODE Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0 2 read-write CTRL_MODE_0 Not affected by any low power mode 0 CTRL_MODE_1 Controlled by CPU power mode of the domain 0x1 CTRL_MODE_2 Controlled by Setpoint 0x2 CPC_LMEM_CM_CTRL CPC local memory CPU mode control 0xC4 32 read-write 0 0xFFFFFFFF MLPL_AT_RUN Memory Low Power Level (MLPL) at RUN mode 0 4 read-write MLPL_AT_WAIT Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 4 4 read-write MLPL_AT_STOP Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 8 4 read-write MLPL_AT_SUSPEND Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 12 4 read-write MLPL_SOFT Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete 16 1 read-write CPC_LMEM_SP_CTRL_0 CPC local memory Setpoint control 0 0xC8 32 read-write 0 0xFFFFFFFF MLPL_AT_SP0 Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0 4 read-write MLPL_AT_SP1 Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 4 4 read-write MLPL_AT_SP2 Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 8 4 read-write MLPL_AT_SP3 Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 12 4 read-write MLPL_AT_SP4 Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 16 4 read-write MLPL_AT_SP5 Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 20 4 read-write MLPL_AT_SP6 Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 24 4 read-write MLPL_AT_SP7 Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 28 4 read-write CPC_LMEM_SP_CTRL_1 CPC local memory Setpoint control 1 0xCC 32 read-write 0 0xFFFFFFFF MLPL_AT_SP8 Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0 4 read-write MLPL_AT_SP9 Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 4 4 read-write MLPL_AT_SP10 Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 8 4 read-write MLPL_AT_SP11 Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 12 4 read-write MLPL_AT_SP12 Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 16 4 read-write MLPL_AT_SP13 Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 20 4 read-write MLPL_AT_SP14 Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 24 4 read-write MLPL_AT_SP15 Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 28 4 read-write PGMC_CPC1 PGMC_CPC PGMC_CPC 0x40C89400 0 0x100 registers PGMC_CPC0_MIF0 PGMC_MIF PGMC_MIF PGMC_MIF 0x40C89100 0 0x100 registers MIF_AUTHEN_CTRL MIF Authentication Control 0x4 32 read-write 0 0xFFFFFFFF LOCK_CFG Configuration lock 20 1 read-write MIF_MLPL_SLEEP MIF MLPL control of SLEEP 0x10 32 read-write 0xFF00 0xFFFFFFFF MLPL_CTRL Signal behavior at each MLPL 0 16 read-write MIF_MLPL_IG MIF MLPL control of IG 0x20 32 read-write 0x60 0xFFFFFFFF MLPL_CTRL Signal behavior at each MLPL 0 16 read-write MIF_MLPL_LS MIF MLPL control of LS 0x30 32 read-write 0x10 0xFFFFFFFF MLPL_CTRL Signal behavior at each MLPL 0 16 read-write MIF_MLPL_HS MIF MLPL control of HS 0x40 32 read-write 0x2 0xFFFFFFFF MLPL_CTRL Signal behavior at each MLPL 0 16 read-write MIF_MLPL_STDBY MIF MLPL control of STDBY 0x50 32 read-write 0x40 0xFFFFFFFF MLPL_CTRL Signal behavior at each MLPL 0 16 read-write MIF_MLPL_ARR_PDN MIF MLPL control of array power down 0x60 32 read-write 0xC00 0xFFFFFFFF MLPL_CTRL Signal behavior at each MLPL 0 16 read-write MIF_MLPL_PER_PDN MIF MLPL control of peripheral power down 0x70 32 read-write 0x4A00 0xFFFFFFFF MLPL_CTRL Signal behavior at each MLPL 0 16 read-write MIF_MLPL_INITN MIF MLPL control of INITN 0x80 32 read-write 0x35FF 0xFFFFFFFF MLPL_CTRL Signal behavior at each MLPL 0 16 read-write BYPASS_VDD_OK Bypass vdd_ok. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 31 1 read-write MIF_MLPL_ISO MIF MLPL control of isolation enable 0xB0 32 read-write 0xCA00 0xFFFFFFFF MLPL_CTRL Signal behavior at each MLPL 0 16 read-write PGMC_CPC0_MIF1 PGMC_MIF PGMC_MIF 0x40C89200 0 0x100 registers PGMC_CPC1_MIF0 PGMC_MIF PGMC_MIF 0x40C89500 0 0x100 registers PGMC_CPC1_MIF1 PGMC_MIF PGMC_MIF 0x40C89600 0 0x100 registers PGMC_PPC0 PGMC_PPC PGMC_PPC 0x40C8B000 0 0x100 registers PPC_AUTHEN_CTRL PPC Authentication Control 0x4 32 read-write 0xF00 0xFFFFFFFF USER Allow user mode access 0 1 read-write NONSECURE Allow non-secure mode access 1 1 read-write LOCK_SETTING Lock NONSECURE and USER 4 1 read-write WHITE_LIST Domain ID white list 8 4 read-write LOCK_LIST White list lock 12 1 read-write LOCK_CFG Configuration lock 20 1 read-write PPC_MODE PPC Mode 0x10 32 read-write 0 0xFFFFFFFF CTRL_MODE Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0 2 read-write CTRL_MODE_0 Not affected by any low power mode 0 CTRL_MODE_1 Controlled by CPU power mode of the domain 0x1 CTRL_MODE_2 Controlled by Setpoint and system standby 0x2 DOMAIN_ASSIGN Domain assignment of the BPC 4 2 read-write d0 Domain 0 0 d1 Domain 1 0x1 d2 Domain 2 0x2 d3 Domain 3 0x3 PPC_STBY_CM_CTRL PPC standby CPU mode control 0x14 32 read-write 0 0xFFFFFFFF STBY_ON_AT_WAIT PMIC Standby on when domain enters WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 1 1 read-write STBY_ON_AT_STOP PMIC Standby on when domain enters STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 2 1 read-write STBY_ON_AT_SUSPEND PMIC Standby on when domain enters SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 3 1 read-write STBY_ON_SOFT Software PMIC standby on trigger 8 1 read-write STBY_OFF_SOFT Software PMIC standby off trigger 9 1 read-write PPC_STBY_SP_CTRL PPC standby Setpoint control 0x18 32 read-write 0 0xFFFFFFFF STBY_ON_AT_SP_ACTIVE PMIC standby on when system enters Setpoint number. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0 16 read-write STBY_ON_AT_SP_SLEEP PMIC standby on when system enters Setpoint number and system is in standby mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 16 16 read-write SNVS SNVS SNVS 0x40C90000 0 0xC00 registers SNVS_HP_NON_TZ 66 SNVS_HP_TZ 67 SNVS_PULSE_EVENT 68 HPLR SNVS_HP Lock Register 0 32 read-write 0 0xFFFFFFFF ZMK_WSL Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR 0 1 read-write WRITE_ALLOWED Write access is allowed 0 WRITE_NOT_ALLOWED Write access is not allowed 0x1 ZMK_RSL Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR 1 1 read-write READ_ALLOWED Read access is allowed (only in software Programming mode) 0 READ_NOT_ALLOWED Read access is not allowed 0x1 SRTC_SL Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits 2 1 read-write WRITE_ALLOWED Write access is allowed 0 WRITE_NOT_ALLOWED Write access is not allowed 0x1 LPCALB_SL LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) 3 1 read-write WRITE_ALLOWED Write access is allowed 0 WRITE_NOT_ALLOWED Write access is not allowed 0x1 MC_SL Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit 4 1 read-write WRITE_ALLOWED Write access (increment) is allowed 0 WRITE_NOT_ALLOWED Write access (increment) is not allowed 0x1 GPR_SL General Purpose Register Soft Lock When set, prevents any writes to the GPR 5 1 read-write WRITE_ALLOWED Write access is allowed 0 WRITE_NOT_ALLOWED Write access is not allowed 0x1 LPSVCR_SL LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR 6 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed 0x1 LPTGFCR_SL LP Tamper Glitch Filter Configuration Register Soft Lock When set, prevents any writes to the LPTGFCR 7 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed 0x1 LPSECR_SL LP Security Events Configuration Register Soft Lock When set, prevents any writes to the LPSECR 8 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed 0x1 MKS_SL Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR 9 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed 0x1 HPSVCR_L HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR 16 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed 0x1 HPSICR_L HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR 17 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed 0x1 HAC_L High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR 18 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed 0x1 AT1_SL Active Tamper 1 Soft Lock When set, prevents any writes to the Active Tamper 1 registers 24 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 AT2_SL Active Tamper 2 Soft Lock When set, prevents any writes to the Active Tamper 2 registers 25 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 AT3_SL Active Tamper 3 Soft Lock When set, prevents any writes to the Active Tamper 3 registers 26 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 AT4_SL Active Tamper 4 Soft Lock When set, prevents any writes to the Active Tamper 4 registers 27 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 AT5_SL Active Tamper 5 Soft Lock When set, prevents any writes to the Active Tamper 5 registers 28 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 HPCOMR SNVS_HP Command Register 0x4 32 read-write 0 0xFFFFFFFF SSM_ST SSM State Transition Transition state of the system security monitor 0 1 write-only SSM_ST_DIS SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state 1 1 read-write ENABLED Secure to Trusted State transition is enabled 0 DISABLED Secure to Trusted State transition is disabled 0x1 SSM_SFNS_DIS SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state 2 1 read-write ENABLED Soft Fail to Non-Secure State transition is enabled 0 DISABLED Soft Fail to Non-Secure State transition is disabled 0x1 LP_SWR LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Monotonic Counter Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set 4 1 write-only NO_ACTION No Action 0 RESET Reset LP section 0x1 LP_SWR_DIS LP Software Reset Disable When set, disables the LP software reset 5 1 read-write ENABLED LP software reset is enabled 0 DISABLED LP software reset is disabled 0x1 SW_SV Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation 8 1 read-write SW_FSV Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation 9 1 read-write SW_LPSV LP Software Security Violation When set, SNVS_LP treats this bit as a security violation 10 1 read-write PROG_ZMK Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism 12 1 write-only NO_ACTION No Action 0 PROGRAM_KEY Activate hardware key programming mechanism 0x1 MKS_EN Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default 13 1 read-write SELECT_OTP OTP master key is selected as an SNVS master key 0 SELECT_PER_LPMKCR SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR 0x1 HAC_EN High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state 16 1 read-write DISABLED High Assurance Counter is disabled 0 ENABLED High Assurance Counter is enabled 0x1 HAC_LOAD High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register 17 1 write-only NO_ACTION No Action 0 LOAD_HAC Load the HAC 0x1 HAC_CLEAR High Assurance Counter Clear When set, it clears the High Assurance Counter Register 18 1 write-only NO_ACTION No Action 0 CLEAR_HAC Clear the HAC 0x1 HAC_STOP High Assurance Counter Stop This bit can be set only when SSM is in soft fail state 19 1 read-write NPSWA_EN Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only 31 1 read-write HPCR SNVS_HP Control Register 0x8 32 read-write 0 0xFFFFFFFF RTC_EN HP Real Time Counter Enable 0 1 read-write DISABLED RTC is disabled 0 ENABLED RTC is enabled 0x1 HPTA_EN HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter 1 1 read-write DISABLED HP Time Alarm Interrupt is disabled 0 ENABLED HP Time Alarm Interrupt is enabled 0x1 DIS_PI Disable periodic interrupt in the functional interrupt 2 1 read-write ENABLED Periodic interrupt will trigger a functional interrupt 0 DISABLED Disable periodic interrupt in the function interrupt 0x1 PI_EN HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled 3 1 read-write DISABLED HP Periodic Interrupt is disabled 0 ENABLED HP Periodic Interrupt is enabled 0x1 PI_FREQ Periodic Interrupt Frequency Defines frequency of the periodic interrupt 4 4 read-write USE_BIT_0 - bit 0 of the HPRTCLR is selected as a source of the periodic interrupt 0 USE_BIT_1 - bit 1 of the HPRTCLR is selected as a source of the periodic interrupt 0x1 USE_BIT_2 - bit 2 of the HPRTCLR is selected as a source of the periodic interrupt 0x2 USE_BIT_3 - bit 3 of the HPRTCLR is selected as a source of the periodic interrupt 0x3 USE_BIT_4 - bit 4 of the HPRTCLR is selected as a source of the periodic interrupt 0x4 USE_BIT_5 - bit 5 of the HPRTCLR is selected as a source of the periodic interrupt 0x5 USE_BIT_6 - bit 6 of the HPRTCLR is selected as a source of the periodic interrupt 0x6 USE_BIT_7 - bit 7 of the HPRTCLR is selected as a source of the periodic interrupt 0x7 USE_BIT_8 - bit 8 of the HPRTCLR is selected as a source of the periodic interrupt 0x8 USE_BIT_9 - bit 9 of the HPRTCLR is selected as a source of the periodic interrupt 0x9 USE_BIT_10 - bit 10 of the HPRTCLR is selected as a source of the periodic interrupt 0xA USE_BIT_11 - bit 11 of the HPRTCLR is selected as a source of the periodic interrupt 0xB USE_BIT_12 - bit 12 of the HPRTCLR is selected as a source of the periodic interrupt 0xC USE_BIT_13 - bit 13 of the HPRTCLR is selected as a source of the periodic interrupt 0xD USE_BIT_14 - bit 14 of the HPRTCLR is selected as a source of the periodic interrupt 0xE USE_BIT_1r5 - bit 15 of the HPRTCLR is selected as a source of the periodic interrupt 0xF HPCALB_EN HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled. 8 1 read-write DISABLED HP Timer calibration disabled 0 ENABLED HP Timer calibration enabled 0x1 HPCALB_VAL HP Calibration Value Defines signed calibration value for the HP Real Time Counter 10 5 read-write ADD_0_PER_32768_TICKS +0 counts per each 32768 ticks of the counter 0 ADD_1_PER_32768_TICKS +1 counts per each 32768 ticks of the counter 0x1 ADD_2_PER_32768_TICKS +2 counts per each 32768 ticks of the counter 0x2 ADD_15_PER_32768_TICKS +15 counts per each 32768 ticks of the counter 0xF SUB_16_PER_32768_TICKS -16 counts per each 32768 ticks of the counter 0x10 SUB_15_PER_32768_TICKS -15 counts per each 32768 ticks of the counter 0x11 SUB_2_PER_32768_TICKS -2 counts per each 32768 ticks of the counter 0x1E SUB_1_PER_32768_TICKS -1 counts per each 32768 ticks of the counter 0x1F HP_TS HP Time Synchronize 16 1 read-write NO_ACTION No Action 0 SYNC_TIME Synchronize the HP Time Counter to the LP Time Counter 0x1 BTN_CONFIG Button Configuration 24 3 read-write BTN_MASK Button interrupt mask 27 1 read-write HPSICR SNVS_HP Security Interrupt Control Register 0xC 32 read-write 0 0xFFFFFFFF CAAM_EN CAAM Security Violation Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the CAAM Security Violation security violation 0 1 read-write DISABLED CAAM Security Violation Interrupt is Disabled 0 ENABLED CAAM Security Violation Interrupt is Enabled 0x1 JTAGC_EN JTAG Active Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the JTAG Active security violation 1 1 read-write DISABLED JTAG Active Interrupt is Disabled 0 ENABLED JTAG Active Interrupt is Enabled 0x1 WDOG2_EN Watchdog 2 Reset Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Watchdog 2 Reset security violation 2 1 read-write DISABLED Watchdog 2 Reset Interrupt is Disabled 0 ENABLED Watchdog 2 Reset Interrupt is Enabled 0x1 SRC_EN Internal Boot Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Internal Boot security violation 4 1 read-write DISABLED Internal Boot Interrupt is Disabled 0 ENABLED Internal Boot Interrupt is Enabled 0x1 OCOTP_EN OCOTP attack error Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the OCOTP attack error security violation 5 1 read-write DISABLED OCOTP attack error Interrupt is Disabled 0 ENABLED OCOTP attack error Interrupt is Enabled 0x1 LPSVI_EN LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section 31 1 read-write DISABLED LP Security Violation Interrupt is Disabled 0 ENABLED LP Security Violation Interrupt is Enabled 0x1 HPSVCR SNVS_HP Security Violation Control Register 0x10 32 read-write 0 0xFFFFFFFF CAAM_CFG CAAM Security Violation Security Violation Configuration This field configures the CAAM Security Violation Security Violation Input 0 1 read-write NON_FATAL CAAM Security Violation is a non-fatal violation 0 FATAL CAAM Security Violation is a fatal violation 0x1 JTAGC_CFG JTAG Active Security Violation Configuration This field configures the JTAG Active Security Violation Input 1 1 read-write NON_FATAL JTAG Active is a non-fatal violation 0 FATAL JTAG Active is a fatal violation 0x1 WDOG2_CFG Watchdog 2 Reset Security Violation Configuration This field configures the Watchdog 2 Reset Security Violation Input 2 1 read-write NON_FATAL Watchdog 2 Reset is a non-fatal violation 0 FATAL Watchdog 2 Reset is a fatal violation 0x1 SRC_CFG Internal Boot Security Violation Configuration This field configures the Internal Boot Security Violation Input 4 1 read-write NON_FATAL Internal Boot is a non-fatal violation 0 FATAL Internal Boot is a fatal violation 0x1 OCOTP_CFG OCOTP attack error Security Violation Configuration This field configures the OCOTP attack error Security Violation Input 5 2 read-write DISABLED OCOTP attack error is disabled 0 NON_FATAL OCOTP attack error is a non-fatal violation 0x1 FATAL OCOTP attack error is a fatal violation #1x LPSV_CFG LP Security Violation Configuration This field configures the LP security violation source. 30 2 read-write DISABLED LP security violation is disabled 0 NON_FATAL LP security violation is a non-fatal violation 0x1 FATAL LP security violation is a fatal violation #1x HPSR SNVS_HP Status Register 0x14 32 read-write 0x8000B000 0xFFFFFFFF HPTA HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared. 0 1 read-write oneToClear NOREPORT No time alarm interrupt occurred. 0 REPORTED A time alarm interrupt occurred. 0x1 PI Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared. 1 1 read-write oneToClear NOREPORT No periodic interrupt occurred. 0 REPORTED A periodic interrupt occurred. 0x1 LPDIS Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS 4 1 read-only BTN Button Value of the BTN input 6 1 read-only BI Button Interrupt Signal ipi_snvs_btn_int_b was asserted. 7 1 read-write oneToClear SSM_STATE System Security Monitor State This field contains the encoded state of the SSM's state machine 8 4 read-only INIT Init 0 HARD_FAIL Hard Fail 0x1 SOFT_FAIL Soft Fail 0x3 INTERMEDIATE Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) 0x8 CHECK Check 0x9 NON_SECURE Non-Secure 0xB TRUSTED Trusted 0xD SECURE Secure 0xF SYS_SECURITY_CFG System Security Configuration This field reflects the three security configuration inputs to SNVS 12 3 read-only FAB_CONFIG Fab Configuration - the default configuration of newly fabricated chips 0 OPEN_CONFIG Open Configuration - the configuration after NXP-programmable fuses have been blown 0x1 CLOSED_CONFIG Closed Configuration - the configuration after OEM-programmable fuses have been blown 0x3 FIELD_RETURN_CONFIG Field Return Configuration - the configuration of chips that are returned to NXP for analysis 0x7 SYS_SECURE_BOOT System Secure Boot If SYS_SECURE_BOOT is 1, the chip boots from internal ROM 15 1 read-only OTPMK_ZERO One Time Programmable Master Key is Equal to Zero 27 1 read-only OTPMK_NOT_ZERO The OTPMK is not zero. 0 OTPMK_IS_ZERO The OTPMK is zero. 0x1 ZMK_ZERO Zeroizable Master Key is Equal to Zero 31 1 read-only ZMK_NOT_ZERO The ZMK is not zero. 0 ZMK_IS_ZERO The ZMK is zero. 0x1 HPSVSR SNVS_HP Security Violation Status Register 0x18 32 read-write 0x80000000 0xFFFFFFFF CAAM CAAM Security Violation security violation was detected. 0 1 read-write oneToClear NOREPORT No CAAM Security Violation security violation was detected. 0 REPORTED CAAM Security Violation security violation was detected. 0x1 JTAGC JTAG Active security violation was detected. 1 1 read-write oneToClear NOREPORT No JTAG Active security violation was detected. 0 REPORTED JTAG Active security violation was detected. 0x1 WDOG2 Watchdog 2 Reset security violation was detected. 2 1 read-write oneToClear NOREPORT No Watchdog 2 Reset security violation was detected. 0 REPORTED Watchdog 2 Reset security violation was detected. 0x1 SRC Internal Boot security violation was detected. 4 1 read-write oneToClear NOREPORT No Internal Boot security violation was detected. 0 REPORTED Internal Boot security violation was detected. 0x1 OCOTP OCOTP attack error security violation was detected. 5 1 read-write oneToClear NOREPORT No OCOTP attack error security violation was detected. 0 REPORTED OCOTP attack error security violation was detected. 0x1 SW_SV Software Security Violation This bit is a read-only copy of the SW_SV bit in the HP Command Register 13 1 read-only SW_FSV Software Fatal Security Violation This bit is a read-only copy of the SW_FSV bit in the HP Command Register 14 1 read-only SW_LPSV LP Software Security Violation This bit is a read-only copy of the SW_LPSV bit in the HP Command Register 15 1 read-only ZMK_SYNDROME Zeroizable Master Key Syndrome The ZMK syndrome indicates the single-bit error location and parity for the ZMK register 16 9 read-only ZMK_ECC_FAIL Zeroizable Master Key Error Correcting Code Check Failure When set, this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section, which clears security sensitive data 27 1 read-write oneToClear NOREPORT ZMK ECC Failure was not detected. 0 REPORTED ZMK ECC Failure was detected. 0x1 LP_SEC_VIO LP Security Violation A security volation was detected in the SNVS low power section 31 1 read-only HPHACIVR SNVS_HP High Assurance Counter IV Register 0x1C 32 read-write 0 0xFFFFFFFF HAC_COUNTER_IV High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter 0 32 read-write HPHACR SNVS_HP High Assurance Counter Register 0x20 32 read-only 0 0xFFFFFFFF HAC_COUNTER High Assurance Counter When the HAC_EN bit is set and the SSM is in the soft fail state, this counter starts to count down with the system clock 0 32 read-only HPRTCMR SNVS_HP Real Time Counter MSB Register 0x24 32 read-write 0 0xFFFFFFFF RTC HP Real Time Counter The most-significant 15 bits of the RTC 0 15 read-write HPRTCLR SNVS_HP Real Time Counter LSB Register 0x28 32 read-write 0 0xFFFFFFFF RTC HP Real Time Counter least-significant 32 bits 0 32 read-write HPTAMR SNVS_HP Time Alarm MSB Register 0x2C 32 read-write 0 0xFFFFFFFF HPTA_MS HP Time Alarm, most-significant 15 bits 0 15 read-write HPTALR SNVS_HP Time Alarm LSB Register 0x30 32 read-write 0 0xFFFFFFFF HPTA_LS HP Time Alarm, 32 least-significant bits 0 32 read-write LPLR SNVS_LP Lock Register 0x34 32 read-write 0 0xFFFFFFFF ZMK_WHL Zeroizable Master Key Write Hard Lock When set, prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR 0 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 ZMK_RHL Zeroizable Master Key Read Hard Lock When set, prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR 1 1 read-write READ_ACCESS_ALLOWED Read access is allowed (only in software programming mode). 0 READ_ACCESS_NOT_ALLOWED Read access is not allowed. 0x1 SRTC_HL Secure Real Time Counter Hard Lock When set, prevents any writes to the SRTC registers, SRTC_ENV, and SRTC_INV_EN bits 2 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 LPCALB_HL LP Calibration Hard Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) 3 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 MC_HL Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit 4 1 read-write WRITE_ACCESS_ALLOWED Write access (increment) is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access (increment) is not allowed. 0x1 GPR_HL General Purpose Register Hard Lock When set, prevents any writes to the GPR 5 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 LPSVCR_HL LP Security Violation Control Register Hard Lock When set, prevents any writes to the LPSVCR 6 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 LPTGFCR_HL LP Tamper Glitch Filter Configuration Register Hard Lock When set, prevents any writes to the LPTGFCR 7 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 LPSECR_HL LP Security Events Configuration Register Hard Lock When set, prevents any writes to the LPSECR 8 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 MKS_HL Master Key Select Hard Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register 9 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 AT1_HL Active Tamper 1 Hard Lock When set, prevents any writes to the Active Tamper 1 registers 24 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 AT2_HL Active Tamper 2 Hard Lock When set, prevents any writes to the Active Tamper 2 registers 25 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 AT3_HL Active Tamper 3 Hard Lock When set, prevents any writes to the Active Tamper 3 registers 26 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 AT4_HL Active Tamper 4 Hard Lock When set, prevents any writes to the Active Tamper 4 registers 27 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 AT5_HL Active Tamper 5 Hard Lock When set, prevents any writes to the Active Tamper 5 registers 28 1 read-write WRITE_ACCESS_ALLOWED Write access is allowed. 0 WRITE_ACCESS_NOT_ALLOWED Write access is not allowed. 0x1 LPCR SNVS_LP Control Register 0x38 32 read-write 0x20 0xFFFFFFFF SRTC_ENV Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational 0 1 read-write DISABLED SRTC is disabled or invalid. 0 ENABLED SRTC is enabled and valid. 0x1 LPTA_EN LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter 1 1 read-write DISABLED LP time alarm interrupt is disabled. 0 ENABLED LP time alarm interrupt is enabled. 0x1 MC_ENV Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR) 2 1 read-write DISABLED MC is disabled or invalid. 0 ENABLED MC is enabled and valid. 0x1 LPWUI_EN LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event, MC rollover, SRTC rollover, or time alarm ) 3 1 read-write SRTC_INV_EN If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared) 4 1 read-write KEEP_VALID SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)). 0 INVALIDATE SRTC is invalidated in the case of security violation. 0x1 DP_EN Dumb PMIC Enabled When set, software can control the system power 5 1 read-write SMART_PMIC_ENABLED Smart PMIC enabled. 0 DUMB_PMIC_ENABLED Dumb PMIC enabled. 0x1 TOP Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power 6 1 read-write KEEP_ON Leave system power on. 0 TURN_OFF Turn off system power. 0x1 LVD_EN Digital Low-Voltage Event Enable By default the detection of a low-voltage event does not cause the pmic_en_b signal to be asserted 7 1 read-write LPCALB_EN LP Calibration Enable When set, enables the SRTC calibration mechanism 8 1 read-write DISABLED SRTC Time calibration is disabled. 0 ENABLED SRTC Time calibration is enabled. 0x1 LPCALB_VAL LP Calibration Value Defines signed calibration value for SRTC 10 5 read-write ADD_0_PER_32768_TICKS +0 counts per each 32768 ticks of the counter clock 0 ADD_1_PER_32768_TICKS +1 counts per each 32768 ticks of the counter clock 0x1 ADD_2_PER_32768_TICKS +2 counts per each 32768 ticks of the counter clock 0x2 ADD_15_PER_32768_TICKS +15 counts per each 32768 ticks of the counter clock 0xF SUB_16_PER_32768_TICKS -16 counts per each 32768 ticks of the counter clock 0x10 SUB_15_PER_32768_TICKS -15 counts per each 32768 ticks of the counter clock 0x11 SUB_2_PER_32768_TICKS -2 counts per each 32768 ticks of the counter clock 0x1E SUB_1_PER_32768_TICKS -1 counts per each 32768 ticks of the counter clock 0x1F BTN_PRESS_TIME This field configures the button press time out values for the PMIC Logic 16 2 read-write DEBOUNCE This field configures the amount of debounce time for the BTN input signal 18 2 read-write ON_TIME The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power 20 2 read-write PK_EN PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en 22 1 read-write PK_OVERRIDE PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override 23 1 read-write GPR_Z_DIS General Purpose Registers Zeroization Disable 24 1 read-write LPMKCR SNVS_LP Master Key Control Register 0x3C 32 read-write 0 0xFFFFFFFF MASTER_KEY_SEL Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR 0 2 read-write SELECT_OTPMK Select one time programmable master key. #0x SELECT_ZMK Select zeroizable master key when MKS_EN bit is set . 0x2 SELECT_COMBO Select combined master key when MKS_EN bit is set . 0x3 ZMK_HWP Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it 2 1 read-write SW_PROG_MODE ZMK is in the software programming mode. 0 HW_PROG_MODE ZMK is in the hardware programming mode. 0x1 ZMK_VAL Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules 3 1 read-write INVALID ZMK is not valid. 0 VALID ZMK is valid. 0x1 ZMK_ECC_EN Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register 4 1 read-write DISABLED ZMK ECC check is disabled. 0 ENABLED ZMK ECC check is enabled. 0x1 ZMK_ECC_VALUE Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register 7 9 read-only LPSVCR SNVS_LP Security Violation Control Register 0x40 32 read-write 0 0xFFFFFFFF CAAM_EN CAAM Security Violation Enable This bit enables CAAM Security Violation Input 0 1 read-write DISABLED CAAM Security Violation is disabled in the LP domain. 0 ENABLED CAAM Security Violation is enabled in the LP domain. 0x1 JTAGC_EN JTAG Active Enable This bit enables JTAG Active Input 1 1 read-write DISABLED JTAG Active is disabled in the LP domain. 0 ENABLED JTAG Active is enabled in the LP domain. 0x1 WDOG2_EN Watchdog 2 Reset Enable This bit enables Watchdog 2 Reset Input 2 1 read-write DISABLED Watchdog 2 Reset is disabled in the LP domain. 0 ENABLED Watchdog 2 Reset is enabled in the LP domain. 0x1 SRC_EN Internal Boot Enable This bit enables Internal Boot Input 4 1 read-write DISABLED Internal Boot is disabled in the LP domain. 0 ENABLED Internal Boot is enabled in the LP domain. 0x1 OCOTP_EN OCOTP attack error Enable This bit enables OCOTP attack error Input 5 1 read-write DISABLED OCOTP attack error is disabled in the LP domain. 0 ENABLED OCOTP attack error is enabled in the LP domain. 0x1 LPTGFCR SNVS_LP Tamper Glitch Filters Configuration Register 0x44 32 read-write 0 0xFFFFFFFF WMTGF Wire-Mesh Tamper Glitch Filter Configures the length of the digital glitch filter for the wire-mesh tamper 1 and 2 pins between 1 and 63 SRTC clock cycles 0 5 read-write WMTGF_EN Wire-Mesh Tamper Glitch Filter Enable When set, enables the wire-mesh tamper glitch filter 7 1 read-write BYPASSED Wire-mesh tamper glitch filter is bypassed. 0 ENABLED Wire-mesh tamper glitch filter is enabled. 0x1 ETGF1 External Tamper Glitch Filter 1 Configures the length of the digital glitch filter for the external tamper 1 pin between 128 and 32640 SRTC clock cycles 16 7 read-write ETGF1_EN External Tamper Glitch Filter 1 Enable When set, enables the external tamper glitch filter 1. 23 1 read-write BYPASSED External tamper glitch filter 1 is bypassed. 0 ENABLED External tamper glitch filter 1 is enabled. 0x1 ETGF2 External Tamper Glitch Filter 2 Configures the length of the digital glitch filter for the external tamper 2 pin between 128 and 32640 SRTC clock cycles 24 7 read-write ETGF2_EN External Tamper Glitch Filter 2 Enable When set, enables the external tamper glitch filter 2. 31 1 read-write BYPASSED External tamper glitch filter 2 is bypassed. 0 ENABLED External tamper glitch filter 2 is enabled. 0x1 LPTDCR SNVS_LP Tamper Detect Configuration Register 0x48 32 read-write 0 0xFFFFFFFF SRTCR_EN SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation. 1 1 read-write DISABLED SRTC rollover is disabled. 0 ENABLED SRTC rollover is enabled. 0x1 MCR_EN MC Rollover Enable When set, an MC Rollover event generates an LP security violation. 2 1 read-write DISABLED MC rollover is disabled. 0 ENABLED MC rollover is enabled. 0x1 CT_EN Clock Tamper Enable When set, a clock monitor tamper generates an LP security violation. 4 1 read-write DISABLED Clock tamper is disabled. 0 ENABLED Clock tamper is enabled. 0x1 TT_EN Temperature Tamper Enable When set, a temperature monitor tamper generates an LP security violation 5 1 read-write DISABLED Temperature tamper is disabled. 0 ENABLED Temperature tamper is enabled. 0x1 VT_EN Voltage Tamper Enable Voltage Tamper Enable should be enabled 500 us after setting SCSC_SOSC_CTR [VOLT_TEMP_TAMPER_EN] 6 1 read-write DISABLED Voltage tamper is disabled. 0 ENABLED Voltage tamper is enabled. 0x1 WMT1_EN Wire-Mesh Tampering 1 Enable When set, wire-mesh tampering 1 detection generates an LP security violation 7 1 read-write DISABLED Wire-mesh tamper 1 is disabled. 0 ENABLED Wire-mesh tamper 1 is enabled. 0x1 WMT2_EN Wire-Mesh Tampering 2 Enable When set, wire-mesh tampering 2 detection generates an LP security violation 8 1 read-write DISABLED Wire-mesh tamper 2 is disabled. 0 ENABLED Wire-mesh tamper 2 is enabled. 0x1 ET1_EN External Tampering 1 Enable When set, external tampering 1 detection generates an LP security violation 9 1 read-write DISABLED External tamper 1 is disabled. 0 ENABLED External tamper 1 is enabled. 0x1 ET2_EN External Tampering 2 Enable When set, external tampering 2 detection generates an LP security violation 10 1 read-write DISABLED External tamper 2 is disabled. 0 ENABLED External tamper 2 is enabled. 0x1 ET1P External Tampering 1 Polarity This bit is used to determine the polarity of external tamper 1. 11 1 read-write ACTIVE_LOW External tamper 1 is active low. 0 ACTIVE_HIGH External tamper 1 is active high. 0x1 ET2P External Tampering 2 Polarity This bit is used to determine the polarity of external tamper 2. 12 1 read-write ACTIVE_LOW External tamper 2 is active low. 0 ACTIVE_HIGH External tamper 2 is active high. 0x1 PFD_OBSERV System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block) 14 1 read-write POR_OBSERV Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS 15 1 read-write LTDC Low Temp Detect Configuration These configuration bits are wired as an output of the module. 16 3 read-write HTDC High Temperature Detect Configuration These configuration bits are wired as an output of the module 20 3 read-write VRC Voltage Reference Configuration These configuration bits are wired as an output of the module. 24 3 read-write OSCB Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted 28 1 read-write NOT_BYPASSED Normal SRTC clock oscillator not bypassed. 0 BYPASSED Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. 0x1 LPSR SNVS_LP Status Register 0x4C 32 read-write 0x8 0xFFFFFFFF LPTA LP Time Alarm 0 1 read-write oneToClear NOREPORT No time alarm interrupt occurred. 0 REPORTED A time alarm interrupt occurred. 0x1 SRTCR Secure Real Time Counter Rollover 1 1 read-write oneToClear NOREPORT SRTC has not reached its maximum value. 0 REPORTED SRTC has reached its maximum value. 0x1 MCR Monotonic Counter Rollover 2 1 read-write oneToClear NOREPORT MC has not reached its maximum value. 0 REPORTED MC has reached its maximum value. 0x1 LVD Digital Low Voltage Event Detected 3 1 read-write oneToClear NOLOWVOLT No low voltage event detected. 0 LOWVOLTDETECTED Low voltage event is detected. 0x1 CTD Clock Tampering Detected 4 1 read-write oneToClear NOREPORT No clock tamper. 0 REPORTED Clock tamper is detected. 0x1 TTD Temperature Tamper Detected 5 1 read-write oneToClear NOREPORT No temperature tamper. 0 REPORTED Temperature tamper is detected. 0x1 VTD Voltage Tampering Detected 6 1 read-write oneToClear NOREPORT Voltage tampering not detected. 0 REPORTED Voltage tampering detected. 0x1 WMT1D Wire-Mesh Tampering 1 Detected 7 1 read-write oneToClear NOREPORT Wire-mesh tampering 1 not detected. 0 REPORTED Wire-mesh tampering 1 detected. 0x1 WMT2D Wire-Mesh Tampering 2 Detected 8 1 read-write oneToClear NOREPORT Wire-mesh tampering 2 not detected. 0 REPORTED Wire-mesh tampering 2 detected. 0x1 ET1D External Tampering 1 Detected 9 1 read-write oneToClear NOREPORT External tampering 1 not detected. 0 REPORTED External tampering 1 detected. 0x1 ET2D External Tampering 2 Detected 10 1 read-write oneToClear NOREPORT External tampering 2 not detected. 0 REPORTED External tampering 2 detected. 0x1 ESVD External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports 16 1 read-write oneToClear NOREPORT No external security violation. 0 REPORTED External security violation is detected. 0x1 EO Emergency Off This bit is set when a power off is requested. 17 1 read-write oneToClear NOREPORT Emergency off was not detected. 0 REPORTED Emergency off was detected. 0x1 SPOF Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time 18 1 read-write oneToClear NOREPORT Set Power Off was not detected. 0 REPORTED Set Power Off was detected. 0x1 LPNS LP Section is Non-Secured Indicates that LP section was provisioned/programmed in the non-secure state 30 1 read-only NOT_PRGRMD_IN_NON_SECURE_STATE LP section was not programmed in the non-secure state. 0 WAS_PRGRMD_IN_NON_SECURE_STATE LP section was programmed in the non-secure state. 0x1 LPS LP Section is Secured Indicates that the LP section is provisioned/programmed in the secure or trusted state 31 1 read-only NOT_PRGRMD_IN_SECURE_OR_TRUSTED_STATE LP section was not programmed in secure or trusted state. 0 WAS_PRGRMD_IN_SECURE_OR_TRUSTED_STATE LP section was programmed in secure or trusted state. 0x1 LPSRTCMR SNVS_LP Secure Real Time Counter MSB Register 0x50 32 read-write 0 0xFFFFFFFF SRTC LP Secure Real Time Counter The most-significant 15 bits of the SRTC 0 15 read-write LPSRTCLR SNVS_LP Secure Real Time Counter LSB Register 0x54 32 read-write 0 0xFFFFFFFF SRTC LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked, meaning the SRTC_ENV, SRTC_SL, and SRTC_HL bits are not set 0 32 read-write LPTAR SNVS_LP Time Alarm Register 0x58 32 read-write 0 0xFFFFFFFF LPTA LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set) 0 32 read-write LPSMCMR SNVS_LP Secure Monotonic Counter MSB Register 0x5C 32 read-write 0 0xFFFFFFFF MON_COUNTER Monotonic Counter most-significant 16 Bits Note that writing to this register does not change the value of this field to the value that was written 0 16 read-write modify MC_ERA_BITS Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses 16 16 read-only LPSMCLR SNVS_LP Secure Monotonic Counter LSB Register 0x60 32 read-write 0 0xFFFFFFFF modify MON_COUNTER Monotonic Counter bits Note that writing to this register does not change the value of this field to the value that was written 0 32 read-write modify LPLVDR SNVS_LP Digital Low-Voltage Detector Register 0x64 32 read-write 0 0xFFFFFFFF LVD Low-Voltage Detector Value 0 32 read-write LPGPR0_legacy_alias SNVS_LP General Purpose Register 0 (legacy alias) 0x68 32 read-write 0 0xFFFFFFFF GPR General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. 0 32 read-write 8 0x4 LPZMKR[%s] SNVS_LP Zeroizable Master Key Register 0x6C 32 read-write 0 0xFFFFFFFF ZMK Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value 0 32 read-write 4 0x4 LPGPR_alias[%s] SNVS_LP General Purpose Registers 0 .. 3 0x90 32 read-write 0 0xFFFFFFFF GPR General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. 0 32 read-write LPTDC2R SNVS_LP Tamper Detectors Config 2 Register 0xA0 32 read-write 0 0xFFFFFFFF ET3_EN External Tampering 3 Enable When set, external tampering 3 detection generates an LP security violation 0 1 read-write DISABLED External tamper 3 is disabled. 0 ENABLED External tamper 3 is enabled. 0x1 ET4_EN External Tampering 4 Enable When set, external tampering 4 detection generates an LP security violation 1 1 read-write DISABLED External tamper 4 is disabled. 0 ENABLED External tamper 4 is enabled. 0x1 ET5_EN External Tampering 5 Enable When set, external tampering 5 detection generates an LP security violation 2 1 read-write DISABLED External tamper 5 is disabled. 0 ENABLED External tamper 5 is enabled. 0x1 ET6_EN External Tampering 6 Enable When set, external tampering 6 detection generates an LP security violation 3 1 read-write DISABLED External tamper 6 is disabled. 0 ENABLED External tamper 6 is enabled. 0x1 ET7_EN External Tampering 7 Enable When set, external tampering 7 detection generates an LP security violation 4 1 read-write DISABLED External tamper 7 is disabled. 0 ENABLED External tamper 7 is enabled. 0x1 ET8_EN External Tampering 8 Enable When set, external tampering 8 detection generates an LP security violation 5 1 read-write DISABLED External tamper 8 is disabled. 0 ENABLED External tamper 8 is enabled. 0x1 ET9_EN External Tampering 9 Enable When set, external tampering 9 detection generates an LP security violation 6 1 read-write DISABLED External tamper 9 is disabled. 0 ENABLED External tamper 9 is enabled. 0x1 ET10_EN External Tampering 10 Enable When set, external tampering 10 detection generates an LP security violation 7 1 read-write DISABLED External tamper 10 is disabled. 0 ENABLED External tamper 10 is enabled. 0x1 ET3P External Tampering 3 Polarity This bit is used to determine the polarity of external tamper 3. 16 1 read-write ACTIVE_LOW External tamper 3 active low. 0 ACTIVE_HIGH External tamper 3 active high. 0x1 ET4P External Tampering 4 Polarity This bit is used to determine the polarity of external tamper 4. 17 1 read-write ACTIVE_LOW External tamper 4 is active low. 0 ACTIVE_HIGH External tamper 4 is active high. 0x1 ET5P External Tampering 5 Polarity This bit is used to determine the polarity of external tamper 5. 18 1 read-write ACTIVE_LOW External tamper 5 is active low. 0 ACTIVE_HIGH External tamper 5 is active high. 0x1 ET6P External Tampering 6 Polarity This bit is used to determine the polarity of external tamper 6. 19 1 read-write ACTIVE_LOW External tamper 6 is active low. 0 ACTIVE_HIGH External tamper 6 is active high. 0x1 ET7P External Tampering 7 Polarity This bit is used to determine the polarity of external tamper 7. 20 1 read-write ACTIVE_LOW External tamper 7 is active low. 0 ACTIVE_HIGH External tamper 7 is active high. 0x1 ET8P External Tampering 8 Polarity This bit is used to determine the polarity of external tamper 8. 21 1 read-write ACTIVE_LOW External tamper 8 is active low. 0 ACTIVE_HIGH External tamper 8 is active high. 0x1 ET9P External Tampering 9 Polarity This bit is used to determine the polarity of external tamper 9. 22 1 read-write ACTIVE_LOW External tamper 9 is active low. 0 ACTIVE_HIGH External tamper 9 is active high. 0x1 ET10P External Tampering 10 Polarity This bit is used to determine the polarity of external tamper 10. 23 1 read-write ACTIVE_LOW External tamper 10 is active low. 0 ACTIVE_HIGH External tamper 10 is active high. 0x1 LPTDSR SNVS_LP Tamper Detectors Status Register 0xA4 32 read-write 0 0xFFFFFFFF oneToClear ET3D External Tampering 3 Detected 0 1 read-write oneToClear NOREPORT External tamper 3 is not detected. 0 REPORTED External tamper 3 is detected. 0x1 ET4D External Tampering 4 Detected 1 1 read-write oneToClear NOREPORT External tamper 4 is not detected. 0 REPORTED External tamper 4 is detected. 0x1 ET5D External Tampering 5 Detected 2 1 read-write oneToClear NOREPORT External tamper 5 is not detected. 0 REPORTED External tamper 5 is detected. 0x1 ET6D External Tampering 6 Detected 3 1 read-write oneToClear NOREPORT External tamper 6 is not detected. 0 REPORTED External tamper 6 is detected. 0x1 ET7D External Tampering 7 Detected 4 1 read-write oneToClear NOREPORT External tamper 7 is not detected. 0 REPORTED External tamper 7 is detected. 0x1 ET8D External Tampering 8 Detected 5 1 read-write oneToClear NOREPORT External tamper 8 is not detected. 0 REPORTED External tamper 8 is detected. 0x1 ET9D External Tampering 9 Enable When set, external tampering 9 detection generates an LP security violation 6 1 read-write oneToClear NOREPORT External tamper 9 is not detected. 0 REPORTED External tamper 9 is detected. 0x1 ET10D External Tampering 10 Detected 7 1 read-write oneToClear NOREPORT External tamper 10 is not detected. 0 REPORTED External tamper 10 is detected. 0x1 LPTGF1CR SNVS_LP Tamper Glitch Filter 1 Configuration Register 0xA8 32 read-write 0 0xFFFFFFFF ETGF3 External Tamper Glitch Filter 3 Configures the length of the digital glitch filter for the external tamper 3 pin between 128 and 32640 SRTC clock cycles 0 7 read-write ETGF3_EN External Tamper Glitch Filter 3 Enable When set, enables the external tamper glitch filter 3. 7 1 read-write BYPASSED External tamper glitch filter 3 is bypassed. 0 ENABLED External tamper glitch filter 3 is enabled. 0x1 ETGF4 External Tamper Glitch Filter 4 Configures the length of the digital glitch filter for the external tamper 4 pin between 128 and 32640 SRTC clock cycles 8 7 read-write ETGF4_EN External Tamper Glitch Filter 4 Enable When set, enables the external tamper glitch filter 4. 15 1 read-write BYPASSED External tamper glitch filter 4 is bypassed. 0 ENABLED External tamper glitch filter 4 is enabled. 0x1 ETGF5 External Tamper Glitch Filter 5 Configures the length of the digital glitch filter for the external tamper 5 pin between 128 and 32640 SRTC clock cycles 16 7 read-write ETGF5_EN External Tamper Glitch Filter 5 Enable When set, enables the external tamper glitch filter 5. 23 1 read-write BYPASSED External tamper glitch filter 5 is bypassed. 0 ENABLED External tamper glitch filter 5 is enabled. 0x1 ETGF6 External Tamper Glitch Filter 6 Configures the length of the digital glitch filter for the external tamper 6 pin between 128 and 32640 SRTC clock cycles 24 7 read-write ETGF6_EN External Tamper Glitch Filter 6 Enable When set, enables the external tamper glitch filter 6. 31 1 read-write BYPASSED External tamper glitch filter 6 is bypassed. 0 ENABLED External tamper glitch filter 6 is enabled. 0x1 LPTGF2CR SNVS_LP Tamper Glitch Filter 2 Configuration Register 0xAC 32 read-write 0 0xFFFFFFFF ETGF7 External Tamper Glitch Filter 7 Configures the length of the digital glitch filter for the external tamper 7 pin between 128 and 32640 SRTC clock cycles 0 7 read-write ETGF7_EN External Tamper Glitch Filter 7 Enable When set, enables the external tamper glitch filter 7. 7 1 read-write BYPASSED External tamper glitch filter 7 is bypassed. 0 ENABLED External tamper glitch filter 7 is enabled. 0x1 ETGF8 External Tamper Glitch Filter 8 Configures the length of the digital glitch filter for the external tamper 8 pin between 128 and 32640 SRTC clock cycles 8 7 read-write ETGF8_EN External Tamper Glitch Filter 8 Enable When set, enables the external tamper glitch filter 8. 15 1 read-write BYPASSED External tamper glitch filter 8 is bypassed. 0 ENABLED External tamper glitch filter 8 is enabled. 0x1 ETGF9 External Tamper Glitch Filter 9 Configures the length of the digital glitch filter for the external tamper 9 pin between 128 and 32640 SRTC clock cycles 16 7 read-write ETGF9_EN External Tamper Glitch Filter 9 Enable When set, enables the external tamper glitch filter 9. 23 1 read-write BYPASSED External tamper glitch filter 9 is bypassed. 0 ENABLED External tamper glitch filter 9 is enabled. 0x1 ETGF10 External Tamper Glitch Filter 10 Configures the length of the digital glitch filter for the external tamper 10 pin between 128 and 32640 SRTC clock cycles 24 7 read-write ETGF10_EN External Tamper Glitch Filter 10 Enable When set, enables the external tamper glitch filter 10. 31 1 read-write BYPASSED External tamper glitch filter 10 is bypassed. 0 ENABLED External tamper glitch filter 10 is enabled. 0x1 LPAT1CR SNVS_LP Active Tamper 1 Configuration Register 0xC0 32 write-only 0 0xFFFFFFFF Seed Active Tamper 1 Initial Seed Default Seed is 1111h. 0 16 write-only Polynomial Active Tamper 1 Polynomial Default Polynomial is 8400h. 16 16 write-only LPAT2CR SNVS_LP Active Tamper 2 Configuration Register 0xC4 32 write-only 0 0xFFFFFFFF Seed Active Tamper 2 Initial Seed Default Seed is 2222h. 0 16 write-only Polynomial Active Tamper 2 Polynomial Default Polynomial is 9C00h. 16 16 write-only LPAT3CR SNVS_LP Active Tamper 3 Configuration Register 0xC8 32 write-only 0 0xFFFFFFFF Seed Active Tamper 3 Initial Seed Default Seed is 3333h. 0 16 write-only Polynomial Active Tamper 3 Polynomial Default Polynomial is CA00h. 16 16 write-only LPAT4CR SNVS_LP Active Tamper 4 Configuration Register 0xCC 32 write-only 0 0xFFFFFFFF Seed Active Tamper 4 Initial Seed Default Seed is 4444h. 0 16 write-only Polynomial Active Tamper 4 Polynomial Default Polynomial is 8580h. 16 16 write-only LPAT5CR SNVS_LP Active Tamper 5 Configuration Register 0xD0 32 write-only 0 0xFFFFFFFF Seed Active Tamper 5 Initial Seed Default Seed is 5555h. 0 16 write-only Polynomial Active Tamper 5 Polynomial Default Polynomial is A840h. 16 16 write-only LPATCTLR SNVS_LP Active Tamper Control Register 0xE0 32 read-write 0 0xFFFFFFFF AT1_EN Active Tamper 1 Enable When set, enables the Active Tamper 1 LFSR. 0 1 read-write DISABLED Active Tamper 1 is disabled. 0 ENABLED Active Tamper 1 is enabled. 0x1 AT2_EN Active Tamper 2 Enable When set, enables the Active Tamper 2 LFSR. 1 1 read-write DISABLED Active Tamper 2 is disabled. 0 ENABLED Active Tamper 2 is enabled. 0x1 AT3_EN Active Tamper 3 Enable When set, enables the Active Tamper 3 LFSR. 2 1 read-write DISABLED Active Tamper 3 is disabled. 0 ENABLED Active Tamper 3 is enabled. 0x1 AT4_EN Active Tamper 4 Enable When set, enables the Active Tamper 4 LFSR. 3 1 read-write DISABLED Active Tamper 4 is disabled. 0 ENABLED Active Tamper 4 is enabled. 0x1 AT5_EN Active Tamper 5 Enable When set, enables the Active Tamper 5 LFSR. 4 1 read-write DISABLED Active Tamper 5 is disabled. 0 ENABLED Active Tamper 5 is enabled. 0x1 AT1_PAD_EN Active Tamper 1 Pad Out Enable When set, enables the Active Tamper 1 external pad. 16 1 read-write DISABLED Active Tamper 1 is disabled. 0 ENABLED Active Tamper 1 is enabled. 0x1 AT2_PAD_EN Active Tamper 2 Pad Out Enable When set, enables the Active Tamper 2 external pad. 17 1 read-write DISABLED Active Tamper 2 is disabled. 0 ENABLED Active Tamper 2 is enabled. 0x1 AT3_PAD_EN Active Tamper 3 Pad Out Enable When set, enables the Active Tamper 3 external pad. 18 1 read-write DISABLED Active Tamper 3 is disabled. 0 ENABLED Active Tamper 3 is enabled 0x1 AT4_PAD_EN Active Tamper 4 Pad Out Enable When set, enables the Active Tamper 4 external pad. 19 1 read-write DISABLED Active Tamper 4 is disabled. 0 ENABLED Active Tamper 4 is enabled. 0x1 AT5_PAD_EN Active Tamper 5 Pad Out Enable When set, enables the Active Tamper 5 external pad. 20 1 read-write DISABLED Active Tamper 5 is disabled. 0 ENABLED Active Tamper 5 is enabled. 0x1 LPATCLKR SNVS_LP Active Tamper Clock Control Register 0xE4 32 read-write 0 0xFFFFFFFF AT1_CLK_CTL Active Tamper 1 Clock Control 00: 16hz 01: 8hz 10: 4hz 11: 2hz 0 2 read-write AT2_CLK_CTL Active Tamper 2 Clock Control 00: 16hz 01: 8hz 10: 4hz 11: 2hz 4 2 read-write AT3_CLK_CTL Active Tamper 3 Clock Control 00: 16hz 01: 8hz 10: 4hz 11: 2hz 8 2 read-write AT4_CLK_CTL Active Tamper 4 Clock Control 00: 16hz 01: 8hz 10: 4hz 11: 2hz 12 2 read-write AT5_CLK_CTL Active Tamper 5 Clock Control 00: 16hz 01: 8hz 10: 4hz 11: 2hz 16 2 read-write LPATRC1R SNVS_LP Active Tamper Routing Control 1 Register 0xE8 32 read-write 0 0xFFFFFFFF ET1RCTL External Tamper 1 Routing Control Any undefined selection will be routed to passive 0 3 read-write ET2RCTL External Tamper 2 Routing Control Any undefined selection will be routed to passive 4 3 read-write ET3RCTL External Tamper 3 Routing Control Any undefined selection will be routed to passive 8 3 read-write ET4RCTL External Tamper 4 Routing Control Any undefined selection will be routed to passive 12 3 read-write ET5RCTL External Tamper 5 Routing Control Any undefined selection will be routed to passive 16 3 read-write ET6RCTL External Tamper 6 Routing Control Any undefined selection will be routed to passive 20 3 read-write ET7RCTL External Tamper 7 Routing Control Any undefined selection will be routed to passive 24 3 read-write ET8RCTL External Tamper 8 Routing Control Any undefined selection will be routed to passive 28 3 read-write LPATRC2R SNVS_LP Active Tamper Routing Control 2 Register 0xEC 32 read-write 0 0xFFFFFFFF ET9RCTL External Tamper 9 Routing Control Any undefined selection will be routed to passive 0 3 read-write ET10RCTL External Tamper 10 Routing Control Any undefined selection will be routed to passive 4 3 read-write 4 0x4 LPGPR[%s] SNVS_LP General Purpose Registers 0 .. 3 0x100 32 read-write 0 0xFFFFFFFF GPR General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. 0 32 read-write HPVIDR1 SNVS_HP Version ID Register 1 0xBF8 32 read-only 0x3E0103 0xFFFFFFFF MINOR_REV SNVS block minor version number 0 8 read-only MAJOR_REV SNVS block major version number 8 8 read-only IP_ID SNVS block ID 16 16 read-only HPVIDR2 SNVS_HP Version ID Register 2 0xBFC 32 read-only 0x6000500 0xFFFFFFFF ECO_REV SNVS ECO Revision The engineering change order revision number for this release of SNVS. 8 8 read-only IP_ERA IP Era 00h - Era 1 or 2 03h - Era 3 04h - Era 4 05h - Era 5 06h - Era 6 24 8 read-only IOMUXC_SNVS IOMUXC SNVS IOMUXC_SNVS 0x40C94000 0 0x74 registers SW_MUX_CTL_PAD_WAKEUP_DIG SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register 0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT5_gpio13_IO0 Select mux mode: ALT5 mux port: GPIO13_IO00 of instance: GPIO13 0x5 ALT7_nmi_glue_NMI Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: NMI_GLUE 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad WAKEUP_DIG 0x1 SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register 0x4 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_snvs_lp_PMIC_ON_REQ Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: SNVS_LP 0 ALT5_gpio13_IO1 Select mux mode: ALT5 mux port: GPIO13_IO01 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad PMIC_ON_REQ_DIG 0x1 SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register 0x8 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_ccm_PMIC_VSTBY_REQ Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: CCM 0 ALT5_gpio13_IO2 Select mux mode: ALT5 mux port: GPIO13_IO02 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad PMIC_STBY_REQ_DIG 0x1 SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register 0xC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_SNVS_TAMPER0 Select mux mode: ALT0 mux port: SNVS_TAMPER0 of instance: SNVS_LP 0 ALT5_gpio13_IO3 Select mux mode: ALT5 mux port: GPIO13_IO03 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SNVS_00_DIG 0x1 SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register 0x10 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_SNVS_TAMPER1 Select mux mode: ALT0 mux port: SNVS_TAMPER1 of instance: SNVS_LP 0 ALT5_gpio13_IO4 Select mux mode: ALT5 mux port: GPIO13_IO04 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SNVS_01_DIG 0x1 SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register 0x14 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_SNVS_TAMPER2 Select mux mode: ALT0 mux port: SNVS_TAMPER2 of instance: SNVS_LP 0 ALT5_gpio13_IO5 Select mux mode: ALT5 mux port: GPIO13_IO05 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SNVS_02_DIG 0x1 SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register 0x18 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_SNVS_TAMPER3 Select mux mode: ALT0 mux port: SNVS_TAMPER3 of instance: SNVS_LP 0 ALT5_gpio13_IO6 Select mux mode: ALT5 mux port: GPIO13_IO06 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SNVS_03_DIG 0x1 SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register 0x1C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_SNVS_TAMPER4 Select mux mode: ALT0 mux port: SNVS_TAMPER4 of instance: SNVS_LP 0 ALT5_gpio13_IO7 Select mux mode: ALT5 mux port: GPIO13_IO07 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SNVS_04_DIG 0x1 SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register 0x20 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_SNVS_TAMPER5 Select mux mode: ALT0 mux port: SNVS_TAMPER5 of instance: SNVS_LP 0 ALT5_gpio13_IO8 Select mux mode: ALT5 mux port: GPIO13_IO08 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SNVS_05_DIG 0x1 SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register 0x24 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_SNVS_TAMPER6 Select mux mode: ALT0 mux port: SNVS_TAMPER6 of instance: SNVS_LP 0 ALT5_gpio13_IO9 Select mux mode: ALT5 mux port: GPIO13_IO09 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SNVS_06_DIG 0x1 SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register 0x28 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_SNVS_TAMPER7 Select mux mode: ALT0 mux port: SNVS_TAMPER7 of instance: SNVS_LP 0 ALT5_gpio13_IO10 Select mux mode: ALT5 mux port: GPIO13_IO10 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SNVS_07_DIG 0x1 SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register 0x2C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_SNVS_TAMPER8 Select mux mode: ALT0 mux port: SNVS_TAMPER8 of instance: SNVS_LP 0 ALT5_gpio13_IO11 Select mux mode: ALT5 mux port: GPIO13_IO11 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SNVS_08_DIG 0x1 SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register 0x30 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0_SNVS_TAMPER9 Select mux mode: ALT0 mux port: SNVS_TAMPER9 of instance: SNVS_LP 0 ALT5_gpio13_IO12 Select mux mode: ALT5 mux port: GPIO13_IO12 of instance: GPIO13 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SNVS_09_DIG 0x1 SW_PAD_CTL_PAD_TEST_MODE_DIG SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register 0x34 32 read-write 0x6 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_POR_B_DIG SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register 0x38 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_ONOFF_DIG SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register 0x3C 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_WAKEUP_DIG SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register 0x40 32 read-write 0xE 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register 0x44 32 read-write 0xA 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register 0x48 32 read-write 0xA 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register 0x4C 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register 0x50 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register 0x54 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register 0x58 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register 0x5C 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register 0x60 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register 0x64 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register 0x68 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register 0x6C 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register 0x70 32 read-write 0x2 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 1 1 read-write DSE_0_normal_driver normal driver 0 DSE_1_high_driver high driver 0x1 PUE Pull / Keep Select Field 2 1 read-write PUE_0_Disable Pull Disable 0 PUE_1_Pull Pull Enable 0x1 PUS Pull Up / Down Config. Field 3 1 read-write PUS_0_Weak_pull_down Weak pull down 0 PUS_1_Weak_pull_up Weak pull up 0x1 ODE_SNVS Open Drain SNVS Field 6 1 read-write ODE_SNVS_0_Disabled Disabled 0 ODE_SNVS_1_Enabled Enabled 0x1 DWP Domain write protection 28 2 read-write forbid_none Both cores are allowed 0 forbid_CM7 CM7 is forbidden 0x1 forbid_CM4 CM4 is forbidden 0x2 forbid_both Both cores are forbidden 0x3 DWP_LOCK Domain write protection lock 30 2 read-writeOnce lock_none Neither of DWP bits is locked 0 lock_low The lower DWP bit is locked 0x1 lock_high The higher DWP bit is locked 0x2 lock_both Both DWP bits are locked 0x3 IOMUXC_SNVS_GPR IOMUXC SNVS GPR IOMUXC_SNVS_GPR 0x40C98000 0 0x98 registers 32 0x4 GPR[%s] GPR0 General Purpose Register 0 32 read-write 0 0xFFFFFFFF GPR General purpose bits 0 32 read-write GPR32 GPR32 General Purpose Register 0x80 32 read-write 0 0xFFFFFFFF GPR General purpose bits 1 15 read-write LOCK Lock the write to bit 15:0 16 16 read-writeOnce GPR33 GPR33 General Purpose Register 0x84 32 read-write 0 0xFFFFFFFF DCDC_STATUS_CAPT_CLR DCDC captured status clear 1 1 read-write OVER No change 0 NO Clear the 3 bits of DCDC captured status: DCDC_OVER_VOL, DCDC_OVER_CUR, and DCDC_IN_LOW_VOL 0x1 SNVS_BYPASS_EN SNVS LDO_SNVS_ANA bypass enable 2 1 read-write NO Disable bypass 0 OVER Enable bypass 0x1 DCDC_IN_LOW_VOL DCDC_IN low voltage detect 16 1 read-only NO Voltage on DCDC_IN is higher than 2.6V 0 OVER Voltage on DCDC_IN is lower than 2.6V 0x1 DCDC_OVER_CUR DCDC output over current alert 17 1 read-only NO No Overcurrent on DCDC output 0 OVER Overcurrent on DCDC output 0x1 DCDC_OVER_VOL DCDC output over voltage alert 18 1 read-only NO No Overvoltage on DCDC VDDLP0 or VDDLP8 output 0 OVERVOLTAGE Overvoltage on DCDC VDDLP0 or VDDLP8 output 0x1 DCDC_STS_DC_OK DCDC status OK 19 1 read-only DISABLE DCDC is settling 0 ENABLE DCDC already settled 0x1 SNVS_XTAL_CLK_OK 32K OSC ok flag 20 1 read-only UNSTABLE 32K oscillator is NOT stable into normal operation 0 STABLE 32K oscillator is stable into normal operation 0x1 GPR34 GPR34 General Purpose Register 0x88 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce OVER1 Write access is not blocked 0 NO1 Write access is blocked 0x1 SNVS_CORE_VOLT_DET_TRIM_SEL SNVS core voltage detect trim select 1 1 read-write OVER1 The trimming codes are selected from eFuse 0 NO1 The trimming codes of core voltage detectors used to change the voltage falling trip point are selected from SNVS_CORE_VOLT_DET_TRIM 0x1 SNVS_CORE_VOLT_DET_TRIM SNVS core voltage detect trim 2 2 read-write SNVS_CLK_DET_TRIM_SEL SNVS clock detect trim select 7 1 read-write OVER1 The trimming codes are selected from eFuse 0 NO1 The trimming codes of clock detector used to change the boundary frequencies are selected from SNVS_CLK_DET_TRIM 0x1 SNVS_CLK_DET_TRIM SNVS clock detect trim bits 8 8 read-write SNVS_CLK_DET_OFFSET_HIGH SNVS clock detect offset of high boundary frequency 16 2 read-write OVER No change (Default) 0 NO Add +5 to the Trim 0x1 OVER1 Add +10 to the trim 0x2 NO1 Add -5 to the Trim 0x3 SNVS_CLK_DET_OFFSET_LOW SNVS clock detect offset of low boundary frequency 18 2 read-write OVER No change (Default) 0 NO Add +5 to the Trim 0x1 OVER1 Add +10 to the trim 0x2 NO1 Add -5 to the Trim 0x3 SNVS_CAP_TRIM_SEL SNVS OSC load capacitor trim select 23 1 read-write OVER The trimming codes are selected from eFuse 0 NO The trimming codes are used from SNVS_OSC_CAP_TRIM (osc32k's load capacitor) 0x1 SNVS_OSC_CAP_TRIM SNVS OSC load capacitor trim 24 4 read-write GPR35 GPR35 General Purpose Register 0x8C 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce OVER1 Write access is not blocked 0 NO1 Write access is blocked 0x1 SNVS_VOLT_DET_TRIM_SEL SNVS voltage detect trim select 3 1 read-write OVER1 The trimming codes are selected from eFuse 0 NO1 The trimming codes of voltage detectors to change the voltage boundaries in battery voltage detecting are selected from SNVS_VOLT_DET_TRIM 0x1 SNVS_VOLT_DET_TRIM SNVS voltage detect trim 4 8 read-write SNVS_TEMP_DET_TRIM_SEL SNVS temperature detect trim select 15 1 read-write OVER1 The trimming codes are selected from eFuse 0 NO1 The trimming codes to define the temperature boundaries of temperature detector are selected from SNVS_TEMP_DET_TRIM 0x1 SNVS_TEMP_DET_TRIM SNVS temperature detect trim 16 12 read-write SNVS_TEMP_DET_OFFSET_HIGH SNVS temperature detect offset of high temperature boundary 28 2 read-write OVER No change (Default) 0 NO Add +5 to the Trim 0x1 OVER1 Add +10 to the trim 0x2 NO1 Add -5 to the Trim 0x3 SNVS_TEMP_DET_OFFSET_LOW SNVS temperature detect offset of low temperature boundary 30 2 read-write OVER No change (Default) 0 NO Add +5 to the Trim 0x1 OVER1 Add +10 to the trim 0x2 NO1 Add -5 to the Trim 0x3 GPR36 GPR36 General Purpose Register 0x90 32 read-write 0x4800000 0xFFFFFFFF SNVSDIG_SNVS1P8_ISO_EN SNVS RAM isolation enable bit 23 1 read-write DIS Enable SRAM access (It should be cleared after LDO_SNVS_DIG and SNVS SRAM peripheral power is back) 0 EN Enable the isolation to avoid extra leakage power before SNVS SRAM peripheral power or LDO_SNVS_DIG is switched off 0x1 SNVS_SRAM_SLEEP SNVS SRAM power-down enable bit 26 1 read-write DIS Enable SRAM access (It should be cleared after LDO_SNVS_DIG is enabled) 0 EN SNVS SRAM can go in Shutdown/ Periphery Off Array On/ Periphery On Array Off mode. In addition, this bit ensures power-up without stuck-at /high DC current states and hence must be held to 1 during wake-up, so this bit is default high. 0x1 SNVS_SRAM_STDBY SNVS SRAM standby enable bit 27 1 read-write No SNVS SRAM does not enter low leakage state 0 DISABLE SNVS SRAM enters low leakage state and large drivers are switched OFF 0x1 SNVS_SRAM_PSWLARGEMP_FORCE SNVS SRAM large switch control bit for peripheral 28 1 read-write No Switch on SNVS SRAM power for peripheral 0 DISABLE Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) 0x1 SNVS_SRAM_PSWLARGE SNVS SRAM large switch control bit 29 1 read-write No Switch on SNVS SRAM power for peripheral and array 0 DISABLE Switch off SNVS SRAM power for peripheral and array 0x1 SNVS_SRAM_PSWSMALLMP_FORCE SNVS SRAM small switch control bit for peripheral 30 1 read-write No Switch on SNVS SRAM power for peripheral 0 DISABLE Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) 0x1 SNVS_SRAM_PSWSMALL SNVS SRAM small switch control bit 31 1 read-write No Switch on SNVS SRAM power for peripheral and array 0 DISABLE Switch off SNVS SRAM power for peripheral and array 0x1 GPR37 GPR37 General Purpose Register 0x94 32 read-write 0 0xFFFFFFFF LOCK Lock the write to bit 31:1 0 1 read-writeOnce OVER1 Write access is not blocked 0 NO1 Write access is blocked 0x1 SNVS_TAMPER_PUE SNVS tamper detect pin pull enable bit 1 10 read-write SNVS_TAMPER_PUS SNVS tamper detect pin pull selection bit 11 10 read-write SRAM Secure RAM SRAM 0x40C9C000 0 0x3004 registers CTRL Control Register 0x3000 32 read-write 0 0xFFFFFFFF RAM_RD_EN RAM Read Enable (with lock) 0 1 read-write DISABLE Disable read access 0 ENABLE Enable read access 0x1 RAM_WR_EN RAM Write Enable (with lock) 1 1 read-write DISABLE Disable write access 0 ENABLE Enable write access 0x1 PWR_EN Power Enable (with lock) 2 4 read-write TAMPER_BLOCK_EN Tamper Block Enable (with lock) 6 1 read-write ACCESS Allow R/W access to secure RAM when tamper is detected 0 BLOCK Block R/W access to secure RAM when tamper is detected 0x1 TAMPER_PWR_OFF_EN Turn off power on tamper event (with lock) 7 1 read-write OFF Disable the turn off function when tamper is detected 0 ON Turn off power for all secure RAM banks when tamper is detected 0x1 LOCK_BIT Lock bits 16 8 read-write DCDC DCDC DCDC 0x40CA8000 0 0x70 registers CTRL0 DCDC Control Register 0 0 32 read-write 0x3 0xFFFFFFFF ENABLE DCDC Enable 0 1 read-write disable Disable (Bypass) 0 enable Enable 0x1 DIG_EN Enable the DCDC_DIG switching converter output 1 1 read-write enable Enable 0x1 STBY_EN DCDC standby mode enable 2 1 read-write enable Enter into standby mode 0x1 LP_MODE_EN DCDC low-power (LP) mode enable DCDC can't start up directly into LP mode 3 1 read-write enable Enter into low-power mode 0x1 STBY_LP_MODE_EN DCDC low-power mode enable by GPC standby request 4 1 read-write disable Disable DCDC entry into low-power mode from a GPC standby request 0 enable Enable DCDC to enter into low-power mode from a GPC standby request 0x1 ENABLE_DCDC_CNT Enable internal count for DCDC_OK timeout 5 1 read-write wait Wait DCDC_OK for ACK 0 enable_count Enable internal count for DCDC_OK timeout 0x1 TRIM_HOLD Hold trim input 6 1 read-write sample Sample trim input 0 hold Hold trim input 0x1 DEBUG_BITS DEBUG_BITS[11:0] 19 12 read-write CONTROL_MODE Control mode 31 1 read-write swctrl Software control mode 0 gpc Hardware control mode (controlled by GPC Setpoints) 0x1 CTRL1 DCDC Control Register 1 0x4 32 read-write 0xF0B100C 0xFFFFFFFF VDD1P8CTRL_TRG Target value of VDD1P8 in buck mode, 25mV each step from 0x00 to 0x1F: 0 5 read-write v1p5 1.5V 0 v1p8 1.8V 0xC v2p275 2.275V 0x1F VDD1P0CTRL_TRG Target value of VDD1P0 in buck mode, 25mV each step from 0x00 to 0x1F: 8 5 read-write v0p6 0.6V 0 v1p0 1.0V 0x10 v1p375 1.375V 0x1F VDD1P8CTRL_STBY_TRG Target value of VDD1P8 in standby mode, 25mV each step from 0x00 to 0x1F: 16 5 read-write v1p525 1.525V 0 v1p8 1.8V 0xB v2p4 2.3V 0x1F VDD1P0CTRL_STBY_TRG Target value of VDD1P0 in standby mode, 25mV each step from 0x00 to 0x1F: 24 5 read-write v0p625 0.625V 0 v1p0 1.0V 0xF v1p4 1.4V 0x1F REG0 DCDC Register 0 0x8 32 read-write 0x4030511 0xFFFFFFFF PWD_ZCD Power Down Zero Cross Detection 0 1 read-write powered_up Zero cross detetion function powered up 0 powered_down Zero cross detetion function powered down 0x1 DISABLE_AUTO_CLK_SWITCH Disable Auto Clock Switch 1 1 read-write xtal_clk If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal ring oscillator to 24M xtal automatically 0 sel_clk If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses 0x1 SEL_CLK Select Clock 2 1 read-write int_rng_osc DCDC uses internal ring oscillator 0 xtal_24M DCDC uses 24M xtal 0x1 PWD_OSC_INT Power down internal ring oscillator 3 1 read-write powered_up Internal ring oscillator powered up 0 powered_down Internal ring oscillator powered down 0x1 PWD_CUR_SNS_CMP Power down signal of the current detector 4 1 read-write powered_up Current Detector powered up 0 powered_down Current Detector powered down 0x1 CUR_SNS_THRSH Current Sense (detector) Threshold 5 3 read-write PWD_OVERCUR_DET Power down overcurrent detection comparator 8 1 read-write enabled Overcurrent detection comparator is enabled 0 disabled Overcurrent detection comparator is disabled 0x1 PWD_CMP_DCDC_IN_DET Set to "1" to power down the low voltage detection comparator 11 1 read-write enabled Low voltage detection comparator is enabled 0 disabled Low voltage detection comparator is disabled 0x1 PWD_HIGH_VDD1P8_DET Power Down High Voltage Detection for VDD1P8 16 1 read-write enabled Overvoltage detection comparator for the VDD1P8 output is enabled 0 disabled Overvoltage detection comparator for the VDD1P8 output is disabled 0x1 PWD_HIGH_VDD1P0_DET Power Down High Voltage Detection for VDD1P0 17 1 read-write enabled Overvoltage detection comparator for the VDD1P0 output is enabled 0 disabled Overvoltage detection comparator for the VDD1P0 output is disabled 0x1 LP_HIGH_HYS Low Power High Hysteric Value 21 1 read-write lp_12p5mV Adjust hysteretic value in low power to 12.5mV 0 lp_25mV Adjust hysteretic value in low power to 25mV 0x1 PWD_CMP_OFFSET power down the out-of-range detection comparator 26 1 read-write powered_up Out-of-range comparator powered up 0 powered_down Out-of-range comparator powered down 0x1 XTALOK_DISABLE Disable xtalok detection circuit 27 1 read-write enabled Enable xtalok detection circuit 0 disabled Disable xtalok detection circuit and always outputs OK signal "1" 0x1 XTAL_24M_OK 24M XTAL OK 29 1 read-write int_rng_osc DCDC uses internal ring oscillator 0 xtal_24M DCDC uses xtal 24M 0x1 STS_DC_OK DCDC Output OK 31 1 read-only not_settled DCDC is settling 0 settled DCDC already settled 0x1 REG1 DCDC Register 1 0xC 32 read-write 0x1CD5430 0xFFFFFFFF DM_CTRL DM Control 3 1 read-write DM_CTRL_0 No change to ripple when the discontinuous current is present in DCM. 0 DM_CTRL_1 Improves ripple when the inductor current goes to zero in DCM. 0x1 RLOAD_REG_EN_LPSR Load Resistor Enable 4 1 read-write loadR_disconnect Disconnect load resistor 0 loadR_connect Connect load resistor 0x1 VBG_TRIM Trim Bandgap Voltage 6 5 read-write minvolt 0.452V 0 default 0.5V 0x10 maxvolt 0.545V 0x1F LP_CMP_ISRC_SEL Low Power Comparator Current Bias 11 2 read-write sel0 50nA 0 sel1 100nA 0x1 sel2 200nA 0x2 sel3 400nA 0x3 LOOPCTRL_CM_HST_THRESH Increase Threshold Detection 27 1 read-write LOOPCTRL_DF_HST_THRESH Increase Threshold Detection 28 1 read-write LOOPCTRL_EN_CM_HYST Enable hysteresis in switching converter common mode analog comparators 29 1 read-write disable Disable hysteresis in switching converter common mode analog comparators 0 enable Enable hysteresis in switching converter common mode analog comparators 0x1 LOOPCTRL_EN_DF_HYST Enable hysteresis in switching converter differential mode analog comparators 30 1 read-write disable Disable hysteresis in switching converter differential mode analog comparators 0 enable Enable hysteresis in switching converter differential mode analog comparators 0x1 REG2 DCDC Register 2 0x10 32 read-write 0x2108089 0xFFFFFFFF LOOPCTRL_DC_C Ratio of integral control parameter to proportional control parameter in the switching DCDC converter, and can be used to optimize efficiency and loop response 0 2 read-write LOOPCTRL_DC_R Magnitude of proportional control parameter in the switching DCDC converter control loop. 2 4 read-write LOOPCTRL_DC_FF Two's complement feed forward step in duty cycle in the switching DCDC converter 6 3 read-write LOOPCTRL_EN_RCSCALE Enable RC Scale 9 3 read-write LOOPCTRL_RCSCALE_THRSH Increase the threshold detection for RC scale circuit. 12 1 read-write LOOPCTRL_HYST_SIGN Invert the sign of the hysteresis in DCDC analog comparators. 13 1 read-write BATTMONITOR_EN_BATADJ This bit enables the DCDC to improve efficiency and minimize ripple using the information from the BATT_VAL field 15 1 read-write BATTMONITOR_BATT_VAL Software should be configured to place the battery voltage in this register measured with an 8-mV LSB resolution through the ADC 16 10 read-write DCM_SET_CTRL DCM Set Control 28 1 read-write LOOPCTRL_TOGGLE_DIF Set high to enable supply stepping to change only after the differential control loop has toggled as well 30 1 read-write REG3 DCDC Register 3 0x14 32 read-write 0x980000 0xFFFFFFFF IN_BROWNOUT signal "1" when the voltage on DCDC_IN is lower than 2.6V 14 1 read-only brownout DCDC_IN is lower than 2.6V 0x1 OVERVOLT_VDD1P8_DET_OUT signal "1" when overvoltage on the VDD1P8 output happens 15 1 read-only overvoltage_1p8 VDD1P8 Overvoltage 0x1 OVERVOLT_VDD1P0_DET_OUT signal "1" when overvoltage on the VDD1P0 output happens 16 1 read-only overvoltage_1p0 VDD1P0 Overvoltage 0x1 OVERCUR_DETECT_OUT signal "1" when overcurrent happens. 17 1 read-only overcurrent_signal Overcurrent 0x1 ENABLE_FF no description available 18 1 read-write enable_ff Enable feed-forward (FF) function that can speed up transient settling. 0x1 DISABLE_PULSE_SKIP Disable Pulse Skip 19 1 read-write stopcharge Stop charging if the duty cycle is lower than what is set by NEGLIMIT_IN 0 DISABLE_IDLE_SKIP no description available 20 1 read-write enable Enable the idle skip function. The DCDC will be idle when out-of-range comparator detects the output voltage is higher than the target by 25mV. This function requires the out-of-range comparator to be enabled (PWD_CMP_OFFSET=0). 0 DOUBLE_IBIAS_CMP_LP_LPSR no description available 21 1 read-write doublebias Double the bias current of the comparator for low-voltage detector in LP (low-power) mode 0x1 REG_FBK_SEL Select the feedback point of the internal regulator 22 2 read-write MINPWR_DC_HALFCLK Set DCDC clock to half freqeuncy for continuous mode. 24 1 read-write fullfreq DCDC clock remains at full frequency for continuous mode 0 halffreq DCDC clock set to half frequency for continuous mode 0x1 MINPWR_HALF_FETS Use half switch FET 26 1 read-write MISC_DELAY_TIMING Miscellaneous Delay Timing 27 1 read-write VDD1P0CTRL_DISABLE_STEP Disable Step for VDD1P0 29 1 read-write enable Enable stepping for VDD1P0 0 disable Disable stepping for VDD1P0 0x1 VDD1P8CTRL_DISABLE_STEP Disable Step for VDD1P8 30 1 read-write enable Enable stepping for VDD1P8 0 disable Disable stepping for VDD1P8 0x1 REG4 DCDC Register 4 0x18 32 read-write 0 0xFFFFFFFF ENABLE_SP Configures CTRL0[ENABLE] (DCDC Enable) for Setpoints 0-15 0 16 read-write REG5 DCDC Register 5 0x1C 32 read-write 0 0xFFFFFFFF DIG_EN_SP Configures CTRL0[DIG_EN] (DCDC_DIG Enable) for Setpoints 0-15. Always set these bits to 1. 0 16 read-write REG6 DCDC Register 6 0x20 32 read-write 0 0xFFFFFFFF LP_MODE_SP Configures CTRL0[LP_MODE_EN] (LP Mode Enable) for Setpoints 0-15 0 16 read-write REG7 DCDC Register 7 0x24 32 read-write 0 0xFFFFFFFF STBY_EN_SP Configures CTRL0[STBY_EN] (Standby Enable) for Setpoints 0-15 0 16 read-write REG7P DCDC Register 7 plus 0x28 32 read-write 0 0xFFFFFFFF STBY_LP_MODE_SP Configures CTRL0[STBY_LP_MODE_EN] (LP Mode via GPC Enable) for Setpoints 0-15 0 16 read-write REG8 DCDC Register 8 0x2C 32 read-write 0 0xFFFFFFFF ANA_TRG_SP0 Configures CTRL1[VDD1P8CTRL_TRG] FOR Setpoints 0-3 0 32 read-write REG9 DCDC Register 9 0x30 32 read-write 0 0xFFFFFFFF ANA_TRG_SP1 Configures CTRL1[VDD1P8CTRL_TRG] FOR Setpoints 4-7 0 32 read-write REG10 DCDC Register 10 0x34 32 read-write 0 0xFFFFFFFF ANA_TRG_SP2 Configures CTRL1[VDD1P8CTRL_TRG] FOR Setpoints 8-11 0 32 read-write REG11 DCDC Register 11 0x38 32 read-write 0 0xFFFFFFFF ANA_TRG_SP3 Configures CTRL1[VDD1P8CTRL_TRG] FOR Setpoints 12-15 0 32 read-write REG12 DCDC Register 12 0x3C 32 read-write 0 0xFFFFFFFF DIG_TRG_SP0 Configures CTRL1[VDD1P0CTRL_TRG] FOR Setpoints 0-3 0 32 read-write REG13 DCDC Register 13 0x40 32 read-write 0 0xFFFFFFFF DIG_TRG_SP1 Configures CTRL1[VDD1P0CTRL_TRG] FOR Setpoints 4-7 0 32 read-write REG14 DCDC Register 14 0x44 32 read-write 0 0xFFFFFFFF DIG_TRG_SP2 Configures CTRL1[VDD1P0CTRL_TRG] FOR Setpoints 8-11 0 32 read-write REG15 DCDC Register 15 0x48 32 read-write 0 0xFFFFFFFF DIG_TRG_SP3 Configures CTRL1[VDD1P0CTRL_TRG] FOR Setpoints 12-15 0 32 read-write REG16 DCDC Register 16 0x4C 32 read-write 0 0xFFFFFFFF ANA_STBY_TRG_SP0 Configures CTRL1[VDD1P8CTRL_STBY_TRG] FOR Setpoints 0-3 0 32 read-write REG17 DCDC Register 17 0x50 32 read-write 0 0xFFFFFFFF ANA_STBY_TRG_SP1 Configures CTRL1[VDD1P8CTRL_STBY_TRG] FOR Setpoints 4-7 0 32 read-write REG18 DCDC Register 18 0x54 32 read-write 0 0xFFFFFFFF ANA_STBY_TRG_SP2 Configures CTRL1[VDD1P8CTRL_STBY_TRG] FOR Setpoints 8-11 0 32 read-write REG19 DCDC Register 19 0x58 32 read-write 0 0xFFFFFFFF ANA_STBY_TRG_SP3 Configures CTRL1[VDD1P8CTRL_STBY_TRG] FOR Setpoints 12-15 0 32 read-write REG20 DCDC Register 20 0x5C 32 read-write 0 0xFFFFFFFF DIG_STBY_TRG_SP0 Configures CTRL1[VDD1P0CTRL_STBY_TRG] FOR Setpoints 0-3 0 32 read-write REG21 DCDC Register 21 0x60 32 read-write 0 0xFFFFFFFF DIG_STBY_TRG_SP1 Configures CTRL1[VDD1P0CTRL_STBY_TRG] FOR Setpoints 4-7 0 32 read-write REG22 DCDC Register 22 0x64 32 read-write 0 0xFFFFFFFF DIG_STBY_TRG_SP2 Configures CTRL1[VDD1P0CTRL_STBY_TRG] FOR Setpoints 8-11 0 32 read-write REG23 DCDC Register 23 0x68 32 read-write 0 0xFFFFFFFF DIG_STBY_TRG_SP3 Configures CTRL1[VDD1P0CTRL_STBY_TRG] FOR Setpoints 12-15 0 32 read-write REG24 DCDC Register 24 0x6C 32 read-write 0x100000 0xFFFFFFFF OK_COUNT Internal count for dcdc_ok timeout 0 32 read-write OCOTP no description available OCOTP 0x40CAC000 0 0x10F4 registers OCOTP_READ_FUSE_ERROR 115 OCOTP_READ_DONE_ERROR 116 CTRL OTP Controller Control and Status Register 0 32 read-write 0 0xFFFFFFFF ADDR OTP write and read access address register 0 10 read-write supp_word Address of one of the 16 supplementary fuse words in OTP memory. 0 supp_word Address of one of the 16 supplementary fuse words in OTP memory. 0x1 supp_word Address of one of the 16 supplementary fuse words in OTP memory. 0x2 supp_word Address of one of the 16 supplementary fuse words in OTP memory. 0x3 supp_word Address of one of the 16 supplementary fuse words in OTP memory. 0x4 supp_word Address of one of the 16 supplementary fuse words in OTP memory. 0x5 supp_word Address of one of the 16 supplementary fuse words in OTP memory. 0x6 supp_word Address of one of the 16 supplementary fuse words in OTP memory. 0x7 supp_word Address of one of the 16 supplementary fuse words in OTP memory. 0x8 supp_word Address of one of the 16 supplementary fuse words in OTP memory. 0x9 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x10 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x11 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x12 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x13 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x14 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x15 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x16 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x17 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x18 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x19 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x1A user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x1B user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x1C user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x1D user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x1E user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x1F user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x20 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x21 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x22 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x23 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x24 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x25 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x26 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x27 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x28 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x29 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x2A user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x2B user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x2C user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x2D user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x2E user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x2F user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x30 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x31 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x32 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x33 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x34 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x35 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x36 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x37 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x38 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x39 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x3A user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x3B user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x3C user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x3D user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x3E user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x3F user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x40 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x41 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x42 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x43 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x44 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x45 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x46 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x47 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x48 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x49 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x4A user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x4B user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x4C user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x4D user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x4E user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x4F user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x50 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x51 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x52 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x53 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x54 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x55 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x56 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x57 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x58 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x59 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x5A user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x5B user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x5C user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x5D user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x5E user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x5F user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x60 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x61 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x62 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x63 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x64 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x65 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x66 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x67 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x68 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x69 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x6A user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x6B user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x6C user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x6D user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x6E user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x6F user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x70 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x71 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x72 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x73 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x74 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x75 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x76 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x77 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x78 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x79 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x7A user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x7B user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x7C user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x7D user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x7E user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x7F user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x80 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x81 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x82 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x83 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x84 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x85 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x86 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x87 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x88 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x89 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x8A user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x8B user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x8C user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x8D user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x8E user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x8F user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x90 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x91 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x92 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x93 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x94 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x95 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x96 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x97 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x98 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x99 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x9A user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x9B user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x9C user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x9D user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x9E user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x9F user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xA0 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xA1 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xA2 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xA3 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xA4 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xA5 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xA6 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xA7 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xA8 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xA9 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xAA user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xAB user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xAC user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xAD user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xAE user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xAF user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xB0 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xB1 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xB2 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xB3 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xB4 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xB5 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xB6 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xB7 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xB8 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xB9 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xBA user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xBB user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xBC user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xBD user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xBE user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xBF user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xC0 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xC1 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xC2 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xC3 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xC4 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xC5 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xC6 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xC7 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xC8 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xC9 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xCA user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xCB user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xCC user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xCD user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xCE user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xCF user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xD0 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xD1 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xD2 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xD3 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xD4 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xD5 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xD6 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xD7 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xD8 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xD9 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xDA user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xDB user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xDC user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xDD user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xDE user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xDF user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xE0 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xE1 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xE2 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xE3 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xE4 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xE5 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xE6 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xE7 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xE8 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xE9 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xEA user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xEB user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xEC user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xED user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xEE user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xEF user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xF0 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xF1 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xF2 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xF3 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xF4 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xF5 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xF6 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xF7 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xF8 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xF9 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xFA user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xFB user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xFC user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xFD user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xFE user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0xFF user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x100 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x101 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x102 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x103 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x104 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x105 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x106 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x107 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x108 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x109 user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x10A user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x10B user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x10C user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x10D user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x10E user_fuse_word Address of one of the 256 user fuse words in OTP memory. 0x10F BUSY OTP controller status bit 10 1 read-only not_busy No write or read access to OTP started. 0 busy Write or read access to OTP started. 0x1 ERROR Locked Region Access Error 11 1 read-write no_error No error. 0 error Error - access to a locked region requested. 0x1 RELOAD_SHADOWS Reload Shadow Registers 12 1 read-write shadow_noforce_reload Do not force shadow register re-load. 0 shadow_force_reload Force shadow register re-load. This bit is cleared automatically after shadow registers are re-loaded. 0x1 WORDLOCK Lock fuse word 15 1 read-write NO_CHANGE No change to LOCK bit when programming a word using redundancy 0 LOCK LOCK bit for fuse word will be set after successfully programming a word using redundancy 0x1 WR_UNLOCK Write unlock 16 16 read-write otp_w_locked OTP write access is locked. 0 otp_w_unlocked OTP write access is unlocked. 0x3E77 CTRL_SET OTP Controller Control and Status Register 0x4 32 read-write 0 0xFFFFFFFF oneToSet ADDR OTP write and read access address register 0 10 read-write oneToSet BUSY OTP controller status bit 10 1 read-only oneToSet ERROR Locked Region Access Error 11 1 read-write oneToSet RELOAD_SHADOWS Reload Shadow Registers 12 1 read-write oneToSet WORDLOCK Lock fuse word 15 1 read-write oneToSet WR_UNLOCK Write unlock 16 16 read-write oneToSet CTRL_CLR OTP Controller Control and Status Register 0x8 32 read-write 0 0xFFFFFFFF oneToClear ADDR OTP write and read access address register 0 10 read-write oneToClear BUSY OTP controller status bit 10 1 read-only oneToClear ERROR Locked Region Access Error 11 1 read-write oneToClear RELOAD_SHADOWS Reload Shadow Registers 12 1 read-write oneToClear WORDLOCK Lock fuse word 15 1 read-write oneToClear WR_UNLOCK Write unlock 16 16 read-write oneToClear CTRL_TOG OTP Controller Control and Status Register 0xC 32 read-write 0 0xFFFFFFFF oneToToggle ADDR OTP write and read access address register 0 10 read-write oneToToggle BUSY OTP controller status bit 10 1 read-only oneToToggle ERROR Locked Region Access Error 11 1 read-write oneToToggle RELOAD_SHADOWS Reload Shadow Registers 12 1 read-write oneToToggle WORDLOCK Lock fuse word 15 1 read-write oneToToggle WR_UNLOCK Write unlock 16 16 read-write oneToToggle PDN OTP Controller PDN Register 0x10 32 read-write 0 0xFFFFFFFF oneToClear PDN PDN value 0 1 read-write oneToClear power_off OTP memory is not powered 0 power_on OTP memory is powered 0x1 DATA OTP Controller Write Data Register 0x20 32 read-write 0 0xFFFFFFFF DATA Data 0 32 read-write READ_CTRL OTP Controller Read Control Register 0x30 32 read-write 0 0xFFFFFFFF READ_FUSE Read Fuse 0 1 read-write DO_NOT_START_RD_OP Do not initiate a read from OTP 0 START_RD_OP Initiate a read from OTP 0x1 READ_FUSE_CNTR Number of words to read. 1 2 read-write ONE_WORD 1 word 0 TWO_WORDS 2 words 0x1 THREE_WORDS 3 words 0x2 FOUR_WORDS 4 words 0x3 READ_FUSE_DONE_INTR_ENA Enable read-done interrupt 3 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 READ_FUSE_ERROR_INTR_ENA Enable read-error interrupt 4 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 OUT_STATUS 8K OTP Memory STATUS Register 0x90 32 read-write 0 0xFFFFFFFF SEC Single Error Correct 9 1 read-write DED Double error detect 10 1 read-write LOCKED Word Locked 11 1 read-write PROGFAIL Programming failed 12 1 read-write ACK Acknowledge 13 1 read-only PWOK Power OK 14 1 read-only FLAGSTATE Flag state 15 4 read-only SEC_RELOAD Indicates single error correction occured on reload 19 1 read-write DED_RELOAD Indicates double error detection occured on reload 20 1 read-write CALIBRATED Calibrated status 21 1 read-only READ_DONE_INTR Read fuse done 22 1 read-write READ_ERROR_INTR Fuse read error 23 1 read-write no_error Read operation finished with out any error 0 error Read operation finished with an error 0x1 DED0 Double error detect 24 1 read-write DED1 Double error detect 25 1 read-write DED2 Double error detect 26 1 read-write DED3 Double error detect 27 1 read-write OUT_STATUS_SET 8K OTP Memory STATUS Register 0x94 32 read-write 0 0xFFFFFFFF oneToSet SEC Single Error Correct 9 1 read-write oneToSet DED Double error detect 10 1 read-write oneToSet LOCKED Word Locked 11 1 read-write oneToSet PROGFAIL Programming failed 12 1 read-write oneToSet ACK Acknowledge 13 1 read-only oneToSet PWOK Power OK 14 1 read-only oneToSet FLAGSTATE Flag state 15 4 read-only oneToSet SEC_RELOAD Indicates single error correction occured on reload 19 1 read-write oneToSet DED_RELOAD Indicates double error detection occured on reload 20 1 read-write oneToSet CALIBRATED Calibrated status 21 1 read-only oneToSet READ_DONE_INTR Read fuse done 22 1 read-write oneToSet READ_ERROR_INTR Fuse read error 23 1 read-write oneToSet DED0 Double error detect 24 1 read-write oneToSet DED1 Double error detect 25 1 read-write oneToSet DED2 Double error detect 26 1 read-write oneToSet DED3 Double error detect 27 1 read-write oneToSet OUT_STATUS_CLR 8K OTP Memory STATUS Register 0x98 32 read-write 0 0xFFFFFFFF oneToClear SEC Single Error Correct 9 1 read-write oneToClear DED Double error detect 10 1 read-write oneToClear LOCKED Word Locked 11 1 read-write oneToClear PROGFAIL Programming failed 12 1 read-write oneToClear ACK Acknowledge 13 1 read-only oneToClear PWOK Power OK 14 1 read-only oneToClear FLAGSTATE Flag state 15 4 read-only oneToClear SEC_RELOAD Indicates single error correction occured on reload 19 1 read-write oneToClear DED_RELOAD Indicates double error detection occured on reload 20 1 read-write oneToClear CALIBRATED Calibrated status 21 1 read-only oneToClear READ_DONE_INTR Read fuse done 22 1 read-write oneToClear READ_ERROR_INTR Fuse read error 23 1 read-write oneToClear DED0 Double error detect 24 1 read-write oneToClear DED1 Double error detect 25 1 read-write oneToClear DED2 Double error detect 26 1 read-write oneToClear DED3 Double error detect 27 1 read-write oneToClear OUT_STATUS_TOG 8K OTP Memory STATUS Register 0x9C 32 read-write 0 0xFFFFFFFF oneToToggle SEC Single Error Correct 9 1 read-write oneToToggle DED Double error detect 10 1 read-write oneToToggle LOCKED Word Locked 11 1 read-write oneToToggle PROGFAIL Programming failed 12 1 read-write oneToToggle ACK Acknowledge 13 1 read-only oneToToggle PWOK Power OK 14 1 read-only oneToToggle FLAGSTATE Flag state 15 4 read-only oneToToggle SEC_RELOAD Indicates single error correction occured on reload 19 1 read-write oneToToggle DED_RELOAD Indicates double error detection occured on reload 20 1 read-write oneToToggle CALIBRATED Calibrated status 21 1 read-only oneToToggle READ_DONE_INTR Read fuse done 22 1 read-write oneToToggle READ_ERROR_INTR Fuse read error 23 1 read-write oneToToggle DED0 Double error detect 24 1 read-write oneToToggle DED1 Double error detect 25 1 read-write oneToToggle DED2 Double error detect 26 1 read-write oneToToggle DED3 Double error detect 27 1 read-write oneToToggle VERSION OTP Controller Version Register 0xB0 32 read-only 0xA000000 0xFFFFFFFF STEP RTL Version Stepping 0 16 read-only MINOR Minor RTL Version 16 8 read-only MAJOR Major RTL Version 24 8 read-only READ_FUSE_DATA0 OTP Controller Read Data 0 Register 0x100 32 read-write 0 0xFFFFFFFF DATA Data 0 32 read-write READ_FUSE_DATA1 OTP Controller Read Data 1 Register 0x110 32 read-write 0 0xFFFFFFFF DATA Data 0 32 read-write READ_FUSE_DATA2 OTP Controller Read Data 2 Register 0x120 32 read-write 0 0xFFFFFFFF DATA Data 0 32 read-write READ_FUSE_DATA3 OTP Controller Read Data 3 Register 0x130 32 read-write 0 0xFFFFFFFF DATA Data 0 32 read-write SW_LOCK SW_LOCK Register 0x140 32 read-write 0 0xFFFFFFFF SW_LOCK This register contains lock information, which has the same function as the RLOCK fuse words (supplementary fuse words 8 (0x880) and 9 (0x890)) in fuse memory 0 32 read-write BIT_LOCK BIT_LOCK Register 0x150 32 read-write 0 0xFFFFFFFF BIT_LOCK Each bit controls the corresponding bit in supplementary fuse word 13 and its shadow register 0 32 read-write LOCKED0 OTP Controller Program Locked Status 0 Register 0x600 32 read-only 0 0xFFFFFFFF LOCKED Stores program locked status for fuse words 0-15. 0 16 read-only LOCKED1 OTP Controller Program Locked Status 1 Register 0x610 32 read-only 0 0xFFFFFFFF LOCKED Stores program locked status for fuse words 16-47 0 32 read-only LOCKED2 OTP Controller Program Locked Status 2 Register 0x620 32 read-only 0 0xFFFFFFFF LOCKED Stores program locked status for fuse words 48-79 0 32 read-only LOCKED3 OTP Controller Program Locked Status 3 Register 0x630 32 read-only 0 0xFFFFFFFF LOCKED Stores program locked status for fuse words 80-111 0 32 read-only LOCKED4 OTP Controller Program Locked Status 4 Register 0x640 32 read-only 0 0xFFFFFFFF LOCKED Stores program locked status for fuse words 112-143 0 32 read-only 144 0x10 FUSEn[%s] no description available 0x800 FUSE Value of fuse word index 0 32 read-only 0 0xFFFFFFFF BITS Reflects value of the fuse word 0 32 read-only SSARC_HP SRAM Registers SSARC_HP 0x40CB4000 0 0x3FFC registers 1024 0x10 DESC[%s] no description available 0 SRAM0_ Description Address Register 0 32 read-write 0 0 ADDR Address field 0 32 read-write SRAM1_ Description Data Register 0x4 32 read-write 0 0 DATA Data field 0 32 read-write SRAM2_ Description Control Register 0x8 32 read-write 0 0 TYPE Type field 0 3 read-write SR SR 0 WO WO 0x1 RMW_OR RMW_OR 0x2 RMW_AND RMW_AND 0x3 DELAY DELAY 0x4 POLLING_0 POLLING_0 0x5 POLLING_1 POLLING_1 0x6 SV_EN Save Enable 4 1 read-write SV_EN_0 Do not use this descriptor in the save operation 0 SV_EN_1 Use this descriptor in the save operation 0x1 RT_EN Restore Enable 5 1 read-write RT_EN_0 Do not use this descriptor for the restore operation 0 RT_EN_1 Use this descriptor for the restore operation 0x1 SIZE Size field 6 2 read-write size_0 8-bit 0 size_1 16-bit 0x1 size_2 32-bit 0x2 SSARC_LP SSARC Registers SSARC_LP 0x40CB8000 0 0x224 registers DESC_CTRL0_0 Descriptor Control0 0 Register 0 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_0 Descriptor Control1 0 Register 0x4 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_0 Descriptor Address Up 0 Register 0x8 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_0 Descriptor Address Down 0 Register 0xC 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_1 Descriptor Control0 1 Register 0x20 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_1 Descriptor Control1 1 Register 0x24 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_1 Descriptor Address Up 1 Register 0x28 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_1 Descriptor Address Down 1 Register 0x2C 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_2 Descriptor Control0 2 Register 0x40 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_2 Descriptor Control1 2 Register 0x44 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_2 Descriptor Address Up 2 Register 0x48 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_2 Descriptor Address Down 2 Register 0x4C 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_3 Descriptor Control0 3 Register 0x60 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_3 Descriptor Control1 3 Register 0x64 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_3 Descriptor Address Up 3 Register 0x68 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_3 Descriptor Address Down 3 Register 0x6C 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_4 Descriptor Control0 4 Register 0x80 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_4 Descriptor Control1 4 Register 0x84 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_4 Descriptor Address Up 4 Register 0x88 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_4 Descriptor Address Down 4 Register 0x8C 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_5 Descriptor Control0 5 Register 0xA0 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_5 Descriptor Control1 5 Register 0xA4 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_5 Descriptor Address Up 5 Register 0xA8 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_5 Descriptor Address Down 5 Register 0xAC 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_6 Descriptor Control0 6 Register 0xC0 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_6 Descriptor Control1 6 Register 0xC4 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_6 Descriptor Address Up 6 Register 0xC8 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_6 Descriptor Address Down 6 Register 0xCC 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_7 Descriptor Control0 7 Register 0xE0 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_7 Descriptor Control1 7 Register 0xE4 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_7 Descriptor Address Up 7 Register 0xE8 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_7 Descriptor Address Down 7 Register 0xEC 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_8 Descriptor Control0 8 Register 0x100 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_8 Descriptor Control1 8 Register 0x104 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_8 Descriptor Address Up 8 Register 0x108 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_8 Descriptor Address Down 8 Register 0x10C 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_9 Descriptor Control0 9 Register 0x120 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_9 Descriptor Control1 9 Register 0x124 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_9 Descriptor Address Up 9 Register 0x128 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_9 Descriptor Address Down 9 Register 0x12C 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_10 Descriptor Control0 10 Register 0x140 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_10 Descriptor Control1 10 Register 0x144 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_10 Descriptor Address Up 10 Register 0x148 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_10 Descriptor Address Down 10 Register 0x14C 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_11 Descriptor Control0 11 Register 0x160 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_11 Descriptor Control1 11 Register 0x164 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_11 Descriptor Address Up 11 Register 0x168 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_11 Descriptor Address Down 11 Register 0x16C 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_12 Descriptor Control0 12 Register 0x180 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_12 Descriptor Control1 12 Register 0x184 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_12 Descriptor Address Up 12 Register 0x188 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_12 Descriptor Address Down 12 Register 0x18C 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_13 Descriptor Control0 13 Register 0x1A0 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_13 Descriptor Control1 13 Register 0x1A4 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_13 Descriptor Address Up 13 Register 0x1A8 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_13 Descriptor Address Down 13 Register 0x1AC 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_14 Descriptor Control0 14 Register 0x1C0 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_14 Descriptor Control1 14 Register 0x1C4 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_14 Descriptor Address Up 14 Register 0x1C8 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_14 Descriptor Address Down 14 Register 0x1CC 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write DESC_CTRL0_15 Descriptor Control0 15 Register 0x1E0 32 read-write 0 0xFFFFFFFF START Start index 0 10 read-write END End index 10 10 read-write SV_ORDER Save Order 20 1 read-write SV_START_END Descriptors within the group are processed from start to end 0 SV_END_START Descriptors within the group are processed from end to start 0x1 RT_ORDER Restore order 21 1 read-write RT_START_END Descriptors within the group are processed from start to end 0 RT_END_START Descriptors within the group are processed from end to start 0x1 DESC_CTRL1_15 Descriptor Control1 15 Register 0x1E4 32 read-write 0 0xFFFFFFFF SW_TRIG_SV Software trigger save 0 1 read-write REQ_NO No software save request/software restore request complete 0 REQ_YES Request a software save operation/software restore operation in progress 0x1 SW_TRIG_RT Software trigger restore 1 1 read-write REQ_NO No software restore request/software restore request complete 0 REQ_YES Request a software restore operation/software restore operation in progress 0x1 POWER_DOMAIN This field describes the mapping (0-7) to external request signals from different domains 4 3 read-write DOMAIN0 PGMC_BPC0 0 DOMAIN1 PGMC_BPC1 0x1 DOMAIN2 PGMC_BPC2 0x2 DOMAIN3 PGMC_BPC3 0x3 DOMAIN4 PGMC_BPC4 0x4 DOMAIN5 PGMC_BPC5 0x5 DOMAIN6 PGMC_BPC6 0x6 DOMAIN7 PGMC_BPC7 0x7 GP_EN Group Enable 7 1 read-write GP_DIS Group disabled 0 GP_EN Group enabled 0x1 SV_PRIORITY Save Priority 8 4 read-write RT_PRIORITY Restore Priority 12 4 read-write CPUD CPU Domain 16 2 read-write RL Read Lock 18 1 read-write R_UNLOCK Group is unlocked (read access allowed) 0 R_LOCK Group is locked (read access not allowed) 0x1 WL Write Lock 19 1 read-write W_UNLOCK Group is unlocked (write access allowed) 0 W_LOCK Group is locked (write access not allowed) 0x1 DL Domain lock 20 1 read-write D_UNLOCK Unlock 0 D_LOCK Lock 0x1 DESC_ADDR_UP_15 Descriptor Address Up 15 Register 0x1E8 32 read-write 0 0xFFFFFFFF ADDR_UP Address field (High) 0 32 read-write DESC_ADDR_DOWN_15 Descriptor Address Down 15 Register 0x1EC 32 read-write 0 0xFFFFFFFF ADDR_DOWN Address field (Low) 0 32 read-write CTRL Control Register 0x200 32 read-write 0 0xFFFFFFFF DIS_HW_REQ Save/Restore request disable 27 1 read-write ENABLE_PGMC PGMC save/restore requests enabled 0 DIS_PGMC PGMC save/restore requests disabled 0x1 SW_RESET Software reset 31 1 read-write INT_STATUS Interrupt Status Register 0x204 32 read-write 0 0xFFFFFFFF ERR_INDEX Error Index 0 10 read-only AHB_RESP AHB Bus response field 10 2 read-only GROUP_CONFLICT Group Conflict field 27 1 read-write oneToClear GRP_CONFLICT_ERR_NO No group conflict error 0 GRP_CONFLICT_ERR A group conflict error has occurred 0x1 TIMEOUT Timeout field 28 1 read-write oneToClear ERR_INDEX_ERR_NO No timeout event 0 ERR_INDEX_ERR A timeout event has occurred 0x1 SW_REQ_DONE Software Request Done 29 1 read-only SW_REQ_ERR_A No software triggered requests or software triggered request still in progress 0 SW_REQ_ERR Atleast one software triggered has been complete 0x1 AHB_ERR AHB Error field 30 1 read-write oneToClear AHB_ERRNO No AHB error 0 AHB_ERR An AHB error has occurred 0x1 ADDR_ERR Address Error field 31 1 read-write oneToClear ADDERR_ERRNO No address error 0 ADDERR_ERR An address error has occurred 0x1 HP_TIMEOUT HP Timeout Register 0x20C 32 read-write 0 0xFFFFFFFF TIMEOUT_VALUE Time out value 0 32 read-write HW_GROUP_PENDING Hardware Request Pending Register 0x21C 32 read-only 0 0xFFFFFFFF HW_SAVE_PENDING This field indicates which groups are pending for save from hardware request 0 16 read-only HW_RESTORE_PENDING This field indicates which groups are pending for restore from hardware request 16 16 read-only SW_GROUP_PENDING Software Request Pending Register 0x220 32 read-only 0 0xFFFFFFFF SW_SAVE_PENDING This field indicates which groups are pending for save from software request 0 16 read-only SW_RESTORE_PENDING This field indicates which groups are pending for restore from software request 16 16 read-only CCM CCM CCM 0x40CC0000 0 0x7140 registers 79 0x80 CLOCK_ROOT[%s] Clock root select Registers 0 CLOCK_ROOT_CONTROL Clock root control 0 32 read-write 0 0xFFFFFFFF DIV Clock divider 0 8 read-write MUX Clock multiplexer 8 3 read-write OFF OFF 24 1 read-write ON Turn on clock 0 OFF Turn off clock 0x1 CLOCK_ROOT_CONTROL_SET Clock root control 0x4 32 read-write 0 0xFFFFFFFF oneToSet DIV Clock divider 0 8 read-write oneToSet MUX Clock multiplexer 8 3 read-write oneToSet OFF OFF 24 1 read-write oneToSet CLOCK_ROOT_CONTROL_CLR Clock root control 0x8 32 read-write 0 0xFFFFFFFF oneToClear DIV Clock divider 0 8 read-write oneToClear MUX Clock multiplexer 8 3 read-write oneToClear OFF OFF 24 1 read-write oneToClear CLOCK_ROOT_CONTROL_TOG Clock root control 0xC 32 read-write 0 0xFFFFFFFF oneToToggle DIV Clock divider 0 8 read-write oneToToggle MUX Clock multiplexer 8 3 read-write oneToToggle OFF OFF 24 1 read-write oneToToggle CLOCK_ROOT_STATUS0 Clock root working status 0x20 32 read-only 0 0xFFFFFFFF DIV Current clock root DIV setting 0 8 read-only MUX Current clock root MUX setting 8 3 read-only OFF Current clock root OFF setting 24 1 read-only OFF_0 Clock is running 0 OFF_1 Clock is disabled/off 0x1 POWERDOWN Current clock root POWERDOWN setting 27 1 read-only RUN Clock root is running 0 PWRDWN Clock root is Powered Down 0x1 SLICE_BUSY Internal updating in generation logic 28 1 read-only DIS Clock generation logic is not busy 0 ENABLE Clock generation logic is applying the new setting 0x1 UPDATE_FORWARD Internal status synchronization to clock generation logic 29 1 read-only DIS Synchronization not in process 0 ENABLE Synchronization in process 0x1 UPDATE_REVERSE Internal status synchronization from clock generation logic 30 1 read-only DIS Synchronization not in process 0 ENABLE Synchronization in process 0x1 CHANGING Internal updating in clock root 31 1 read-only DIS Clock Status is not updating currently 0 ENABLE Clock generation logic is updating currently 0x1 CLOCK_ROOT_STATUS1 Clock root low power status 0x24 32 read-only 0 0xFFFFFFFF TARGET_SETPOINT Target Setpoint 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only DOWN_REQUEST Clock frequency decrease request 24 1 read-only DIS Frequency decrease not requested 0 ENABLE Frequency decrease requested 0x1 DOWN_DONE Clock frequency decrease finish 25 1 read-only DIS Frequency decrease not completed 0 ENABLE Frequency decrease completed 0x1 UP_REQUEST Clock frequency increase request 26 1 read-only DIS Frequency increase not requested 0 ENABLE Frequency increase requested 0x1 UP_DONE Clock frequency increase finish 27 1 read-only DIS Frequency increase not completed 0 ENABLE Frequency increase completed 0x1 CLOCK_ROOT_CONFIG Clock root configuration 0x2C 32 read-only 0 0xFFFFFFEF SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 CLOCK_ROOT_AUTHEN Clock root access control 0x30 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode 0 TZ_USER_1 Clock can be changed in user mode 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode 0 TZ_NS_1 Can be changed in Non-secure mode 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked 0 LOCK_TZ_1 Trustzone setting is locked 0x1 WHITE_LIST Whitelist 8 4 read-write WHITE_LIST_0 This domain is NOT allowed to change clock 0 WHITE_LIST_1 This domain is allowed to change clock 0x1 LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked 0 LOCK_LIST_1 Whitelist is locked 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does NOT work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write SETPOINT_MODE_0 Clock does NOT work in Setpoint Mode 0 SETPOINT_MODE_1 Clock works in Setpoint Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked 0 LOCK_MODE_1 MODE is locked 0x1 CLOCK_ROOT_AUTHEN_SET Clock root access control 0x34 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST Whitelist 8 4 read-write oneToSet LOCK_LIST Lock Whitelist 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToSet SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet CLOCK_ROOT_AUTHEN_CLR Clock root access control 0x38 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST Whitelist 8 4 read-write oneToClear LOCK_LIST Lock Whitelist 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToClear SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear CLOCK_ROOT_AUTHEN_TOG Clock root access control 0x3C 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST Whitelist 8 4 read-write oneToToggle LOCK_LIST Lock Whitelist 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToToggle SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle 16 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 CLOCK_ROOT_SETPOINT%s Setpoint setting 0x40 32 read-write 0 0xFFFFFFFF DIV Clock divider 0 8 read-write MUX Clock multiplexer 8 3 read-write OFF OFF 24 1 read-write ENABLE ON 0 DISABLE OFF 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_CONTROL Clock group control 0x4000 32 read-write 0 0xFFFFFFFF DIV0 Clock divider0 0 4 read-write RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running 0 OFF_1 Turn off clock 0x1 CLOCK_GROUP0_CONTROL_SET Clock group control 0x4004 32 read-write 0 0xFFFFFFFF oneToSet DIV0 Clock divider0 0 4 read-write oneToSet RSTDIV Clock group global restart count 16 8 read-write oneToSet OFF OFF 24 1 read-write oneToSet CLOCK_GROUP0_CONTROL_CLR Clock group control 0x4008 32 read-write 0 0xFFFFFFFF oneToClear DIV0 Clock divider0 0 4 read-write oneToClear RSTDIV Clock group global restart count 16 8 read-write oneToClear OFF OFF 24 1 read-write oneToClear CLOCK_GROUP0_CONTROL_TOG Clock group control 0x400C 32 read-write 0 0xFFFFFFFF oneToToggle DIV0 Clock divider0 0 4 read-write oneToToggle RSTDIV Clock group global restart count 16 8 read-write oneToToggle OFF OFF 24 1 read-write oneToToggle CLOCK_GROUP0_STATUS0 Clock group working status 0x4020 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write RSTDIV Clock divider 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 POWERDOWN Current clock root POWERDOWN setting 27 1 read-only RUN Clock root is running 0 PWRDWN Clock root is Powered Down 0x1 SLICE_BUSY Internal updating in generation logic 28 1 read-only DIS Clock generation logic is not busy 0 ENABLE Clock generation logic is applying the new setting 0x1 UPDATE_FORWARD Internal status synchronization to clock generation logic 29 1 read-only DIS Synchronization not in process 0 ENABLE Synchronization in process 0x1 UPDATE_REVERSE Internal status synchronization from clock generation logic 30 1 read-only DIS Synchronization not in process 0 ENABLE Synchronization in process 0x1 CHANGING Internal updating in clock group 31 1 read-only DIS Clock root is not updating currently 0 ENABLE Clock root logic is updating currently 0x1 CLOCK_GROUP0_STATUS1 Clock group low power/extend status 0x4024 32 read-only 0 0xFFFFFFFF TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only DOWN_REQUEST Clock frequency decrease request 24 1 read-only NOTREQ No handshake signal is not requested 0 REQUEST Handshake signal with GPC status indicating frequency decrease is requested 0x1 DOWN_DONE Clock frequency decrease complete 25 1 read-only DISABLE Handshake signal with GPC status indicating frequency decrease is not complete 0 COMPL Handshake signal with GPC status indicating frequency decrease is complete 0x1 UP_REQUEST Clock frequency increase request 26 1 read-only NOTREQ No handshake signal is not requested 0 REQUEST Handshake signal with GPC status indicating frequency increase is requested 0x1 UP_DONE Clock frequency increase complete 27 1 read-only DISABLE Handshake signal with GPC status indicating frequency increase is not complete 0 COMPL Handshake signal with GPC status indicating frequency increase is complete 0x1 CLOCK_GROUP0_CONFIG Clock group configuration 0x402C 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 CLOCK_GROUP0_AUTHEN Clock group access control 0x4030 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode. 0 TZ_USER_1 Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode. 0 DOMAIN_MODE_1 Clock works in Domain Mode. 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 CLOCK_GROUP0_AUTHEN_SET Clock group access control 0x4034 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST Whitelist 8 4 read-write oneToSet LOCK_LIST Lock Whitelist 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToSet SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet CLOCK_GROUP0_AUTHEN_CLR Clock group access control 0x4038 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST Whitelist 8 4 read-write oneToClear LOCK_LIST Lock Whitelist 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToClear SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear CLOCK_GROUP0_AUTHEN_TOG Clock group access control 0x403C 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST Whitelist 8 4 read-write oneToToggle LOCK_LIST Lock Whitelist 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToToggle SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle CLOCK_GROUP0_SETPOINT0 Setpoint setting 0x4040 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT1 Setpoint setting 0x4044 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT2 Setpoint setting 0x4048 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT3 Setpoint setting 0x404C 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT4 Setpoint setting 0x4050 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT5 Setpoint setting 0x4054 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT6 Setpoint setting 0x4058 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT7 Setpoint setting 0x405C 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT8 Setpoint setting 0x4060 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT9 Setpoint setting 0x4064 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT10 Setpoint setting 0x4068 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT11 Setpoint setting 0x406C 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT12 Setpoint setting 0x4070 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT13 Setpoint setting 0x4074 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT14 Setpoint setting 0x4078 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP0_SETPOINT15 Setpoint setting 0x407C 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_CONTROL Clock group control 0x4080 32 read-write 0 0xFFFFFFFF DIV0 Clock divider0 0 4 read-write RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running 0 OFF_1 Turn off clock 0x1 CLOCK_GROUP1_CONTROL_SET Clock group control 0x4084 32 read-write 0 0xFFFFFFFF oneToSet DIV0 Clock divider0 0 4 read-write oneToSet RSTDIV Clock group global restart count 16 8 read-write oneToSet OFF OFF 24 1 read-write oneToSet CLOCK_GROUP1_CONTROL_CLR Clock group control 0x4088 32 read-write 0 0xFFFFFFFF oneToClear DIV0 Clock divider0 0 4 read-write oneToClear RSTDIV Clock group global restart count 16 8 read-write oneToClear OFF OFF 24 1 read-write oneToClear CLOCK_GROUP1_CONTROL_TOG Clock group control 0x408C 32 read-write 0 0xFFFFFFFF oneToToggle DIV0 Clock divider0 0 4 read-write oneToToggle RSTDIV Clock group global restart count 16 8 read-write oneToToggle OFF OFF 24 1 read-write oneToToggle CLOCK_GROUP1_STATUS0 Clock group working status 0x40A0 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write RSTDIV Clock divider 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 POWERDOWN Current clock root POWERDOWN setting 27 1 read-only RUN Clock root is running 0 PWRDWN Clock root is Powered Down 0x1 SLICE_BUSY Internal updating in generation logic 28 1 read-only DIS Clock generation logic is not busy 0 ENABLE Clock generation logic is applying the new setting 0x1 UPDATE_FORWARD Internal status synchronization to clock generation logic 29 1 read-only DIS Synchronization not in process 0 ENABLE Synchronization in process 0x1 UPDATE_REVERSE Internal status synchronization from clock generation logic 30 1 read-only DIS Synchronization not in process 0 ENABLE Synchronization in process 0x1 CHANGING Internal updating in clock group 31 1 read-only DIS Clock root is not updating currently 0 ENABLE Clock root logic is updating currently 0x1 CLOCK_GROUP1_STATUS1 Clock group low power/extend status 0x40A4 32 read-only 0 0xFFFFFFFF TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only DOWN_REQUEST Clock frequency decrease request 24 1 read-only NOTREQ No handshake signal is not requested 0 REQUEST Handshake signal with GPC status indicating frequency decrease is requested 0x1 DOWN_DONE Clock frequency decrease complete 25 1 read-only DISABLE Handshake signal with GPC status indicating frequency decrease is not complete 0 COMPL Handshake signal with GPC status indicating frequency decrease is complete 0x1 UP_REQUEST Clock frequency increase request 26 1 read-only NOTREQ No handshake signal is not requested 0 REQUEST Handshake signal with GPC status indicating frequency increase is requested 0x1 UP_DONE Clock frequency increase complete 27 1 read-only DISABLE Handshake signal with GPC status indicating frequency increase is not complete 0 COMPL Handshake signal with GPC status indicating frequency increase is complete 0x1 CLOCK_GROUP1_CONFIG Clock group configuration 0x40AC 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 CLOCK_GROUP1_AUTHEN Clock group access control 0x40B0 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode. 0 TZ_USER_1 Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode. 0 DOMAIN_MODE_1 Clock works in Domain Mode. 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 CLOCK_GROUP1_AUTHEN_SET Clock group access control 0x40B4 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST Whitelist 8 4 read-write oneToSet LOCK_LIST Lock Whitelist 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToSet SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet CLOCK_GROUP1_AUTHEN_CLR Clock group access control 0x40B8 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST Whitelist 8 4 read-write oneToClear LOCK_LIST Lock Whitelist 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToClear SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear CLOCK_GROUP1_AUTHEN_TOG Clock group access control 0x40BC 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST Whitelist 8 4 read-write oneToToggle LOCK_LIST Lock Whitelist 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToToggle SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle CLOCK_GROUP1_SETPOINT0 Setpoint setting 0x40C0 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT1 Setpoint setting 0x40C4 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT2 Setpoint setting 0x40C8 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT3 Setpoint setting 0x40CC 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT4 Setpoint setting 0x40D0 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT5 Setpoint setting 0x40D4 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT6 Setpoint setting 0x40D8 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT7 Setpoint setting 0x40DC 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT8 Setpoint setting 0x40E0 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT9 Setpoint setting 0x40E4 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT10 Setpoint setting 0x40E8 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT11 Setpoint setting 0x40EC 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT12 Setpoint setting 0x40F0 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT13 Setpoint setting 0x40F4 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT14 Setpoint setting 0x40F8 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write CLOCK_GROUP1_SETPOINT15 Setpoint setting 0x40FC 32 read-write 0 0xFFFFFFFF DIV0 Clock divider 0 4 read-write DIV0_0 Direct output. 0 DIV0_1 Divide by 2. 0x1 DIV0_2 Divide by 3. 0x2 DIV0_3 Divide by 4. 0x3 DIV0_15 Divide by 16. 0xF RSTDIV Clock group global restart count 16 8 read-write OFF OFF 24 1 read-write OFF_0 Clock is running. 0 OFF_1 Turn off clock. 0x1 GRADE Grade 28 4 read-write 8 0x20 GPR_SHARED[%s] General Purpose Registers 0x4800 GPR_SHARED General Purpose Register 0 32 read-write 0 0xFFFFFFFF GPR GP register 0 32 read-write GPR_SHARED_SET General Purpose Register 0x4 32 read-write 0 0xFFFFFFFF oneToSet GPR GP register 0 32 read-write oneToSet GPR_SHARED_CLR General Purpose Register 0x8 32 read-write 0 0xFFFFFFFF oneToClear GPR GP register 0 32 read-write oneToClear GPR_SHARED_TOG General Purpose Register 0xC 32 read-write 0 0xFFFFFFFF oneToToggle GPR GP register 0 32 read-write oneToToggle GPR_SHARED_AUTHEN GPR access control 0x10 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write CANNOT_CHANGE Clock cannot be changed in user mode. 0 CHANGE Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write WHITE_LIST_0 This domain is NOT allowed to change clock. 0 WHITE_LIST_1 This domain is allowed to change clock. 0x1 LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does NOT work in Domain Mode. 0 DOMAIN_MODE_1 Clock works in Domain Mode. 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 GPR_SHARED_AUTHEN_SET GPR access control 0x14 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST Whitelist 8 4 read-write oneToSet LOCK_LIST Lock Whitelist 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet GPR_SHARED_AUTHEN_CLR GPR access control 0x18 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST Whitelist 8 4 read-write oneToClear LOCK_LIST Lock Whitelist 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear GPR_SHARED_AUTHEN_TOG GPR access control 0x1C 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST Whitelist 8 4 read-write oneToToggle LOCK_LIST Lock Whitelist 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by domain 16 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle GPR_PRIVATE1 General Purpose Register 0x4C20 32 read-write 0 0xFFFFFFFF GPR GP register 0 32 read-write GPR_PRIVATE1_SET General Purpose Register 0x4C24 32 read-write 0 0xFFFFFFFF oneToSet GPR GP register 0 32 read-write oneToSet GPR_PRIVATE1_CLR General Purpose Register 0x4C28 32 read-write 0 0xFFFFFFFF oneToClear GPR GP register 0 32 read-write oneToClear GPR_PRIVATE1_TOG General Purpose Register 0x4C2C 32 read-write 0 0xFFFFFFFF oneToToggle GPR GP register 0 32 read-write oneToToggle GPR_PRIVATE1_AUTHEN GPR access control 0x4C30 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode. 0 TZ_USER_1 Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write WHITE_LIST_0 This domain is NOT allowed to change clock. 0 WHITE_LIST_1 This domain is allowed to change clock. 0x1 LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by Domain 16 1 read-write DOMAIN_MODE_0 Clock does NOT work in Domain Mode. 0 DOMAIN_MODE_1 Clock works in Domain Mode. 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 GPR_PRIVATE1_AUTHEN_SET GPR access control 0x4C34 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST Whitelist 8 4 read-write oneToSet LOCK_LIST Lock Whitelist 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet GPR_PRIVATE1_AUTHEN_CLR GPR access control 0x4C38 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST Whitelist 8 4 read-write oneToClear LOCK_LIST Lock Whitelist 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear GPR_PRIVATE1_AUTHEN_TOG GPR access control 0x4C3C 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST Whitelist 8 4 read-write oneToToggle LOCK_LIST Lock Whitelist 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle GPR_PRIVATE2 General Purpose Register 0x4C40 32 read-write 0 0xFFFFFFFF GPR GP register 0 32 read-write GPR_PRIVATE2_SET General Purpose Register 0x4C44 32 read-write 0 0xFFFFFFFF oneToSet GPR GP register 0 32 read-write oneToSet GPR_PRIVATE2_CLR General Purpose Register 0x4C48 32 read-write 0 0xFFFFFFFF oneToClear GPR GP register 0 32 read-write oneToClear GPR_PRIVATE2_TOG General Purpose Register 0x4C4C 32 read-write 0 0xFFFFFFFF oneToToggle GPR GP register 0 32 read-write oneToToggle GPR_PRIVATE2_AUTHEN GPR access control 0x4C50 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode. 0 TZ_USER_1 Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write WHITE_LIST_0 This domain is NOT allowed to change clock. 0 WHITE_LIST_1 This domain is allowed to change clock. 0x1 LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by Domain 16 1 read-write DOMAIN_MODE_0 Clock does NOT work in Domain Mode. 0 DOMAIN_MODE_1 Clock works in Domain Mode. 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 GPR_PRIVATE2_AUTHEN_SET GPR access control 0x4C54 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST Whitelist 8 4 read-write oneToSet LOCK_LIST Lock Whitelist 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet GPR_PRIVATE2_AUTHEN_CLR GPR access control 0x4C58 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST Whitelist 8 4 read-write oneToClear LOCK_LIST Lock Whitelist 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear GPR_PRIVATE2_AUTHEN_TOG GPR access control 0x4C5C 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST Whitelist 8 4 read-write oneToToggle LOCK_LIST Lock Whitelist 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle GPR_PRIVATE3 General Purpose Register 0x4C60 32 read-write 0 0xFFFFFFFF GPR GP register 0 32 read-write GPR_PRIVATE3_SET General Purpose Register 0x4C64 32 read-write 0 0xFFFFFFFF oneToSet GPR GP register 0 32 read-write oneToSet GPR_PRIVATE3_CLR General Purpose Register 0x4C68 32 read-write 0 0xFFFFFFFF oneToClear GPR GP register 0 32 read-write oneToClear GPR_PRIVATE3_TOG General Purpose Register 0x4C6C 32 read-write 0 0xFFFFFFFF oneToToggle GPR GP register 0 32 read-write oneToToggle GPR_PRIVATE3_AUTHEN GPR access control 0x4C70 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode. 0 TZ_USER_1 Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write WHITE_LIST_0 This domain is NOT allowed to change clock. 0 WHITE_LIST_1 This domain is allowed to change clock. 0x1 LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by Domain 16 1 read-write DOMAIN_MODE_0 Clock does NOT work in Domain Mode. 0 DOMAIN_MODE_1 Clock works in Domain Mode. 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 GPR_PRIVATE3_AUTHEN_SET GPR access control 0x4C74 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST Whitelist 8 4 read-write oneToSet LOCK_LIST Lock Whitelist 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet GPR_PRIVATE3_AUTHEN_CLR GPR access control 0x4C78 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST Whitelist 8 4 read-write oneToClear LOCK_LIST Lock Whitelist 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear GPR_PRIVATE3_AUTHEN_TOG GPR access control 0x4C7C 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST Whitelist 8 4 read-write oneToToggle LOCK_LIST Lock Whitelist 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle GPR_PRIVATE4 General Purpose Register 0x4C80 32 read-write 0 0xFFFFFFFF GPR GP register 0 32 read-write GPR_PRIVATE4_SET General Purpose Register 0x4C84 32 read-write 0 0xFFFFFFFF oneToSet GPR GP register 0 32 read-write oneToSet GPR_PRIVATE4_CLR General Purpose Register 0x4C88 32 read-write 0 0xFFFFFFFF oneToClear GPR GP register 0 32 read-write oneToClear GPR_PRIVATE4_TOG General Purpose Register 0x4C8C 32 read-write 0 0xFFFFFFFF oneToToggle GPR GP register 0 32 read-write oneToToggle GPR_PRIVATE4_AUTHEN GPR access control 0x4C90 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode. 0 TZ_USER_1 Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write WHITE_LIST_0 This domain is NOT allowed to change clock. 0 WHITE_LIST_1 This domain is allowed to change clock. 0x1 LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by Domain 16 1 read-write DOMAIN_MODE_0 Clock does NOT work in Domain Mode. 0 DOMAIN_MODE_1 Clock works in Domain Mode. 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 GPR_PRIVATE4_AUTHEN_SET GPR access control 0x4C94 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST Whitelist 8 4 read-write oneToSet LOCK_LIST Lock Whitelist 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet GPR_PRIVATE4_AUTHEN_CLR GPR access control 0x4C98 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST Whitelist 8 4 read-write oneToClear LOCK_LIST Lock Whitelist 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear GPR_PRIVATE4_AUTHEN_TOG GPR access control 0x4C9C 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST Whitelist 8 4 read-write oneToToggle LOCK_LIST Lock Whitelist 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle GPR_PRIVATE5 General Purpose Register 0x4CA0 32 read-write 0 0xFFFFFFFF GPR GP register 0 32 read-write GPR_PRIVATE5_SET General Purpose Register 0x4CA4 32 read-write 0 0xFFFFFFFF oneToSet GPR GP register 0 32 read-write oneToSet GPR_PRIVATE5_CLR General Purpose Register 0x4CA8 32 read-write 0 0xFFFFFFFF oneToClear GPR GP register 0 32 read-write oneToClear GPR_PRIVATE5_TOG General Purpose Register 0x4CAC 32 read-write 0 0xFFFFFFFF oneToToggle GPR GP register 0 32 read-write oneToToggle GPR_PRIVATE5_AUTHEN GPR access control 0x4CB0 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode. 0 TZ_USER_1 Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write WHITE_LIST_0 This domain is NOT allowed to change clock. 0 WHITE_LIST_1 This domain is allowed to change clock. 0x1 LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by Domain 16 1 read-write DOMAIN_MODE_0 Clock does NOT work in Domain Mode. 0 DOMAIN_MODE_1 Clock works in Domain Mode. 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 GPR_PRIVATE5_AUTHEN_SET GPR access control 0x4CB4 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST Whitelist 8 4 read-write oneToSet LOCK_LIST Lock Whitelist 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet GPR_PRIVATE5_AUTHEN_CLR GPR access control 0x4CB8 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST Whitelist 8 4 read-write oneToClear LOCK_LIST Lock Whitelist 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear GPR_PRIVATE5_AUTHEN_TOG GPR access control 0x4CBC 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST Whitelist 8 4 read-write oneToToggle LOCK_LIST Lock Whitelist 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle GPR_PRIVATE6 General Purpose Register 0x4CC0 32 read-write 0 0xFFFFFFFF GPR GP register 0 32 read-write GPR_PRIVATE6_SET General Purpose Register 0x4CC4 32 read-write 0 0xFFFFFFFF oneToSet GPR GP register 0 32 read-write oneToSet GPR_PRIVATE6_CLR General Purpose Register 0x4CC8 32 read-write 0 0xFFFFFFFF oneToClear GPR GP register 0 32 read-write oneToClear GPR_PRIVATE6_TOG General Purpose Register 0x4CCC 32 read-write 0 0xFFFFFFFF oneToToggle GPR GP register 0 32 read-write oneToToggle GPR_PRIVATE6_AUTHEN GPR access control 0x4CD0 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode. 0 TZ_USER_1 Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write WHITE_LIST_0 This domain is NOT allowed to change clock. 0 WHITE_LIST_1 This domain is allowed to change clock. 0x1 LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by Domain 16 1 read-write DOMAIN_MODE_0 Clock does NOT work in Domain Mode. 0 DOMAIN_MODE_1 Clock works in Domain Mode. 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 GPR_PRIVATE6_AUTHEN_SET GPR access control 0x4CD4 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST Whitelist 8 4 read-write oneToSet LOCK_LIST Lock Whitelist 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet GPR_PRIVATE6_AUTHEN_CLR GPR access control 0x4CD8 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST Whitelist 8 4 read-write oneToClear LOCK_LIST Lock Whitelist 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear GPR_PRIVATE6_AUTHEN_TOG GPR access control 0x4CDC 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST Whitelist 8 4 read-write oneToToggle LOCK_LIST Lock Whitelist 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle GPR_PRIVATE7 General Purpose Register 0x4CE0 32 read-write 0 0xFFFFFFFF GPR GP register 0 32 read-write GPR_PRIVATE7_SET General Purpose Register 0x4CE4 32 read-write 0 0xFFFFFFFF oneToSet GPR GP register 0 32 read-write oneToSet GPR_PRIVATE7_CLR General Purpose Register 0x4CE8 32 read-write 0 0xFFFFFFFF oneToClear GPR GP register 0 32 read-write oneToClear GPR_PRIVATE7_TOG General Purpose Register 0x4CEC 32 read-write 0 0xFFFFFFFF oneToToggle GPR GP register 0 32 read-write oneToToggle GPR_PRIVATE7_AUTHEN GPR access control 0x4CF0 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode. 0 TZ_USER_1 Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ Lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write WHITE_LIST_0 This domain is NOT allowed to change clock. 0 WHITE_LIST_1 This domain is allowed to change clock. 0x1 LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by Domain 16 1 read-write DOMAIN_MODE_0 Clock does NOT work in Domain Mode. 0 DOMAIN_MODE_1 Clock works in Domain Mode. 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 GPR_PRIVATE7_AUTHEN_SET GPR access control 0x4CF4 32 read-write 0 0xFFFFFFFF oneToSet TZ_USER User access 0 1 read-write oneToSet TZ_NS Non-secure access 1 1 read-write oneToSet LOCK_TZ Lock truszone setting 4 1 read-write oneToSet WHITE_LIST Whitelist 8 4 read-write oneToSet LOCK_LIST Lock Whitelist 12 1 read-write oneToSet DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToSet LOCK_MODE Lock low power and access mode 20 1 read-write oneToSet GPR_PRIVATE7_AUTHEN_CLR GPR access control 0x4CF8 32 read-write 0 0xFFFFFFFF oneToClear TZ_USER User access 0 1 read-write oneToClear TZ_NS Non-secure access 1 1 read-write oneToClear LOCK_TZ Lock truszone setting 4 1 read-write oneToClear WHITE_LIST Whitelist 8 4 read-write oneToClear LOCK_LIST Lock Whitelist 12 1 read-write oneToClear DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToClear LOCK_MODE Lock low power and access mode 20 1 read-write oneToClear GPR_PRIVATE7_AUTHEN_TOG GPR access control 0x4CFC 32 read-write 0 0xFFFFFFFF oneToToggle TZ_USER User access 0 1 read-write oneToToggle TZ_NS Non-secure access 1 1 read-write oneToToggle LOCK_TZ Lock truszone setting 4 1 read-write oneToToggle WHITE_LIST Whitelist 8 4 read-write oneToToggle LOCK_LIST Lock Whitelist 12 1 read-write oneToToggle DOMAIN_MODE Low power and access control by Domain 16 1 read-write oneToToggle LOCK_MODE Lock low power and access mode 20 1 read-write oneToToggle 29 0x20 OSCPLL[%s] Clock source select Registers 0x5000 OSCPLL_DIRECT Clock source direct control 0 32 read-write 0x1 0xFFFFFFFF ON turn on clock source 0 1 read-write ON_0 OSCPLL is OFF 0 ON_1 OSCPLL is ON 0x1 OSCPLL_DOMAIN Clock source domain control 0x4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Dependence level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 OSCPLL_SETPOINT Clock source Setpoint setting 0x8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoint 0 16 read-write STANDBY Standby 16 16 read-write OSCPLL_STATUS0 Clock source working status 0x10 32 read-only 0 0xFFFFFFFF ON Clock source current state 0 1 read-only ON_0 Clock source is OFF 0 ON_1 Clock source is ON 0x1 STATUS_EARLY Clock source active 4 1 read-only DIS Clock source is not active 0 ENABLE Clock source is active 0x1 STATUS_LATE Clock source ready 5 1 read-only DIS Clock source is not ready to use 0 ENABLE Clock source is ready to use 0x1 ACTIVE_DOMAIN Domains that own this clock source 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF IN_USE In use 28 1 read-only DIS Clock source is not being used by clock roots 0 ENABLE Clock source is being used by clock roots 0x1 OSCPLL_STATUS1 Clock source low power status 0x14 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock source turn off finish from GPC Setpoint 25 1 read-only DIS Clock source is not turned off 0 ENABLE Clock source is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS No request 0 ENABLE Request to turn on clock gate 0x1 STANDBY_IN_REQUEST Clock gate turn off request from GPC standby 28 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 STANDBY_IN_DONE Clock source turn off finish from GPC standby 29 1 read-only DIS Clock source is not turned off 0 ENABLE Clock source is turned off 0x1 STANDBY_OUT_DONE Clock gate turn on finish from GPC standby 30 1 read-only DIS Request to turn on Clock gate is not complete 0 ENABLE Request to turn on Clock gate is complete 0x1 STANDBY_OUT_REQUEST Clock gate turn on request from GPC standby 31 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 OSCPLL_CONFIG Clock source configuration 0x18 32 read-only 0 0xFFFFFFED AUTOMODE_PRESENT Automode Present 1 1 read-only notPresent Not present 0 present Present 0x1 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 OSCPLL_AUTHEN Clock source access control 0x1C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 Clock cannot be changed in user mode. 0 TZ_USER_1 Clock can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode. 0 DOMAIN_MODE_1 Clock works in Domain Mode. 0x1 SETPOINT_MODE LPCG works in Setpoint controlled Mode. 17 1 read-write CPULPM CPU Low Power Mode 18 1 read-write DISABLE PLL does not function in Low power Mode 0 ENABLE PLL functions in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG0_DIRECT LPCG direct control 0x6000 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG0_DOMAIN LPCG domain control 0x6004 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG0_STATUS0 LPCG working status 0x6010 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG0_STATUS1 LPCG low power status 0x6014 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG0_CONFIG LPCG configuration 0x6018 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG0_AUTHEN LPCG access control 0x601C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG1_DIRECT LPCG direct control 0x6020 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG1_DOMAIN LPCG domain control 0x6024 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG1_STATUS0 LPCG working status 0x6030 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG1_STATUS1 LPCG low power status 0x6034 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG1_CONFIG LPCG configuration 0x6038 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG1_AUTHEN LPCG access control 0x603C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG2_DIRECT LPCG direct control 0x6040 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG2_DOMAIN LPCG domain control 0x6044 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG2_SETPOINT LPCG Setpoint setting 0x6048 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG2_STATUS0 LPCG working status 0x6050 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG2_STATUS1 LPCG low power status 0x6054 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG2_CONFIG LPCG configuration 0x6058 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG2_AUTHEN LPCG access control 0x605C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG3_DIRECT LPCG direct control 0x6060 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG3_DOMAIN LPCG domain control 0x6064 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG3_SETPOINT LPCG Setpoint setting 0x6068 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG3_STATUS0 LPCG working status 0x6070 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG3_STATUS1 LPCG low power status 0x6074 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG3_CONFIG LPCG configuration 0x6078 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG3_AUTHEN LPCG access control 0x607C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG4_DIRECT LPCG direct control 0x6080 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG4_DOMAIN LPCG domain control 0x6084 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG4_SETPOINT LPCG Setpoint setting 0x6088 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG4_STATUS0 LPCG working status 0x6090 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG4_STATUS1 LPCG low power status 0x6094 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG4_CONFIG LPCG configuration 0x6098 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG4_AUTHEN LPCG access control 0x609C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG5_DIRECT LPCG direct control 0x60A0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG5_DOMAIN LPCG domain control 0x60A4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG5_SETPOINT LPCG Setpoint setting 0x60A8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG5_STATUS0 LPCG working status 0x60B0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG5_STATUS1 LPCG low power status 0x60B4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG5_CONFIG LPCG configuration 0x60B8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG5_AUTHEN LPCG access control 0x60BC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG6_DIRECT LPCG direct control 0x60C0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG6_DOMAIN LPCG domain control 0x60C4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG6_SETPOINT LPCG Setpoint setting 0x60C8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG6_STATUS0 LPCG working status 0x60D0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG6_STATUS1 LPCG low power status 0x60D4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG6_CONFIG LPCG configuration 0x60D8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG6_AUTHEN LPCG access control 0x60DC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG7_DIRECT LPCG direct control 0x60E0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG7_DOMAIN LPCG domain control 0x60E4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG7_SETPOINT LPCG Setpoint setting 0x60E8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG7_STATUS0 LPCG working status 0x60F0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG7_STATUS1 LPCG low power status 0x60F4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG7_CONFIG LPCG configuration 0x60F8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG7_AUTHEN LPCG access control 0x60FC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG8_DIRECT LPCG direct control 0x6100 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG8_DOMAIN LPCG domain control 0x6104 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG8_SETPOINT LPCG Setpoint setting 0x6108 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG8_STATUS0 LPCG working status 0x6110 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG8_STATUS1 LPCG low power status 0x6114 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG8_CONFIG LPCG configuration 0x6118 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG8_AUTHEN LPCG access control 0x611C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG9_DIRECT LPCG direct control 0x6120 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG9_DOMAIN LPCG domain control 0x6124 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG9_SETPOINT LPCG Setpoint setting 0x6128 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG9_STATUS0 LPCG working status 0x6130 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG9_STATUS1 LPCG low power status 0x6134 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG9_CONFIG LPCG configuration 0x6138 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG9_AUTHEN LPCG access control 0x613C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG10_DIRECT LPCG direct control 0x6140 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG10_DOMAIN LPCG domain control 0x6144 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG10_SETPOINT LPCG Setpoint setting 0x6148 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG10_STATUS0 LPCG working status 0x6150 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG10_STATUS1 LPCG low power status 0x6154 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG10_CONFIG LPCG configuration 0x6158 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG10_AUTHEN LPCG access control 0x615C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG11_DIRECT LPCG direct control 0x6160 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG11_DOMAIN LPCG domain control 0x6164 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG11_SETPOINT LPCG Setpoint setting 0x6168 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG11_STATUS0 LPCG working status 0x6170 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG11_STATUS1 LPCG low power status 0x6174 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG11_CONFIG LPCG configuration 0x6178 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG11_AUTHEN LPCG access control 0x617C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG12_DIRECT LPCG direct control 0x6180 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG12_DOMAIN LPCG domain control 0x6184 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG12_SETPOINT LPCG Setpoint setting 0x6188 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG12_STATUS0 LPCG working status 0x6190 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG12_STATUS1 LPCG low power status 0x6194 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG12_CONFIG LPCG configuration 0x6198 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG12_AUTHEN LPCG access control 0x619C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG13_DIRECT LPCG direct control 0x61A0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG13_DOMAIN LPCG domain control 0x61A4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG13_STATUS0 LPCG working status 0x61B0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG13_STATUS1 LPCG low power status 0x61B4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG13_CONFIG LPCG configuration 0x61B8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG13_AUTHEN LPCG access control 0x61BC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG14_DIRECT LPCG direct control 0x61C0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG14_DOMAIN LPCG domain control 0x61C4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG14_SETPOINT LPCG Setpoint setting 0x61C8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG14_STATUS0 LPCG working status 0x61D0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG14_STATUS1 LPCG low power status 0x61D4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG14_CONFIG LPCG configuration 0x61D8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG14_AUTHEN LPCG access control 0x61DC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG15_DIRECT LPCG direct control 0x61E0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG15_DOMAIN LPCG domain control 0x61E4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG15_SETPOINT LPCG Setpoint setting 0x61E8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG15_STATUS0 LPCG working status 0x61F0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG15_STATUS1 LPCG low power status 0x61F4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG15_CONFIG LPCG configuration 0x61F8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG15_AUTHEN LPCG access control 0x61FC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG16_DIRECT LPCG direct control 0x6200 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG16_DOMAIN LPCG domain control 0x6204 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG16_SETPOINT LPCG Setpoint setting 0x6208 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG16_STATUS0 LPCG working status 0x6210 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG16_STATUS1 LPCG low power status 0x6214 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG16_CONFIG LPCG configuration 0x6218 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG16_AUTHEN LPCG access control 0x621C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG17_DIRECT LPCG direct control 0x6220 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG17_DOMAIN LPCG domain control 0x6224 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG17_SETPOINT LPCG Setpoint setting 0x6228 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG17_STATUS0 LPCG working status 0x6230 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG17_STATUS1 LPCG low power status 0x6234 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG17_CONFIG LPCG configuration 0x6238 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG17_AUTHEN LPCG access control 0x623C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG18_DIRECT LPCG direct control 0x6240 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG18_DOMAIN LPCG domain control 0x6244 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG18_SETPOINT LPCG Setpoint setting 0x6248 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG18_STATUS0 LPCG working status 0x6250 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG18_STATUS1 LPCG low power status 0x6254 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG18_CONFIG LPCG configuration 0x6258 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG18_AUTHEN LPCG access control 0x625C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG19_DIRECT LPCG direct control 0x6260 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG19_DOMAIN LPCG domain control 0x6264 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG19_SETPOINT LPCG Setpoint setting 0x6268 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG19_STATUS0 LPCG working status 0x6270 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG19_STATUS1 LPCG low power status 0x6274 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG19_CONFIG LPCG configuration 0x6278 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG19_AUTHEN LPCG access control 0x627C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG20_DIRECT LPCG direct control 0x6280 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG20_DOMAIN LPCG domain control 0x6284 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG20_STATUS0 LPCG working status 0x6290 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG20_STATUS1 LPCG low power status 0x6294 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG20_CONFIG LPCG configuration 0x6298 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG20_AUTHEN LPCG access control 0x629C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG21_DIRECT LPCG direct control 0x62A0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG21_DOMAIN LPCG domain control 0x62A4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG21_STATUS0 LPCG working status 0x62B0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG21_STATUS1 LPCG low power status 0x62B4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG21_CONFIG LPCG configuration 0x62B8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG21_AUTHEN LPCG access control 0x62BC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG22_DIRECT LPCG direct control 0x62C0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG22_DOMAIN LPCG domain control 0x62C4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG22_STATUS0 LPCG working status 0x62D0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG22_STATUS1 LPCG low power status 0x62D4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG22_CONFIG LPCG configuration 0x62D8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG22_AUTHEN LPCG access control 0x62DC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG23_DIRECT LPCG direct control 0x62E0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG23_DOMAIN LPCG domain control 0x62E4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG23_STATUS0 LPCG working status 0x62F0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG23_STATUS1 LPCG low power status 0x62F4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG23_CONFIG LPCG configuration 0x62F8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG23_AUTHEN LPCG access control 0x62FC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG24_DIRECT LPCG direct control 0x6300 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG24_DOMAIN LPCG domain control 0x6304 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG24_SETPOINT LPCG Setpoint setting 0x6308 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG24_STATUS0 LPCG working status 0x6310 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG24_STATUS1 LPCG low power status 0x6314 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG24_CONFIG LPCG configuration 0x6318 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG24_AUTHEN LPCG access control 0x631C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG25_DIRECT LPCG direct control 0x6320 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG25_DOMAIN LPCG domain control 0x6324 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG25_SETPOINT LPCG Setpoint setting 0x6328 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG25_STATUS0 LPCG working status 0x6330 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG25_STATUS1 LPCG low power status 0x6334 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG25_CONFIG LPCG configuration 0x6338 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG25_AUTHEN LPCG access control 0x633C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG26_DIRECT LPCG direct control 0x6340 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG26_DOMAIN LPCG domain control 0x6344 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG26_SETPOINT LPCG Setpoint setting 0x6348 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG26_STATUS0 LPCG working status 0x6350 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG26_STATUS1 LPCG low power status 0x6354 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG26_CONFIG LPCG configuration 0x6358 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG26_AUTHEN LPCG access control 0x635C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG27_DIRECT LPCG direct control 0x6360 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG27_DOMAIN LPCG domain control 0x6364 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG27_SETPOINT LPCG Setpoint setting 0x6368 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG27_STATUS0 LPCG working status 0x6370 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG27_STATUS1 LPCG low power status 0x6374 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG27_CONFIG LPCG configuration 0x6378 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG27_AUTHEN LPCG access control 0x637C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG28_DIRECT LPCG direct control 0x6380 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG28_DOMAIN LPCG domain control 0x6384 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG28_SETPOINT LPCG Setpoint setting 0x6388 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG28_STATUS0 LPCG working status 0x6390 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG28_STATUS1 LPCG low power status 0x6394 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG28_CONFIG LPCG configuration 0x6398 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG28_AUTHEN LPCG access control 0x639C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG29_DIRECT LPCG direct control 0x63A0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG29_DOMAIN LPCG domain control 0x63A4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG29_SETPOINT LPCG Setpoint setting 0x63A8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG29_STATUS0 LPCG working status 0x63B0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG29_STATUS1 LPCG low power status 0x63B4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG29_CONFIG LPCG configuration 0x63B8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG29_AUTHEN LPCG access control 0x63BC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG30_DIRECT LPCG direct control 0x63C0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG30_DOMAIN LPCG domain control 0x63C4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG30_SETPOINT LPCG Setpoint setting 0x63C8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG30_STATUS0 LPCG working status 0x63D0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG30_STATUS1 LPCG low power status 0x63D4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG30_CONFIG LPCG configuration 0x63D8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG30_AUTHEN LPCG access control 0x63DC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG31_DIRECT LPCG direct control 0x63E0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG31_DOMAIN LPCG domain control 0x63E4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG31_SETPOINT LPCG Setpoint setting 0x63E8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG31_STATUS0 LPCG working status 0x63F0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG31_STATUS1 LPCG low power status 0x63F4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG31_CONFIG LPCG configuration 0x63F8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG31_AUTHEN LPCG access control 0x63FC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG32_DIRECT LPCG direct control 0x6400 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG32_DOMAIN LPCG domain control 0x6404 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG32_SETPOINT LPCG Setpoint setting 0x6408 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG32_STATUS0 LPCG working status 0x6410 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG32_STATUS1 LPCG low power status 0x6414 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG32_CONFIG LPCG configuration 0x6418 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG32_AUTHEN LPCG access control 0x641C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG33_DIRECT LPCG direct control 0x6420 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG33_DOMAIN LPCG domain control 0x6424 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG33_SETPOINT LPCG Setpoint setting 0x6428 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG33_STATUS0 LPCG working status 0x6430 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG33_STATUS1 LPCG low power status 0x6434 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG33_CONFIG LPCG configuration 0x6438 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG33_AUTHEN LPCG access control 0x643C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG34_DIRECT LPCG direct control 0x6440 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG34_DOMAIN LPCG domain control 0x6444 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG34_SETPOINT LPCG Setpoint setting 0x6448 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG34_STATUS0 LPCG working status 0x6450 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG34_STATUS1 LPCG low power status 0x6454 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG34_CONFIG LPCG configuration 0x6458 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG34_AUTHEN LPCG access control 0x645C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG35_DIRECT LPCG direct control 0x6460 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG35_DOMAIN LPCG domain control 0x6464 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG35_SETPOINT LPCG Setpoint setting 0x6468 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG35_STATUS0 LPCG working status 0x6470 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG35_STATUS1 LPCG low power status 0x6474 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG35_CONFIG LPCG configuration 0x6478 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG35_AUTHEN LPCG access control 0x647C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG36_DIRECT LPCG direct control 0x6480 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG36_DOMAIN LPCG domain control 0x6484 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG36_SETPOINT LPCG Setpoint setting 0x6488 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG36_STATUS0 LPCG working status 0x6490 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG36_STATUS1 LPCG low power status 0x6494 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG36_CONFIG LPCG configuration 0x6498 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG36_AUTHEN LPCG access control 0x649C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG37_DIRECT LPCG direct control 0x64A0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG37_DOMAIN LPCG domain control 0x64A4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG37_SETPOINT LPCG Setpoint setting 0x64A8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG37_STATUS0 LPCG working status 0x64B0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG37_STATUS1 LPCG low power status 0x64B4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG37_CONFIG LPCG configuration 0x64B8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG37_AUTHEN LPCG access control 0x64BC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG38_DIRECT LPCG direct control 0x64C0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG38_DOMAIN LPCG domain control 0x64C4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG38_SETPOINT LPCG Setpoint setting 0x64C8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG38_STATUS0 LPCG working status 0x64D0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG38_STATUS1 LPCG low power status 0x64D4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG38_CONFIG LPCG configuration 0x64D8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG38_AUTHEN LPCG access control 0x64DC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG39_DIRECT LPCG direct control 0x64E0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG39_DOMAIN LPCG domain control 0x64E4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG39_SETPOINT LPCG Setpoint setting 0x64E8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG39_STATUS0 LPCG working status 0x64F0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG39_STATUS1 LPCG low power status 0x64F4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG39_CONFIG LPCG configuration 0x64F8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG39_AUTHEN LPCG access control 0x64FC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG40_DIRECT LPCG direct control 0x6500 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG40_DOMAIN LPCG domain control 0x6504 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG40_SETPOINT LPCG Setpoint setting 0x6508 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG40_STATUS0 LPCG working status 0x6510 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG40_STATUS1 LPCG low power status 0x6514 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG40_CONFIG LPCG configuration 0x6518 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG40_AUTHEN LPCG access control 0x651C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG41_DIRECT LPCG direct control 0x6520 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG41_DOMAIN LPCG domain control 0x6524 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG41_STATUS0 LPCG working status 0x6530 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG41_STATUS1 LPCG low power status 0x6534 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG41_CONFIG LPCG configuration 0x6538 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG41_AUTHEN LPCG access control 0x653C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG42_DIRECT LPCG direct control 0x6540 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG42_DOMAIN LPCG domain control 0x6544 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG42_STATUS0 LPCG working status 0x6550 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG42_STATUS1 LPCG low power status 0x6554 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG42_CONFIG LPCG configuration 0x6558 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG42_AUTHEN LPCG access control 0x655C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG43_DIRECT LPCG direct control 0x6560 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG43_DOMAIN LPCG domain control 0x6564 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG43_SETPOINT LPCG Setpoint setting 0x6568 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG43_STATUS0 LPCG working status 0x6570 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG43_STATUS1 LPCG low power status 0x6574 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG43_CONFIG LPCG configuration 0x6578 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG43_AUTHEN LPCG access control 0x657C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG44_DIRECT LPCG direct control 0x6580 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG44_DOMAIN LPCG domain control 0x6584 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG44_SETPOINT LPCG Setpoint setting 0x6588 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG44_STATUS0 LPCG working status 0x6590 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG44_STATUS1 LPCG low power status 0x6594 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG44_CONFIG LPCG configuration 0x6598 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG44_AUTHEN LPCG access control 0x659C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG45_DIRECT LPCG direct control 0x65A0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG45_DOMAIN LPCG domain control 0x65A4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG45_SETPOINT LPCG Setpoint setting 0x65A8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG45_STATUS0 LPCG working status 0x65B0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG45_STATUS1 LPCG low power status 0x65B4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG45_CONFIG LPCG configuration 0x65B8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG45_AUTHEN LPCG access control 0x65BC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG46_DIRECT LPCG direct control 0x65C0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG46_DOMAIN LPCG domain control 0x65C4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG46_SETPOINT LPCG Setpoint setting 0x65C8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG46_STATUS0 LPCG working status 0x65D0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG46_STATUS1 LPCG low power status 0x65D4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG46_CONFIG LPCG configuration 0x65D8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG46_AUTHEN LPCG access control 0x65DC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG47_DIRECT LPCG direct control 0x65E0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG47_DOMAIN LPCG domain control 0x65E4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG47_SETPOINT LPCG Setpoint setting 0x65E8 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG47_STATUS0 LPCG working status 0x65F0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG47_STATUS1 LPCG low power status 0x65F4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG47_CONFIG LPCG configuration 0x65F8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG47_AUTHEN LPCG access control 0x65FC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG48_DIRECT LPCG direct control 0x6600 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG48_DOMAIN LPCG domain control 0x6604 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG48_SETPOINT LPCG Setpoint setting 0x6608 32 read-write 0 0xFFFFFFFF SETPOINT Setpoints 0 16 read-write STANDBY Standby 16 16 read-write LPCG48_STATUS0 LPCG working status 0x6610 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG48_STATUS1 LPCG low power status 0x6614 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG48_CONFIG LPCG configuration 0x6618 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG48_AUTHEN LPCG access control 0x661C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG49_DIRECT LPCG direct control 0x6620 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG49_DOMAIN LPCG domain control 0x6624 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG49_STATUS0 LPCG working status 0x6630 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG49_STATUS1 LPCG low power status 0x6634 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG49_CONFIG LPCG configuration 0x6638 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG49_AUTHEN LPCG access control 0x663C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG50_DIRECT LPCG direct control 0x6640 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG50_DOMAIN LPCG domain control 0x6644 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG50_STATUS0 LPCG working status 0x6650 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG50_STATUS1 LPCG low power status 0x6654 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG50_CONFIG LPCG configuration 0x6658 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG50_AUTHEN LPCG access control 0x665C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG51_DIRECT LPCG direct control 0x6660 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG51_DOMAIN LPCG domain control 0x6664 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG51_STATUS0 LPCG working status 0x6670 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG51_STATUS1 LPCG low power status 0x6674 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG51_CONFIG LPCG configuration 0x6678 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG51_AUTHEN LPCG access control 0x667C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG52_DIRECT LPCG direct control 0x6680 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG52_DOMAIN LPCG domain control 0x6684 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG52_STATUS0 LPCG working status 0x6690 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG52_STATUS1 LPCG low power status 0x6694 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG52_CONFIG LPCG configuration 0x6698 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG52_AUTHEN LPCG access control 0x669C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG53_DIRECT LPCG direct control 0x66A0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG53_DOMAIN LPCG domain control 0x66A4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG53_STATUS0 LPCG working status 0x66B0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG53_STATUS1 LPCG low power status 0x66B4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG53_CONFIG LPCG configuration 0x66B8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG53_AUTHEN LPCG access control 0x66BC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG54_DIRECT LPCG direct control 0x66C0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG54_DOMAIN LPCG domain control 0x66C4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG54_STATUS0 LPCG working status 0x66D0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG54_STATUS1 LPCG low power status 0x66D4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG54_CONFIG LPCG configuration 0x66D8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG54_AUTHEN LPCG access control 0x66DC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG55_DIRECT LPCG direct control 0x66E0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG55_DOMAIN LPCG domain control 0x66E4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG55_STATUS0 LPCG working status 0x66F0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG55_STATUS1 LPCG low power status 0x66F4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG55_CONFIG LPCG configuration 0x66F8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG55_AUTHEN LPCG access control 0x66FC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG56_DIRECT LPCG direct control 0x6700 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG56_DOMAIN LPCG domain control 0x6704 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG56_STATUS0 LPCG working status 0x6710 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG56_STATUS1 LPCG low power status 0x6714 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG56_CONFIG LPCG configuration 0x6718 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG56_AUTHEN LPCG access control 0x671C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG57_DIRECT LPCG direct control 0x6720 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG57_DOMAIN LPCG domain control 0x6724 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG57_STATUS0 LPCG working status 0x6730 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG57_STATUS1 LPCG low power status 0x6734 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG57_CONFIG LPCG configuration 0x6738 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG57_AUTHEN LPCG access control 0x673C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG58_DIRECT LPCG direct control 0x6740 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG58_DOMAIN LPCG domain control 0x6744 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG58_STATUS0 LPCG working status 0x6750 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG58_STATUS1 LPCG low power status 0x6754 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG58_CONFIG LPCG configuration 0x6758 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG58_AUTHEN LPCG access control 0x675C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG59_DIRECT LPCG direct control 0x6760 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG59_DOMAIN LPCG domain control 0x6764 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG59_STATUS0 LPCG working status 0x6770 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG59_STATUS1 LPCG low power status 0x6774 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG59_CONFIG LPCG configuration 0x6778 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG59_AUTHEN LPCG access control 0x677C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG60_DIRECT LPCG direct control 0x6780 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG60_DOMAIN LPCG domain control 0x6784 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG60_STATUS0 LPCG working status 0x6790 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG60_STATUS1 LPCG low power status 0x6794 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG60_CONFIG LPCG configuration 0x6798 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG60_AUTHEN LPCG access control 0x679C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG61_DIRECT LPCG direct control 0x67A0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG61_DOMAIN LPCG domain control 0x67A4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG61_STATUS0 LPCG working status 0x67B0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG61_STATUS1 LPCG low power status 0x67B4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG61_CONFIG LPCG configuration 0x67B8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG61_AUTHEN LPCG access control 0x67BC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG62_DIRECT LPCG direct control 0x67C0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG62_DOMAIN LPCG domain control 0x67C4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG62_STATUS0 LPCG working status 0x67D0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG62_STATUS1 LPCG low power status 0x67D4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG62_CONFIG LPCG configuration 0x67D8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG62_AUTHEN LPCG access control 0x67DC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG63_DIRECT LPCG direct control 0x67E0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG63_DOMAIN LPCG domain control 0x67E4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG63_STATUS0 LPCG working status 0x67F0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG63_STATUS1 LPCG low power status 0x67F4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG63_CONFIG LPCG configuration 0x67F8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG63_AUTHEN LPCG access control 0x67FC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG64_DIRECT LPCG direct control 0x6800 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG64_DOMAIN LPCG domain control 0x6804 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG64_STATUS0 LPCG working status 0x6810 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG64_STATUS1 LPCG low power status 0x6814 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG64_CONFIG LPCG configuration 0x6818 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG64_AUTHEN LPCG access control 0x681C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG65_DIRECT LPCG direct control 0x6820 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG65_DOMAIN LPCG domain control 0x6824 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG65_STATUS0 LPCG working status 0x6830 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG65_STATUS1 LPCG low power status 0x6834 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG65_CONFIG LPCG configuration 0x6838 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG65_AUTHEN LPCG access control 0x683C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG66_DIRECT LPCG direct control 0x6840 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG66_DOMAIN LPCG domain control 0x6844 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG66_STATUS0 LPCG working status 0x6850 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG66_STATUS1 LPCG low power status 0x6854 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG66_CONFIG LPCG configuration 0x6858 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG66_AUTHEN LPCG access control 0x685C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG67_DIRECT LPCG direct control 0x6860 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG67_DOMAIN LPCG domain control 0x6864 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG67_STATUS0 LPCG working status 0x6870 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG67_STATUS1 LPCG low power status 0x6874 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG67_CONFIG LPCG configuration 0x6878 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG67_AUTHEN LPCG access control 0x687C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG68_DIRECT LPCG direct control 0x6880 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG68_DOMAIN LPCG domain control 0x6884 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG68_STATUS0 LPCG working status 0x6890 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG68_STATUS1 LPCG low power status 0x6894 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG68_CONFIG LPCG configuration 0x6898 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG68_AUTHEN LPCG access control 0x689C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG69_DIRECT LPCG direct control 0x68A0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG69_DOMAIN LPCG domain control 0x68A4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG69_STATUS0 LPCG working status 0x68B0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG69_STATUS1 LPCG low power status 0x68B4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG69_CONFIG LPCG configuration 0x68B8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG69_AUTHEN LPCG access control 0x68BC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG70_DIRECT LPCG direct control 0x68C0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG70_DOMAIN LPCG domain control 0x68C4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG70_STATUS0 LPCG working status 0x68D0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG70_STATUS1 LPCG low power status 0x68D4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG70_CONFIG LPCG configuration 0x68D8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG70_AUTHEN LPCG access control 0x68DC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG71_DIRECT LPCG direct control 0x68E0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG71_DOMAIN LPCG domain control 0x68E4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG71_STATUS0 LPCG working status 0x68F0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG71_STATUS1 LPCG low power status 0x68F4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG71_CONFIG LPCG configuration 0x68F8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG71_AUTHEN LPCG access control 0x68FC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG72_DIRECT LPCG direct control 0x6900 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG72_DOMAIN LPCG domain control 0x6904 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG72_STATUS0 LPCG working status 0x6910 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG72_STATUS1 LPCG low power status 0x6914 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG72_CONFIG LPCG configuration 0x6918 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG72_AUTHEN LPCG access control 0x691C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG73_DIRECT LPCG direct control 0x6920 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG73_DOMAIN LPCG domain control 0x6924 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG73_STATUS0 LPCG working status 0x6930 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG73_STATUS1 LPCG low power status 0x6934 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG73_CONFIG LPCG configuration 0x6938 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG73_AUTHEN LPCG access control 0x693C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG74_DIRECT LPCG direct control 0x6940 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG74_DOMAIN LPCG domain control 0x6944 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG74_STATUS0 LPCG working status 0x6950 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG74_STATUS1 LPCG low power status 0x6954 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG74_CONFIG LPCG configuration 0x6958 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG74_AUTHEN LPCG access control 0x695C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG75_DIRECT LPCG direct control 0x6960 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG75_DOMAIN LPCG domain control 0x6964 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG75_STATUS0 LPCG working status 0x6970 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG75_STATUS1 LPCG low power status 0x6974 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG75_CONFIG LPCG configuration 0x6978 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG75_AUTHEN LPCG access control 0x697C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG76_DIRECT LPCG direct control 0x6980 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG76_DOMAIN LPCG domain control 0x6984 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG76_STATUS0 LPCG working status 0x6990 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG76_STATUS1 LPCG low power status 0x6994 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG76_CONFIG LPCG configuration 0x6998 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG76_AUTHEN LPCG access control 0x699C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG77_DIRECT LPCG direct control 0x69A0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG77_DOMAIN LPCG domain control 0x69A4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG77_STATUS0 LPCG working status 0x69B0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG77_STATUS1 LPCG low power status 0x69B4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG77_CONFIG LPCG configuration 0x69B8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG77_AUTHEN LPCG access control 0x69BC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG78_DIRECT LPCG direct control 0x69C0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG78_DOMAIN LPCG domain control 0x69C4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG78_STATUS0 LPCG working status 0x69D0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG78_STATUS1 LPCG low power status 0x69D4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG78_CONFIG LPCG configuration 0x69D8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG78_AUTHEN LPCG access control 0x69DC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG79_DIRECT LPCG direct control 0x69E0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG79_DOMAIN LPCG domain control 0x69E4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG79_STATUS0 LPCG working status 0x69F0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG79_STATUS1 LPCG low power status 0x69F4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG79_CONFIG LPCG configuration 0x69F8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG79_AUTHEN LPCG access control 0x69FC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG80_DIRECT LPCG direct control 0x6A00 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG80_DOMAIN LPCG domain control 0x6A04 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG80_STATUS0 LPCG working status 0x6A10 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG80_STATUS1 LPCG low power status 0x6A14 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG80_CONFIG LPCG configuration 0x6A18 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG80_AUTHEN LPCG access control 0x6A1C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG81_DIRECT LPCG direct control 0x6A20 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG81_DOMAIN LPCG domain control 0x6A24 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG81_STATUS0 LPCG working status 0x6A30 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG81_STATUS1 LPCG low power status 0x6A34 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG81_CONFIG LPCG configuration 0x6A38 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG81_AUTHEN LPCG access control 0x6A3C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG82_DIRECT LPCG direct control 0x6A40 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG82_DOMAIN LPCG domain control 0x6A44 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG82_STATUS0 LPCG working status 0x6A50 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG82_STATUS1 LPCG low power status 0x6A54 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG82_CONFIG LPCG configuration 0x6A58 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG82_AUTHEN LPCG access control 0x6A5C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG83_DIRECT LPCG direct control 0x6A60 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG83_DOMAIN LPCG domain control 0x6A64 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG83_STATUS0 LPCG working status 0x6A70 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG83_STATUS1 LPCG low power status 0x6A74 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG83_CONFIG LPCG configuration 0x6A78 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG83_AUTHEN LPCG access control 0x6A7C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG84_DIRECT LPCG direct control 0x6A80 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG84_DOMAIN LPCG domain control 0x6A84 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG84_STATUS0 LPCG working status 0x6A90 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG84_STATUS1 LPCG low power status 0x6A94 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG84_CONFIG LPCG configuration 0x6A98 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG84_AUTHEN LPCG access control 0x6A9C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG85_DIRECT LPCG direct control 0x6AA0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG85_DOMAIN LPCG domain control 0x6AA4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG85_STATUS0 LPCG working status 0x6AB0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG85_STATUS1 LPCG low power status 0x6AB4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG85_CONFIG LPCG configuration 0x6AB8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG85_AUTHEN LPCG access control 0x6ABC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG86_DIRECT LPCG direct control 0x6AC0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG86_DOMAIN LPCG domain control 0x6AC4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG86_STATUS0 LPCG working status 0x6AD0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG86_STATUS1 LPCG low power status 0x6AD4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG86_CONFIG LPCG configuration 0x6AD8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG86_AUTHEN LPCG access control 0x6ADC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG87_DIRECT LPCG direct control 0x6AE0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG87_DOMAIN LPCG domain control 0x6AE4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG87_STATUS0 LPCG working status 0x6AF0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG87_STATUS1 LPCG low power status 0x6AF4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG87_CONFIG LPCG configuration 0x6AF8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG87_AUTHEN LPCG access control 0x6AFC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG88_DIRECT LPCG direct control 0x6B00 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG88_DOMAIN LPCG domain control 0x6B04 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG88_STATUS0 LPCG working status 0x6B10 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG88_STATUS1 LPCG low power status 0x6B14 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG88_CONFIG LPCG configuration 0x6B18 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG88_AUTHEN LPCG access control 0x6B1C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG89_DIRECT LPCG direct control 0x6B20 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG89_DOMAIN LPCG domain control 0x6B24 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG89_STATUS0 LPCG working status 0x6B30 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG89_STATUS1 LPCG low power status 0x6B34 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG89_CONFIG LPCG configuration 0x6B38 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG89_AUTHEN LPCG access control 0x6B3C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG90_DIRECT LPCG direct control 0x6B40 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG90_DOMAIN LPCG domain control 0x6B44 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG90_STATUS0 LPCG working status 0x6B50 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG90_STATUS1 LPCG low power status 0x6B54 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG90_CONFIG LPCG configuration 0x6B58 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG90_AUTHEN LPCG access control 0x6B5C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG91_DIRECT LPCG direct control 0x6B60 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG91_DOMAIN LPCG domain control 0x6B64 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG91_STATUS0 LPCG working status 0x6B70 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG91_STATUS1 LPCG low power status 0x6B74 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG91_CONFIG LPCG configuration 0x6B78 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG91_AUTHEN LPCG access control 0x6B7C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG92_DIRECT LPCG direct control 0x6B80 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG92_DOMAIN LPCG domain control 0x6B84 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG92_STATUS0 LPCG working status 0x6B90 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG92_STATUS1 LPCG low power status 0x6B94 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG92_CONFIG LPCG configuration 0x6B98 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG92_AUTHEN LPCG access control 0x6B9C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG93_DIRECT LPCG direct control 0x6BA0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG93_DOMAIN LPCG domain control 0x6BA4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG93_STATUS0 LPCG working status 0x6BB0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG93_STATUS1 LPCG low power status 0x6BB4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG93_CONFIG LPCG configuration 0x6BB8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG93_AUTHEN LPCG access control 0x6BBC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG94_DIRECT LPCG direct control 0x6BC0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG94_DOMAIN LPCG domain control 0x6BC4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG94_STATUS0 LPCG working status 0x6BD0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG94_STATUS1 LPCG low power status 0x6BD4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG94_CONFIG LPCG configuration 0x6BD8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG94_AUTHEN LPCG access control 0x6BDC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG95_DIRECT LPCG direct control 0x6BE0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG95_DOMAIN LPCG domain control 0x6BE4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG95_STATUS0 LPCG working status 0x6BF0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG95_STATUS1 LPCG low power status 0x6BF4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG95_CONFIG LPCG configuration 0x6BF8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG95_AUTHEN LPCG access control 0x6BFC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG96_DIRECT LPCG direct control 0x6C00 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG96_DOMAIN LPCG domain control 0x6C04 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG96_STATUS0 LPCG working status 0x6C10 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG96_STATUS1 LPCG low power status 0x6C14 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG96_CONFIG LPCG configuration 0x6C18 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG96_AUTHEN LPCG access control 0x6C1C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG97_DIRECT LPCG direct control 0x6C20 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG97_DOMAIN LPCG domain control 0x6C24 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG97_STATUS0 LPCG working status 0x6C30 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG97_STATUS1 LPCG low power status 0x6C34 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG97_CONFIG LPCG configuration 0x6C38 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG97_AUTHEN LPCG access control 0x6C3C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG98_DIRECT LPCG direct control 0x6C40 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG98_DOMAIN LPCG domain control 0x6C44 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG98_STATUS0 LPCG working status 0x6C50 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG98_STATUS1 LPCG low power status 0x6C54 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG98_CONFIG LPCG configuration 0x6C58 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG98_AUTHEN LPCG access control 0x6C5C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG99_DIRECT LPCG direct control 0x6C60 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG99_DOMAIN LPCG domain control 0x6C64 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG99_STATUS0 LPCG working status 0x6C70 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG99_STATUS1 LPCG low power status 0x6C74 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG99_CONFIG LPCG configuration 0x6C78 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG99_AUTHEN LPCG access control 0x6C7C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG100_DIRECT LPCG direct control 0x6C80 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG100_DOMAIN LPCG domain control 0x6C84 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG100_STATUS0 LPCG working status 0x6C90 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG100_STATUS1 LPCG low power status 0x6C94 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG100_CONFIG LPCG configuration 0x6C98 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG100_AUTHEN LPCG access control 0x6C9C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG101_DIRECT LPCG direct control 0x6CA0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG101_DOMAIN LPCG domain control 0x6CA4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG101_STATUS0 LPCG working status 0x6CB0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG101_STATUS1 LPCG low power status 0x6CB4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG101_CONFIG LPCG configuration 0x6CB8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG101_AUTHEN LPCG access control 0x6CBC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG102_DIRECT LPCG direct control 0x6CC0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG102_DOMAIN LPCG domain control 0x6CC4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG102_STATUS0 LPCG working status 0x6CD0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG102_STATUS1 LPCG low power status 0x6CD4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG102_CONFIG LPCG configuration 0x6CD8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG102_AUTHEN LPCG access control 0x6CDC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG103_DIRECT LPCG direct control 0x6CE0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG103_DOMAIN LPCG domain control 0x6CE4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG103_STATUS0 LPCG working status 0x6CF0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG103_STATUS1 LPCG low power status 0x6CF4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG103_CONFIG LPCG configuration 0x6CF8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG103_AUTHEN LPCG access control 0x6CFC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG104_DIRECT LPCG direct control 0x6D00 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG104_DOMAIN LPCG domain control 0x6D04 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG104_STATUS0 LPCG working status 0x6D10 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG104_STATUS1 LPCG low power status 0x6D14 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG104_CONFIG LPCG configuration 0x6D18 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG104_AUTHEN LPCG access control 0x6D1C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG105_DIRECT LPCG direct control 0x6D20 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG105_DOMAIN LPCG domain control 0x6D24 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG105_STATUS0 LPCG working status 0x6D30 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG105_STATUS1 LPCG low power status 0x6D34 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG105_CONFIG LPCG configuration 0x6D38 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG105_AUTHEN LPCG access control 0x6D3C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG106_DIRECT LPCG direct control 0x6D40 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG106_DOMAIN LPCG domain control 0x6D44 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG106_STATUS0 LPCG working status 0x6D50 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG106_STATUS1 LPCG low power status 0x6D54 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG106_CONFIG LPCG configuration 0x6D58 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG106_AUTHEN LPCG access control 0x6D5C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG107_DIRECT LPCG direct control 0x6D60 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG107_DOMAIN LPCG domain control 0x6D64 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG107_STATUS0 LPCG working status 0x6D70 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG107_STATUS1 LPCG low power status 0x6D74 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG107_CONFIG LPCG configuration 0x6D78 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG107_AUTHEN LPCG access control 0x6D7C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG108_DIRECT LPCG direct control 0x6D80 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG108_DOMAIN LPCG domain control 0x6D84 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG108_STATUS0 LPCG working status 0x6D90 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG108_STATUS1 LPCG low power status 0x6D94 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG108_CONFIG LPCG configuration 0x6D98 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG108_AUTHEN LPCG access control 0x6D9C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG109_DIRECT LPCG direct control 0x6DA0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG109_DOMAIN LPCG domain control 0x6DA4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG109_STATUS0 LPCG working status 0x6DB0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG109_STATUS1 LPCG low power status 0x6DB4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG109_CONFIG LPCG configuration 0x6DB8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG109_AUTHEN LPCG access control 0x6DBC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG110_DIRECT LPCG direct control 0x6DC0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG110_DOMAIN LPCG domain control 0x6DC4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG110_STATUS0 LPCG working status 0x6DD0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG110_STATUS1 LPCG low power status 0x6DD4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG110_CONFIG LPCG configuration 0x6DD8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG110_AUTHEN LPCG access control 0x6DDC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG111_DIRECT LPCG direct control 0x6DE0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG111_DOMAIN LPCG domain control 0x6DE4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG111_STATUS0 LPCG working status 0x6DF0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG111_STATUS1 LPCG low power status 0x6DF4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG111_CONFIG LPCG configuration 0x6DF8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG111_AUTHEN LPCG access control 0x6DFC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG112_DIRECT LPCG direct control 0x6E00 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG112_DOMAIN LPCG domain control 0x6E04 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG112_STATUS0 LPCG working status 0x6E10 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG112_STATUS1 LPCG low power status 0x6E14 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG112_CONFIG LPCG configuration 0x6E18 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG112_AUTHEN LPCG access control 0x6E1C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG113_DIRECT LPCG direct control 0x6E20 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG113_DOMAIN LPCG domain control 0x6E24 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG113_STATUS0 LPCG working status 0x6E30 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG113_STATUS1 LPCG low power status 0x6E34 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG113_CONFIG LPCG configuration 0x6E38 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG113_AUTHEN LPCG access control 0x6E3C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG114_DIRECT LPCG direct control 0x6E40 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG114_DOMAIN LPCG domain control 0x6E44 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG114_STATUS0 LPCG working status 0x6E50 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG114_STATUS1 LPCG low power status 0x6E54 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG114_CONFIG LPCG configuration 0x6E58 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG114_AUTHEN LPCG access control 0x6E5C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG115_DIRECT LPCG direct control 0x6E60 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG115_DOMAIN LPCG domain control 0x6E64 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG115_STATUS0 LPCG working status 0x6E70 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG115_STATUS1 LPCG low power status 0x6E74 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG115_CONFIG LPCG configuration 0x6E78 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG115_AUTHEN LPCG access control 0x6E7C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG116_DIRECT LPCG direct control 0x6E80 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG116_DOMAIN LPCG domain control 0x6E84 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG116_STATUS0 LPCG working status 0x6E90 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG116_STATUS1 LPCG low power status 0x6E94 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG116_CONFIG LPCG configuration 0x6E98 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG116_AUTHEN LPCG access control 0x6E9C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG117_DIRECT LPCG direct control 0x6EA0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG117_DOMAIN LPCG domain control 0x6EA4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG117_STATUS0 LPCG working status 0x6EB0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG117_STATUS1 LPCG low power status 0x6EB4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG117_CONFIG LPCG configuration 0x6EB8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG117_AUTHEN LPCG access control 0x6EBC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG118_DIRECT LPCG direct control 0x6EC0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG118_DOMAIN LPCG domain control 0x6EC4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG118_STATUS0 LPCG working status 0x6ED0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG118_STATUS1 LPCG low power status 0x6ED4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG118_CONFIG LPCG configuration 0x6ED8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG118_AUTHEN LPCG access control 0x6EDC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG119_DIRECT LPCG direct control 0x6EE0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG119_DOMAIN LPCG domain control 0x6EE4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG119_STATUS0 LPCG working status 0x6EF0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG119_STATUS1 LPCG low power status 0x6EF4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG119_CONFIG LPCG configuration 0x6EF8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG119_AUTHEN LPCG access control 0x6EFC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG120_DIRECT LPCG direct control 0x6F00 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG120_DOMAIN LPCG domain control 0x6F04 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG120_STATUS0 LPCG working status 0x6F10 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG120_STATUS1 LPCG low power status 0x6F14 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG120_CONFIG LPCG configuration 0x6F18 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG120_AUTHEN LPCG access control 0x6F1C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG121_DIRECT LPCG direct control 0x6F20 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG121_DOMAIN LPCG domain control 0x6F24 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG121_STATUS0 LPCG working status 0x6F30 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG121_STATUS1 LPCG low power status 0x6F34 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG121_CONFIG LPCG configuration 0x6F38 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG121_AUTHEN LPCG access control 0x6F3C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG122_DIRECT LPCG direct control 0x6F40 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG122_DOMAIN LPCG domain control 0x6F44 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG122_STATUS0 LPCG working status 0x6F50 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG122_STATUS1 LPCG low power status 0x6F54 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG122_CONFIG LPCG configuration 0x6F58 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG122_AUTHEN LPCG access control 0x6F5C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG123_DIRECT LPCG direct control 0x6F60 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG123_DOMAIN LPCG domain control 0x6F64 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG123_STATUS0 LPCG working status 0x6F70 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG123_STATUS1 LPCG low power status 0x6F74 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG123_CONFIG LPCG configuration 0x6F78 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG123_AUTHEN LPCG access control 0x6F7C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG124_DIRECT LPCG direct control 0x6F80 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG124_DOMAIN LPCG domain control 0x6F84 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG124_STATUS0 LPCG working status 0x6F90 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG124_STATUS1 LPCG low power status 0x6F94 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG124_CONFIG LPCG configuration 0x6F98 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG124_AUTHEN LPCG access control 0x6F9C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG125_DIRECT LPCG direct control 0x6FA0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG125_DOMAIN LPCG domain control 0x6FA4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG125_STATUS0 LPCG working status 0x6FB0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG125_STATUS1 LPCG low power status 0x6FB4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG125_CONFIG LPCG configuration 0x6FB8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG125_AUTHEN LPCG access control 0x6FBC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG126_DIRECT LPCG direct control 0x6FC0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG126_DOMAIN LPCG domain control 0x6FC4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG126_STATUS0 LPCG working status 0x6FD0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG126_STATUS1 LPCG low power status 0x6FD4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG126_CONFIG LPCG configuration 0x6FD8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG126_AUTHEN LPCG access control 0x6FDC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG127_DIRECT LPCG direct control 0x6FE0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG127_DOMAIN LPCG domain control 0x6FE4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG127_STATUS0 LPCG working status 0x6FF0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG127_STATUS1 LPCG low power status 0x6FF4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG127_CONFIG LPCG configuration 0x6FF8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG127_AUTHEN LPCG access control 0x6FFC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG128_DIRECT LPCG direct control 0x7000 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG128_DOMAIN LPCG domain control 0x7004 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG128_STATUS0 LPCG working status 0x7010 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG128_STATUS1 LPCG low power status 0x7014 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG128_CONFIG LPCG configuration 0x7018 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG128_AUTHEN LPCG access control 0x701C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG129_DIRECT LPCG direct control 0x7020 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG129_DOMAIN LPCG domain control 0x7024 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG129_STATUS0 LPCG working status 0x7030 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG129_STATUS1 LPCG low power status 0x7034 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG129_CONFIG LPCG configuration 0x7038 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG129_AUTHEN LPCG access control 0x703C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG130_DIRECT LPCG direct control 0x7040 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG130_DOMAIN LPCG domain control 0x7044 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG130_STATUS0 LPCG working status 0x7050 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG130_STATUS1 LPCG low power status 0x7054 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG130_CONFIG LPCG configuration 0x7058 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG130_AUTHEN LPCG access control 0x705C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG131_DIRECT LPCG direct control 0x7060 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG131_DOMAIN LPCG domain control 0x7064 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG131_STATUS0 LPCG working status 0x7070 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG131_STATUS1 LPCG low power status 0x7074 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG131_CONFIG LPCG configuration 0x7078 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG131_AUTHEN LPCG access control 0x707C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG132_DIRECT LPCG direct control 0x7080 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG132_DOMAIN LPCG domain control 0x7084 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG132_STATUS0 LPCG working status 0x7090 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG132_STATUS1 LPCG low power status 0x7094 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG132_CONFIG LPCG configuration 0x7098 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG132_AUTHEN LPCG access control 0x709C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG133_DIRECT LPCG direct control 0x70A0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG133_DOMAIN LPCG domain control 0x70A4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG133_STATUS0 LPCG working status 0x70B0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG133_STATUS1 LPCG low power status 0x70B4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG133_CONFIG LPCG configuration 0x70B8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG133_AUTHEN LPCG access control 0x70BC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG134_DIRECT LPCG direct control 0x70C0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG134_DOMAIN LPCG domain control 0x70C4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG134_STATUS0 LPCG working status 0x70D0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG134_STATUS1 LPCG low power status 0x70D4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG134_CONFIG LPCG configuration 0x70D8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG134_AUTHEN LPCG access control 0x70DC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG135_DIRECT LPCG direct control 0x70E0 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG135_DOMAIN LPCG domain control 0x70E4 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG135_STATUS0 LPCG working status 0x70F0 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG135_STATUS1 LPCG low power status 0x70F4 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG135_CONFIG LPCG configuration 0x70F8 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG135_AUTHEN LPCG access control 0x70FC 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG136_DIRECT LPCG direct control 0x7100 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG136_DOMAIN LPCG domain control 0x7104 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG136_STATUS0 LPCG working status 0x7110 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG136_STATUS1 LPCG low power status 0x7114 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG136_CONFIG LPCG configuration 0x7118 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG136_AUTHEN LPCG access control 0x711C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 LPCG137_DIRECT LPCG direct control 0x7120 32 read-write 0x1 0xFFFFFFFF ON LPCG on 0 1 read-write ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 LPCG137_DOMAIN LPCG domain control 0x7124 32 read-write 0x10001 0xFFFFFFFF LEVEL Current dependence level 0 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL0 Depend level 16 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL1 Depend level 20 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL2 Depend level 24 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LEVEL3 Depend level 28 3 read-write NO This clock source is not needed in any mode, and can be turned off 0 R This clock source is needed in RUN mode, but not needed in WAIT, STOP mode 0x1 RW This clock source is needed in RUN and WAIT mode, but not needed in STOP mode 0x2 RWS This clock source is needed in RUN, WAIT and STOP mode 0x3 ALL This clock source is always on in any mode (including SUSPEND) 0x4 LPCG137_STATUS0 LPCG working status 0x7130 32 read-only 0 0xFFFFFFFF ON LPCG current state 0 1 read-only ON_0 LPCG is OFF. 0 ON_1 LPCG is ON. 0x1 ACTIVE_DOMAIN Domains that own this clock gate 8 4 read-only NO Clock not owned by any domain 0 ZERO Clock owned by Domain0 0x1 TWO Clock owned by Domain1 0x2 THREE Clock owned by Domain0 and Domain1 0x3 FOUR Clock owned by Domain2 0x4 FIVE Clock owned by Domain0 and Domain2 0x5 SIX Clock owned by Domain1 and Domain2 0x6 SEVEN Clock owned by Domain0, Domain1 and Domain 2 0x7 EIGHT Clock owned by Domain3 0x8 NINE Clock owned by Domain0 and Domain3 0x9 TEN Clock owned by Domain1 and Domain3 0xA ELV Clock owned by Domain2 and Domain3 0xB TW Clock owned by Domain0, Domain 1, and Domain3 0xC TH Clock owned by Domain0, Domain 2, and Domain3 0xD FR Clock owned by Domain1, Domain 2, and Domain3 0xE all Clock owned by all domains 0xF DOMAIN_ENABLE Enable status from each domain 12 4 read-only NO No domain request 0 ZERO Request from Domain0 0x1 TWO Request from Domain1 0x2 THREE Request from Domain0 and Domain1 0x3 FOUR Request from Domain2 0x4 FIVE Request from Domain0 and Domain2 0x5 SIX Request from Domain1 and Domain2 0x6 SEVEN Request from Domain0, Domain1 and Domain 2 0x7 EIGHT Request from Domain3 0x8 NINE Request from Domain0 and Domain3 0x9 TEN Request from Domain1 and Domain3 0xA ELV Request from Domain2 and Domain3 0xB TW Request from Domain0, Domain 1, and Domain3 0xC TH Request from Domain0, Domain 2, and Domain3 0xD FR Request from Domain1, Domain 2, and Domain3 0xE all Request from all domains 0xF LPCG137_STATUS1 LPCG low power status 0x7134 32 read-only 0 0xFFFFFFFF CPU0_MODE Domain0 Low Power Mode 0 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU0_MODE_REQUEST Domain0 request enter Low Power Mode 2 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU0_MODE_DONE Domain0 Low Power Mode task done 3 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU1_MODE Domain1 Low Power Mode 4 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU1_MODE_REQUEST Domain1 request enter Low Power Mode 6 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU1_MODE_DONE Domain1 Low Power Mode task done 7 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU2_MODE Domain2 Low Power Mode 8 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU2_MODE_REQUEST Domain2 request enter Low Power Mode 10 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU2_MODE_DONE Domain2 Low Power Mode task done 11 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 CPU3_MODE Domain3 Low Power Mode 12 2 read-only RUN Run 0 WAIT Wait 0x1 STOP Stop 0x2 SUSPEND Suspend 0x3 CPU3_MODE_REQUEST Domain3 request enter Low Power Mode 14 1 read-only DIS No request 0 ENABLE Request from domain to enter Low Power Mode 0x1 CPU3_MODE_DONE Domain3 Low Power Mode task done 15 1 read-only DIS Clock is not gated 0 ENABLE Clock is gated-off 0x1 TARGET_SETPOINT Next Setpoint to change to 16 4 read-only CURRENT_SETPOINT Current Setpoint 20 4 read-only SETPOINT_OFF_REQUEST Clock gate turn off request from GPC Setpoint 24 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned off 0x1 SETPOINT_OFF_DONE Clock gate turn off finish from GPC Setpoint 25 1 read-only DIS Clock gate is not turned off 0 ENABLE Clock gate is turned off 0x1 SETPOINT_ON_REQUEST Clock gate turn on request from GPC Setpoint 26 1 read-only DIS No request 0 ENABLE Clock gate requested to be turned on 0x1 SETPOINT_ON_DONE Clock gate turn on finish from GPC Setpoint 27 1 read-only DIS Clock gate is not turned on 0 ENABLE Clock gate is turned on 0x1 LPCG137_CONFIG LPCG configuration 0x7138 32 read-only 0 0 SETPOINT_PRESENT Setpoint present 4 1 read-only SETPOINT_PRESENT_0 Setpoint is not implemented. 0 SETPOINT_PRESENT_1 Setpoint is implemented. 0x1 LPCG137_AUTHEN LPCG access control 0x713C 32 read-write 0 0xFFFFFFFF TZ_USER User access 0 1 read-write TZ_USER_0 LPCG cannot be changed in user mode. 0 TZ_USER_1 LPCG can be changed in user mode. 0x1 TZ_NS Non-secure access 1 1 read-write TZ_NS_0 Cannot be changed in Non-secure mode. 0 TZ_NS_1 Can be changed in Non-secure mode. 0x1 LOCK_TZ lock truszone setting 4 1 read-write LOCK_TZ_0 Trustzone setting is not locked. 0 LOCK_TZ_1 Trustzone setting is locked. 0x1 WHITE_LIST Whitelist 8 4 read-write LOCK_LIST Lock Whitelist 12 1 read-write LOCK_LIST_0 Whitelist is not locked. 0 LOCK_LIST_1 Whitelist is locked. 0x1 DOMAIN_MODE Low power and access control by domain 16 1 read-write DOMAIN_MODE_0 Clock does not work in Domain Mode 0 DOMAIN_MODE_1 Clock works in Domain Mode 0x1 SETPOINT_MODE Low power and access control by Setpoint 17 1 read-write DISABLE LPCG is not functioning in Setpoint controlled Mode 0 ENABLE LPCG is functioning in Setpoint controlled Mode 0x1 CPULPM CPU Low Power Mode 18 1 read-write DISABLE LPCG is not functioning in Low power Mode 0 ENABLE LPCG is functioning in Low Power Mode 0x1 LOCK_MODE Lock low power and access mode 20 1 read-write LOCK_MODE_0 MODE is not locked. 0 LOCK_MODE_1 MODE is locked. 0x1 SEMA4 IPS_Semaphores SEMA4 SEMA4_ 0x40CC8000 0 0x106 registers SEMA4_CP0 175 SEMA4_CP1 176 16 0x1 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 Gate%s Semaphores Gate n Register 0 8 read-write 0 0xFF GTFSM Gate Finite State Machine. 0 2 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. 0x3 2 0x8 0,1 CP%sINE Semaphores Processor n IRQ Notification Enable 0x40 16 read-write 0 0xFFFF INE7 Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 7. 0 1 read-write INE7_0 The generation of the notification interrupt is disabled. 0 INE7_1 The generation of the notification interrupt is enabled. 0x1 INE6 Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 6. 1 1 read-write INE6_0 The generation of the notification interrupt is disabled. 0 INE6_1 The generation of the notification interrupt is enabled. 0x1 INE5 Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 5. 2 1 read-write INE5_0 The generation of the notification interrupt is disabled. 0 INE5_1 The generation of the notification interrupt is enabled. 0x1 INE4 Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 4. 3 1 read-write INE4_0 The generation of the notification interrupt is disabled. 0 INE4_1 The generation of the notification interrupt is enabled. 0x1 INE3 Interrupt Request Notification Enable 3 4 1 read-write INE3_0 The generation of the notification interrupt is disabled. 0 INE3_1 The generation of the notification interrupt is enabled. 0x1 INE2 Interrupt Request Notification Enable 2 5 1 read-write INE2_0 The generation of the notification interrupt is disabled. 0 INE2_1 The generation of the notification interrupt is enabled. 0x1 INE1 Interrupt Request Notification Enable 1 6 1 read-write INE1_0 The generation of the notification interrupt is disabled. 0 INE1_1 The generation of the notification interrupt is enabled. 0x1 INE0 Interrupt Request Notification Enable 0 7 1 read-write INE0_0 The generation of the notification interrupt is disabled. 0 INE0_1 The generation of the notification interrupt is enabled. 0x1 INE15 Interrupt Request Notification Enable 15. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 15. 8 1 read-write INE15_0 The generation of the notification interrupt is disabled. 0 INE15_1 The generation of the notification interrupt is enabled. 0x1 INE14 Interrupt Request Notification Enable 14. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 14. 9 1 read-write INE14_0 The generation of the notification interrupt is disabled. 0 INE14_1 The generation of the notification interrupt is enabled. 0x1 INE13 Interrupt Request Notification Enable 13. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 13. 10 1 read-write INE13_0 The generation of the notification interrupt is disabled. 0 INE13_1 The generation of the notification interrupt is enabled. 0x1 INE12 Interrupt Request Notification Enable 12. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 12. 11 1 read-write INE12_0 The generation of the notification interrupt is disabled. 0 INE12_1 The generation of the notification interrupt is enabled. 0x1 INE11 Interrupt Request Notification Enable 11. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 11. 12 1 read-write INE11_0 The generation of the notification interrupt is disabled. 0 INE11_1 The generation of the notification interrupt is enabled. 0x1 INE10 Interrupt Request Notification Enable 10. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 10. 13 1 read-write INE10_0 The generation of the notification interrupt is disabled. 0 INE10_1 The generation of the notification interrupt is enabled. 0x1 INE9 Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 9. 14 1 read-write INE9_0 The generation of the notification interrupt is disabled. 0 INE9_1 The generation of the notification interrupt is enabled. 0x1 INE8 Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 8. 15 1 read-write INE8_0 The generation of the notification interrupt is disabled. 0 INE8_1 The generation of the notification interrupt is enabled. 0x1 2 0x8 0,1 CP%sNTF Semaphores Processor n IRQ Notification 0x80 16 read-only 0 0xFFFF GN7 Gate 7 Notification 0 1 read-only GN6 Gate 6 Notification 1 1 read-only GN5 Gate 5 Notification 2 1 read-only GN4 Gate 4 Notification 3 1 read-only GN3 Gate 3 Notification 4 1 read-only GN2 Gate 2 Notification 5 1 read-only GN1 Gate 1 Notification 6 1 read-only GN0 Gate 0 Notification 7 1 read-only GN15 Gate 15 Notification 8 1 read-only GN14 Gate 14 Notification 9 1 read-only GN13 Gate 13 Notification 10 1 read-only GN12 Gate 12 Notification 11 1 read-only GN11 Gate 11 Notification 12 1 read-only GN10 Gate 10 Notification 13 1 read-only GN9 Gate 9 Notification 14 1 read-only GN8 Gate 8 Notification 15 1 read-only RSTGT Semaphores (Secure) Reset Gate n 0x100 16 read-write 0 0xFFFF RSTGSM_RSTGMS_RSTGDP This field contains sub-fields that vary depending on whether it is being read or written 0 8 read-write RSTGTN Reset Gate Number 8 8 read-write RSTNTF Semaphores (Secure) Reset IRQ Notification 0x104 16 read-write 0 0xFFFF RSTNSM_RSTNMS_RSTNDP This field contains sub-fields that vary depending on whether it is being read or written 0 8 read-write RSTNTN Reset Notification Number 8 8 read-write XRDC2_D0 XRDC2 XRDC2 XRDC2 0x40CE0000 0 0xFFFC registers MCR Module Control Register 0 32 read-write 0 0xFFFFFFFF GVLDM Global Valid MDAC 0 1 read-write disabled MDACs are disabled. 0 enabled MDACs are enabled. 0x1 GVLDC Global Valid Access Control 1 1 read-write disabled Access controls are disabled, XRDC2 allows all transactions. 0 enabled Access controls are enabled. 0x1 GCL Global Configuration Lock 4 2 read-write disabled_00 Lock disabled, registers can be written by any domain. 0 disabled_01 Lock disabled until the next reset, registers can be written by any domain. 0x1 enabled_10 Lock enabled, only the global configuration lock owner (SR[GCLO]) can write to registers. 0x2 enabled_11 Lock enabled, all registers are read only until the next reset. 0x3 SR Status Register 0x4 32 read-only 0x10 0xFFFFFFFF DIN Domain Identifier Number 0 4 read-only HRL Hardware Revision Level 4 4 read-only GCLO Global Configuration Lock Owner 8 4 read-only 128 0x8 msci_msac_wk[%s] no description available 0x1000 MSC_MSAC_W0 Memory Slot Access Control 0 32 read-write 0 0xFFFFFFFF D0ACP Domain "x" access control policy 0 3 read-write D1ACP Domain "x" access control policy 3 3 read-write D2ACP Domain "x" access control policy 6 3 read-write D3ACP Domain "x" access control policy 9 3 read-write D4ACP Domain "x" access control policy 12 3 read-write D5ACP Domain "x" access control policy 15 3 read-write D6ACP Domain "x" access control policy 18 3 read-write D7ACP Domain "x" access control policy 21 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MSC_MSAC_W1 Memory Slot Access Control 0x4 32 read-write 0 0xFFFFFFFF D8ACP Domain "x" access control policy 0 3 read-write D9ACP Domain "x" access control policy 3 3 read-write D10ACP Domain "x" access control policy 6 3 read-write D11ACP Domain "x" access control policy 9 3 read-write D12ACP Domain "x" access control policy 12 3 read-write D13ACP Domain "x" access control policy 15 3 read-write D14ACP Domain "x" access control policy 18 3 read-write D15ACP Domain "x" access control policy 21 3 read-write EAL Exclusive Access Lock 24 2 read-write disabled_00 Lock disabled. 0 disabled_01 Lock disabled until next reset. 0x1 enabled_10 Lock enabled, lock state = available. 0x2 enabled_11 Lock enabled, lock state = not available. 0x3 DL2 Descriptor Lock 29 2 read-write disabled_00 Lock disabled, descriptor registers can be written. 0 disabled_01 Lock disabled until the next reset, descriptor registers can be written. 0x1 enabled_10 Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written. 0x2 enabled_11 Lock enabled, descriptor registers are read-only until the next reset. 0x3 VLD Valid 31 1 read-write invalid The MSAC assignment is invalid. 0 valid The MSAC assignment is valid. 0x1 32 0x100 mdaci[%s] no description available 0x2000 32 0x8 mdaci_mdaj[%s] no description available 0 MDAC_MDA_W0 Master Domain Assignment 0 32 read-write 0 0xFFFFFFFF MASK Mask 0 16 read-write MATCH Match 16 16 read-write MDAC_MDA_W1 Master Domain Assignment 0x4 32 read-write 0 0xFFFFFFFF DID Domain Identifier 16 4 read-write PA Privileged attribute 24 2 read-write pa_00 Use the bus master's privileged/user attribute directly. 0 pa_01 Use the bus master's privileged/user attribute directly. 0x1 pa_10 Force the bus attribute for this master to user. 0x2 pa_11 Force the bus attribute for this master to privileged. 0x3 SA Secure attribute 26 2 read-write sa_00 Use the bus master's secure/nonsecure attribute directly. 0 sa_01 Use the bus master's secure/nonsecure attribute directly. 0x1 sa_10 Force the bus attribute for this master to secure. 0x2 sa_11 Force the bus attribute for this master to nonsecure. 0x3 DL Descriptor Lock 30 1 read-write disabled Lock disabled, registers can be written. 0 enabled Lock enabled, registers are read-only until the next reset. 0x1 VLD Valid 31 1 read-write invalid The MDA is invalid. 0 valid The MDA is valid. 0x1 8 0x800 paci[%s] no description available 0x4000 256 0x8 paci_pdacj[%s] no description available 0 PAC_PDAC_W0 Peripheral Domain Access Control 0 32 read-write 0 0xFFFFFFFF D0ACP Domain "x" access control policy 0 3 read-write D1ACP Domain "x" access control policy 3 3 read-write D2ACP Domain "x" access control policy 6 3 read-write D3ACP Domain "x" access control policy 9 3 read-write D4ACP Domain "x" access control policy 12 3 read-write D5ACP Domain "x" access control policy 15 3 read-write D6ACP Domain "x" access control policy 18 3 read-write D7ACP Domain "x" access control policy 21 3 read-write EALO Exclusive Access Lock Owner 24 4 read-write PAC_PDAC_W1 Peripheral Domain Access Control 0x4 32 read-write 0 0xFFFFFFFF D8ACP Domain "x" access control policy 0 3 read-write D9ACP Domain "x" access control policy 3 3 read-write D10ACP Domain "x" access control policy 6 3 read-write D11ACP Domain "x" access control policy 9 3 read-write D12ACP Domain "x" access control policy 12 3 read-write D13ACP Domain "x" access control policy 15 3 read-write D14ACP Domain "x" access control policy 18 3 read-write D15ACP Domain "x" access control policy 21 3 read-write EAL Exclusive Access Lock 24 2 read-write disabled_00 Lock disabled. 0 disabled_01 Lock disabled until next reset. 0x1 enabled_10 Lock enabled, lock state = available. 0x2 enabled_11 Lock enabled, lock state = not available. 0x3 DL2 Descriptor Lock 29 2 read-write disabled_00 Lock disabled, descriptor registers can be written.. 0 disabled_01 Lock disabled until the next reset, descriptor registers can be written.. 0x1 enabled_10 Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written.. 0x2 enabled_11 Lock enabled, descriptor registers are read-only until the next reset. 0x3 VLD Valid 31 1 read-write invalid The PDAC assignment is invalid. 0 valid The PDAC assignment is valid. 0x1 32 0x400 mrci[%s] no description available 0x8000 32 0x20 mrci_mrgdj[%s] no description available 0 MRC_MRGD_W0 Memory Region Descriptor 0 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 12 20 read-write MRC_MRGD_W1 Memory Region Descriptor 0x4 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 0 4 read-write MRC_MRGD_W2 Memory Region Descriptor 0x8 32 read-write 0xFFF 0xFFFFFFFF ENDADDR End Address 12 20 read-write MRC_MRGD_W3 Memory Region Descriptor 0xC 32 read-write 0 0xFFFFFFFF ENDADDR End Address 0 4 read-write MRC_MRGD_W5 Memory Region Descriptor 0x14 32 read-write 0 0xFFFFFFFF D0ACP Domain "x" access control policy 0 3 read-write D1ACP Domain "x" access control policy 3 3 read-write D2ACP Domain "x" access control policy 6 3 read-write D3ACP Domain "x" access control policy 9 3 read-write D4ACP Domain "x" access control policy 12 3 read-write D5ACP Domain "x" access control policy 15 3 read-write D6ACP Domain "x" access control policy 18 3 read-write D7ACP Domain "x" access control policy 21 3 read-write EALO Exclusive Access Lock Owner 24 4 read-write MRC_MRGD_W6 Memory Region Descriptor 0x18 32 read-write 0 0xFFFFFFFF D8ACP Domain "x" access control policy 0 3 read-write D9ACP Domain "x" access control policy 3 3 read-write D10ACP Domain "x" access control policy 6 3 read-write D11ACP Domain "x" access control policy 9 3 read-write D12ACP Domain "x" access control policy 12 3 read-write D13ACP Domain "x" access control policy 15 3 read-write D14ACP Domain "x" access control policy 18 3 read-write D15ACP Domain "x" access control policy 21 3 read-write EAL Exclusive Access Lock 24 2 read-write disabled_00 Lock disabled. 0 disabled_01 Lock disabled until next reset. 0x1 enabled_10 Lock enabled, lock state = available. 0x2 enabled_11 Lock enabled, lock state = not available. 0x3 DL2 Descriptor Lock 29 2 read-write disabled_00 Lock disabled, descriptor registers can be written. 0 disabled_01 Lock disabled until the next reset, descriptor registers can be written. 0x1 enabled_10 Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written. 0x2 enabled_11 Lock enabled, descriptor registers are read-only until the next reset. 0x3 VLD Valid 31 1 read-write invalid The MRGD is invalid. 0 valid The MRGD is valid. 0x1 XRDC2_D1 XRDC2 XRDC2 0x40CD0000 0 0xFFFC registers CDOG CDOG CDOG 0x41900000 0 0x4C registers CDOG 75 CONTROL Control 0 32 read-write 0x50092492 0xFFFFFFFF LOCK_CTRL Lock control 0 2 read-write LOCKED Locked 0x1 UNLOCKED Unlocked 0x2 TIMEOUT_CTRL TIMEOUT fault control 2 3 read-write ENABLE_RESET Enable reset 0x1 ENABLE_INTERRUPT Enable interrupt 0x2 DISABLE_BOTH Disable both reset and interrupt 0x4 MISCOMPARE_CTRL MISCOMPARE fault control 5 3 read-write ENABLE_RESET Enable reset 0x1 ENABLE_INTERRUPT Enable interrupt 0x2 DISABLE_BOTH Disable both reset and interrupt 0x4 SEQUENCE_CTRL SEQUENCE fault control 8 3 read-write ENABLE_RESET Enable reset 0x1 ENABLE_INTERRUPT Enable interrupt 0x2 DISABLE_BOTH Disable both reset and interrupt 0x4 CONTROL_CTRL CONTROL fault control 11 3 read-write ENABLE_RESET Enable reset 0x1 DISABLE_BOTH Disable reset 0x4 STATE_CTRL STATE fault control 14 3 read-write ENABLE_RESET Enable reset 0x1 ENABLE_INTERRUPT Enable interrupt 0x2 DISABLE_BOTH Disable both reset and interrupt 0x4 ADDRESS_CTRL ADDRESS fault control 17 3 read-write ENABLE_RESET Enable reset 0x1 ENABLE_INTERRUPT Enable interrupt 0x2 DISABLE_BOTH Disable both reset and interrupt 0x4 IRQ_PAUSE IRQ pause control 28 2 read-write RUN_TIMER Keep the timer running 0x1 PAUSE_TIMER Stop the timer 0x2 DEBUG_HALT_CTRL DEBUG_HALT control 30 2 read-write RUN_TIMER Keep the timer running 0x1 PAUSE_TIMER Stop the timer 0x2 RELOAD Instruction Timer reload 0x4 32 read-write 0xFFFFFFFF 0xFFFFFFFF RLOAD Instruction Timer reload value 0 32 read-write INSTRUCTION_TIMER Instruction Timer 0x8 32 read-write 0xFFFFFFFF 0xFFFFFFFF INSTIM Current value of the Instruction Timer 0 32 read-write SECURE_COUNTER Secure Counter 0xC 32 write-only 0 0xFFFFFFFF SECCNT Secure Counter 0 32 write-only STATUS Status 1 0x10 32 read-only 0x50000000 0xFFFFFFFF NUMTOF Number of TIMEOUT faults since the last POR 0 8 read-only NUMMISCOMPF Number of MISCOMPARE faults since the last POR 8 8 read-only NUMILSEQF Number of SEQUENCE faults since the last POR 16 8 read-only CURST Current State 28 4 read-only STATUS2 Status 2 0x14 32 read-only 0 0xFFFFFFFF NUMCNTF Number of CONTROL faults since the last POR 0 8 read-only NUMILLSTF Number of STATE faults since the last POR 8 8 read-only NUMILLA Number of ADDRESS faults since the last POR 16 8 read-only FLAGS Flags 0x18 32 read-write 0 0xFFFFFFFF TO_FLAG TIMEOUT fault flag 0 1 read-write NO_FLAG A TIMEOUT fault has not occurred 0 FLAG A TIMEOUT fault has occurred 0x1 MISCOM_FLAG MISCOMPARE fault flag 1 1 read-write NO_FLAG A MISCOMPARE fault has not occurred 0 FLAG A MISCOMPARE fault has occurred 0x1 SEQ_FLAG SEQUENCE fault flag 2 1 read-write NO_FLAG A SEQUENCE fault has not occurred 0 FLAG A SEQUENCE fault has occurred 0x1 CNT_FLAG CONTROL fault flag 3 1 read-write NO_FLAG A CONTROL fault has not occurred 0 FLAG A CONTROL fault has occurred 0x1 STATE_FLAG STATE fault flag 4 1 read-write NO_FLAG A STATE fault has not occurred 0 FLAG A STATE fault has occurred 0x1 ADDR_FLAG ADDRESS fault flag 5 1 read-write NO_FLAG An ADDRESS fault has not occurred 0 FLAG An ADDRESS fault has occurred 0x1 POR_FLAG Power-on reset flag 16 1 read-write NO_FLAG A Power-on reset event has not occurred 0 FLAG A Power-on reset event has occurred 0x1 PERSISTENT Persistent Data Storage 0x1C 32 read-write 0 0xFFFFFFFF PERSIS Persistent Storage 0 32 read-write START START Command 0x20 32 write-only 0 0xFFFFFFFF STRT Start command 0 32 write-only STOP STOP Command 0x24 32 write-only 0 0xFFFFFFFF STP Stop command 0 32 write-only RESTART RESTART Command 0x28 32 write-only 0 0xFFFFFFFF RSTRT Restart command 0 32 write-only ADD ADD Command 0x2C 32 write-only 0 0xFFFFFFFF AD ADD Write Value 0 32 write-only ADD1 ADD1 Command 0x30 32 write-only 0 0xFFFFFFFF AD1 ADD 1 0 32 write-only ADD16 ADD16 Command 0x34 32 write-only 0 0xFFFFFFFF AD16 ADD 16 0 32 write-only ADD256 ADD256 Command 0x38 32 write-only 0 0xFFFFFFFF AD256 ADD 256 0 32 write-only SUB SUB Command 0x3C 32 write-only 0 0xFFFFFFFF S0B Subtract Write Value 0 32 write-only SUB1 SUB1 Command 0x40 32 write-only 0 0xFFFFFFFF S1B Subtract 1 0 32 write-only SUB16 SUB16 Command 0x44 32 write-only 0 0xFFFFFFFF SB16 Subtract 16 0 32 write-only SUB256 SUB256 Command 0x48 32 write-only 0 0xFFFFFFFF SB256 Subtract 256 0 32 write-only CM7_GPIO2 GPIO GPIO GPIO 0x42008000 0 0x90 registers CM7_GPIO2_3 99 DR GPIO data register 0 32 read-write 0 0xFFFFFFFF DR DR data bits 0 32 read-write GDIR GPIO direction register 0x4 32 read-write 0 0xFFFFFFFF GDIR GPIO direction bits 0 32 read-write PSR GPIO pad status register 0x8 32 read-only 0 0xFFFFFFFF PSR GPIO pad status bits 0 32 read-only ICR1 GPIO interrupt configuration register1 0xC 32 read-write 0 0xFFFFFFFF ICR0 Interrupt configuration field for GPIO interrupt 0 0 2 read-write LOW_LEVEL Interrupt 0 is low-level sensitive. 0 HIGH_LEVEL Interrupt 0 is high-level sensitive. 0x1 RISING_EDGE Interrupt 0 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 0 is falling-edge sensitive. 0x3 ICR1 Interrupt configuration field for GPIO interrupt 1 2 2 read-write LOW_LEVEL Interrupt 1 is low-level sensitive. 0 HIGH_LEVEL Interrupt 1 is high-level sensitive. 0x1 RISING_EDGE Interrupt 1 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 1 is falling-edge sensitive. 0x3 ICR2 Interrupt configuration field for GPIO interrupt 2 4 2 read-write LOW_LEVEL Interrupt 2 is low-level sensitive. 0 HIGH_LEVEL Interrupt 2 is high-level sensitive. 0x1 RISING_EDGE Interrupt 2 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 2 is falling-edge sensitive. 0x3 ICR3 Interrupt configuration field for GPIO interrupt 3 6 2 read-write LOW_LEVEL Interrupt 3 is low-level sensitive. 0 HIGH_LEVEL Interrupt 3 is high-level sensitive. 0x1 RISING_EDGE Interrupt 3 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 3 is falling-edge sensitive. 0x3 ICR4 Interrupt configuration field for GPIO interrupt 4 8 2 read-write LOW_LEVEL Interrupt 4 is low-level sensitive. 0 HIGH_LEVEL Interrupt 4 is high-level sensitive. 0x1 RISING_EDGE Interrupt 4 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 4 is falling-edge sensitive. 0x3 ICR5 Interrupt configuration field for GPIO interrupt 5 10 2 read-write LOW_LEVEL Interrupt 5 is low-level sensitive. 0 HIGH_LEVEL Interrupt 5 is high-level sensitive. 0x1 RISING_EDGE Interrupt 5 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 5 is falling-edge sensitive. 0x3 ICR6 Interrupt configuration field for GPIO interrupt 6 12 2 read-write LOW_LEVEL Interrupt 6 is low-level sensitive. 0 HIGH_LEVEL Interrupt 6 is high-level sensitive. 0x1 RISING_EDGE Interrupt 6 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 6 is falling-edge sensitive. 0x3 ICR7 Interrupt configuration field for GPIO interrupt 7 14 2 read-write LOW_LEVEL Interrupt 7 is low-level sensitive. 0 HIGH_LEVEL Interrupt 7 is high-level sensitive. 0x1 RISING_EDGE Interrupt 7 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 7 is falling-edge sensitive. 0x3 ICR8 Interrupt configuration field for GPIO interrupt 8 16 2 read-write LOW_LEVEL Interrupt 8 is low-level sensitive. 0 HIGH_LEVEL Interrupt 8 is high-level sensitive. 0x1 RISING_EDGE Interrupt 8 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 8 is falling-edge sensitive. 0x3 ICR9 Interrupt configuration field for GPIO interrupt 9 18 2 read-write LOW_LEVEL Interrupt 9 is low-level sensitive. 0 HIGH_LEVEL Interrupt 9 is high-level sensitive. 0x1 RISING_EDGE Interrupt 9 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 9 is falling-edge sensitive. 0x3 ICR10 Interrupt configuration field for GPIO interrupt 10 20 2 read-write LOW_LEVEL Interrupt 10 is low-level sensitive. 0 HIGH_LEVEL Interrupt 10 is high-level sensitive. 0x1 RISING_EDGE Interrupt 10 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 10 is falling-edge sensitive. 0x3 ICR11 Interrupt configuration field for GPIO interrupt 11 22 2 read-write LOW_LEVEL Interrupt 11 is low-level sensitive. 0 HIGH_LEVEL Interrupt 11 is high-level sensitive. 0x1 RISING_EDGE Interrupt 11 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 11 is falling-edge sensitive. 0x3 ICR12 Interrupt configuration field for GPIO interrupt 12 24 2 read-write LOW_LEVEL Interrupt 12 is low-level sensitive. 0 HIGH_LEVEL Interrupt 12 is high-level sensitive. 0x1 RISING_EDGE Interrupt 12 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 12 is falling-edge sensitive. 0x3 ICR13 Interrupt configuration field for GPIO interrupt 13 26 2 read-write LOW_LEVEL Interrupt 13 is low-level sensitive. 0 HIGH_LEVEL Interrupt 13 is high-level sensitive. 0x1 RISING_EDGE Interrupt 13 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 13 is falling-edge sensitive. 0x3 ICR14 Interrupt configuration field for GPIO interrupt 14 28 2 read-write LOW_LEVEL Interrupt 14 is low-level sensitive. 0 HIGH_LEVEL Interrupt 14 is high-level sensitive. 0x1 RISING_EDGE Interrupt 14 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 14 is falling-edge sensitive. 0x3 ICR15 Interrupt configuration field for GPIO interrupt 15 30 2 read-write LOW_LEVEL Interrupt 15 is low-level sensitive. 0 HIGH_LEVEL Interrupt 15 is high-level sensitive. 0x1 RISING_EDGE Interrupt 15 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 15 is falling-edge sensitive. 0x3 ICR2 GPIO interrupt configuration register2 0x10 32 read-write 0 0xFFFFFFFF ICR16 Interrupt configuration field for GPIO interrupt 16 0 2 read-write LOW_LEVEL Interrupt 16 is low-level sensitive. 0 HIGH_LEVEL Interrupt 16 is high-level sensitive. 0x1 RISING_EDGE Interrupt 16 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 16 is falling-edge sensitive. 0x3 ICR17 Interrupt configuration field for GPIO interrupt 17 2 2 read-write LOW_LEVEL Interrupt 17 is low-level sensitive. 0 HIGH_LEVEL Interrupt 17 is high-level sensitive. 0x1 RISING_EDGE Interrupt 17 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 17 is falling-edge sensitive. 0x3 ICR18 Interrupt configuration field for GPIO interrupt 18 4 2 read-write LOW_LEVEL Interrupt 18 is low-level sensitive. 0 HIGH_LEVEL Interrupt 18 is high-level sensitive. 0x1 RISING_EDGE Interrupt 18 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 18 is falling-edge sensitive. 0x3 ICR19 Interrupt configuration field for GPIO interrupt 19 6 2 read-write LOW_LEVEL Interrupt 19 is low-level sensitive. 0 HIGH_LEVEL Interrupt 19 is high-level sensitive. 0x1 RISING_EDGE Interrupt 19 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 19 is falling-edge sensitive. 0x3 ICR20 Interrupt configuration field for GPIO interrupt 20 8 2 read-write LOW_LEVEL Interrupt 20 is low-level sensitive. 0 HIGH_LEVEL Interrupt 20 is high-level sensitive. 0x1 RISING_EDGE Interrupt 20 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 20 is falling-edge sensitive. 0x3 ICR21 Interrupt configuration field for GPIO interrupt 21 10 2 read-write LOW_LEVEL Interrupt 21 is low-level sensitive. 0 HIGH_LEVEL Interrupt 21 is high-level sensitive. 0x1 RISING_EDGE Interrupt 21 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 21 is falling-edge sensitive. 0x3 ICR22 Interrupt configuration field for GPIO interrupt 22 12 2 read-write LOW_LEVEL Interrupt 22 is low-level sensitive. 0 HIGH_LEVEL Interrupt 22 is high-level sensitive. 0x1 RISING_EDGE Interrupt 22 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 22 is falling-edge sensitive. 0x3 ICR23 Interrupt configuration field for GPIO interrupt 23 14 2 read-write LOW_LEVEL Interrupt 23 is low-level sensitive. 0 HIGH_LEVEL Interrupt 23 is high-level sensitive. 0x1 RISING_EDGE Interrupt 23 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 23 is falling-edge sensitive. 0x3 ICR24 Interrupt configuration field for GPIO interrupt 24 16 2 read-write LOW_LEVEL Interrupt 24 is low-level sensitive. 0 HIGH_LEVEL Interrupt 24 is high-level sensitive. 0x1 RISING_EDGE Interrupt 24 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 24 is falling-edge sensitive. 0x3 ICR25 Interrupt configuration field for GPIO interrupt 25 18 2 read-write LOW_LEVEL Interrupt 25 is low-level sensitive. 0 HIGH_LEVEL Interrupt 25 is high-level sensitive. 0x1 RISING_EDGE Interrupt 25 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 25 is falling-edge sensitive. 0x3 ICR26 Interrupt configuration field for GPIO interrupt 26 20 2 read-write LOW_LEVEL Interrupt 26 is low-level sensitive. 0 HIGH_LEVEL Interrupt 26 is high-level sensitive. 0x1 RISING_EDGE Interrupt 26 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 26 is falling-edge sensitive. 0x3 ICR27 Interrupt configuration field for GPIO interrupt 27 22 2 read-write LOW_LEVEL Interrupt 27 is low-level sensitive. 0 HIGH_LEVEL Interrupt 27 is high-level sensitive. 0x1 RISING_EDGE Interrupt 27 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 27 is falling-edge sensitive. 0x3 ICR28 Interrupt configuration field for GPIO interrupt 28 24 2 read-write LOW_LEVEL Interrupt 28 is low-level sensitive. 0 HIGH_LEVEL Interrupt 28 is high-level sensitive. 0x1 RISING_EDGE Interrupt 28 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 28 is falling-edge sensitive. 0x3 ICR29 Interrupt configuration field for GPIO interrupt 29 26 2 read-write LOW_LEVEL Interrupt 29 is low-level sensitive. 0 HIGH_LEVEL Interrupt 29 is high-level sensitive. 0x1 RISING_EDGE Interrupt 29 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 29 is falling-edge sensitive. 0x3 ICR30 Interrupt configuration field for GPIO interrupt 30 28 2 read-write LOW_LEVEL Interrupt 30 is low-level sensitive. 0 HIGH_LEVEL Interrupt 30 is high-level sensitive. 0x1 RISING_EDGE Interrupt 30 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 30 is falling-edge sensitive. 0x3 ICR31 Interrupt configuration field for GPIO interrupt 31 30 2 read-write LOW_LEVEL Interrupt 31 is low-level sensitive. 0 HIGH_LEVEL Interrupt 31 is high-level sensitive. 0x1 RISING_EDGE Interrupt 31 is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt 31 is falling-edge sensitive. 0x3 IMR GPIO interrupt mask register 0x14 32 read-write 0 0xFFFFFFFF IMR Interrupt Mask bits 0 32 read-write ISR GPIO interrupt status register 0x18 32 read-write 0 0xFFFFFFFF oneToClear ISR Interrupt status bits 0 32 read-write oneToClear EDGE_SEL GPIO edge select register 0x1C 32 read-write 0 0xFFFFFFFF GPIO_EDGE_SEL Edge select 0 32 read-write DR_SET GPIO data register SET 0x84 32 write-only 0 0xFFFFFFFF DR_SET Set 0 32 write-only DR_CLEAR GPIO data register CLEAR 0x88 32 write-only 0 0xFFFFFFFF DR_CLEAR Clear 0 32 write-only DR_TOGGLE GPIO data register TOGGLE 0x8C 32 write-only 0 0xFFFFFFFF DR_TOGGLE Toggle 0 32 write-only GPIO1 GPIO GPIO 0x4012C000 0 0x90 registers GPIO1_Combined_0_15 100 GPIO1_Combined_16_31 101 GPIO2 GPIO GPIO 0x40130000 0 0x90 registers GPIO2_Combined_0_15 102 GPIO2_Combined_16_31 103 GPIO3 GPIO GPIO 0x40134000 0 0x90 registers GPIO3_Combined_0_15 104 GPIO3_Combined_16_31 105 GPIO4 GPIO GPIO 0x40138000 0 0x90 registers GPIO4_Combined_0_15 106 GPIO4_Combined_16_31 107 GPIO5 GPIO GPIO 0x4013C000 0 0x90 registers GPIO5_Combined_0_15 108 GPIO5_Combined_16_31 109 GPIO6 GPIO GPIO 0x40140000 0 0x90 registers GPIO6_Combined_0_15 61 GPIO6_Combined_16_31 62 GPIO7 GPIO GPIO 0x40C5C000 0 0x90 registers GPIO8 GPIO GPIO 0x40C60000 0 0x90 registers GPIO9 GPIO GPIO 0x40C64000 0 0x90 registers GPIO10 GPIO GPIO 0x40C68000 0 0x90 registers GPIO11 GPIO GPIO 0x40C6C000 0 0x90 registers GPIO12 GPIO GPIO 0x40C70000 0 0x90 registers GPIO13 GPIO GPIO 0x40CA0000 0 0x90 registers GPIO13_Combined_0_31 93 CM7_GPIO3 GPIO GPIO 0x4200C000 0 0x90 registers CM7_GPIO2_3 99 SystemControl System Control Block SCB SCB_ 0xE000E000 0 0xFAC registers ACTLR Auxiliary Control Register, 0x8 32 read-write 0 0xFFFFFFFF DISFOLD Disables folding of IT instructions. 2 1 read-write DISFOLD_0 Normal operation. 0 FPEXCODIS Disables FPU exception outputs. 10 1 read-write FPEXCODIS_0 Normal operation. 0 FPEXCODIS_1 FPU exception outputs are disabled. 0x1 DISRAMODE Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions. 11 1 read-write DISRAMODE_0 Normal operation. 0 DISRAMODE_1 Dynamic disabled. 0x1 DISITMATBFLUSH Disables ITM and DWT ATB flush. 12 1 read-write DISITMATBFLUSH_1 ITM and DWT ATB flush disabled, this bit is always 1. 0x1 DISBTACREAD Disables BTAC read. 13 1 read-write DISBTACREAD_0 Normal operation. 0 DISBTACREAD_1 BTAC is not used and only static branch prediction can occur. 0x1 DISBTACALLOC Disables BTAC allocate. 14 1 read-write DISBTACALLOC_0 Normal operation. 0 DISBTACALLOC_1 No new entries are allocated in Branch Target Address Cache (BTAC), but existing entries can be updated. 0x1 DISCRITAXIRUR Disables critical AXI Read-Under-Read. 15 1 read-write DISCRITAXIRUR_0 Normal operation. 0 DISCRITAXIRUR_1 An AXI read to Strongly-Ordered or Device memory, or an LDREX to Shareable memory, is not put on AXI if there are any outstanding reads on AXI. Transactions on AXI cannot be interrupted. This bit might reduce the time that these transactions are in progress and might improve worst case interrupt latency. Performance is decreased when this bit is set. 0x1 DISDI Disables dual-issued. 16 5 read-write DISDI_0 Normal operation. 0 DISDI_1 Nothing can be dual-issued when this instruction type is in channel 0. 0x1 DISISSCH1 Disables dual-issued. 21 5 read-write DISISSCH1_0 Normal operation. 0 DISISSCH1_1 Nothing can be dual-issued when this instruction type is in channel 1. 0x1 DISDYNADD Disables dynamic allocation of ADD and SUB instructions 26 1 read-write DISDYNADD_0 Normal operation. Some ADD and SUB instrctions are resolved in EX1. 0 DISDYNADD_1 All ADD and SUB instructions are resolved in EX2. 0x1 DISCRITAXIRUW Disables critical AXI read-under-write 27 1 read-write DISCRITAXIRUW_0 Normal operation. This is backwards compatible with r0. 0 DISCRITAXIRUW_1 AXI reads to DEV/SO memory. Exclusive reads to Shareable memory are not initiated on the AXIM AR channel until all outstanding stores on AXI are complete. 0x1 DISFPUISSOPT Disables critical AXI read-under-write 28 1 read-write DISFPUISSOPT_0 Normal operation. 0 CPUID CPUID Base Register 0xD00 32 read-only 0x410FC240 0xFFFFFFFF REVISION Indicates patch release: 0x0 = Patch 0 0 4 read-only PARTNO Indicates part number 4 12 read-only ARCHITECTURE ARCHITECTURE 16 4 read-only VARIANT Indicates processor revision: 0x2 = Revision 2 20 4 read-only IMPLEMENTER Implementer code 24 8 read-only ICSR Interrupt Control and State Register 0xD04 32 read-write 0 0xFFFFFFFF VECTACTIVE Active exception number 0 9 read-only RETTOBASE Indicates whether there are preempted active exceptions 11 1 read-only RETTOBASE_0 there are preempted active exceptions to execute 0 RETTOBASE_1 there are no active exceptions, or the currently-executing exception is the only active exception 0x1 VECTPENDING Exception number of the highest priority pending enabled exception 12 9 read-only ISRPENDING Interrupt pending flag, excluding NMI and Faults 22 1 read-only ISRPENDING_0 No external interrupt pending. 0 ISRPENDING_1 External interrupt pending. 0x1 PENDSTCLR SysTick exception clear-pending bit 25 1 write-only PENDSTCLR_0 no effect 0 PENDSTCLR_1 removes the pending state from the SysTick exception 0x1 PENDSTSET SysTick exception set-pending bit 26 1 read-write PENDSTSET_0 write: no effect; read: SysTick exception is not pending 0 PENDSTSET_1 write: changes SysTick exception state to pending; read: SysTick exception is pending 0x1 PENDSVCLR PendSV clear-pending bit 27 1 write-only PENDSVCLR_0 no effect 0 PENDSVCLR_1 removes the pending state from the PendSV exception 0x1 PENDSVSET PendSV set-pending bit 28 1 read-write PENDSVSET_0 write: no effect; read: PendSV exception is not pending 0 PENDSVSET_1 write: changes PendSV exception state to pending; read: PendSV exception is pending 0x1 NMIPENDSET NMI set-pending bit 31 1 read-write NMIPENDSET_0 write: no effect; read: NMI exception is not pending 0 NMIPENDSET_1 write: changes NMI exception state to pending; read: NMI exception is pending 0x1 VTOR Vector Table Offset Register 0xD08 32 read-write 0 0xFFFFFFFF TBLOFF Vector table base offset 7 25 read-write AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write 0xFA050000 0xFFFFFFFF VECTRESET Writing 1 to this bit causes a local system reset 0 1 write-only VECTRESET_0 No change 0 VECTRESET_1 Causes a local system reset 0x1 VECTCLRACTIVE Writing 1 to this bit clears all active state information for fixed and configurable exceptions. 1 1 write-only VECTCLRACTIVE_0 No change 0 VECTCLRACTIVE_1 Clears all active state information for fixed and configurable exceptions 0x1 SYSRESETREQ System reset request 2 1 write-only SYSRESETREQ_0 no system reset request 0 SYSRESETREQ_1 asserts a signal to the outer system that requests a reset 0x1 PRIGROUP Interrupt priority grouping field. This field determines the split of group priority from subpriority. 8 3 read-write ENDIANNESS Data endianness 15 1 read-only ENDIANNESS_0 Little-endian 0 ENDIANNESS_1 Big-endian 0x1 VECTKEY Register key 16 16 read-write SCR System Control Register 0xD10 32 read-write 0 0xFFFFFFFF SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode 1 1 read-write SLEEPONEXIT_0 o not sleep when returning to Thread mode 0 SLEEPONEXIT_1 enter sleep, or deep sleep, on return from an ISR 0x1 SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode 2 1 read-write SLEEPDEEP_0 sleep 0 SLEEPDEEP_1 deep sleep 0x1 SEVONPEND Send Event on Pending bit 4 1 read-write SEVONPEND_0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 0 SEVONPEND_1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor 0x1 CCR Configuration and Control Register 0xD14 32 read-write 0x40000 0xFFFFFFFF NONBASETHRDENA Indicates how the processor enters Thread mode 0 1 read-write NONBASETHRDENA_0 processor can enter Thread mode only when no exception is active 0 NONBASETHRDENA_1 processor can enter Thread mode from any level under the control of an EXC_RETURN value 0x1 USERSETMPEND Enables unprivileged software access to the STIR 1 1 read-write USERSETMPEND_0 disable 0 USERSETMPEND_1 enable 0x1 UNALIGN_TRP Enables unaligned access traps 3 1 read-write UNALIGN_TRP_0 do not trap unaligned halfword and word accesses 0 UNALIGN_TRP_1 trap unaligned halfword and word accesses 0x1 DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 4 1 read-write DIV_0_TRP_0 do not trap divide by 0 0 DIV_0_TRP_1 trap divide by 0 0x1 BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. 8 1 read-write BFHFNMIGN_0 data bus faults caused by load and store instructions cause a lock-up 0 BFHFNMIGN_1 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions 0x1 STKALIGN Indicates stack alignment on exception entry 9 1 read-write STKALIGN_0 4-byte aligned 0 STKALIGN_1 8-byte aligned 0x1 DC Enables L1 data cache. 16 1 read-write DC_0 L1 data cache disabled 0 DC_1 L1 data cache enabled 0x1 IC Enables L1 instruction cache. 17 1 read-write IC_0 L1 instruction cache disabled 0 IC_1 L1 instruction cache enabled 0x1 BP Always reads-as-one. It indicates branch prediction is enabled. 18 1 read-only SHPR1 System Handler Priority Register 1 0xD18 32 read-write 0 0xFFFFFFFF PRI_4 Priority of system handler 4, MemManage 0 8 read-write PRI_5 Priority of system handler 5, BusFault 8 8 read-write PRI_6 Priority of system handler 6, UsageFault 16 8 read-write SHPR2 System Handler Priority Register 2 0xD1C 32 read-write 0 0xFFFFFFFF PRI_11 Priority of system handler 11, SVCall 24 8 read-write SHPR3 System Handler Priority Register 3 0xD20 32 read-write 0 0xFFFFFFFF PRI_14 Priority of system handler 14, PendSV 16 8 read-write PRI_15 Priority of system handler 15, SysTick exception 24 8 read-write SHCSR System Handler Control and State Register 0xD24 32 read-write 0 0xFFFFFFFF MEMFAULTACT MemManage exception active bit 0 1 read-write MEMFAULTACT_0 exception is not active 0 MEMFAULTACT_1 exception is active 0x1 BUSFAULTACT BusFault exception active bit 1 1 read-write BUSFAULTACT_0 exception is not active 0 BUSFAULTACT_1 exception is active 0x1 USGFAULTACT UsageFault exception active bit 3 1 read-write USGFAULTACT_0 exception is not active 0 USGFAULTACT_1 exception is active 0x1 SVCALLACT SVCall active bit 7 1 read-write SVCALLACT_0 exception is not active 0 SVCALLACT_1 exception is active 0x1 MONITORACT Debug monitor active bit 8 1 read-write MONITORACT_0 exception is not active 0 MONITORACT_1 exception is active 0x1 PENDSVACT PendSV exception active bit 10 1 read-write PENDSVACT_0 exception is not active 0 PENDSVACT_1 exception is active 0x1 SYSTICKACT SysTick exception active bit 11 1 read-write SYSTICKACT_0 exception is not active 0 SYSTICKACT_1 exception is active 0x1 USGFAULTPENDED UsageFault exception pending bit 12 1 read-write USGFAULTPENDED_0 exception is not pending 0 USGFAULTPENDED_1 exception is pending 0x1 MEMFAULTPENDED MemManage exception pending bit 13 1 read-write MEMFAULTPENDED_0 exception is not pending 0 MEMFAULTPENDED_1 exception is pending 0x1 BUSFAULTPENDED BusFault exception pending bit 14 1 read-write BUSFAULTPENDED_0 exception is not pending 0 BUSFAULTPENDED_1 exception is pending 0x1 SVCALLPENDED SVCall pending bit 15 1 read-write SVCALLPENDED_0 exception is not pending 0 SVCALLPENDED_1 exception is pending 0x1 MEMFAULTENA MemManage enable bit 16 1 read-write MEMFAULTENA_0 disable the exception 0 MEMFAULTENA_1 enable the exception 0x1 BUSFAULTENA BusFault enable bit 17 1 read-write BUSFAULTENA_0 disable the exception 0 BUSFAULTENA_1 enable the exception 0x1 USGFAULTENA UsageFault enable bit 18 1 read-write USGFAULTENA_0 disable the exception 0 USGFAULTENA_1 enable the exception 0x1 CFSR Configurable Fault Status Register 0xD28 32 read-write 0 0xFFFFFFFF IACCVIOL Instruction access violation flag 0 1 read-write IACCVIOL_0 no instruction access violation fault 0 IACCVIOL_1 the processor attempted an instruction fetch from a location that does not permit execution 0x1 DACCVIOL Data access violation flag 1 1 read-write DACCVIOL_0 no data access violation fault 0 DACCVIOL_1 the processor attempted a load or store at a location that does not permit the operation 0x1 MUNSTKERR MemManage fault on unstacking for a return from exception 3 1 read-write MUNSTKERR_0 no unstacking fault 0 MUNSTKERR_1 unstack for an exception return has caused one or more access violations 0x1 MSTKERR MemManage fault on stacking for exception entry 4 1 read-write MSTKERR_0 no stacking fault 0 MSTKERR_1 stacking for an exception entry has caused one or more access violations 0x1 MLSPERR MemManage fault occurred during floating-point lazy state preservation 5 1 read-write MLSPERR_0 No MemManage fault occurred during floating-point lazy state preservation 0 MLSPERR_1 A MemManage fault occurred during floating-point lazy state preservation 0x1 MMARVALID MemManage Fault Address Register (MMFAR) valid flag 7 1 read-write MMARVALID_0 value in MMAR is not a valid fault address 0 MMARVALID_1 MMAR holds a valid fault address 0x1 IBUSERR Instruction bus error 8 1 read-write IBUSERR_0 no instruction bus error 0 IBUSERR_1 instruction bus error 0x1 PRECISERR Precise data bus error 9 1 read-write PRECISERR_0 no precise data bus error 0 PRECISERR_1 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault 0x1 IMPRECISERR Imprecise data bus error 10 1 read-write IMPRECISERR_0 no imprecise data bus error 0 IMPRECISERR_1 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error 0x1 UNSTKERR BusFault on unstacking for a return from exception 11 1 read-write UNSTKERR_0 no unstacking fault 0 UNSTKERR_1 unstack for an exception return has caused one or more BusFaults 0x1 STKERR BusFault on stacking for exception entry 12 1 read-write STKERR_0 no stacking fault 0 STKERR_1 stacking for an exception entry has caused one or more BusFaults 0x1 LSPERR Bus fault occurred during floating-point lazy state preservation 13 1 read-write LSPERR_0 No bus fault occurred during floating-point lazy state preservation 0 LSPERR_1 A bus fault occurred during floating-point lazy state preservation 0x1 BFARVALID BusFault Address Register (BFAR) valid flag 15 1 read-write BFARVALID_0 value in BFAR is not a valid fault address 0 BFARVALID_1 BFAR holds a valid fault address 0x1 UNDEFINSTR Undefined instruction UsageFault 16 1 read-write UNDEFINSTR_0 no undefined instruction UsageFault 0 UNDEFINSTR_1 the processor has attempted to execute an undefined instruction 0x1 INVSTATE Invalid state UsageFault 17 1 read-write INVSTATE_0 no invalid state UsageFault 0 INVSTATE_1 the processor has attempted to execute an instruction that makes illegal use of the EPSR 0x1 INVPC Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN 18 1 read-write INVPC_0 no invalid PC load UsageFault 0 INVPC_1 the processor has attempted an illegal load of EXC_RETURN to the PC 0x1 NOCP No coprocessor UsageFault 19 1 read-write NOCP_0 no UsageFault caused by attempting to access a coprocessor 0 NOCP_1 the processor has attempted to access a coprocessor 0x1 UNALIGNED Unaligned access UsageFault 24 1 read-write UNALIGNED_0 no unaligned access fault, or unaligned access trapping not enabled 0 UNALIGNED_1 the processor has made an unaligned memory access 0x1 DIVBYZERO Divide by zero UsageFault 25 1 read-write DIVBYZERO_0 no divide by zero fault, or divide by zero trapping not enabled 0 DIVBYZERO_1 the processor has executed an SDIV or UDIV instruction with a divisor of 0 0x1 HFSR HardFault Status register 0xD2C 32 read-write 0 0xFFFFFFFF VECTTBL Indicates a BusFault on a vector table read during exception processing. 1 1 read-write VECTTBL_0 no BusFault on vector table read 0 VECTTBL_1 BusFault on vector table read 0x1 FORCED Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled. 30 1 read-write FORCED_0 no forced HardFault 0 FORCED_1 forced HardFault 0x1 DEBUGEVT Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. 31 1 read-write DEBUGEVT_0 No Debug event has occurred. 0 DEBUGEVT_1 Debug event has occurred. The Debug Fault Status Register has been updated. 0x1 DFSR Debug Fault Status Register 0xD30 32 read-write 0 0xFFFFFFFF HALTED Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1. 0 1 read-write HALTED_0 No active halt request debug event 0 HALTED_1 Halt request debug event active 0x1 BKPT Debug event generated by BKPT instruction execution or a breakpoint match in FPB 1 1 read-write BKPT_0 No current breakpoint debug event 0 BKPT_1 At least one current breakpoint debug event 0x1 DWTTRAP Debug event generated by the DWT 2 1 read-write DWTTRAP_0 No current debug events generated by the DWT 0 DWTTRAP_1 At least one current debug event generated by the DWT 0x1 VCATCH Indicates triggering of a Vector catch 3 1 read-write VCATCH_0 No Vector catch triggered 0 VCATCH_1 Vector catch triggered 0x1 EXTERNAL Debug event generated because of the assertion of an external debug request 4 1 read-write EXTERNAL_0 No external debug request debug event 0 EXTERNAL_1 External debug request debug event 0x1 MMFAR MemManage Fault Address Register 0xD34 32 read-write 0 0xFFFFFFFF ADDRESS Address of MemManage fault location 0 32 read-write BFAR BusFault Address Register 0xD38 32 read-write 0 0xFFFFFFFF ADDRESS Address of the BusFault location 0 32 read-write ID_PFR0 Processor Feature Register 0 0xD40 32 read-only 0 0xFFFFFFFF STATE0 ARM instruction set support 0 4 read-only STATE0_0 ARMv7-M unused 0 STATE0_1 ARMv7-M unused 0x1 STATE0_2 ARMv7-M unused 0x2 STATE0_3 Support for Thumb encoding including Thumb-2 technology, with all basic 16-bit and 32-bit instructions. 0x3 STATE1 Thumb instruction set support 4 4 read-only STATE1_0 The processor does not support the ARM instruction set. 0 STATE1_1 ARMv7-M unused 0x1 STATE2 ARMv7-M unused 8 4 read-only STATE3 ARMv7-M unused 12 4 read-only ID_PFR1 Processor Feature Register 1 0xD44 32 read-only 0 0xFFFFFFFF PROGMODEL M profile programmers' model 8 4 read-only PROGMODEL_0 ARMv7-M unused 0 PROGMODEL_2 Two-stack programmers' model supported 0x2 ID_DFR0 Debug Feature Register 0xD48 32 read-only 0 0xFFFFFFFF DEBUGMODEL Support for memory-mapped debug model for M profile processors 20 4 read-only DEBUGMODEL_0 Not supported 0 DEBUGMODEL_1 Support for M profile Debug architecture, with memory-mapped access. 0x1 ID_AFR0 Auxiliary Feature Register 0xD4C 32 read-only 0 0xFFFFFFFF IMPLEMENTATION_DEFINED0 Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. 0 4 read-only IMPLEMENTATION_DEFINED1 Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. 4 4 read-only IMPLEMENTATION_DEFINED2 Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. 8 4 read-only IMPLEMENTATION_DEFINED3 Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. 12 4 read-only ID_MMFR0 Memory Model Feature Register 0 0xD50 32 read-only 0 0xFFFFFFFF PMSASUPPORT Indicates support for a PMSA 4 4 read-only PMSASUPPORT_0 Not supported 0 PMSASUPPORT_1 ARMv7-M unused 0x1 PMSASUPPORT_2 ARMv7-M unused 0x2 PMSASUPPORT_3 PMSAv7, providing support for a base region and subregions. 0x3 OUTERMOST_SHAREABILITY Indicates the outermost shareability domain implemented 8 4 read-only OUTERMOST_SHAREABILITY_0 Implemented as Non-cacheable 0 OUTERMOST_SHAREABILITY_1 ARMv7-M unused 0x1 OUTERMOST_SHAREABILITY_2 ARMv7-M unused 0x2 OUTERMOST_SHAREABILITY_3 ARMv7-M unused 0x3 OUTERMOST_SHAREABILITY_4 ARMv7-M unused 0x4 OUTERMOST_SHAREABILITY_5 ARMv7-M unused 0x5 OUTERMOST_SHAREABILITY_6 ARMv7-M unused 0x6 OUTERMOST_SHAREABILITY_7 ARMv7-M unused 0x7 OUTERMOST_SHAREABILITY_8 ARMv7-M unused 0x8 OUTERMOST_SHAREABILITY_9 ARMv7-M unused 0x9 OUTERMOST_SHAREABILITY_10 ARMv7-M unused 0xA OUTERMOST_SHAREABILITY_11 ARMv7-M unused 0xB OUTERMOST_SHAREABILITY_12 ARMv7-M unused 0xC OUTERMOST_SHAREABILITY_13 ARMv7-M unused 0xD OUTERMOST_SHAREABILITY_14 ARMv7-M unused 0xE OUTERMOST_SHAREABILITY_15 Shareability ignored. 0xF SHAREABILITY_LEVELS Indicates the number of shareability levels implemented 12 4 read-only SHAREABILITY_LEVELS_0 One level of shareability implemented 0 SHAREABILITY_LEVELS_1 ARMv7-M unused 0x1 TCM_SUPPORT Indicates the support for Tightly Coupled Memory 16 4 read-only TCM_SUPPORT_0 No tightly coupled memories implemented. 0 TCM_SUPPORT_1 Tightly coupled memories implemented with IMPLEMENTATION DEFINED control. 0x1 TCM_SUPPORT_2 ARMv7-M unused 0x2 AUXILIARY_REGISTERS Indicates the support for Auxiliary registers 20 4 read-only AUXILIARY_REGISTERS_0 Not supported 0 AUXILIARY_REGISTERS_1 Support for Auxiliary Control Register only. 0x1 AUXILIARY_REGISTERS_2 ARMv7-M unused 0x2 ID_MMFR1 Memory Model Feature Register 1 0xD54 32 read-only 0 0xFFFFFFFF ID_MMFR1 Gives information about the implemented memory model and memory management support. 0 32 read-only ID_MMFR2 Memory Model Feature Register 2 0xD58 32 read-only 0 0xFFFFFFFF WFI_STALL Indicates the support for Wait For Interrupt (WFI) stalling 24 4 read-only WFI_STALL_0 Not supported 0 WFI_STALL_1 Support for WFI stalling 0x1 ID_MMFR3 Memory Model Feature Register 3 0xD5C 32 read-only 0 0xFFFFFFFF ID_MMFR3 Gives information about the implemented memory model and memory management support. 0 32 read-only ID_ISAR0 Instruction Set Attributes Register 0 0xD60 32 read-only 0 0xFFFFFFFF BITCOUNT_INSTRS Indicates the supported Bit Counting instructions 4 4 read-only BITCOUNT_INSTRS_0 None supported, ARMv7-M unused 0 BITCOUNT_INSTRS_1 Adds support for the CLZ instruction 0x1 BITFIELD_INSTRS Indicates the supported BitField instructions 8 4 read-only BITFIELD_INSTRS_0 None supported, ARMv7-M unused 0 BITFIELD_INSTRS_1 Adds support for the BFC, BFI, SBFX, and UBFX instructions 0x1 CMPBRANCH_INSTRS Indicates the supported combined Compare and Branch instructions 12 4 read-only CMPBRANCH_INSTRS_0 None supported, ARMv7-M unused 0 CMPBRANCH_INSTRS_1 Adds support for the CBNZ and CBZ instructions 0x1 COPROC_INSTRS Indicates the supported Coprocessor instructions 16 4 read-only COPROC_INSTRS_0 None supported, except for separately attributed architectures, for example the Floating-point extension 0 COPROC_INSTRS_1 Adds support for generic CDP, LDC, MCR, MRC, and STC instructions 0x1 COPROC_INSTRS_2 As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions 0x2 COPROC_INSTRS_3 As for 2, and adds support for generic MCRR and MRRC instructions 0x3 COPROC_INSTRS_4 As for 3, and adds support for generic MCRR2 and MRRC2 instructions 0x4 DEBUG_INSTRS Indicates the supported Debug instructions 20 4 read-only DEBUG_INSTRS_0 None supported, ARMv7-M unused 0 DEBUG_INSTRS_1 Adds support for the BKPT instruction 0x1 DIVIDE_INSTRS Indicates the supported Divide instructions 24 4 read-only DIVIDE_INSTRS_0 None supported, ARMv7-M unused 0 DIVIDE_INSTRS_1 Adds support for the SDIV and UDIV instructions 0x1 ID_ISAR1 Instruction Set Attributes Register 1 0xD64 32 read-only 0 0xFFFFFFFF EXTEND_INSTRS Indicates the supported Extend instructions 12 4 read-only EXTEND_INSTRS_0 None supported, ARMv7-M unused 0 EXTEND_INSTRS_1 Adds support for the SXTB, SXTH, UXTB, and UXTH instructions 0x1 EXTEND_INSTRS_2 As for 1, and adds support for the SXTAB, SXTAB16, SXTAH, SXTB16, UXTAB, UXTAB16, UXTAH, and UXTB16 instructions 0x2 IFTHEN_INSTRS Indicates the supported IfThen instructions 16 4 read-only IFTHEN_INSTRS_0 None supported, ARMv7-M unused 0 IFTHEN_INSTRS_1 Adds support for the IT instructions, and for the IT bits in the PSRs 0x1 IMMEDIATE_INSTRS Indicates the support for data-processing instructions with long immediate 20 4 read-only IMMEDIATE_INSTRS_0 None supported, ARMv7-M unused 0 IMMEDIATE_INSTRS_1 Adds support for the ADDW, MOVW, MOVT, and SUBW instructions 0x1 INTERWORK_INSTRS Indicates the supported Interworking instructions 24 4 read-only INTERWORK_INSTRS_0 None supported, ARMv7-M unused 0 INTERWORK_INSTRS_1 Adds support for the BX instruction, and the T bit in the PSR 0x1 INTERWORK_INSTRS_2 As for 1, and adds support for the BLX instruction, and PC loads have BX-like behavior 0x2 INTERWORK_INSTRS_3 ARMv7-M unused 0x3 ID_ISAR2 Instruction Set Attributes Register 2 0xD68 32 read-only 0 0xFFFFFFFF LOADSTORE_INSTRS Indicates the supported additional load and store instructions 0 4 read-only LOADSTORE_INSTRS_0 None supported, ARMv7-M unused 0 LOADSTORE_INSTRS_1 Adds support for the LDRD and STRD instructions 0x1 MEMHINT_INSTRS Indicates the supported Memory Hint instructions 4 4 read-only MEMHINT_INSTRS_0 None supported, ARMv7-M unused. 0 MEMHINT_INSTRS_1 Adds support for the PLD instruction, ARMv7-M unused. 0x1 MEMHINT_INSTRS_2 As for 1, ARMv7-M unused. 0x2 MEMHINT_INSTRS_3 As for 1 or 2, and adds support for the PLI instruction. 0x3 MULTIACCESSINT_INSTRS Indicates the support for multi-access interruptible instructions 8 4 read-only MULTIACCESSINT_INSTRS_0 None supported. This means the LDM and STM instructions are not interruptible. ARMv7-M unused. 0 MULTIACCESSINT_INSTRS_1 LDM and STM instructions are restartable. 0x1 MULTIACCESSINT_INSTRS_2 LDM and STM instructions are continuable. 0x2 MULT_INSTRS Indicates the supported additional Multiply instructions 12 4 read-only MULT_INSTRS_0 None supported. This means only MUL is supported. ARMv7-M unused. 0 MULT_INSTRS_1 Adds support for the MLA instruction, ARMv7-M unused. 0x1 MULT_INSTRS_2 As for 1, and adds support for the MLS instruction. 0x2 MULTS_INSTRS Indicates the supported advanced signed Multiply instructions 16 4 read-only MULTS_INSTRS_0 None supported, ARMv7-M unused 0 MULTS_INSTRS_1 Adds support for the SMULL and SMLAL instructions 0x1 MULTS_INSTRS_2 As for 1, and adds support for the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions. 0x2 MULTS_INSTRS_3 As for 2, and adds support for the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions. 0x3 MULTU_INSTRS Indicates the supported advanced unsigned Multiply instructions 20 4 read-only MULTU_INSTRS_0 None supported, ARMv7-M unused 0 MULTU_INSTRS_1 Adds support for the UMULL and UMLAL instructions. 0x1 MULTU_INSTRS_2 As for 1, and adds support for the UMAAL instruction. 0x2 REVERSAL_INSTRS Indicates the supported Reversal instructions 28 4 read-only REVERSAL_INSTRS_0 None supported, ARMv7-M unused 0 REVERSAL_INSTRS_1 Adds support for the REV, REV16, and REVSH instructions, ARMv7-M unused. 0x1 REVERSAL_INSTRS_2 As for 1, and adds support for the RBIT instruction. 0x2 ID_ISAR3 Instruction Set Attributes Register 3 0xD6C 32 read-only 0 0xFFFFFFFF SATURATE_INSTRS Indicates the supported Saturate instructions 0 4 read-only SATURATE_INSTRS_0 None supported 0 SATURATE_INSTRS_1 Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit in the PSRs. 0x1 SIMD_INSTRS Indicates the supported SIMD instructions 4 4 read-only SIMD_INSTRS_0 None supported, ARMv7-M unused. 0 SIMD_INSTRS_1 Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs. 0x1 SIMD_INSTRS_3 As for 1, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs. 0x3 SVC_INSTRS Indicates the supported SVC instructions 8 4 read-only SVC_INSTRS_0 None supported, ARMv7-M unused. 0 SVC_INSTRS_1 Adds support for the SVC instruction. 0x1 SYNCHPRIM_INSTRS Together with the ID_ISAR4[SYNCHPRIM_INSTRS_FRAC] indicates the supported Synchronization Primitives 12 4 read-only TABBRANCH_INSTRS Indicates the supported Table Branch instructions 16 4 read-only TABBRANCH_INSTRS_0 None supported, ARMv7-M unused. 0 TABBRANCH_INSTRS_1 Adds support for the TBB and TBH instructions. 0x1 THUMBCOPY_INSTRS Indicates the supported non flag-setting MOV instructions 20 4 read-only THUMBCOPY_INSTRS_0 None supported, ARMv7-M unused. 0 THUMBCOPY_INSTRS_1 Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. 0x1 TRUENOP_INSTRS Indicates the supported non flag-setting MOV instructions 24 4 read-only TRUENOP_INSTRS_0 None supported, ARMv7-M unused. 0 TRUENOP_INSTRS_1 Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. 0x1 ID_ISAR4 Instruction Set Attributes Register 4 0xD70 32 read-only 0 0xFFFFFFFF UNPRIV_INSTRS Indicates the supported unprivileged instructions. These are the instruction variants indicated by a T suffix. 0 4 read-only UNPRIV_INSTRS_0 None supported, ARMv7-M unused. 0 UNPRIV_INSTRS_1 Adds support for the LDRBT, LDRT, STRBT, and STRT instructions. 0x1 UNPRIV_INSTRS_2 As for 1, and adds support for the LDRHT, LDRSBT, LDRSHT, and STRHT instructions. 0x2 WITHSHIFTS_INSTRS Indicates the support for instructions with shifts 4 4 read-only WITHSHIFTS_INSTRS_0 Nonzero shifts supported only in MOV and shift instructions. 0 WITHSHIFTS_INSTRS_1 Adds support for shifts of loads and stores over the range LSL 0-3. 0x1 WITHSHIFTS_INSTRS_3 As for 1, and adds support for other constant shift options, on loads, stores, and other instructions. 0x3 WITHSHIFTS_INSTRS_4 ARMv7-M unused. 0x4 WRITEBACK_INSTRS Indicates the support for Writeback addressing modes 8 4 read-only WRITEBACK_INSTRS_0 Basic support. Only the LDM, STM, PUSH, and POP instructions support writeback addressing modes. ARMv7-M unused. 0 WRITEBACK_INSTRS_1 Adds support for all of the writeback addressing modes defined in the ARMv7-M architecture. 0x1 BARRIER_INSTRS Indicates the supported Barrier instructions 16 4 read-only BARRIER_INSTRS_0 None supported, ARMv7-M unused. 0 BARRIER_INSTRS_1 Adds support for the DMB, DSB, and ISB barrier instructions. 0x1 SYNCHPRIM_INSTRS_FRAC Together with the ID_ISAR3[SYNCHPRIM_INSTRS] indicates the supported Synchronization Primitives 20 4 read-only PSR_M_INSTRS Indicates the supported M profile instructions to modify the PSRs 24 4 read-only PSR_M_INSTRS_0 None supported, ARMv7-M unused. 0 PSR_M_INSTRS_1 Adds support for the M-profile forms of the CPS, MRS, and MSR instructions, to access the PSRs. 0x1 CLIDR Cache Level ID register 0xD78 32 read-only 0 0xFFFFFFFF CL1 Indicate the type of cache implemented at level 1. 0 3 read-only CL1_0 No cache 0 CL1_1 Instruction cache only 0x1 CL1_2 Data cache only 0x2 CL1_3 Separate instruction and data caches 0x3 CL1_4 Unified cache 0x4 CL2 Indicate the type of cache implemented at level 2. 3 3 read-only CL2_0 No cache 0 CL2_1 Instruction cache only 0x1 CL2_2 Data cache only 0x2 CL2_3 Separate instruction and data caches 0x3 CL2_4 Unified cache 0x4 CL3 Indicate the type of cache implemented at level 3. 6 3 read-only CL3_0 No cache 0 CL3_1 Instruction cache only 0x1 CL3_2 Data cache only 0x2 CL3_3 Separate instruction and data caches 0x3 CL3_4 Unified cache 0x4 CL4 Indicate the type of cache implemented at level 4. 9 3 read-only CL4_0 No cache 0 CL4_1 Instruction cache only 0x1 CL4_2 Data cache only 0x2 CL4_3 Separate instruction and data caches 0x3 CL4_4 Unified cache 0x4 CL5 Indicate the type of cache implemented at level 5. 12 3 read-only CL5_0 No cache 0 CL5_1 Instruction cache only 0x1 CL5_2 Data cache only 0x2 CL5_3 Separate instruction and data caches 0x3 CL5_4 Unified cache 0x4 CL6 Indicate the type of cache implemented at level 6. 15 3 read-only CL6_0 No cache 0 CL6_1 Instruction cache only 0x1 CL6_2 Data cache only 0x2 CL6_3 Separate instruction and data caches 0x3 CL6_4 Unified cache 0x4 CL7 Indicate the type of cache implemented at level 7. 18 3 read-only CL7_0 No cache 0 CL7_1 Instruction cache only 0x1 CL7_2 Data cache only 0x2 CL7_3 Separate instruction and data caches 0x3 CL7_4 Unified cache 0x4 LOUIS Level of Unification Inner Shareable for the cache hierarchy. This field is RAZ. 21 3 read-only LOUIS_0 0 0 LOUIS_1 1 0x1 LOUIS_2 2 0x2 LOUIS_3 3 0x3 LOUIS_4 4 0x4 LOUIS_5 5 0x5 LOUIS_6 6 0x6 LOUIS_7 7 0x7 LOC Level of Coherency for the cache hierarchy 24 3 read-only LOC_0 0 0 LOC_1 1 0x1 LOC_2 2 0x2 LOC_3 3 0x3 LOC_4 4 0x4 LOC_5 5 0x5 LOC_6 6 0x6 LOC_7 7 0x7 LOU Level of Unification for the cache hierarchy 27 3 read-only LOU_0 0 0 LOU_1 1 0x1 LOU_2 2 0x2 LOU_3 3 0x3 LOU_4 4 0x4 LOU_5 5 0x5 LOU_6 6 0x6 LOU_7 7 0x7 CTR Cache Type register 0xD7C 32 read-only 0x8000C000 0xFFFFFFFF IMINLINE Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor. 0 4 read-only DMINLINE Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor. 16 4 read-only ERG Exclusives Reservation Granule. The maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions, encoded as Log2 of the number of words. 20 4 read-only CWG Cache Write-back Granule. The maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified, encoded as Log2 of the number of words. 24 4 read-only FORMAT Indicates the implemented CTR format. 29 3 read-only FORMAT_4 ARMv7 format. 0x4 CCSIDR Cache Size ID Register 0xD80 32 read-only 0 0xFFFFFFFF LINESIZE (Log2(Number of words in cache line)) - 2. 0 3 read-only LINESIZE_0 The line length of 4 words. 0 LINESIZE_1 The line length of 8 words. 0x1 LINESIZE_2 The line length of 16 words. 0x2 LINESIZE_3 The line length of 32 words. 0x3 LINESIZE_4 The line length of 64 words. 0x4 LINESIZE_5 The line length of 128 words. 0x5 LINESIZE_6 The line length of 256 words. 0x6 LINESIZE_7 The line length of 512 words. 0x7 ASSOCIATIVITY (Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2. 3 10 read-only NUMSETS (Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2. 13 15 read-only WA Indicates whether the cache level supports write-allocation 28 1 read-only WA_0 Feature not supported 0 WA_1 Feature supported 0x1 RA Indicates whether the cache level supports read-allocation 29 1 read-only RA_0 Feature not supported 0 RA_1 Feature supported 0x1 WB Indicates whether the cache level supports write-back 30 1 read-only WB_0 Feature not supported 0 WB_1 Feature supported 0x1 WT Indicates whether the cache level supports write-through 31 1 read-only WT_0 Feature not supported 0 WT_1 Feature supported 0x1 CSSELR Cache Size Selection Register 0xD84 32 read-write 0 0xFFFFFFFF IND Instruction not data bit 0 1 read-write IND_0 Data or unified cache. 0 IND_1 Instruction cache. 0x1 LEVEL Cache level of required cache 1 3 read-write LEVEL_0 Level 1 cache. 0 LEVEL_1 Level 2 cache. 0x1 LEVEL_2 Level 3 cache. 0x2 LEVEL_3 Level 4 cache. 0x3 LEVEL_4 Level 5 cache. 0x4 LEVEL_5 Level 6 cache. 0x5 LEVEL_6 Level 7 cache. 0x6 CPACR Coprocessor Access Control Register 0xD88 32 read-write 0 0xFFFFFFFF CP0 Access privileges for coprocessor 0. 0 2 read-write CP0_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP0_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP0_3 Full access. 0x3 CP1 Access privileges for coprocessor 1. 2 2 read-write CP1_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP1_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP1_3 Full access. 0x3 CP2 Access privileges for coprocessor 2. 4 2 read-write CP2_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP2_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP2_3 Full access. 0x3 CP3 Access privileges for coprocessor 3. 6 2 read-write CP3_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP3_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP3_3 Full access. 0x3 CP4 Access privileges for coprocessor 4. 8 2 read-write CP4_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP4_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP4_3 Full access. 0x3 CP5 Access privileges for coprocessor 5. 10 2 read-write CP5_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP5_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP5_3 Full access. 0x3 CP6 Access privileges for coprocessor 6. 12 2 read-write CP6_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP6_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP6_3 Full access. 0x3 CP7 Access privileges for coprocessor 7. 14 2 read-write CP7_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP7_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP7_3 Full access. 0x3 CP10 Access privileges for coprocessor 10. 20 2 read-write CP10_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP10_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP10_3 Full access. 0x3 CP11 Access privileges for coprocessor 11. 22 2 read-write CP11_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP11_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP11_3 Full access. 0x3 STIR Instruction cache invalidate all to Point of Unification (PoU) 0xF00 32 write-only 0 0xFFFFFFFF INTID Indicates the interrupt to be triggered 0 9 write-only ICIALLU Instruction cache invalidate all to Point of Unification (PoU) 0xF50 32 write-only 0 0xFFFFFFFF ICIALLU I-cache invalidate all to PoU 0 32 write-only ICIMVAU Instruction cache invalidate by address to PoU 0xF58 32 write-only 0 0xFFFFFFFF ICIMVAU I-cache invalidate by MVA to PoU 0 32 write-only DCIMVAC Data cache invalidate by address to Point of Coherency (PoC) 0xF5C 32 write-only 0 0xFFFFFFFF DCIMVAC D-cache invalidate by MVA to PoC 0 32 write-only DCISW Data cache invalidate by set/way 0xF60 32 write-only 0 0xFFFFFFFF DCISW D-cache invalidate by set-way 0 32 write-only DCCMVAU Data cache by address to PoU 0xF64 32 write-only 0 0xFFFFFFFF DCCMVAU D-cache clean by MVA to PoU 0 32 write-only DCCMVAC Data cache clean by address to PoC 0xF68 32 write-only 0 0xFFFFFFFF DCCMVAC D-cache clean by MVA to PoC 0 32 write-only DCCSW Data cache clean by set/way 0xF6C 32 write-only 0 0xFFFFFFFF DCCSW D-cache clean by set-way 0 32 write-only DCCIMVAC Data cache clean and invalidate by address to PoC 0xF70 32 write-only 0 0xFFFFFFFF DCCIMVAC D-cache clean and invalidate by MVA to PoC 0 32 write-only DCCISW Data cache clean and invalidate by set/way 0xF74 32 write-only 0 0xFFFFFFFF DCCISW D-cache clean and invalidate by set-way 0 32 write-only CM7_ITCMCR Instruction Tightly-Coupled Memory Control Register 0xF90 32 read-write 0 0xFFFFFFFF EN TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. 0 1 read-write EN_0 TCM disabled. 0 EN_1 TCM enabled. 0x1 RMW Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. 1 1 read-write RMW_0 RMW disabled. 0 RMW_1 RMW enabled. 0x1 RETEN Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. 2 1 read-write RETEN_0 Retry phase disabled. 0 RETEN_1 Retry phase enabled. 0x1 SZ TCM size. Indicates the size of the relevant TCM. 3 4 read-only SZ_0 No TCM implemented. 0 SZ_3 4KB. 0x3 SZ_4 8KB. 0x4 SZ_5 16KB. 0x5 SZ_6 32KB. 0x6 SZ_7 64KB. 0x7 SZ_8 128KB. 0x8 SZ_9 256KB. 0x9 SZ_10 512KB. 0xA SZ_11 1MB. 0xB SZ_12 2MB. 0xC SZ_13 4MB. 0xD SZ_14 8MB. 0xE SZ_15 16MB. 0xF CM7_DTCMCR Data Tightly-Coupled Memory Control Register 0xF94 32 read-write 0 0xFFFFFFFF EN TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. 0 1 read-write EN_0 TCM disabled. 0 EN_1 TCM enabled. 0x1 RMW Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. 1 1 read-write RMW_0 RMW disabled. 0 RMW_1 RMW enabled. 0x1 RETEN Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. 2 1 read-write RETEN_0 Retry phase disabled. 0 RETEN_1 Retry phase enabled. 0x1 SZ TCM size. Indicates the size of the relevant TCM. 3 4 read-only SZ_0 No TCM implemented. 0 SZ_3 4KB. 0x3 SZ_4 8KB. 0x4 SZ_5 16KB. 0x5 SZ_6 32KB. 0x6 SZ_7 64KB. 0x7 SZ_8 128KB. 0x8 SZ_9 256KB. 0x9 SZ_10 512KB. 0xA SZ_11 1MB. 0xB SZ_12 2MB. 0xC SZ_13 4MB. 0xD SZ_14 8MB. 0xE SZ_15 16MB. 0xF CM7_AHBPCR AHBP Control Register 0xF98 32 read-write 0 0xFFFFFFFF EN AHBP enable. 0 1 read-write EN_0 AHBP disabled. When disabled all accesses are made to the AXIM interface. 0 EN_1 AHBP enabled. 0x1 SZ AHBP size. 1 3 read-only SZ_0 0MB. AHBP disabled. 0 SZ_1 64MB. 0x1 SZ_2 128MB. 0x2 SZ_3 256MB. 0x3 SZ_4 512MB. 0x4 CM7_CACR L1 Cache Control Register 0xF9C 32 read-write 0 0xFFFFFFFF SIWT Shared cacheable-is-WT for data cache. Enables limited cache coherency usage. 0 1 read-write SIWT_0 Normal Cacheable Shared locations are treated as being Non-cacheable. Default mode of operation for Shared memory. 0 SIWT_1 Normal Cacheable shared locations are treated as Write-Through. 0x1 ECCDIS Enables ECC in the instruction and data cache. 1 1 read-write ECCDIS_0 Enables ECC in the instruction and data cache. 0 ECCDIS_1 Disables ECC in the instruction and data cache. 0x1 FORCEWT Enables Force Write-Through in the data cache. 2 1 read-write FORCEWT_0 Disables Force Write-Through. 0 FORCEWT_1 Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through. 0x1 CM7_AHBSCR AHB Slave Control Register 0xFA0 32 read-write 0 0xFFFFFFFF CTL AHBS prioritization control. 0 2 read-write CTL_0 AHBS access priority demoted. This is the reset value. 0 CTL_1 Software access priority demoted. 0x1 CTL_2 AHBS access priority demoted by initializing the fairness counter to the CM7_AHBSCR[INITCOUNT] value when the software execution priority is higher than or equal to the threshold level programed in CM7_AHBSCR[TPRI]. 0x2 CTL_3 AHBSPRI signal has control of access priority. 0x3 TPRI Threshold execution priority for AHBS traffic demotion. 2 9 read-write INITCOUNT Fairness counter initialization value. 11 5 read-write CM7_ABFSR Auxiliary Bus Fault Status Register 0xFA8 32 read-write 0 0xFFFFFFFF ITCM Asynchronous fault on ITCM interface. 0 1 read-write DTCM Asynchronous fault on DTCM interface. 1 1 read-write AHBP Asynchronous fault on AHBP interface. 2 1 read-write AXIM Asynchronous fault on AXIM interface. 3 1 read-write EPPB Asynchronous fault on EPPB interface. 4 1 read-write AXIMTYPE Indicates the type of fault on the AXIM interface. Only valid when AXIM is 1. 8 2 read-write AXIMTYPE_0 OKAY. 0 AXIMTYPE_1 EXOKAY. 0x1 AXIMTYPE_2 SLVERR. 0x2 AXIMTYPE_3 DECERR. 0x3 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0 0xE04 registers DMA0_DMA16 0 DMA1_DMA17 1 DMA2_DMA18 2 DMA3_DMA19 3 DMA4_DMA20 4 DMA5_DMA21 5 DMA6_DMA22 6 DMA7_DMA23 7 DMA8_DMA24 8 DMA9_DMA25 9 DMA10_DMA26 10 DMA11_DMA27 11 DMA12_DMA28 12 DMA13_DMA29 13 DMA14_DMA30 14 DMA15_DMA31 15 DMA_ERROR 16 CTI_TRIGGER_OUT0 17 CTI_TRIGGER_OUT1 18 CORE 19 LPUART1 20 LPUART2 21 LPUART3 22 LPUART4 23 LPUART5 24 LPUART6 25 LPUART7 26 LPUART8 27 LPUART9 28 LPUART10 29 LPUART11 30 LPUART12 31 LPI2C1 32 LPI2C2 33 LPI2C3 34 LPI2C4 35 LPI2C5 36 LPI2C6 37 LPSPI1 38 LPSPI2 39 LPSPI3 40 LPSPI4 41 LPSPI5 42 LPSPI6 43 CAN1 44 CAN1_ERROR 45 CAN2 46 CAN2_ERROR 47 CAN3 48 CAN3_ERROR 49 FLEXRAM 50 KPP 51 Reserved68 52 GPR_IRQ 53 eLCDIF 54 LCDIFv2 55 CSI 56 PXP 57 MIPI_CSI 58 MIPI_DSI 59 GPU2D 60 GPIO6_Combined_0_15 61 GPIO6_Combined_16_31 62 DAC 63 KEY_MANAGER 64 WDOG2 65 SNVS_HP_NON_TZ 66 SNVS_HP_TZ 67 SNVS_PULSE_EVENT 68 CAAM_IRQ0 69 CAAM_IRQ1 70 CAAM_IRQ2 71 CAAM_IRQ3 72 CAAM_RECORVE_ERRPR 73 CAAM_RTIC 74 CDOG 75 SAI1 76 SAI2 77 SAI3_RX 78 SAI3_TX 79 SAI4_RX 80 SAI4_TX 81 SPDIF 82 TMPSNS_INT 83 TMPSNS_LOW_HIGH 84 TMPSNS_PANIC 85 LPSR_LP8_BROWNOUT 86 LPSR_LP0_BROWNOUT 87 ADC1 88 ADC2 89 USBPHY1 90 USBPHY2 91 RDC 92 GPIO13_Combined_0_31 93 DCIC1 95 DCIC2 96 ASRC 97 FLEXRAM_ECC 98 CM7_GPIO2_3 99 GPIO1_Combined_0_15 100 GPIO1_Combined_16_31 101 GPIO2_Combined_0_15 102 GPIO2_Combined_16_31 103 GPIO3_Combined_0_15 104 GPIO3_Combined_16_31 105 GPIO4_Combined_0_15 106 GPIO4_Combined_16_31 107 GPIO5_Combined_0_15 108 GPIO5_Combined_16_31 109 FLEXIO1 110 FLEXIO2 111 WDOG1 112 RTWDOG3 113 EWM 114 OCOTP_READ_FUSE_ERROR 115 OCOTP_READ_DONE_ERROR 116 GPC 117 MUA 118 GPT1 119 GPT2 120 GPT3 121 GPT4 122 GPT5 123 GPT6 124 PWM1_0 125 PWM1_1 126 PWM1_2 127 PWM1_3 128 PWM1_FAULT 129 FLEXSPI2 131 SEMC 132 USDHC1 133 USDHC2 134 USB_OTG2 135 USB_OTG1 136 ENET 137 ENET_1588_Timer 138 ENET_1G_MAC0_Tx_Rx_1 139 ENET_1G_MAC0_Tx_Rx_2 140 ENET_1G 141 ENET_1G_1588_Timer 142 XBAR1_IRQ_0_1 143 XBAR1_IRQ_2_3 144 ADC_ETC_IRQ0 145 ADC_ETC_IRQ1 146 ADC_ETC_IRQ2 147 ADC_ETC_IRQ3 148 ADC_ETC_ERROR_IRQ 149 PIT1 155 PIT2 156 ACMP1 157 ACMP2 158 ACMP3 159 ACMP4 160 Reserved177 161 Reserved178 162 Reserved179 163 Reserved180 164 ENC1 165 ENC2 166 ENC3 167 ENC4 168 Reserved185 169 Reserved186 170 TMR1 171 TMR2 172 TMR3 173 TMR4 174 SEMA4_CP0 175 SEMA4_CP1 176 PWM2_0 177 PWM2_1 178 PWM2_2 179 PWM2_3 180 PWM2_FAULT 181 PWM3_0 182 PWM3_1 183 PWM3_2 184 PWM3_3 185 PWM3_FAULT 186 PWM4_0 187 PWM4_1 188 PWM4_2 189 PWM4_3 190 PWM4_FAULT 191 Reserved208 192 Reserved209 193 Reserved210 194 Reserved211 195 Reserved212 196 Reserved213 197 Reserved214 198 Reserved215 199 PDM_HWVAD_EVENT 200 PDM_HWVAD_ERROR 201 PDM_EVENT 202 PDM_ERROR 203 EMVSIM1 204 EMVSIM2 205 MECC1_INT 206 MECC1_FATAL_INT 207 MECC2_INT 208 MECC2_FATAL_INT 209 XECC_FLEXSPI1_INT 210 XECC_FLEXSPI1_FATAL_INT 211 XECC_FLEXSPI2_INT 212 XECC_FLEXSPI2_FATAL_INT 213 XECC_SEMC_INT 214 XECC_SEMC_FATAL_INT 215 ENET_QOS 216 ENET_QOS_PMT 217 NVICISER0 Interrupt Set Enable Register n 0 32 read-write 0 0xFFFFFFFF oneToClear SETENA Interrupt set enable bits 0 32 read-write oneToClear NVICISER1 Interrupt Set Enable Register n 0x4 32 read-write 0 0xFFFFFFFF oneToClear SETENA Interrupt set enable bits 0 32 read-write oneToClear NVICISER2 Interrupt Set Enable Register n 0x8 32 read-write 0 0xFFFFFFFF oneToClear SETENA Interrupt set enable bits 0 32 read-write oneToClear NVICISER3 Interrupt Set Enable Register n 0xC 32 read-write 0 0xFFFFFFFF oneToClear SETENA Interrupt set enable bits 0 32 read-write oneToClear NVICICER0 Interrupt Clear Enable Register n 0x80 32 read-write 0 0xFFFFFFFF oneToClear CLRENA Interrupt clear-enable bits 0 32 read-write oneToClear NVICICER1 Interrupt Clear Enable Register n 0x84 32 read-write 0 0xFFFFFFFF oneToClear CLRENA Interrupt clear-enable bits 0 32 read-write oneToClear NVICICER2 Interrupt Clear Enable Register n 0x88 32 read-write 0 0xFFFFFFFF oneToClear CLRENA Interrupt clear-enable bits 0 32 read-write oneToClear NVICICER3 Interrupt Clear Enable Register n 0x8C 32 read-write 0 0xFFFFFFFF oneToClear CLRENA Interrupt clear-enable bits 0 32 read-write oneToClear NVICISPR0 Interrupt Set Pending Register n 0x100 32 read-write 0 0xFFFFFFFF oneToClear SETPEND Interrupt set-pending bits 0 32 read-write oneToClear NVICISPR1 Interrupt Set Pending Register n 0x104 32 read-write 0 0xFFFFFFFF oneToClear SETPEND Interrupt set-pending bits 0 32 read-write oneToClear NVICISPR2 Interrupt Set Pending Register n 0x108 32 read-write 0 0xFFFFFFFF oneToClear SETPEND Interrupt set-pending bits 0 32 read-write oneToClear NVICISPR3 Interrupt Set Pending Register n 0x10C 32 read-write 0 0xFFFFFFFF oneToClear SETPEND Interrupt set-pending bits 0 32 read-write oneToClear NVICICPR0 Interrupt Clear Pending Register n 0x180 32 read-write 0 0xFFFFFFFF oneToClear CLRPEND Interrupt clear-pending bits 0 32 read-write oneToClear NVICICPR1 Interrupt Clear Pending Register n 0x184 32 read-write 0 0xFFFFFFFF oneToClear CLRPEND Interrupt clear-pending bits 0 32 read-write oneToClear NVICICPR2 Interrupt Clear Pending Register n 0x188 32 read-write 0 0xFFFFFFFF oneToClear CLRPEND Interrupt clear-pending bits 0 32 read-write oneToClear NVICICPR3 Interrupt Clear Pending Register n 0x18C 32 read-write 0 0xFFFFFFFF oneToClear CLRPEND Interrupt clear-pending bits 0 32 read-write oneToClear NVICIABR0 Interrupt Active bit Register n 0x200 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR1 Interrupt Active bit Register n 0x204 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR2 Interrupt Active bit Register n 0x208 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR3 Interrupt Active bit Register n 0x20C 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIP0 Interrupt Priority Register 0 0x300 8 read-write 0 0xFF PRI0 Priority of interrupt 0 4 4 read-write NVICIP1 Interrupt Priority Register 1 0x301 8 read-write 0 0xFF PRI1 Priority of interrupt 1 4 4 read-write NVICIP2 Interrupt Priority Register 2 0x302 8 read-write 0 0xFF PRI2 Priority of interrupt 2 4 4 read-write NVICIP3 Interrupt Priority Register 3 0x303 8 read-write 0 0xFF PRI3 Priority of interrupt 3 4 4 read-write NVICIP4 Interrupt Priority Register 4 0x304 8 read-write 0 0xFF PRI4 Priority of interrupt 4 4 4 read-write NVICIP5 Interrupt Priority Register 5 0x305 8 read-write 0 0xFF PRI5 Priority of interrupt 5 4 4 read-write NVICIP6 Interrupt Priority Register 6 0x306 8 read-write 0 0xFF PRI6 Priority of interrupt 6 4 4 read-write NVICIP7 Interrupt Priority Register 7 0x307 8 read-write 0 0xFF PRI7 Priority of interrupt 7 4 4 read-write NVICIP8 Interrupt Priority Register 8 0x308 8 read-write 0 0xFF PRI8 Priority of interrupt 8 4 4 read-write NVICIP9 Interrupt Priority Register 9 0x309 8 read-write 0 0xFF PRI9 Priority of interrupt 9 4 4 read-write NVICIP10 Interrupt Priority Register 10 0x30A 8 read-write 0 0xFF PRI10 Priority of interrupt 10 4 4 read-write NVICIP11 Interrupt Priority Register 11 0x30B 8 read-write 0 0xFF PRI11 Priority of interrupt 11 4 4 read-write NVICIP12 Interrupt Priority Register 12 0x30C 8 read-write 0 0xFF PRI12 Priority of interrupt 12 4 4 read-write NVICIP13 Interrupt Priority Register 13 0x30D 8 read-write 0 0xFF PRI13 Priority of interrupt 13 4 4 read-write NVICIP14 Interrupt Priority Register 14 0x30E 8 read-write 0 0xFF PRI14 Priority of interrupt 14 4 4 read-write NVICIP15 Interrupt Priority Register 15 0x30F 8 read-write 0 0xFF PRI15 Priority of interrupt 15 4 4 read-write NVICIP16 Interrupt Priority Register 16 0x310 8 read-write 0 0xFF PRI16 Priority of interrupt 16 4 4 read-write NVICIP17 Interrupt Priority Register 17 0x311 8 read-write 0 0xFF PRI17 Priority of interrupt 17 4 4 read-write NVICIP18 Interrupt Priority Register 18 0x312 8 read-write 0 0xFF PRI18 Priority of interrupt 18 4 4 read-write NVICIP19 Interrupt Priority Register 19 0x313 8 read-write 0 0xFF PRI19 Priority of interrupt 19 4 4 read-write NVICIP20 Interrupt Priority Register 20 0x314 8 read-write 0 0xFF PRI20 Priority of interrupt 20 4 4 read-write NVICIP21 Interrupt Priority Register 21 0x315 8 read-write 0 0xFF PRI21 Priority of interrupt 21 4 4 read-write NVICIP22 Interrupt Priority Register 22 0x316 8 read-write 0 0xFF PRI22 Priority of interrupt 22 4 4 read-write NVICIP23 Interrupt Priority Register 23 0x317 8 read-write 0 0xFF PRI23 Priority of interrupt 23 4 4 read-write NVICIP24 Interrupt Priority Register 24 0x318 8 read-write 0 0xFF PRI24 Priority of interrupt 24 4 4 read-write NVICIP25 Interrupt Priority Register 25 0x319 8 read-write 0 0xFF PRI25 Priority of interrupt 25 4 4 read-write NVICIP26 Interrupt Priority Register 26 0x31A 8 read-write 0 0xFF PRI26 Priority of interrupt 26 4 4 read-write NVICIP27 Interrupt Priority Register 27 0x31B 8 read-write 0 0xFF PRI27 Priority of interrupt 27 4 4 read-write NVICIP28 Interrupt Priority Register 28 0x31C 8 read-write 0 0xFF PRI28 Priority of interrupt 28 4 4 read-write NVICIP29 Interrupt Priority Register 29 0x31D 8 read-write 0 0xFF PRI29 Priority of interrupt 29 4 4 read-write NVICIP30 Interrupt Priority Register 30 0x31E 8 read-write 0 0xFF PRI30 Priority of interrupt 30 4 4 read-write NVICIP31 Interrupt Priority Register 31 0x31F 8 read-write 0 0xFF PRI31 Priority of interrupt 31 4 4 read-write NVICIP32 Interrupt Priority Register 32 0x320 8 read-write 0 0xFF PRI32 Priority of interrupt 32 4 4 read-write NVICIP33 Interrupt Priority Register 33 0x321 8 read-write 0 0xFF PRI33 Priority of interrupt 33 4 4 read-write NVICIP34 Interrupt Priority Register 34 0x322 8 read-write 0 0xFF PRI34 Priority of interrupt 34 4 4 read-write NVICIP35 Interrupt Priority Register 35 0x323 8 read-write 0 0xFF PRI35 Priority of interrupt 35 4 4 read-write NVICIP36 Interrupt Priority Register 36 0x324 8 read-write 0 0xFF PRI36 Priority of interrupt 36 4 4 read-write NVICIP37 Interrupt Priority Register 37 0x325 8 read-write 0 0xFF PRI37 Priority of interrupt 37 4 4 read-write NVICIP38 Interrupt Priority Register 38 0x326 8 read-write 0 0xFF PRI38 Priority of interrupt 38 4 4 read-write NVICIP39 Interrupt Priority Register 39 0x327 8 read-write 0 0xFF PRI39 Priority of interrupt 39 4 4 read-write NVICIP40 Interrupt Priority Register 40 0x328 8 read-write 0 0xFF PRI40 Priority of interrupt 40 4 4 read-write NVICIP41 Interrupt Priority Register 41 0x329 8 read-write 0 0xFF PRI41 Priority of interrupt 41 4 4 read-write NVICIP42 Interrupt Priority Register 42 0x32A 8 read-write 0 0xFF PRI42 Priority of interrupt 42 4 4 read-write NVICIP43 Interrupt Priority Register 43 0x32B 8 read-write 0 0xFF PRI43 Priority of interrupt 43 4 4 read-write NVICIP44 Interrupt Priority Register 44 0x32C 8 read-write 0 0xFF PRI44 Priority of interrupt 44 4 4 read-write NVICIP45 Interrupt Priority Register 45 0x32D 8 read-write 0 0xFF PRI45 Priority of interrupt 45 4 4 read-write NVICIP46 Interrupt Priority Register 46 0x32E 8 read-write 0 0xFF PRI46 Priority of interrupt 46 4 4 read-write NVICIP47 Interrupt Priority Register 47 0x32F 8 read-write 0 0xFF PRI47 Priority of interrupt 47 4 4 read-write NVICIP48 Interrupt Priority Register 48 0x330 8 read-write 0 0xFF PRI48 Priority of interrupt 48 4 4 read-write NVICIP49 Interrupt Priority Register 49 0x331 8 read-write 0 0xFF PRI49 Priority of interrupt 49 4 4 read-write NVICIP50 Interrupt Priority Register 50 0x332 8 read-write 0 0xFF PRI50 Priority of interrupt 50 4 4 read-write NVICIP51 Interrupt Priority Register 51 0x333 8 read-write 0 0xFF PRI51 Priority of interrupt 51 4 4 read-write NVICIP52 Interrupt Priority Register 52 0x334 8 read-write 0 0xFF PRI52 Priority of interrupt 52 4 4 read-write NVICIP53 Interrupt Priority Register 53 0x335 8 read-write 0 0xFF PRI53 Priority of interrupt 53 4 4 read-write NVICIP54 Interrupt Priority Register 54 0x336 8 read-write 0 0xFF PRI54 Priority of interrupt 54 4 4 read-write NVICIP55 Interrupt Priority Register 55 0x337 8 read-write 0 0xFF PRI55 Priority of interrupt 55 4 4 read-write NVICIP56 Interrupt Priority Register 56 0x338 8 read-write 0 0xFF PRI56 Priority of interrupt 56 4 4 read-write NVICIP57 Interrupt Priority Register 57 0x339 8 read-write 0 0xFF PRI57 Priority of interrupt 57 4 4 read-write NVICIP58 Interrupt Priority Register 58 0x33A 8 read-write 0 0xFF PRI58 Priority of interrupt 58 4 4 read-write NVICIP59 Interrupt Priority Register 59 0x33B 8 read-write 0 0xFF PRI59 Priority of interrupt 59 4 4 read-write NVICIP60 Interrupt Priority Register 60 0x33C 8 read-write 0 0xFF PRI60 Priority of interrupt 60 4 4 read-write NVICIP61 Interrupt Priority Register 61 0x33D 8 read-write 0 0xFF PRI61 Priority of interrupt 61 4 4 read-write NVICIP62 Interrupt Priority Register 62 0x33E 8 read-write 0 0xFF PRI62 Priority of interrupt 62 4 4 read-write NVICIP63 Interrupt Priority Register 63 0x33F 8 read-write 0 0xFF PRI63 Priority of interrupt 63 4 4 read-write NVICIP64 Interrupt Priority Register 64 0x340 8 read-write 0 0xFF PRI64 Priority of interrupt 64 4 4 read-write NVICIP65 Interrupt Priority Register 65 0x341 8 read-write 0 0xFF PRI65 Priority of interrupt 65 4 4 read-write NVICIP66 Interrupt Priority Register 66 0x342 8 read-write 0 0xFF PRI66 Priority of interrupt 66 4 4 read-write NVICIP67 Interrupt Priority Register 67 0x343 8 read-write 0 0xFF PRI67 Priority of interrupt 67 4 4 read-write NVICIP68 Interrupt Priority Register 68 0x344 8 read-write 0 0xFF PRI68 Priority of interrupt 68 4 4 read-write NVICIP69 Interrupt Priority Register 69 0x345 8 read-write 0 0xFF PRI69 Priority of interrupt 69 4 4 read-write NVICIP70 Interrupt Priority Register 70 0x346 8 read-write 0 0xFF PRI70 Priority of interrupt 70 4 4 read-write NVICIP71 Interrupt Priority Register 71 0x347 8 read-write 0 0xFF PRI71 Priority of interrupt 71 4 4 read-write NVICIP72 Interrupt Priority Register 72 0x348 8 read-write 0 0xFF PRI72 Priority of interrupt 72 4 4 read-write NVICIP73 Interrupt Priority Register 73 0x349 8 read-write 0 0xFF PRI73 Priority of interrupt 73 4 4 read-write NVICIP74 Interrupt Priority Register 74 0x34A 8 read-write 0 0xFF PRI74 Priority of interrupt 74 4 4 read-write NVICIP75 Interrupt Priority Register 75 0x34B 8 read-write 0 0xFF PRI75 Priority of interrupt 75 4 4 read-write NVICIP76 Interrupt Priority Register 76 0x34C 8 read-write 0 0xFF PRI76 Priority of interrupt 76 4 4 read-write NVICIP77 Interrupt Priority Register 77 0x34D 8 read-write 0 0xFF PRI77 Priority of interrupt 77 4 4 read-write NVICIP78 Interrupt Priority Register 78 0x34E 8 read-write 0 0xFF PRI78 Priority of interrupt 78 4 4 read-write NVICIP79 Interrupt Priority Register 79 0x34F 8 read-write 0 0xFF PRI79 Priority of interrupt 79 4 4 read-write NVICIP80 Interrupt Priority Register 80 0x350 8 read-write 0 0xFF PRI80 Priority of interrupt 80 4 4 read-write NVICIP81 Interrupt Priority Register 81 0x351 8 read-write 0 0xFF PRI81 Priority of interrupt 81 4 4 read-write NVICIP82 Interrupt Priority Register 82 0x352 8 read-write 0 0xFF PRI82 Priority of interrupt 82 4 4 read-write NVICIP83 Interrupt Priority Register 83 0x353 8 read-write 0 0xFF PRI83 Priority of interrupt 83 4 4 read-write NVICIP84 Interrupt Priority Register 84 0x354 8 read-write 0 0xFF PRI84 Priority of interrupt 84 4 4 read-write NVICIP85 Interrupt Priority Register 85 0x355 8 read-write 0 0xFF PRI85 Priority of interrupt 85 4 4 read-write NVICIP86 Interrupt Priority Register 86 0x356 8 read-write 0 0xFF PRI86 Priority of interrupt 86 4 4 read-write NVICIP87 Interrupt Priority Register 87 0x357 8 read-write 0 0xFF PRI87 Priority of interrupt 87 4 4 read-write NVICIP88 Interrupt Priority Register 88 0x358 8 read-write 0 0xFF PRI88 Priority of interrupt 88 4 4 read-write NVICIP89 Interrupt Priority Register 89 0x359 8 read-write 0 0xFF PRI89 Priority of interrupt 89 4 4 read-write NVICIP90 Interrupt Priority Register 90 0x35A 8 read-write 0 0xFF PRI90 Priority of interrupt 90 4 4 read-write NVICIP91 Interrupt Priority Register 91 0x35B 8 read-write 0 0xFF PRI91 Priority of interrupt 91 4 4 read-write NVICIP92 Interrupt Priority Register 92 0x35C 8 read-write 0 0xFF PRI92 Priority of interrupt 92 4 4 read-write NVICIP93 Interrupt Priority Register 93 0x35D 8 read-write 0 0xFF PRI93 Priority of interrupt 93 4 4 read-write NVICIP94 Interrupt Priority Register 94 0x35E 8 read-write 0 0xFF PRI94 Priority of interrupt 94 4 4 read-write NVICIP95 Interrupt Priority Register 95 0x35F 8 read-write 0 0xFF PRI95 Priority of interrupt 95 4 4 read-write NVICIP96 Interrupt Priority Register 96 0x360 8 read-write 0 0xFF PRI96 Priority of interrupt 96 4 4 read-write NVICIP97 Interrupt Priority Register 97 0x361 8 read-write 0 0xFF PRI97 Priority of interrupt 97 4 4 read-write NVICIP98 Interrupt Priority Register 98 0x362 8 read-write 0 0xFF PRI98 Priority of interrupt 98 4 4 read-write NVICIP99 Interrupt Priority Register 99 0x363 8 read-write 0 0xFF PRI99 Priority of interrupt 99 4 4 read-write NVICIP100 Interrupt Priority Register 100 0x364 8 read-write 0 0xFF PRI100 Priority of interrupt 100 4 4 read-write NVICIP101 Interrupt Priority Register 101 0x365 8 read-write 0 0xFF PRI101 Priority of interrupt 101 4 4 read-write NVICIP102 Interrupt Priority Register 102 0x366 8 read-write 0 0xFF PRI102 Priority of interrupt 102 4 4 read-write NVICIP103 Interrupt Priority Register 103 0x367 8 read-write 0 0xFF PRI103 Priority of interrupt 103 4 4 read-write NVICIP104 Interrupt Priority Register 104 0x368 8 read-write 0 0xFF PRI104 Priority of interrupt 104 4 4 read-write NVICIP105 Interrupt Priority Register 105 0x369 8 read-write 0 0xFF PRI105 Priority of interrupt 105 4 4 read-write NVICSTIR Software Trigger Interrupt Register 0xE00 32 read-write 0 0xFFFFFFFF INTID Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 read-write CM7_MCM CM7_MCM CM7_MCM 0xE0080000 0 0x14 registers ISCR Interrupt Status and Control Register 0x10 32 read-write 0 0xFFFFFFFF WABS Write Abort on Slave 5 1 read-write oneToClear noabort No abort 0 abort Abort 0x1 WABSO Write Abort on Slave Overrun 6 1 read-only no No write abort overrun 0 yes Write abort overrun occurred 0x1 FIOC FPU Invalid Operation interrupt Status 8 1 read-only No No interrupt 0 Yes Interrupt occured 0x1 FDZC FPU Divide-by-Zero Interrupt Status 9 1 read-only No No interrupt 0 Yes Interrupt occured 0x1 FOFC FPU Overflow interrupt status 10 1 read-only No No interrupt 0 Yes Interrupt occured 0x1 FUFC FPU Underflow Interrupt Status 11 1 read-only No No interrupt 0 Yes Interrupt occured 0x1 FIXC FPU Inexact Interrupt Status 12 1 read-only No No interrupt 0 Yes Interrupt occured 0x1 FIDC FPU Input Denormal Interrupt Status 15 1 read-only No No interrupt 0 Yes Interrupt occured 0x1 WABE TCM Write Abort Interrupt enable 21 1 read-write DISABLE Disable interrupt 0 ENABLE Enable interrupt 0x1 FIOCE FPU Invalid Operation Interrupt Enable 24 1 read-write DISABLE Disable interrupt 0 ENABLE Enable interrupt 0x1 FDZCE FPU Divide-by-Zero Interrupt Enable 25 1 read-write DISABLE Disable interrupt 0 ENABLE Enable interrupt 0x1 FOFCE FPU Overflow Interrupt Enable 26 1 read-write DISABLE Disable interrupt 0 ENABLE Enable interrupt 0x1 FUFCE FPU Underflow Interrupt Enable 27 1 read-write DISABLE Disable interrupt 0 ENABLE Enable interrupt 0x1 FIXCE FPU Inexact Interrupt Enable 28 1 read-write DISABLE Disable interrupt 0 ENABLE Enable interrupt 0x1 FIDCE FPU Input Denormal Interrupt Enable 31 1 read-write DISABLE Disable interrupt 0 ENABLE Enable interrupt 0x1