/* generated HAL source file - do not edit */ #include "hal_data.h" dtc_instance_ctrl_t g_transfer1_ctrl; transfer_info_t g_transfer1_info = { .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, .transfer_settings_word_b.irq = TRANSFER_IRQ_END, .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED, .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, .p_dest = (void *) NULL, .p_src = (void const *) NULL, .num_blocks = 0, .length = 0, }; const dtc_extended_cfg_t g_transfer1_cfg_extend = { .activation_source = VECTOR_NUMBER_SCI9_RXI, }; const transfer_cfg_t g_transfer1_cfg = { .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; /* Instance structure to use this module. */ const transfer_instance_t g_transfer1 = { .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; dtc_instance_ctrl_t g_transfer0_ctrl; transfer_info_t g_transfer0_info = { .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE, .transfer_settings_word_b.irq = TRANSFER_IRQ_END, .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, .p_dest = (void *) NULL, .p_src = (void const *) NULL, .num_blocks = 0, .length = 0, }; const dtc_extended_cfg_t g_transfer0_cfg_extend = { .activation_source = VECTOR_NUMBER_SCI9_TXI, }; const transfer_cfg_t g_transfer0_cfg = { .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; /* Instance structure to use this module. */ const transfer_instance_t g_transfer0 = { .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; sci_spi_instance_ctrl_t g_sci_spi9_ctrl; /** SPI extended configuration */ const sci_spi_extended_cfg_t g_sci_spi9_cfg_extend = { .clk_div = { /* Actual calculated bitrate: 6250000. */ .cks = 0, .brr = 3, .mddr = 0, } }; const spi_cfg_t g_sci_spi9_cfg = { .channel = 9, .operating_mode = SPI_MODE_MASTER, .clk_phase = SPI_CLK_PHASE_EDGE_ODD, .clk_polarity = SPI_CLK_POLARITY_LOW, .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, .bit_order = SPI_BIT_ORDER_MSB_FIRST, #define RA_NOT_DEFINED (1) #if (RA_NOT_DEFINED == g_transfer0) .p_transfer_tx = NULL, #else .p_transfer_tx = &g_transfer0, #endif #if (RA_NOT_DEFINED == g_transfer1) .p_transfer_rx = NULL, #else .p_transfer_rx = &g_transfer1, #endif #undef RA_NOT_DEFINED .p_callback = sci_spi9_callback, .p_context = NULL, .rxi_irq = VECTOR_NUMBER_SCI9_RXI, .txi_irq = VECTOR_NUMBER_SCI9_TXI, .tei_irq = VECTOR_NUMBER_SCI9_TEI, .eri_irq = VECTOR_NUMBER_SCI9_ERI, .rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), .p_extend = &g_sci_spi9_cfg_extend, }; /* Instance structure to use this module. */ const spi_instance_t g_sci_spi9 = { .p_ctrl = &g_sci_spi9_ctrl, .p_cfg = &g_sci_spi9_cfg, .p_api = &g_spi_on_sci }; sci_uart_instance_ctrl_t g_uart4_ctrl; baud_setting_t g_uart4_baud_setting = { /* Baud rate calculated with 0.014% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 38, .mddr = (uint8_t) 184, .semr_baudrate_bits_b.brme = true }; /** UART extended configuration for UARTonSCI HAL driver */ const sci_uart_extended_cfg_t g_uart4_cfg_extend = { .clock = SCI_UART_CLOCK_INT, .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting = &g_uart4_baud_setting, .flow_control = SCI_UART_FLOW_CONTROL_RTS, #if 0xFF != 0xFF .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, #else .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, #endif .rs485_setting = { .enable = SCI_UART_RS485_DISABLE, .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, #if 0xFF != 0xFF .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, #else .de_control_pin = (bsp_io_port_pin_t) UINT16_MAX, #endif }, }; /** UART interface configuration */ const uart_cfg_t g_uart4_cfg = { .channel = 4, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = user_uart4_callback, .p_context = NULL, .p_extend = &g_uart4_cfg_extend, #define RA_NOT_DEFINED (1) #if (RA_NOT_DEFINED == RA_NOT_DEFINED) .p_transfer_tx = NULL, #else .p_transfer_tx = &RA_NOT_DEFINED, #endif #if (RA_NOT_DEFINED == RA_NOT_DEFINED) .p_transfer_rx = NULL, #else .p_transfer_rx = &RA_NOT_DEFINED, #endif #undef RA_NOT_DEFINED .rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), #if defined(VECTOR_NUMBER_SCI4_RXI) .rxi_irq = VECTOR_NUMBER_SCI4_RXI, #else .rxi_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_SCI4_TXI) .txi_irq = VECTOR_NUMBER_SCI4_TXI, #else .txi_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_SCI4_TEI) .tei_irq = VECTOR_NUMBER_SCI4_TEI, #else .tei_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_SCI4_ERI) .eri_irq = VECTOR_NUMBER_SCI4_ERI, #else .eri_irq = FSP_INVALID_VECTOR, #endif }; /* Instance structure to use this module. */ const uart_instance_t g_uart4 = { .p_ctrl = &g_uart4_ctrl, .p_cfg = &g_uart4_cfg, .p_api = &g_uart_on_sci }; sci_uart_instance_ctrl_t g_uart0_ctrl; baud_setting_t g_uart0_baud_setting = { /* Baud rate calculated with 0.014% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 38, .mddr = (uint8_t) 184, .semr_baudrate_bits_b.brme = true }; /** UART extended configuration for UARTonSCI HAL driver */ const sci_uart_extended_cfg_t g_uart0_cfg_extend = { .clock = SCI_UART_CLOCK_INT, .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting = &g_uart0_baud_setting, .flow_control = SCI_UART_FLOW_CONTROL_RTS, #if 0xFF != 0xFF .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, #else .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, #endif .rs485_setting = { .enable = SCI_UART_RS485_DISABLE, .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, #if 0xFF != 0xFF .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, #else .de_control_pin = (bsp_io_port_pin_t) UINT16_MAX, #endif }, }; /** UART interface configuration */ const uart_cfg_t g_uart0_cfg = { .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = user_uart0_callback, .p_context = NULL, .p_extend = &g_uart0_cfg_extend, #define RA_NOT_DEFINED (1) #if (RA_NOT_DEFINED == RA_NOT_DEFINED) .p_transfer_tx = NULL, #else .p_transfer_tx = &RA_NOT_DEFINED, #endif #if (RA_NOT_DEFINED == RA_NOT_DEFINED) .p_transfer_rx = NULL, #else .p_transfer_rx = &RA_NOT_DEFINED, #endif #undef RA_NOT_DEFINED .rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), #if defined(VECTOR_NUMBER_SCI0_RXI) .rxi_irq = VECTOR_NUMBER_SCI0_RXI, #else .rxi_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_SCI0_TXI) .txi_irq = VECTOR_NUMBER_SCI0_TXI, #else .txi_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_SCI0_TEI) .tei_irq = VECTOR_NUMBER_SCI0_TEI, #else .tei_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_SCI0_ERI) .eri_irq = VECTOR_NUMBER_SCI0_ERI, #else .eri_irq = FSP_INVALID_VECTOR, #endif }; /* Instance structure to use this module. */ const uart_instance_t g_uart0 = { .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci }; void g_hal_init(void) { g_common_init(); }