HPMICRO HPM5301 HPM5300 1.0 HPM5300 device /* * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ other r0p0 little false true true 7 false 8 32 32 read-write 0x0 0xFFFFFFFF FGPIO FGPIO GPIO 0xc0000 0x0 0x8f0 registers 15 0x10 gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy DI[%s] no description available 0x0 VALUE GPIO input value 0x0 32 0x00000000 0xFFFFFFFF INPUT GPIO input bus value, each bit represents a bus bit 0: low level presents on chip pin 1: high level presents on chip pin 0 32 read-only 15 0x10 gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy DO[%s] no description available 0x100 VALUE GPIO output value 0x0 32 0x00000000 0xFFFFFFFF OUTPUT GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output 0 32 read-write SET GPIO output set 0x4 32 0x00000000 0xFFFFFFFF OUTPUT GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output 0 32 read-write CLEAR GPIO output clear 0x8 32 0x00000000 0xFFFFFFFF OUTPUT GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output 0 32 read-write TOGGLE GPIO output toggle 0xc 32 0x00000000 0xFFFFFFFF OUTPUT GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output 0 32 read-write 15 0x10 gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy OE[%s] no description available 0x200 VALUE GPIO direction value 0x0 32 0x00000000 0xFFFFFFFF DIRECTION GPIO direction, each bit represents a bus bit 0: input 1: output 0 32 read-write SET GPIO direction set 0x4 32 0x00000000 0xFFFFFFFF DIRECTION GPIO direction, each bit represents a bus bit 0: input 1: output 0 32 read-write CLEAR GPIO direction clear 0x8 32 0x00000000 0xFFFFFFFF DIRECTION GPIO direction, each bit represents a bus bit 0: input 1: output 0 32 read-write TOGGLE GPIO direction toggle 0xc 32 0x00000000 0xFFFFFFFF DIRECTION GPIO direction, each bit represents a bus bit 0: input 1: output 0 32 read-write 15 0x10 gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy IF[%s] no description available 0x300 VALUE GPIO interrupt flag value 0x0 32 0x00000000 0xFFFFFFFF IRQ_FLAG GPIO interrupt flag, write 1 to clear this flag 0: no irq 1: irq pending 0 32 write-only 15 0x10 gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy IE[%s] no description available 0x400 VALUE GPIO interrupt enable value 0x0 32 0x00000000 0xFFFFFFFF IRQ_EN GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable 0 32 read-write SET GPIO interrupt enable set 0x4 32 0x00000000 0xFFFFFFFF IRQ_EN GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable 0 32 read-write CLEAR GPIO interrupt enable clear 0x8 32 0x00000000 0xFFFFFFFF IRQ_EN GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable 0 32 read-write TOGGLE GPIO interrupt enable toggle 0xc 32 0x00000000 0xFFFFFFFF IRQ_EN GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable 0 32 read-write 15 0x10 gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy PL[%s] no description available 0x500 VALUE GPIO interrupt polarity value 0x0 32 0x00000000 0xFFFFFFFF IRQ_POL GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge 0 32 read-write SET GPIO interrupt polarity set 0x4 32 0x00000000 0xFFFFFFFF IRQ_POL GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge 0 32 read-write CLEAR GPIO interrupt polarity clear 0x8 32 0x00000000 0xFFFFFFFF IRQ_POL GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge 0 32 read-write TOGGLE GPIO interrupt polarity toggle 0xc 32 0x00000000 0xFFFFFFFF IRQ_POL GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge 0 32 read-write 15 0x10 gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy TP[%s] no description available 0x600 VALUE GPIO interrupt type value 0x0 32 0x00000000 0xFFFFFFFF IRQ_TYPE GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge 0 32 read-write SET GPIO interrupt type set 0x4 32 0x00000000 0xFFFFFFFF IRQ_TYPE GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge 0 32 read-write CLEAR GPIO interrupt type clear 0x8 32 0x00000000 0xFFFFFFFF IRQ_TYPE GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge 0 32 read-write TOGGLE GPIO interrupt type toggle 0xc 32 0x00000000 0xFFFFFFFF IRQ_TYPE GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge 0 32 read-write 15 0x10 gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy AS[%s] no description available 0x700 VALUE GPIO interrupt asynchronous value 0x0 32 0x00000000 0xFFFFFFFF IRQ_ASYNC GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise 0 32 read-write SET GPIO interrupt asynchronous set 0x4 32 0x00000000 0xFFFFFFFF IRQ_ASYNC GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise 0 32 read-write CLEAR GPIO interrupt asynchronous clear 0x8 32 0x00000000 0xFFFFFFFF IRQ_ASYNC GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise 0 32 read-write TOGGLE GPIO interrupt asynchronous toggle 0xc 32 0x00000000 0xFFFFFFFF IRQ_ASYNC GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise 0 32 read-write 15 0x10 gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy PD[%s] no description available 0x800 VALUE GPIO dual edge interrupt enable value 0x0 32 0x00000000 0x00000001 IRQ_DUAL GPIO dual edge interrupt enable 0: single edge interrupt 1: dual edge interrupt enable 0 1 read-write SET GPIO dual edge interrupt enable set 0x4 32 0x00000000 0x00000001 IRQ_DUAL GPIO dual edge interrupt enable set 0: keep original edge interrupt type 1: dual edge interrupt enable 0 1 read-write CLEAR GPIO dual edge interrupt enable clear 0x8 32 0x00000000 0x00000001 IRQ_DUAL GPIO dual edge interrupt enable clear 0: keep original edge interrupt type 1: single edge interrupt enable 0 1 read-write TOGGLE GPIO dual edge interrupt enable toggle 0xc 32 0x00000000 0x00000001 IRQ_DUAL GPIO dual edge interrupt enable toggle 0: keep original edge interrupt type 1: change original edge interrupt type to another one. 0 1 read-write GPIO0 GPIO0 GPIO 0xf00d0000 PGPIO PGPIO GPIO 0xf411c000 PLIC PLIC PLIC 0xe4000000 0x0 0x201000 registers feature Feature enable register 0x0 32 0x00000000 0x00000003 VECTORED Vector mode enable 0: Disabled 1: Enabled 1 1 read-write PREEMPT Preemptive priority interrupt enable 0: Disabled 1: Enabled 0 1 read-write 127 0x4 PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 PRIORITY[%s] no description available 0x4 32 0x00000001 0xFFFFFFFF PRIORITY Interrupt source priority. The valid range of this field is 0-7. 0: Never interrupt 1-7: Interrupt source priority. The larger the value, the higher the priority. 0 32 read-write 4 0x4 PENDING0,PENDING1,PENDING2,PENDING3 PENDING[%s] no description available 0x1000 32 0x00000000 0xFFFFFFFF INTERRUPT The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. 0 32 read-write 4 0x4 TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 TRIGGER[%s] no description available 0x1080 32 0x00000000 0xFFFFFFFF INTERRUPT The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. 0: Level-triggered interrupt 1: Edge-triggered interrupt 0 32 read-only NUMBER Number of supported interrupt sources and targets 0x1100 32 0xFFFFFFFF NUM_TARGET The number of supported targets 16 16 read-only NUM_INTERRUPT The number of supported interrupt sources 0 16 read-only INFO Version and the maximum priority 0x1104 32 0xFFFFFFFF MAX_PRIORITY The maximum priority supported 16 16 read-only VERSION The version of the PLIC design 0 16 read-only 1 0x80 target0 TARGETINT[%s] no description available 0x2000 4 0x4 INTEN0,INTEN1,INTEN2,INTEN3 INTEN[%s] no description available 0x0 32 0x00000000 0xFFFFFFFF INTERRUPT The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. 0 32 read-write 1 0x1000 target0 TARGETCONFIG[%s] no description available 0x200000 THRESHOLD Target0 priority threshold 0x0 32 0x00000000 0xFFFFFFFF THRESHOLD Interrupt priority threshold. 0 32 read-write CLAIM Target claim and complete 0x4 32 0x00000000 0x000003FF INTERRUPT_ID On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). 0 10 read-write PPS Preempted priority stack 0x400 32 0x00000000 0xFFFFFFFF PRIORITY_PREEMPTED Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. 0 32 read-write MCHTMR MCHTMR MCHTMR 0xe6000000 0x0 0x10 registers MTIME Machine Time 0x0 64 0x0000000000020210 0xFFFFFFFFFFFFFFFF MTIME Machine time 0 64 read-write MTIMECMP Machine Time Compare 0x8 64 0x0000000000020210 0xFFFFFFFFFFFFFFFF MTIMECMP Machine time compare 0 64 read-write PLICSW PLICSW PLIC_SW 0xe6400000 0x1000 0x1ff008 registers PENDING Pending status 0x1000 32 0x00000000 0x00000002 INTERRUPT writing 1 to trigger software interrupt 1 1 read-write INTEN Interrupt enable 0x2000 32 0x00000000 0x00000001 INTERRUPT enable software interrupt 0 1 read-write CLAIM Claim and complete. 0x200004 32 0x00000000 0x00000001 INTERRUPT_ID On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). 0 1 read-write GPTMR0 GPTMR0 TMR 0xf0000000 0x0 0x20c registers 4 0x40 ch0,ch1,ch2,ch3 CHANNEL[%s] no description available 0x0 CR Control Register 0x0 32 0x00000000 0x80007FFF CNTUPT 1- update counter to new value as CNTUPTVAL This bit will be auto cleared after 1 cycle 31 1 write-only CNTRST 1- reset counter 14 1 read-write SYNCFLW 1- enable this channel to reset counter to reload(RLD) together with its previous channel. This bit is not valid for channel 0. 13 1 read-write SYNCIFEN 1- SYNCI is valid on its falling edge 12 1 read-write SYNCIREN 1- SYNCI is valid on its rising edge 11 1 read-write CEN 1- counter enable 10 1 read-write CMPINIT Output compare initial poliarity 1- The channel output initial level is high 0- The channel output initial level is low User should set this bit before set CMPEN to 1. 9 1 read-write CMPEN 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. 8 1 read-write DMASEL select one of DMA request: 00- CMP0 flag 01- CMP1 flag 10- Input signal toggle captured 11- RLD flag, counter reload; 6 2 read-write DMAEN 1- enable dma 5 1 read-write SWSYNCIEN 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set 4 1 read-write DBGPAUSE 1- counter will pause if chip is in debug mode 3 1 read-write CAPMODE This bitfield define the input capture mode 100: width measure mode, timer will calculate the input signal period and duty cycle 011: capture at both rising edge and falling edge 010: capture at falling edge 001: capture at rising edge 000: No capture 0 3 read-write 2 0x4 CMP0,CMP1 CMP[%s] no description available 0x4 32 0xFFFFFFF0 0xFFFFFFFF CMP compare value 0 0 32 read-write RLD Reload register 0xc 32 0xFFFFFFFF 0xFFFFFFFF RLD reload value 0 32 read-write CNTUPTVAL Counter update value register 0x10 32 0x00000000 0xFFFFFFFF CNTUPTVAL counter will be set to this value when software write cntupt bit in CR 0 32 read-write CAPPOS Capture rising edge register 0x20 32 0x00000000 0xFFFFFFFF CAPPOS This register contains the counter value captured at input signal rising edge 0 32 read-only CAPNEG Capture falling edge register 0x24 32 0x00000000 0xFFFFFFFF CAPNEG This register contains the counter value captured at input signal falling edge 0 32 read-only CAPPRD PWM period measure register 0x28 32 0x00000000 0xFFFFFFFF CAPPRD This register contains the input signal period when channel is configured to input capture measure mode. 0 32 read-only CAPDTY PWM duty cycle measure register 0x2c 32 0x00000000 0xFFFFFFFF MEAS_HIGH This register contains the input signal duty cycle when channel is configured to input capture measure mode. 0 32 read-only CNT Counter 0x30 32 0x00000000 0xFFFFFFFF COUNTER 32 bit counter value 0 32 read-only SR Status register 0x200 32 0x00000000 0xFFFFFFFF CH3CMP1F channel 3 compare value 1 match flag 15 1 write-only CH3CMP0F channel 3 compare value 1 match flag 14 1 write-only CH3CAPF channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 13 1 write-only CH3RLDF channel 3 counter reload flag 12 1 write-only CH2CMP1F channel 2 compare value 1 match flag 11 1 write-only CH2CMP0F channel 2 compare value 1 match flag 10 1 write-only CH2CAPF channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 9 1 write-only CH2RLDF channel 2 counter reload flag 8 1 write-only CH1CMP1F channel 1 compare value 1 match flag 7 1 write-only CH1CMP0F channel 1 compare value 1 match flag 6 1 write-only CH1CAPF channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 5 1 write-only CH1RLDF channel 1 counter reload flag 4 1 write-only CH0CMP1F channel 1 compare value 1 match flag 3 1 write-only CH0CMP0F channel 1 compare value 1 match flag 2 1 write-only CH0CAPF channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 1 1 write-only CH0RLDF channel 1 counter reload flag 0 1 write-only IRQEN Interrupt request enable register 0x204 32 0x00000000 0xFFFFFFFF CH3CMP1EN 1- generate interrupt request when ch3cmp1f flag is set 15 1 read-write CH3CMP0EN 1- generate interrupt request when ch3cmp0f flag is set 14 1 read-write CH3CAPEN 1- generate interrupt request when ch3capf flag is set 13 1 read-write CH3RLDEN 1- generate interrupt request when ch3rldf flag is set 12 1 read-write CH2CMP1EN 1- generate interrupt request when ch2cmp1f flag is set 11 1 read-write CH2CMP0EN 1- generate interrupt request when ch2cmp0f flag is set 10 1 read-write CH2CAPEN 1- generate interrupt request when ch2capf flag is set 9 1 read-write CH2RLDEN 1- generate interrupt request when ch2rldf flag is set 8 1 read-write CH1CMP1EN 1- generate interrupt request when ch1cmp1f flag is set 7 1 read-write CH1CMP0EN 1- generate interrupt request when ch1cmp0f flag is set 6 1 read-write CH1CAPEN 1- generate interrupt request when ch1capf flag is set 5 1 read-write CH1RLDEN 1- generate interrupt request when ch1rldf flag is set 4 1 read-write CH0CMP1EN 1- generate interrupt request when ch0cmp1f flag is set 3 1 read-write CH0CMP0EN 1- generate interrupt request when ch0cmp0f flag is set 2 1 read-write CH0CAPEN 1- generate interrupt request when ch0capf flag is set 1 1 read-write CH0RLDEN 1- generate interrupt request when ch0rldf flag is set 0 1 read-write GCR Global control register 0x208 32 0x00000000 0x0000000F SWSYNCT set this bitfield to trigger software counter sync event 0 4 read-write GPTMR1 GPTMR1 TMR 0xf0004000 PTMR PTMR TMR 0xf4120000 UART0 UART0 UART 0xf0040000 0x4 0x3c registers IDLE_CFG Idle Configuration Register 0x4 32 0x00000000 0x03FF0BFF TX_IDLE_COND IDLE Detection Condition 0 - Treat as idle if TX pin is logic one 1 - Treat as idle if UART state machine state is idle 25 1 read-write TX_IDLE_EN UART TX Idle Detect Enable 0 - Disable 1 - Enable 24 1 read-write TX_IDLE_THR Threshold for UART transmit Idle detection (in terms of bits) 16 8 read-write RXEN UART receive enable. 0 - hold RX input to high, avoide wrong data input when config pinmux 1 - bypass RX input from PIN software should set it after config pinmux 11 1 read-write RX_IDLE_COND IDLE Detection Condition 0 - Treat as idle if RX pin is logic one 1 - Treat as idle if UART state machine state is idle 9 1 read-write RX_IDLE_EN UART Idle Detect Enable 0 - Disable 1 - Enable it should be enabled if enable address match feature 8 1 read-write RX_IDLE_THR Threshold for UART Receive Idle detection (in terms of bits) 0 8 read-write ADDR_CFG address match config register 0x8 32 0x00000000 0x001FFFFF TXEN_9BIT set to use 9bit mode for transmitter, will set the MSB for the first character as address flag, keep 0 for others. 20 1 read-write RXEN_ADDR_MSB set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). Clr to use first character as address. Only needed if enable address match feature 19 1 read-write RXEN_9BIT set to use 9bit mode for receiver, only valid if rxen_addr_msb is set 18 1 read-write A1_EN enable addr1 compare for the first character. If a1_en OR a0_en, then do not receive data if address not match. If ~a1_en AND ~a0_en, the receive all data like before. NOTE: should set idle_tmout_en if enable address match feature 17 1 read-write A0_EN enable addr0 compare for the first character 16 1 read-write ADDR1 address 1 fileld. in 9bit mode, this is the full address byte. For other mode(8/7/6/5bit), MSB should be set for address flag. If want address==0 to be matched at 8bit mode, should set addr1=0x80 8 8 read-write ADDR0 address 0 field. 0 8 read-write IIR2 Interrupt Identification Register2 0xc 32 0x00000001 0xF80000CF RXIDLE_FLAG UART RX IDLE Flag, assert after rxd high and then rx idle timeout, write one clear 0 - UART RX is busy 1 - UART RX is idle 31 1 write-only TXIDLE_FLAG UART TX IDLE Flag, assert after txd high and then tx idle timeout, write one clear 0 - UART TX is busy 1 - UART TX is idle 30 1 write-only ADDR_MATCH address match irq status, assert if either address match(and enabled). Write one clear NOTE: the address byte may not moved by DMA at this point. User can wait next addr_match_idle irq for the whole data include address 29 1 write-only ADDR_MATCH_IDLE address match and idle irq status, assert at rx bus idle if address match event triggered. Write one clear; 28 1 write-only DATA_LOST assert if data lost before address match status, write one clear; It will not assert if no address match occurs 27 1 write-only FIFOED FIFOs enabled These two bits are 1 when bit 0 of the FIFO Control Register (FIFOE) is set to 1. 6 2 read-only INTRID Interrupt ID, see IIR2 for detail decoding 0 4 read-only Cfg Configuration Register 0x10 32 0x00000000 0xFFFFFFFF FIFOSIZE The depth of RXFIFO and TXFIFO 0: 16-byte FIFO 1: 32-byte FIFO 2: 64-byte FIFO 3: 128-byte FIFO 0 2 read-only OSCR Over Sample Control Register 0x14 32 0x00000010 0x0000001F OSC Over-sample control The value must be an even number; any odd value writes to this field will be converted to an even value. OSC=0: reserved OSC<=8: The over-sample ratio is 8 8 < OSC< 32: The over sample ratio is OSC 0 5 read-write FCRR FIFO Control Register config 0x18 32 0x00000000 0x008F0FFF FIFOT4EN set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) clr to use 2bit(TFIFOT and RFIFOT) 23 1 read-write TFIFOT4 txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold. 16 4 read-write RFIFOT4 rxfifo threshold(0 for 1byte, 0xF for 16bytes). Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled 8 4 read-write RFIFOT Receiver FIFO trigger level 6 2 read-write TFIFOT Transmitter FIFO trigger level 4 2 read-write DMAE DMA enable 0: Disable 1: Enable 3 1 read-write TFIFORST Transmitter FIFO reset Write 1 to clear all bytes in the TXFIFO and resets its counter. The Transmitter Shift Register is not cleared. This bit will automatically be cleared. 2 1 write-only RFIFORST Receiver FIFO reset Write 1 to clear all bytes in the RXFIFO and resets its counter. The Receiver Shift Register is not cleared. This bit will automatically be cleared. 1 1 write-only FIFOE FIFO enable Write 1 to enable both the transmitter and receiver FIFOs. The FIFOs are reset when the value of this bit toggles. 0 1 read-write MOTO_CFG moto system control register 0x1c 32 0x00000000 0x8000FFF0 SWTRG software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. Hardware auto reset. 31 1 write-only TXSTP_BITS if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits 8 8 read-write HWTRG_EN set to enable hardware trigger(trigger from moto is shared by other UART) 7 1 read-write TRG_MODE set to enable trigger mode. software should push needed data into txbuffer frist, uart will not start transmission at this time. User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty NOTE: the hw_trigger should be pulse signal from trig mux. 6 1 read-write TRG_CLR_RFIFO set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo. 5 1 read-write TXSTOP_INSERT set to insert STOP bits between each tx byte till tx fifo empty. NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set 4 1 read-write RBR Receiver Buffer Register (when DLAB = 0) UNION_20 0x20 32 0x00000000 0x000000FF RBR Receive data read port 0 8 read-only THR Transmitter Holding Register (when DLAB = 0) UNION_20 0x20 32 0x00000000 0x000000FF THR Transmit data write port 0 8 write-only DLL Divisor Latch LSB (when DLAB = 1) UNION_20 0x20 32 0x00000001 0x000000FF DLL Least significant byte of the Divisor Latch 0 8 read-write IER Interrupt Enable Register (when DLAB = 0) UNION_24 0x24 32 0x00000000 0xF800000F ERXIDLE Enable Receive Idle interrupt 0 - Disable Idle interrupt 1 - Enable Idle interrupt 31 1 read-write ETXIDLE enable transmit idle interrupt 30 1 read-write EADDRM enable ADDR_MATCH interrupt 29 1 read-write EADDRM_IDLE enable ADDR_MATCH_IDLE interrupt 28 1 read-write EDATLOST enable DATA_LOST interrupt 27 1 read-write EMSI Enable modem status interrupt The interrupt asserts when the status of one of the following occurs: The status of modem_rin, modem_dcdn, modem_dsrn or modem_ctsn (If the auto-cts mode is disabled) has been changed. If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), modem_ctsn would be used to control the transmitter. 3 1 read-write ELSI Enable receiver line status interrupt 2 1 read-write ETHEI Enable transmitter holding register interrupt 1 1 read-write ERBI Enable received data available interrupt and the character timeout interrupt 0: Disable 1: Enable 0 1 read-write DLM Divisor Latch MSB (when DLAB = 1) UNION_24 0x24 32 0x00000000 0x000000FF DLM Most significant byte of the Divisor Latch 0 8 read-write IIR Interrupt Identification Register UNION_28 0x28 32 0x00000001 0x800000CF RXIDLE_FLAG UART IDLE Flag 0 - UART is busy 1 - UART is idle NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR 31 1 write-only FIFOED FIFOs enabled These two bits are 1 when bit 0 of the FIFO Control Register (FIFOE) is set to 1. 6 2 read-only INTRID Interrupt ID, see IIR2 for detail decoding 0 4 read-only FCR FIFO Control Register UNION_28 0x28 32 0x00000000 0x000000FF RFIFOT Receiver FIFO trigger level 6 2 write-only TFIFOT Transmitter FIFO trigger level 4 2 write-only DMAE DMA enable 0: Disable 1: Enable 3 1 write-only TFIFORST Transmitter FIFO reset Write 1 to clear all bytes in the TXFIFO and resets its counter. The Transmitter Shift Register is not cleared. This bit will automatically be cleared. 2 1 write-only RFIFORST Receiver FIFO reset Write 1 to clear all bytes in the RXFIFO and resets its counter. The Receiver Shift Register is not cleared. This bit will automatically be cleared. 1 1 write-only FIFOE FIFO enable Write 1 to enable both the transmitter and receiver FIFOs. The FIFOs are reset when the value of this bit toggles. 0 1 write-only LCR Line Control Register 0x2c 32 0x00000000 0x000000FF DLAB Divisor latch access bit 7 1 read-write BC Break control 6 1 read-write SPS Stick parity 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). 0: Disable the sticky bit parity. 5 1 read-write EPS Even parity select 1: Even parity (an even number of logic-1 is in the data and parity bits) 0: Old parity. 4 1 read-write PEN Parity enable When this bit is set, a parity bit is generated in transmitted data before the first STOP bit and the parity bit would be checked for the received data. 3 1 read-write STB Number of STOP bits 0: 1 bits 1: The number of STOP bit is based on the WLS setting When WLS = 0, STOP bit is 1.5 bits When WLS = 1, 2, 3, STOP bit is 2 bits 2 1 read-write WLS Word length setting 0: 5 bits 1: 6 bits 2: 7 bits 3: 8 bits 0 2 read-write MCR Modem Control Register ( 0x30 32 0x00000000 0x00000032 AFE Auto flow control enable 0: Disable 1: The auto-CTS and auto-RTS setting is based on the RTS bit setting: When RTS = 0, auto-CTS only When RTS = 1, auto-CTS and auto-RTS 5 1 read-write LOOP Enable loopback mode 0: Disable 1: Enable 4 1 read-write RTS Request to send This bit controls the modem_rtsn output. 0: The modem_rtsn output signal will be driven HIGH 1: The modem_rtsn output signal will be driven LOW 1 1 read-write LSR Line Status Register 0x34 32 0x00000000 0xC01F1FFF RXIDLE rxidle after timeout, clear after rx idle condition not match 31 1 read-only TXIDLE txidle after timeout, clear after tx idle condition not match 30 1 read-only RFIFO_NUM data bytes in rxfifo not read 16 5 read-only TFIFO_NUM data bytes in txfifo not sent 8 5 read-only ERRF Error in RXFIFO In the FIFO mode, this bit is set when there is at least one parity error, framing error, or line break associated with data in the RXFIFO. It is cleared when this register is read and there is no more error for the rest of data in the RXFIFO. 7 1 read-only TEMT Transmitter empty This bit is 1 when the THR (TXFIFO in the FIFO mode) and the Transmitter Shift Register (TSR) are both empty. Otherwise, it is zero. 6 1 read-only THRE Transmitter Holding Register empty This bit is 1 when the THR (TXFIFO in the FIFO mode) is empty. Otherwise, it is zero. If the THRE interrupt is enabled, an interrupt is triggered when THRE becomes 1. 5 1 read-only LBREAK Line break This bit is set when the uart_sin input signal was held LOWfor longer than the time for a full-word transmission. A full-word transmission is the transmission of the START, data, parity, and STOP bits. It is cleared when this register is read. In the FIFO mode, this bit indicates the line break for the received data at the top of the RXFIFO. 4 1 read-only FE Framing error This bit is set when the received STOP bit is not HIGH. It is cleared when this register is read. In the FIFO mode, this bit indicates the framing error for the received data at the top of the RXFIFO. 3 1 read-only PE Parity error This bit is set when the received parity does not match with the parity selected in the LCR[5:4]. It is cleared when this register is read. In the FIFO mode, this bit indicates the parity error for the received data at the top of the RXFIFO. 2 1 read-only OE Overrun error This bit indicates that data in the Receiver Buffer Register (RBR) is overrun. 1 1 read-only DR Data ready. This bit is set when there are incoming received data in the Receiver Buffer Register (RBR). It is cleared when all of the received data are read. 0 1 read-only MSR Modem Status Register 0x38 32 0x00000000 0x00000011 CTS Clear to send 0: The modem_ctsn input signal is HIGH. 1: The modem_ctsn input signal is LOW. 4 1 read-only DCTS Delta clear to send This bit is set when the state of the modem_ctsn input signal has been changed since the last time this register is read. 0 1 read-only GPR GPR Register 0x3c 32 0x00000000 0x000000FF DATA A one-byte storage register 0 8 read-write UART1 UART1 UART 0xf0044000 UART2 UART2 UART 0xf0048000 UART3 UART3 UART 0xf004c000 PUART PUART UART 0xf4124000 I2C0 I2C0 I2C 0xf0060000 0x4 0x30 registers Cfg Configuration Register 0x10 32 0x00000001 0xFFFFFFFF FIFOSIZE FIFO Size: 0: 2 bytes 1: 4 bytes 2: 8 bytes 3: 16 bytes 0 2 read-only IntEn Interrupt Enable Register 0x14 32 0x00000000 0xFFFFFFFF CMPL Set to enable the Completion Interrupt. Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. Slave: interrupts when a transaction addressing the controller is completed. 9 1 read-write BYTERECV Set to enable the Byte Receive Interrupt. Interrupts when a byte of data is received Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. 8 1 read-write BYTETRANS Set to enable the Byte Transmit Interrupt. Interrupts when a byte of data is transmitted. 7 1 read-write START Set to enable the START Condition Interrupt. Interrupts when a START condition/repeated START condition is detected. 6 1 read-write STOP Set to enable the STOP Condition Interrupt Interrupts when a STOP condition is detected. 5 1 read-write ARBLOSE Set to enable the Arbitration Lose Interrupt. Master: interrupts when the controller loses the bus arbitration Slave: not available in this mode. 4 1 read-write ADDRHIT Set to enable the Address Hit Interrupt. Master: interrupts when the addressed slave returned an ACK. Slave: interrupts when the controller is addressed. 3 1 read-write FIFOHALF Set to enable the FIFO Half Interrupt. Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. 2 1 read-write FIFOFULL Set to enable the FIFO Full Interrupt. Interrupts when the FIFO is full. 1 1 read-write FIFOEMPTY Set to enabled the FIFO Empty Interrupt Interrupts when the FIFO is empty. 0 1 read-write Status Status Register 0x18 32 0x00000001 0xFFFFFFFF LINESDA Indicates the current status of the SDA line on the bus 1: high 0: low 14 1 read-only LINESCL Indicates the current status of the SCL line on the bus 1: high 0: low 13 1 read-only GENCALL Indicates that the address of the current transaction is a general call address: 1: General call 0: Not general call 12 1 read-only BUSBUSY Indicates that the bus is busy The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus 1: Busy 0: Not busy 11 1 read-only ACK Indicates the type of the last received/transmitted acknowledgement bit: 1: ACK 0: NACK 10 1 read-only CMPL Transaction Completion Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. 9 1 write-only BYTERECV Indicates that a byte of data has been received. 8 1 write-only BYTETRANS Indicates that a byte of data has been transmitted. 7 1 write-only START Indicates that a START Condition or a repeated START condition has been transmitted/received. 6 1 write-only STOP Indicates that a STOP Condition has been transmitted/received. 5 1 write-only ARBLOSE Indicates that the controller has lost the bus arbitration. 4 1 write-only ADDRHIT Master: indicates that a slave has responded to the transaction. Slave: indicates that a transaction is targeting the controller (including the General Call). 3 1 write-only FIFOHALF Transmitter: Indicates that the FIFO is half-empty. 2 1 read-only FIFOFULL Indicates that the FIFO is full. 1 1 read-only FIFOEMPTY Indicates that the FIFO is empty. 0 1 read-only Addr Address Register 0x1c 32 0x00000000 0xFFFFFFFF ADDR The slave address. For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid 0 10 read-write Data Data Register 0x20 32 0x00000000 0xFFFFFFFF DATA Write this register to put one byte of data to the FIFO. Read this register to get one byte of data from the FIFO. 0 8 read-write Ctrl Control Register 0x24 32 0x00905E00 0xFFFFFFFF DATACNT_HIGH Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. 24 8 read-write RESET_LEN reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. 20 4 read-write RESET_HOLD_SCKIN set to hold input clock to high when reset is active 14 1 read-write RESET_ON set to send reset signals(just toggle clock bus defined by reset_len). this register is clered when reset is end, can't be cleared by software 13 1 read-write PHASE_START Enable this bit to send a START condition at the beginning of transaction. Master mode only. 12 1 read-write PHASE_ADDR Enable this bit to send the address after START condition. Master mode only. 11 1 read-write PHASE_DATA Enable this bit to send the data after Address phase. Master mode only. 10 1 read-write PHASE_STOP Enable this bit to send a STOP condition at the end of a transaction. Master mode only. 9 1 read-write DIR Transaction direction Master: Set this bit to determine the direction for the next transaction. 0: Transmitter 1: Receiver Slave: The direction of the last received transaction. 0: Receiver 1: Transmitter 8 1 read-write DATACNT Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. 0 8 read-write Cmd Command Register 0x28 32 0x00000000 0xFFFFFFFF CMD Write this register with the following values to perform the corresponding actions: 0x0: no action 0x1: issue a data transaction (Master only) 0x2: respond with an ACK to the received byte 0x3: respond with a NACK to the received byte 0x4: clear the FIFO 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. 0 3 read-write Setup Setup Register 0x2c 32 0x05252100 0xFFFFFFFF T_SUDAT T_SUDAT defines the data setup time before releasing the SCL. Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) tpclk = PCLK period TPM = The multiplier value in Timing Parameter Multiplier Register 24 5 read-write T_SP T_SP defines the pulse width of spikes that must be suppressed by the input filter. Pulse width = T_SP * tpclk* (TPM+1) 21 3 read-write T_HDDAT T_HDDAT defines the data hold time after SCL goes LOW Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) 16 5 read-write T_SCLRADIO The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) 1: ratio = 2 0: ratio = 1 This field is only valid when the controller is in the master mode. 13 1 read-write T_SCLHI The HIGH period of generated SCL clock is defined by T_SCLHi. SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) The T_SCLHi value must be greater than T_SP and T_HDDAT values. This field is only valid when the controller is in the master mode. 4 9 read-write DMAEN Enable the direct memory access mode data transfer. 1: Enable 0: Disable 3 1 read-write MASTER Configure this device as a master or a slave. 1: Master mode 0: Slave mode 2 1 read-write ADDRESSING I2C addressing mode: 1: 10-bit addressing mode 0: 7-bit addressing mode 1 1 read-write IICEN Enable the I2C controller. 1: Enable 0: Disable 0 1 read-write TPM I2C Timing Paramater Multiplier 0x30 32 0x00000000 0xFFFFFFFF TPM A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). 0 5 read-write I2C1 I2C1 I2C 0xf0064000 I2C2 I2C2 I2C 0xf0068000 I2C3 I2C3 I2C 0xf006c000 SPI0 SPI0 SPI 0xf0070000 0x4 0x7c registers wr_trans_cnt Transfer count for write data 0x4 32 0x00000000 0xFFFFFFFF WRTRANCNT Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt. 0 32 read-write rd_trans_cnt Transfer count for read data 0x8 32 0x00000000 0xFFFFFFFF RDTRANCNT Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt. 0 32 read-write TransFmt Transfer Format Register 0x10 32 0x00020780 0xFFFF1F9F ADDRLEN Address length in bytes 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: 4 bytes 16 2 read-write DATALEN The length of each data unit in bits The actual bit number of a data unit is (DataLen + 1) 8 5 read-write DATAMERGE Enable Data Merge mode, which does automatic data split on write and data coalescing on read. This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. 7 1 read-write MOSIBIDIR Bi-directional MOSI in regular (single) mode 0x0: MOSI is uni-directional signal in regular mode. 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two 4 1 read-write LSB Transfer data with the least significant bit first 0x0: Most significant bit first 0x1: Least significant bit first 3 1 read-write SLVMODE SPI Master/Slave mode selection 0x0: Master mode 0x1: Slave mode 2 1 read-write CPOL SPI Clock Polarity 0x0: SCLK is LOW in the idle states 0x1: SCLK is HIGH in the idle states 1 1 read-write CPHA SPI Clock Phase 0x0: Sampling data at odd SCLK edges 0x1: Sampling data at even SCLK edges 0 1 read-write DirectIO Direct IO Control Register 0x14 32 0x00003100 0x013F3F3F DIRECTIOEN Enable Direct IO 0x0: Disable 0x1: Enable 24 1 read-write HOLD_OE Output enable for the SPI Flash hold signal 21 1 read-write WP_OE Output enable for the SPI Flash write protect signal 20 1 read-write MISO_OE Output enable fo the SPI MISO signal 19 1 read-write MOSI_OE Output enable for the SPI MOSI signal 18 1 read-write SCLK_OE Output enable for the SPI SCLK signal 17 1 read-write CS_OE Output enable for SPI CS (chip select) signal 16 1 read-write HOLD_O Output value for the SPI Flash hold signal 13 1 read-write WP_O Output value for the SPI Flash write protect signal 12 1 read-write MISO_O Output value for the SPI MISO signal 11 1 read-write MOSI_O Output value for the SPI MOSI signal 10 1 read-write SCLK_O Output value for the SPI SCLK signal 9 1 read-write CS_O Output value for the SPI CS (chip select) signal 8 1 read-write HOLD_I Status of the SPI Flash hold signal 5 1 read-only WP_I Status of the SPI Flash write protect signal 4 1 read-only MISO_I Status of the SPI MISO signal 3 1 read-only MOSI_I Status of the SPI MOSI signal 2 1 read-only SCLK_I Status of the SPI SCLK signal 1 1 read-only CS_I Status of the SPI CS (chip select) signal 0 1 read-only TransCtrl Transfer Control Register 0x20 32 0x00000000 0xFFFFFFFF SLVDATAONLY Data-only mode (slave mode only) 0x0: Disable the data-only mode 0x1: Enable the data-only mode Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. 31 1 read-write CMDEN SPI command phase enable (Master mode only) 0x0: Disable the command phase 0x1: Enable the command phase 30 1 read-write ADDREN SPI address phase enable (Master mode only) 0x0: Disable the address phase 0x1: Enable the address phase 29 1 read-write ADDRFMT SPI address phase format (Master mode only) 0x0: Address phase is the regular (single) mode 0x1: The format of the address phase is the same as the data phase (DualQuad). 28 1 read-write TRANSMODE Transfer mode The transfer sequence could be 0x0: Write and read at the same time 0x1: Write only 0x2: Read only 0x3: Write, Read 0x4: Read, Write 0x5: Write, Dummy, Read 0x6: Read, Dummy, Write 0x7: None Data (must enable CmdEn or AddrEn in master mode) 0x8: Dummy, Write 0x9: Dummy, Read 0xa~0xf: Reserved 24 4 read-write DUALQUAD SPI data phase format 0x0: Regular (Single) mode 0x1: Dual I/O mode 0x2: Quad I/O mode 0x3: Reserved 22 2 read-write TOKENEN Token transfer enable (Master mode only) Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. 0x0: Disable the one-byte special token 0x1: Enable the one-byte special token 21 1 read-write WRTRANCNT Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt. 12 9 read-write TOKENVALUE Token value (Master mode only) The value of the one-byte special token following the address phase for SPI read transfers. 0x0: token value = 0x00 0x1: token value = 0x69 11 1 read-write DUMMYCNT Dummy data count. The actual dummy count is (DummyCnt +1). The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) The Data pins are put into the high impedance during the dummy data phase. DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. 9 2 read-write RDTRANCNT Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt. 0 9 read-write Cmd Command Register 0x24 32 0x00000000 0x000000FF CMD SPI Command 0 8 read-write Addr Address Register 0x28 32 0x00000000 0xFFFFFFFF ADDR SPI Address (Master mode only) 0 32 read-write Data Data Register 0x2c 32 0x00000000 0xFFFFFFFF DATA Data to transmit or the received data For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. 0 32 read-write Ctrl Control Register 0x30 32 0x00000000 0x0FFFFF1F CS_EN No description available 24 4 read-write TXTHRES Transmit (TX) FIFO Threshold The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. 16 8 read-write RXTHRES Receive (RX) FIFO Threshold The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. 8 8 read-write TXDMAEN TX DMA enable 4 1 read-write RXDMAEN RX DMA enable 3 1 read-write TXFIFORST Transmit FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. 2 1 read-write RXFIFORST Receive FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. 1 1 read-write SPIRST SPI reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. 0 1 read-write Status Status Register 0x34 32 0x00000000 0x33FFFF01 TXNUM_7_6 Number of valid entries in the Transmit FIFO 28 2 read-only RXNUM_7_6 Number of valid entries in the Receive FIFO 24 2 read-only TXFULL Transmit FIFO Full flag 23 1 read-only TXEMPTY Transmit FIFO Empty flag 22 1 read-only TXNUM_5_0 Number of valid entries in the Transmit FIFO 16 6 read-only RXFULL Receive FIFO Full flag 15 1 read-only RXEMPTY Receive FIFO Empty flag 14 1 read-only RXNUM_5_0 Number of valid entries in the Receive FIFO 8 6 read-only SPIACTIVE SPI register programming is in progress. In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. 0 1 read-only IntrEn Interrupt Enable Register 0x38 32 0x00000000 0x0000003F SLVCMDEN Enable the Slave Command Interrupt. Control whether interrupts are triggered whenever slave commands are received. (Slave mode only) 5 1 read-write ENDINTEN Enable the End of SPI Transfer interrupt. Control whether interrupts are triggered when SPI transfers end. (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) 4 1 read-write TXFIFOINTEN Enable the SPI Transmit FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. 3 1 read-write RXFIFOINTEN Enable the SPI Receive FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. 2 1 read-write TXFIFOURINTEN Enable the SPI Transmit FIFO Underrun interrupt. Control whether interrupts are triggered when the Transmit FIFO run out of data. (Slave mode only) 1 1 read-write RXFIFOORINTEN Enable the SPI Receive FIFO Overrun interrupt. Control whether interrupts are triggered when the Receive FIFO overflows. (Slave mode only) 0 1 read-write IntrSt Interrupt Status Register 0x3c 32 0x00000000 0x0000003F SLVCMDINT Slave Command Interrupt. This bit is set when Slave Command interrupts occur. (Slave mode only) 5 1 write-only ENDINT End of SPI Transfer interrupt. This bit is set when End of SPI Transfer interrupts occur. 4 1 write-only TXFIFOINT TX FIFO Threshold interrupt. This bit is set when TX FIFO Threshold interrupts occur. 3 1 write-only RXFIFOINT RX FIFO Threshold interrupt. This bit is set when RX FIFO Threshold interrupts occur. 2 1 write-only TXFIFOURINT TX FIFO Underrun interrupt. This bit is set when TX FIFO Underrun interrupts occur. (Slave mode only) 1 1 write-only RXFIFOORINT RX FIFO Overrun interrupt. This bit is set when RX FIFO Overrun interrupts occur. (Slave mode only) 0 1 write-only Timing Interface Timing Register 0x40 32 0x00000000 0x00003FFF CS2SCLK The minimum time between the edges of SPI CS and the edges of SCLK. SCLK_period * (CS2SCLK + 1) / 2 12 2 read-write CSHT The minimum time that SPI CS should stay HIGH. SCLK_period * (CSHT + 1) / 2 8 4 read-write SCLK_DIV The clock frequency ratio between the clock source and SPI interface SCLK. SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. 0 8 read-write SlvSt Slave Status Register 0x60 32 0x00000000 0x0007FFFF UNDERRUN Data underrun occurs in the last transaction 18 1 write-only OVERRUN Data overrun occurs in the last transaction 17 1 read-write READY Set this bit to indicate that the ATCSPI200 is ready for data transaction. When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. 16 1 read-write USR_STATUS User defined status flags 0 16 read-write SlvDataCnt Slave Data Count Register 0x64 32 0x00000000 0x03FF03FF WCNT Slave transmitted data count 16 10 read-only RCNT Slave received data count 0 10 read-only SlvDataWCnt WCnt 0x68 32 0x00000000 0xFFFFFFFF VAL No description available 0 32 read-only SlvDataRCnt RCnt 0x6c 32 0x00000000 0xFFFFFFFF VAL No description available 0 32 read-only Config Configuration Register 0x7c 32 0x00004311 0x000043FF SLAVE Support for SPI Slave mode 14 1 read-only QUADSPI Support for Quad I/O SPI 9 1 read-only DUALSPI Support for Dual I/O SPI 8 1 read-only TXFIFOSIZE Depth of TX FIFO 0x0: 2 words 0x1: 4 words 0x2: 8 words 0x3: 16 words 0x4: 32 words 0x5: 64 words 0x6: 128 words 4 4 read-only RXFIFOSIZE Depth of RX FIFO 0x0: 2 words 0x1: 4 words 0x2: 8 words 0x3: 16 words 0x4: 32 words 0x5: 64 words 0x6: 128 words 0 4 read-only SPI1 SPI1 SPI 0xf0074000 SPI2 SPI2 SPI 0xf0078000 SPI3 SPI3 SPI 0xf007c000 CRC CRC CRC 0xf0080000 0x0 0x200 registers 8 0x40 0,1,2,3,4,5,6,7 CHN[%s] no description available 0x0 pre_set &index0 pre set for crc setting 0x0 32 0x00000000 0x000000FF PRE_SET 0: no pre set 1: CRC32 2: CRC32-AUTOSAR 3: CRC16-CCITT 4: CRC16-XMODEM 5: CRC16-MODBUS 1: CRC32 2: CRC32-autosar 3: CRC16-ccitt 4: CRC16-xmodem 5: CRC16-modbus 6: crc16_dnp 7: crc16_x25 8: crc16_usb 9: crc16_maxim 10: crc16_ibm 11: crc8_maxim 12: crc8_rohc 13: crc8_itu 14: crc8 15: crc5_usb 0 8 read-write clr chn&index0 clear crc result and setting 0x4 32 0x00000000 0x00000001 CLR write 1 to clr crc setting and result for its channel. always read 0. 0 1 read-write poly chn&index0 poly 0x8 32 0x00000000 0xFFFFFFFF POLY poly setting 0 32 read-write init_data chn&index0 init_data 0xc 32 0x00000000 0xFFFFFFFF INIT_DATA initial data of CRC 0 32 read-write xorout chn&index0 xorout 0x10 32 0x00000000 0xFFFFFFFF XOROUT XOR for CRC result 0 32 read-write misc_setting chn&index0 misc_setting 0x14 32 0x00000000 0x0101013F BYTE_REV 0: no wrap input byte order 1: wrap input byte order 24 1 read-write REV_OUT 0: no wrap output bit order 1: wrap output bit order 16 1 read-write REV_IN 0: no wrap input bit order 1: wrap input bit order 8 1 read-write POLY_WIDTH crc data length 0 6 read-write data chn&index0 data 0x18 32 0x00000000 0xFFFFFFFF DATA data for crc 0 32 read-write result chn&index0 result 0x1c 32 0x00000000 0xFFFFFFFF RESULT crc result 0 32 read-write TSNS TSNS TSNS 0xf0090000 0x0 0x3c registers T Temperature 0x0 32 0x00000000 0xFFFFFFFF T Signed number of temperature in 256 x celsius degree 0 32 read-only TMAX Maximum Temperature 0x4 32 0xFF800000 0xFFFFFFFF T maximum temperature ever found 0 32 read-only TMIN Minimum Temperature 0x8 32 0x007FFFFF 0xFFFFFFFF T minimum temperature ever found 0 32 read-only AGE Sample age 0xc 32 0x00000000 0xFFFFFFFF AGE age of T register in 24MHz clock cycles 0 32 read-only STATUS Status 0x10 32 0x00000000 0x80000001 VALID indicate value in T is valid or not 0: not valid 1:valid 31 1 read-only TRIGGER Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode 0 1 write-only CONFIG Configuration 0x14 32 0x00600300 0xC3FF0713 IRQ_EN Enable interrupt 31 1 read-write RST_EN Enable reset 30 1 read-write COMPARE_MIN_EN Enable compare for minimum temperature 25 1 read-write COMPARE_MAX_EN Enable compare for maximum temperature 24 1 read-write SPEED cycles of a progressive step in 24M clock, valid from 24-255, default 96 24: 24 cycle for a step 25: 25 cycle for a step 26: 26 cycle for a step ... 255: 255 cycle for a step 16 8 read-write AVERAGE Average time, default in 3 0: measure and return 1: twice and average 2: 4 times and average . . . 7: 128 times and average 8 3 read-write CONTINUOUS continuous mode that keep sampling temperature peridically 0: trigger mode 1: continuous mode 4 1 read-write ASYNC Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value 0: active mode 1: Async mode 1 1 read-write ENABLE Enable temperature 0: disable, temperature sensor is shut down 1: enable. Temperature sensor enabled 0 1 read-write VALIDITY Sample validity 0x18 32 0x016E3600 0xFFFFFFFF VALIDITY time for temperature values to expire in 24M clock cycles 0 32 read-write FLAG Temperature flag 0x1c 32 0x00000000 0x00330001 RECORD_MIN_CLR Clear minimum recorder of temerature, write 1 to clear 21 1 read-write RECORD_MAX_CLR Clear maximum recorder of temerature, write 1 to clear 20 1 read-write UNDER_TEMP Clear under temperature status, write 1 to clear 17 1 read-write OVER_TEMP Clear over temperature status, write 1 to clear 16 1 read-write IRQ IRQ flag, write 1 to clear 0 1 read-write UPPER_LIM_IRQ Maximum temperature to interrupt 0x20 32 0x00000000 0xFFFFFFFF T Maximum temperature for compare 0 32 read-write LOWER_LIM_IRQ Minimum temperature to interrupt 0x24 32 0x00000000 0xFFFFFFFF T Minimum temperature for compare 0 32 read-write UPPER_LIM_RST Maximum temperature to reset 0x28 32 0x00000000 0xFFFFFFFF T Maximum temperature for compare 0 32 read-write LOWER_LIM_RST Minimum temperature to reset 0x2c 32 0x00000000 0xFFFFFFFF T Minimum temperature for compare 0 32 read-write ASYNC Configuration in asynchronous mode 0x30 32 0x00000000 0x010107FF ASYNC_TYPE Compare hotter than or colder than in asynchoronous mode 0: hotter than 1: colder than 24 1 read-write POLARITY Polarity of internal comparator 16 1 read-write VALUE Value of async mode to compare 0 11 read-write ADVAN Advance configuration 0x38 32 0x00000000 0x03010003 ASYNC_IRQ interrupt status of asynchronous mode 25 1 read-only ACTIVE_IRQ interrupt status of active mode 24 1 read-only SAMPLING temperature sampling is working 16 1 read-only NEG_ONLY use negative compare polarity only 1 1 read-write POS_ONLY use positive compare polarity only 0 1 read-write MBX0A MBX0A MBX 0xf00a0000 0x0 0x24 registers CR Command Registers 0x0 32 0x00000000 0xFFFFFFFF TXRESET Reset TX Fifo and word. 31 1 read-write BARCTL Bus Access Response Control, when bit 15:14= 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. 11: reserved. 14 2 read-write BEIE Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. 1, enable the bus access error interrupt. 0, disable the bus access error interrupt. 8 1 read-write TFMAIE TX FIFO message available interrupt enable. 1, enable the TX FIFO massage available interrupt. 0, disable the TX FIFO message available interrupt. 7 1 read-write TFMEIE TX FIFO message empty interrupt enable. 1, enable the TX FIFO massage empty interrupt. 0, disable the TX FIFO message empty interrupt. 6 1 read-write RFMAIE RX FIFO message available interrupt enable. 1, enable the RX FIFO massage available interrupt. 0, disable the RX FIFO message available interrupt. 5 1 read-write RFMFIE RX fifo message full interrupt enable. 1, enable the RX fifo message full interrupt. 0, disable the RX fifo message full interrupt. 4 1 read-write TWMEIE TX word message empty interrupt enable. 1, enable the TX word massage empty interrupt. 0, disable the TX word message empty interrupt. 1 1 read-write RWMVIE RX word message valid interrupt enable. 1, enable the RX word massage valid interrupt. 0, disable the RX word message valid interrupt. 0 1 read-write SR Status Registers 0x4 32 0x000000E2 0xFFFF3FFF RFVC RX FIFO valid message count 20 4 read-only TFEC TX FIFO empty message word count 16 4 read-only ERRRE bus Error for read when rx word message are still invalid, this bit is W1C bit. 1, read from word message when the word message are still invalid will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 13 1 write-only EWTRF bus Error for write when tx word message are still valid, this bit is W1C bit. 1, write to word message when the word message are still valid will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 12 1 write-only ERRFE bus Error for read when rx fifo empty, this bit is W1C bit. 1, read from a empty rx fifo will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 11 1 write-only EWTFF bus Error for write when tx fifo full, this bit is W1C bit. 1, write to a fulled tx fifo will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 10 1 write-only EAIVA bus Error for Accessing Invalid Address; this bit is W1C bit. 1, read and write to invalid address in the bus of this block, will set this bit. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 9 1 write-only EW2RO bus Error for Write to Read Only address; this bit is W1C bit. 1, write to read only address happened in the bus of this block. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 8 1 write-only TFMA TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. 1, TXFIFO message buffer has slot available 0, no slot available (fifo full) 7 1 read-write TFME TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. 1, no any message data in TXFIFO from other core. 0, there are some data in the 4x32 TX FIFO from other core yet. 6 1 read-write RFMA RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, no any data in the 4x32 TXFIFO message buffer. 0, there are some data in the the 4x32 TXFIFO message buffer already. 5 1 read-only RFMF RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, the other core had written 4x32 message in the RXFIFO. 0, no 4x32 RX FIFO message from other core yet. 4 1 read-only TWME TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, means this core had write word message to TXREG. 0, means no valid word message in the TXREG yet. 1 1 read-only RWMV RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, the other core had written word message in the RXREG. 0, no valid word message yet in the RXREG. 0 1 read-only TXREG Transmit word message to other core. 0x8 32 0x00000000 0xFFFFFFFF TXREG Transmit word message to other core. 0 32 write-only RXREG Receive word message from other core. 0xc 32 0x00000000 0xFFFFFFFF RXREG Receive word message from other core. 0 32 read-only 1 0x4 TXFIFO0 TXWRD[%s] no description available 0x10 32 0x00000000 0xFFFFFFFF TXFIFO TXFIFO for sending message to other core, FIFO size, 4x32 can write one of the word address to push data to the FIFO; can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. 0 32 write-only 1 0x4 RXFIFO0 RXWRD[%s] no description available 0x20 32 0x00000000 0xFFFFFFFF RXFIFO RXFIFO for receiving message from other core, FIFO size, 4x32 can read one of the word address to pop data to the FIFO; can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. 0 32 read-only MBX0B MBX0B MBX 0xf00a4000 EWDG0 EWDG0 EWDG 0xf00b0000 0x0 0x28 registers CTRL0 wdog ctrl register 0 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits 0x0 32 0x00000000 0x2FE2F03F CLK_SEL clock select 0：bus clock 1：ext clock 29 1 read-write DIV_VALUE clock divider, the clock divider works as 2 ^ div_value for wdt counter 25 3 read-write WIN_EN window mode enable 24 1 read-write WIN_LOWER Once window mode is opened, the lower counter value to refresh wdt 00: 4/8 overtime value 01: 5/8 of overtime value 10: 6/8 of overtime value 11: 7/8 of overtime value 22 2 read-write CFG_LOCK The register is locked and unlock is needed before re-config registers Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. The register update needs to be finished in the required period defined by UPD_OT_TIME register 21 1 read-write OT_SELF_CLEAR overtime reset can be self released after 32 function cycles 17 1 read-write REF_OT_REQ If refresh event has to be limited into a period after refresh unlocked. Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter 15 1 read-write WIN_UPPER The upper threshold of window value The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value If this register value is zero, then no upper level limitation 12 3 read-write REF_LOCK WDT refresh has to be unlocked firstly once refresh lock is enable. 5 1 read-write REF_UNLOCK_MEC Unlock refresh mechanism 00: the required unlock password is the same with refresh_psd_register 01: the required unlock password is a ring shift left value of refresh_psd_register 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 3 2 read-write EN_DBG WTD enable or not in debug mode 2 1 read-write EN_LP WDT enable or not in low power mode 2'b00: wdt is halted once in low power mode 2'b01: wdt will work with 1/4 normal clock freq in low power mode 2'b10: wdt will work with 1/2 normal clock freq in low power mode 2'b11: wdt will work with normal clock freq in low power mode 0 2 read-write CTRL1 wdog ctrl register 1 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits 0x4 32 0x00000000 0x00F300FC REF_FAIL_RST_EN Refresh violation will trigger an reset. These event will be taken as a refresh violation: 1) Not refresh in the window once window mode is enabled 2) Not unlock refresh firstly if unlock is required 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. 4) Not write the required word to refresh wdt. 23 1 read-write REF_FAIL_INT_EN Refresh violation will trigger an interrupt 22 1 read-write UNL_REF_FAIL_RST_EN Refresh unlock fail will trigger a reset 21 1 read-write UNL_REF_FAIL_INT_EN Refresh unlock fail will trigger a interrupt 20 1 read-write OT_RST_EN WDT overtime will generate a reset 17 1 read-write OT_INT_EN WDT can generate an interrupt warning before timeout 16 1 read-write CTL_VIO_RST_EN Ctrl update violation will trigger a reset The violation event is to try updating the locked register before unlock them 7 1 read-write CTL_VIO_INT_EN Ctrl update violation will trigger a interrupt 6 1 read-write UNL_CTL_FAIL_RST_EN Unlock register update failure will trigger a reset 5 1 read-write UNL_CTL_FAIL_INT_EN Unlock register update failure will trigger a interrupt 4 1 read-write PARITY_FAIL_RST_EN Parity error will trigger a reset A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits 3 1 read-write PARITY_FAIL_INT_EN Parity error will trigger a interrupt 2 1 read-write OT_INT_VAL wdog timeout interrupt counter value 0x8 32 0x00000000 0x0000FFFF OT_INT_VAL WDT timeout interrupt value 0 16 read-write OT_RST_VAL wdog timeout reset counter value 0xc 32 0x00000000 0x0000FFFF OT_RST_VAL WDT timeout reset value 0 16 read-write WDT_REFRESH_REG wdog refresh register 0x10 32 0x00000000 0xFFFFFFFF WDT_REFRESH_REG Write this register by 32'h5A45_524F to refresh wdog Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose 0 32 write-only WDT_STATUS wdog status register 0x14 32 0x00000000 0x0000007F PARITY_ERROR parity error Write one to clear the bit 6 1 read-write OT_RST Timeout happens, a reset will happen once enable bit set This bit can be cleared only by refreshing wdt or reset 5 1 read-only OT_INT Timeout happens, a interrupt will happen once enable bit set This bit can be cleared only by refreshing wdt or reset 4 1 read-only CTL_UNL_FAIL Unlock ctrl reg update protection fail Write one to clear the bit 3 1 read-write CTL_VIO Violate register update protection mechanism Write one to clear the bit 2 1 read-write REF_UNL_FAIL Refresh unlock fail Write one to clear the bit 1 1 read-write REF_VIO Refresh fail Write one to clear the bit 0 1 read-write CFG_PROT ctrl register protection register 0x18 32 0x00000000 0x000FFFFF UPD_OT_TIME The period in which register update has to be in after unlock The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle 16 4 read-write UPD_PSD The password of unlocking register update 0 16 read-write REF_PROT refresh protection register 0x1c 32 0x00000000 0x0000FFFF REF_UNL_PSD The password to unlock refreshing 0 16 read-write WDT_EN Wdog enable 0x20 32 0x00000000 0x00000001 WDOG_EN Wdog is enabled, the re-written of this register is impacted by enable lock function 0 1 read-write REF_TIME Refresh period value 0x24 32 0x00000000 0x0000FFFF REFRESH_PERIOD The refresh period after refresh unlocked Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter 0 16 read-write EWDG1 EWDG1 EWDG 0xf00b4000 PEWDG PEWDG EWDG 0xf4128000 DMAMUX DMAMUX DMAMUX 0xf00c4000 0x0 0x80 registers 32 0x4 HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,HDMA_MUX8,HDMA_MUX9,HDMA_MUX10,HDMA_MUX11,HDMA_MUX12,HDMA_MUX13,HDMA_MUX14,HDMA_MUX15,HDMA_MUX16,HDMA_MUX17,HDMA_MUX18,HDMA_MUX19,HDMA_MUX20,HDMA_MUX21,HDMA_MUX22,HDMA_MUX23,HDMA_MUX24,HDMA_MUX25,HDMA_MUX26,HDMA_MUX27,HDMA_MUX28,HDMA_MUX29,HDMA_MUX30,HDMA_MUX31 MUXCFG[%s] no description available 0x0 32 0x00000000 0x8000007F ENABLE DMA Mux Channel Enable Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0b - DMA Mux channel is disabled 1b - DMA Mux channel is enabled 31 1 write-only SOURCE DMA Channel Source Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" 0 7 write-only HDMA HDMA DMAV2 0xf00c8000 0x4 0x43c registers IDMisc ID Misc 0x4 32 0x00000000 0x0000FF00 DMASTATE DMA state machine localparam ST_IDLE = 3'b000; localparam ST_READ = 3'b001; localparam ST_READ_ACK = 3'b010; localparam ST_WRITE = 3'b011; localparam ST_WRITE_ACK = 3'b100; localparam ST_LL = 3'b101; localparam ST_END = 3'b110; localparam ST_END_WAIT = 3'b111; 13 3 read-only CURCHAN current channel in used 8 5 read-only DMACfg DMAC Configuration Register 0x10 32 0x00000000 0xC3FFFFFF CHAINXFR Chain transfer 0x0: Chain transfer is not configured 0x1: Chain transfer is configured 31 1 read-only REQSYNC DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. 0x0: Request synchronization is not configured 0x1: Request synchronization is configured 30 1 read-only DATAWIDTH AXI bus data width 0x0: 32 bits 0x1: 64 bits 0x2: 128 bits 0x3: 256 bits 24 2 read-only ADDRWIDTH AXI bus address width 0x18: 24 bits 0x19: 25 bits ... 0x40: 64 bits Others: Invalid 17 7 read-only CORENUM DMA core number 0x0: 1 core 0x1: 2 cores 16 1 read-only BUSNUM AXI bus interface number 0x0: 1 AXI bus 0x1: 2 AXI busses 15 1 read-only REQNUM Request/acknowledge pair number 0x0: 0 pair 0x1: 1 pair 0x2: 2 pairs ... 0x10: 16 pairs 10 5 read-only FIFODEPTH FIFO depth 0x4: 4 entries 0x8: 8 entries 0x10: 16 entries 0x20: 32 entries Others: Invalid 4 6 read-only CHANNELNUM Channel number 0x1: 1 channel 0x2: 2 channels ... 0x8: 8 channels Others: Invalid 0 4 read-only DMACtrl DMAC Control Register 0x14 32 0x00000000 0x00000001 RESET Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. Note: The software reset may cause the in-completion of AXI transaction. 0 1 write-only ChAbort Channel Abort Register 0x18 32 0x00000000 0xFFFFFFFF CHABORT Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) 0 32 write-only INTHALFSTS Harlf Complete Interrupt Status 0x24 32 0x00000000 0xFFFFFFFF STS half transfer done irq status 0 32 read-write INTTCSTS Trans Complete Interrupt Status Register 0x28 32 0x00000000 0xFFFFFFFF STS The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. 0x0: Channel n has no terminal count status 0x1: Channel n has terminal count status 0 32 write-only INTABORTSTS Abort Interrupt Status Register 0x2c 32 0x00000000 0xFFFFFFFF STS The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. 0x0: Channel n has no abort status 0x1: Channel n has abort status 0 32 write-only INTERRSTS Error Interrupt Status Register 0x30 32 0x00000000 0xFFFFFFFF STS The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: - Bus error - Unaligned address - Unaligned transfer width - Reserved configuration 0x0: Channel n has no error status 0x1: Channel n has error status 0 32 write-only ChEN Channel Enable Register 0x34 32 0x00000000 0xFFFFFFFF CHEN Alias of the Enable field of all ChnCtrl registers 0 32 read-only 32 0x20 ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8,ch9,ch10,ch11,ch12,ch13,ch14,ch15,ch16,ch17,ch18,ch19,ch20,ch21,ch22,ch23,ch24,ch25,ch26,ch27,ch28,ch29,ch30,ch31 CHCTRL[%s] no description available 0x40 Ctrl Channel &index0 Control Register 0x0 32 0x00000000 0xFFFFF01F INFINITELOOP set to loop current config infinitely 31 1 read-write HANDSHAKEOPT 0: one request to transfer one burst 1: one request to transfer all the data defined in ch_tts 30 1 read-write PRIORITY Channel priority level 0x0: Lower priority 0x1: Higher priority 29 1 read-write BURSTOPT set to change burst_size definition 28 1 read-write SRCBURSTSIZE Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x0: 1 transfer 0x1: 2 transfers 0x2: 4 transfers 0x3: 8 transfers 0x4: 16 transfers 0x5: 32 transfers 0x6: 64 transfers 0x7: 128 transfers 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception 24 4 read-write SRCWIDTH Source transfer width 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception 21 3 read-write DSTWIDTH Destination transfer width. Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception 18 3 read-write SRCMODE Source DMA handshake mode 0x0: Normal mode 0x1: Handshake mode Normal mode is enabled and started by software set Enable bit; Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block 17 1 read-write DSTMODE Destination DMA handshake mode 0x0: Normal mode 0x1: Handshake mode the difference bewteen Source/Destination handshake mode is: the dma block will response hardware request after read in Source handshake mode; the dma block will response hardware request after write in Destination handshake mode; NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. 16 1 read-write SRCADDRCTRL Source address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception 14 2 read-write DSTADDRCTRL Destination address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception 12 2 read-write INTHALFCNTMASK Channel half interrupt mask 0x0: Allow the half interrupt to be triggered 0x1: Disable the half interrupt 4 1 read-write INTABTMASK Channel abort interrupt mask 0x0: Allow the abort interrupt to be triggered 0x1: Disable the abort interrupt 3 1 read-write INTERRMASK Channel error interrupt mask 0x0: Allow the error interrupt to be triggered 0x1: Disable the error interrupt 2 1 read-write INTTCMASK Channel terminal count interrupt mask 0x0: Allow the terminal count interrupt to be triggered 0x1: Disable the terminal count interrupt 1 1 read-write ENABLE Channel enable bit 0x0: Disable 0x1: Enable 0 1 read-write TranSize Channel &index0Transfer Size Register 0x4 32 0x00000000 0x0FFFFFFF TRANSIZE Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. 0 28 read-write SrcAddr Channel &index0 Source Address Low Part Register 0x8 32 0x00000000 0xFFFFFFFF SRCADDRL Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. This address must be aligned to the source transfer size; otherwise, an error event will be triggered. 0 32 read-write ChanReqCtrl Channel &index0 DMA Request Control Register 0xc 32 0x00000000 0x1F1F0000 SRCREQSEL Source DMA request select. Select the request/ack handshake pair that the source device is connected to. 24 5 read-write DSTREQSEL Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. 16 5 read-write DstAddr Channel &index0 Destination Address Low Part Register 0x10 32 0x00000000 0xFFFFFFFF DSTADDRL Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. This address must be aligned to the destination transfer size; otherwise the error event will be triggered. 0 32 read-write LLPointer Channel &index0 Linked List Pointer Low Part Register 0x18 32 0x00000000 0xFFFFFFF8 LLPOINTERL Low part of the pointer to the next descriptor. The pointer must be double word aligned. 3 29 read-write GPIOM GPIOM GPIOM 0xf00d8000 0x0 0x780 registers 15 0x80 gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy ASSIGN[%s] no description available 0x0 32 0x4 PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 PIN[%s] no description available 0x0 32 0x00000000 0x80000F03 LOCK lock fields in this register, lock can only be cleared by soc reset 0: fields can be changed 1: fields locked to current value, not changeable 31 1 read-write HIDE pin value visibility to gpios, bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio 8 4 read-write SELECT select which gpio controls chip pin, 0: soc gpio0; 2: cpu0 fastgpio 0 2 read-write USB0 USB0 USB 0xf300c000 0x80 0x1a8 registers GPTIMER0LD General Purpose Timer #0 Load Register 0x80 32 0x00000000 0x00FFFFFF GPTLD GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds. 0 24 read-write GPTIMER0CTRL General Purpose Timer #0 Controller Register 0x84 32 0x00000000 0xC1FFFFFF GPTRUN GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run 31 1 read-write GPTRST GPTRST General Purpose Timer Reset 0 - No action 1 - Load counter value from GPTLD bits in n_GPTIMER0LD 30 1 write-only GPTMODE GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode 24 1 read-write GPTCNT GPTCNT General Purpose Timer Counter. This field is the count value of the countdown timer. 0 24 read-only GPTIMER1LD General Purpose Timer #1 Load Register 0x88 32 0x00000000 0x00FFFFFF GPTLD GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds. 0 24 read-write GPTIMER1CTRL General Purpose Timer #1 Controller Register 0x8c 32 0x00000000 0xC1FFFFFF GPTRUN GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run 31 1 read-write GPTRST GPTRST General Purpose Timer Reset 0 - No action 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD 30 1 write-only GPTMODE GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode 24 1 read-write GPTCNT GPTCNT General Purpose Timer Counter. This field is the count value of the countdown timer. 0 24 read-only SBUSCFG System Bus Config Register 0x90 32 0x00000000 0x00000007 AHBBRST AHBBRST AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority). NOTE: This register overrides n_BURSTSIZE register when its value is not zero. 000 - Incremental burst of unspecified length only 001 - INCR4 burst, then single transfer 010 - INCR8 burst, INCR4 burst, then single transfer 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer 100 - Reserved, don't use 101 - INCR4 burst, then incremental burst of unspecified length 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length 0 3 read-write USBCMD USB Command Register 0x140 32 0x00080000 0x00FFFB7F ITC ITC Interrupt Threshold Control -Read/Write. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. Value Maximum Interrupt Interval 00000000 - Immediate (no threshold) 00000001 - 1 micro-frame 00000010 - 2 micro-frames 00000100 - 4 micro-frames 00001000 - 8 micro-frames 00010000 - 16 micro-frames 00100000 - 32 micro-frames 01000000 - 64 micro-frames 16 8 read-write FS_2 FS_2 Frame List Size - (Read/Write or Read Only). [host mode only] This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. NOTE: This field is made up from USBCMD bits 15, 3 and 2. Value Meaning 0b000 - 1024 elements (4096 bytes) Default value 0b001 - 512 elements (2048 bytes) 0b010 - 256 elements (1024 bytes) 0b011 - 128 elements (512 bytes) 0b100 - 64 elements (256 bytes) 0b101 - 32 elements (128 bytes) 0b110 - 16 elements (64 bytes) 0b111 - 8 elements (32 bytes) 15 1 read-write ATDTW ATDTW Add dTD TripWire - Read/Write. [device mode only] This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software. This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized. 14 1 read-write SUTW SUTW Setup TripWire - Read/Write. [device mode only] This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. This bit would also be cleared by hardware when a hazard detected. 13 1 read-write PRM Asynchronous Schedule start- Write only， host mode only。 this bit is used to notify hostcontroller to start async schedule immediately. 12 1 write-only ASPE ASPE Asynchronous Schedule Park Mode Enable - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. NOTE: ASPE bit reset value: '0b' for OTG controller . 11 1 read-write ASP ASP Asynchronous Schedule Park Mode Count - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. This field is set to 3h in all controller core. 8 2 read-write IAA IAA Interrupt on Async Advance Doorbell - Read/Write. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. 6 1 read-write ASE ASE Asynchronous Schedule Enable - Read/Write. Default 0b. This bit controls whether the host controller skips processing the Asynchronous Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Asynchronous Schedule. 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. 5 1 read-write PSE PSE Periodic Schedule Enable- Read/Write. Default 0b. This bit controls whether the host controller skips processing the Periodic Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Periodic Schedule 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. 4 1 read-write FS_1 FS_1 See description at bit 15 2 2 read-write RST RST Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. Host operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. Device operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. 1 1 read-write RS RS Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. Host operation mode: When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). Device operation mode: Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. 0 1 read-write USBSTS USB Status Register 0x144 32 0x00000000 0x030DF1FF TI1 TI1 General Purpose Timer Interrupt 1(GPTINT1)--R/WC. This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this bit will clear it. 25 1 read-write TI0 TI0 General Purpose Timer Interrupt 0(GPTINT0)--R/WC. This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this bit clears it. 24 1 read-write UPI USB Host Periodic Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero. 19 1 read-write UAI USB Host Asynchronous Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero 18 1 read-write NAKI NAKI NAK Interrupt Bit--RO. This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware when all Enabled TX/RX Endpoint NAK bits are cleared. 16 1 read-only AS AS Asynchronous Schedule Status - Read Only. This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). Only used in the host operation mode. 15 1 read-only PS PS Periodic Schedule Status - Read Only. This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). Only used in the host operation mode. 14 1 read-only RCL RCL Reclamation - Read Only. This is a read-only status bit used to detect an empty asynchronous schedule. Only used in the host operation mode. 13 1 read-only HCH HCH HCHaIted - Read Only. This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). Only used in the host operation mode. Default value is '0b' for OTG core . This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE register. NOTE: HCH bit reset value: '0b' for OTG controller core . 12 1 read-only SLI SLI DCSuspend - R/WC. When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. Only used in device operation mode. 8 1 read-write SRI SRI SOF Received - R/WC. When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. Software writes a 1 to this bit to clear it. 7 1 read-write URI URI USB Reset Received - R/WC. When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. Software can write a 1 to this bit to clear the USB Reset Received status bit. Only used in device operation mode. 6 1 read-write AAI AAI Interrupt on Async Advance - R/WC. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. Only used in host operation mode. 5 1 read-write SEI System Error – RWC. Default = 0b. In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) 4 1 read-write FRI FRI Frame List Rollover - R/WC. The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FHINDEX [12] toggles. Only used in host operation mode. 3 1 read-write PCI PCI Port Change Detect - R/WC. The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. 2 1 read-write UEI UEI USB Error Interrupt (USBERRINT) - R/WC. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. 1 1 read-write UI UI USB Interrupt (USBINT) - R/WC. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. 0 1 read-write USBINTR Interrupt Enable Register 0x148 32 0x00000000 0x030D01FF TIE1 TIE1 General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. 25 1 read-write TIE0 TIE0 General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. 24 1 read-write UPIE UPIE USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold. 19 1 read-write UAIE UAIE USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold. 18 1 read-write NAKE NAKE NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. 16 1 read-only SLE SLE Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode. 8 1 read-write SRE SRE SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. 7 1 read-write URE URE USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode. 6 1 read-write AAE AAE Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode. 5 1 read-write SEE SEE System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode. 4 1 read-write FRE FRE Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode. 3 1 read-write PCE PCE Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. 2 1 read-write UEE UEE USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. 1 1 read-write UE UE USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. 0 1 read-write FRINDEX USB Frame Index Register 0x14c 32 0x00000000 0x00003FFF FRINDEX FRINDEX Frame Index. The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. USBCMD [Frame List Size] Number Elements N In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. In either mode bits 2:0 indicate the current microframe. The bit field values description below is represented as (Frame List Size) Number Elements N. 00000000000000 - (1024) 12 00000000000001 - (512) 11 00000000000010 - (256) 10 00000000000011 - (128) 9 00000000000100 - (64) 8 00000000000101 - (32) 7 00000000000110 - (16) 6 00000000000111 - (8) 5 0 14 read-write DEVICEADDR Device Address Register UNION_154 0x154 32 0x00000000 0xFF000000 USBADR USBADR Device Address. These bits correspond to the USB device address 25 7 read-write USBADRA USBADRA Device Address Advance. Default=0. When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). 3) Device Reset occurs (USBADR is reset to 0). NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. 24 1 read-write PERIODICLISTBASE Frame List Base Address Register UNION_154 0x154 32 0x00000000 0xFFFFF000 BASEADR BASEADR Base Address (Low). These bits correspond to memory address signals [31:12], respectively. Only used by the host controller. 12 20 read-write ASYNCLISTADDR Next Asynch. Address Register UNION_158 0x158 32 0x00000000 0xFFFFFFE0 ASYBASE ASYBASE Link Pointer Low (LPL). These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH). Only used by the host controller. 5 27 read-write ENDPTLISTADDR Endpoint List Address Register UNION_158 0x158 32 0x00000000 0xFFFFF800 EPBASE EPBASE Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). 11 21 read-write BURSTSIZE Programmable Burst Size Register 0x160 32 0x00000000 0x0000FFFF TXPBURST TXPBURST Programmable TX Burst Size. Default value is determined by TXBURST bits in n_HWTXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus. 8 8 read-write RXPBURST RXPBURST Programmable RX Burst Size. Default value is determined by TXBURST bits in n_HWRXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory. 0 8 read-write TXFILLTUNING TX FIFO Fill Tuning Register 0x164 32 0x00000000 0x003F1F7F TXFIFOTHRES TXFIFOTHRES FIFO Burst Threshold. (Read/Write) This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. 16 6 read-write TXSCHHEALTH TXSCHHEALTH Scheduler Health Counter. (Read/Write To Clear) Table continues on the next page This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. 8 5 read-write TXSCHOH TXSCHOH Scheduler Overhead. (Read/Write) [Default = 0] This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. Default value is '08h' for OTG controller core . 0 7 read-write ENDPTNAK Endpoint NAK Register 0x178 32 0x00000000 0xFFFFFFFF EPTN EPTN TX Endpoint NAK - R/WC. Each TX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit [N] - Endpoint #[N], N is 0-7 16 16 read-write EPRN EPRN RX Endpoint NAK - R/WC. Each RX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit [N] - Endpoint #[N], N is 0-7 0 16 read-write ENDPTNAKEN Endpoint NAK Enable Register 0x17c 32 0x00000000 0xFFFFFFFF EPTNE EPTNE TX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit [N] - Endpoint #[N], N is 0-7 16 16 read-write EPRNE EPRNE RX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit [N] - Endpoint #[N], N is 0-7 0 16 read-write PORTSC1 Port Status & Control 0x184 32 0x00000000 0x3DFF1FFF STS STS Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. 29 1 read-write PTW PTW Parallel Transceiver Width This bit has no effect if serial interface engine is used. 0 - Select the 8-bit UTMI interface [60MHz] 1 - Select the 16-bit UTMI interface [30MHz] 28 1 read-write PSPD PSPD Port Speed - Read Only. This register field indicates the speed at which the port is operating. 00 - Full Speed 01 - Low Speed 10 - High Speed 11 - Undefined 26 2 read-only PFSC PFSC Port Force Full Speed Connect - Read/Write. Default = 0b. When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp sequence that allows the port to identify itself as High Speed. 0 - Normal operation 1 - Forced to full speed 24 1 read-write PHCD PHCD PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock cannot be disabled if it is being used as the system clock. In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend will be cleared automatically when the host initials resume. Before forcing a resume from the device, the device controller driver must clear this bit. In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0 - Enable PHY clock 1 - Disable PHY clock 23 1 read-write WKOC WKOC Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. This field is zero if Port Power(PORTSC1) is zero. 22 1 read-write WKDC WKDC Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode. 21 1 read-write WKCN WKCN Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode. 20 1 read-write PTC PTC Port Test Control - Read/Write. Default = 0000b. Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. NOTE: Low speed operations are not supported as a peripheral device. Any other value than zero indicates that the port is operating in test mode. Value Specific Test 0000 - TEST_MODE_DISABLE 0001 - J_STATE 0010 - K_STATE 0011 - SE0 (host) / NAK (device) 0100 - Packet 0101 - FORCE_ENABLE_HS 0110 - FORCE_ENABLE_FS 0111 - FORCE_ENABLE_LS 1000-1111 - Reserved 16 4 read-write PP PP Port Power (PP)-Read/Write or Read Only. The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: PPC PP Operation 0 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. 1 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). This feature is implemented in all controller cores (PPC = 1). 12 1 read-write LS LS Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because the port controller state machine and the port routing manage the connection of LS and FS. In device mode, the use of linestate by the device controller driver is not necessary. The encoding of the bits are: Bits [11:10] Meaning 00 - SE0 01 - K-state 10 - J-state 11 - Undefined 10 2 read-only HSP HSP High-Speed Port - Read Only. Default = 0b. When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the host/device connected to the port is not in a high-speed mode. NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. 9 1 read-only PR PR Port Reset - Read/Write or Read Only. Default = 0b. In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. 8 1 read-write SUSP SUSP Suspend - Read/Write or Read Only. Default = 0b. 1=Port in suspend state. 0=Port not in suspend state. In Host Mode: Read/Write. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits [Port Enabled, Suspend] Port State 0x Disable 10 Enable 11 Suspend When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: Read Only. In device mode this bit is a read only status bit. 7 1 read-write FPR FPR Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. In Host Mode: Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. This field is zero if Port Power(PORTSC1) is zero in host mode. This bit is not-EHCI compatible. In Device mode: After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. 6 1 read-write OCC OCC Over-current Change-R/WC. Default=0. This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. 5 1 read-write OCA OCA Over-current Active-Read Only. Default 0. This bit will automatically transition from one to zero when the over current condition is removed. 0 - This port does not have an over-current condition. 1 - This port currently has an over-current condition 4 1 read-only PEC PEC Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. In Host Mode: For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This field is zero if Port Power(PORTSC1) is zero. In Device mode: The device port is always enabled, so this bit is always '0b'. 3 1 read-write PE PE Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. In Host Mode: Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled, (0b) downstream propagation of data is blocked except for reset. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: The device port is always enabled, so this bit is always '1b'. 2 1 read-write CSC CSC Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. In Host Mode: Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: This bit is undefined in device controller mode. 1 1 read-write CCS CCS Current Connect Status-Read Only. In Host Mode: 1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: 1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended. 0 1 read-write OTGSC On-The-Go Status & control Register 0x1a4 32 0x00000000 0x07070723 ASVIE ASVIE A Session Valid Interrupt Enable - Read/Write. 26 1 read-write AVVIE AVVIE A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt. 25 1 read-write IDIE IDIE USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt. 24 1 read-write ASVIS ASVIS A Session Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the A session valid threshold. Software must write a one to clear this bit. 18 1 read-write AVVIS AVVIS A VBus Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. Software must write a one to clear this bit. 17 1 read-write IDIS IDIS USB ID Interrupt Status - Read/Write. This bit is set when a change on the ID input has been detected. Software must write a one to clear this bit. 16 1 read-write ASV ASV A Session Valid - Read Only. Indicates VBus is above the A session valid threshold. 10 1 read-only AVV AVV A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold. 9 1 read-only ID ID USB ID - Read Only. 0 = A device, 1 = B device 8 1 read-only IDPU IDPU ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input will not be sampled. 5 1 read-write VC VC VBUS Charge - Read/Write. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. 1 1 read-write VD VD VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor. 0 1 read-write USBMODE USB Device Mode Register 0x1a8 32 0x00000000 0x0000001F SDIS SDIS Stream Disable Mode. (0 - Inactive [default]; 1 - Active) Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for the scheduler when using this feature. NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. 4 1 read-write SLOM SLOM Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . 0 - Setup Lockouts On (default); 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. 3 1 read-write ES ES Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected by the value of this bit because they are based upon the 32-bit word. Bit Meaning 0 - Little Endian [Default] 1 - Big Endian 2 1 read-write CM CM Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host & device capability, the controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ device controllers, this register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. For OTG controller core, reset value is '00b'. 00 - Idle [Default for combination host/device] 01 - Reserved 10 - Device Controller [Default for device only controller] 11 - Host Controller [Default for host only controller] 0 2 read-write ENDPTSETUPSTAT Endpoint Setup Status Register 0x1ac 32 0x00000000 0x0000FFFF ENDPTSETUPSTAT ENDPTSETUPSTAT Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. This register is only used in device mode. 0 16 read-write ENDPTPRIME Endpoint Prime Register 0x1b0 32 0x00000000 0xFFFFFFFF PETB PETB Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PETB[N] - Endpoint #N, N is in 0..7 16 16 read-write PERB PERB Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PERB[N] - Endpoint #N, N is in 0..7 0 16 read-write ENDPTFLUSH Endpoint Flush Register 0x1b4 32 0x00000000 0xFFFFFFFF FETB FETB Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FETB[N] - Endpoint #N, N is in 0..7 16 16 read-write FERB FERB Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FERB[N] - Endpoint #N, N is in 0..7 0 16 read-write ENDPTSTAT Endpoint Status Register 0x1b8 32 0x00000000 0xFFFFFFFF ETBR ETBR Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ETBR[N] - Endpoint #N, N is in 0..7 16 16 read-only ERBR ERBR Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ERBR[N] - Endpoint #N, N is in 0..7 0 16 read-only ENDPTCOMPLETE Endpoint Complete Register 0x1bc 32 0x00000000 0xFFFFFFFF ETCE ETCE Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ETCE[N] - Endpoint #N, N is in 0..7 16 16 read-write ERCE ERCE Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ERCE[N] - Endpoint #N, N is in 0..7 0 16 read-write 16 0x4 ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7,ENDPTCTRL8,ENDPTCTRL9,ENDPTCTRL10,ENDPTCTRL11,ENDPTCTRL12,ENDPTCTRL13,ENDPTCTRL14,ENDPTCTRL15 ENDPTCTRL[%s] no description available 0x1c0 32 0x00000000 0x00CD00CD TXE TXE TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured. 23 1 read-write TXR TXR TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device. 22 1 write-only TXT TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 18 2 read-write TXS TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. 16 1 read-write RXE RXE RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured. 7 1 read-write RXR RXR RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device. 6 1 write-only RXT RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 2 2 read-write RXS RXS RX Endpoint Stall - Read/Write 0 End Point OK. [Default] 1 End Point Stalled This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. 0 1 read-write OTG_CTRL0 No description available 0x200 32 0x00000000 0x020B3F90 OTG_WKDPDMCHG_EN No description available 25 1 read-write AUTORESUME_EN No description available 19 1 read-write OTG_VBUS_WAKEUP_EN No description available 17 1 read-write OTG_ID_WAKEUP_EN No description available 16 1 read-write OTG_VBUS_SOURCE_SEL No description available 13 1 read-write OTG_UTMI_SUSPENDM_SW default 0 for naneng usbphy 12 1 read-write OTG_UTMI_RESET_SW default 1 for naneng usbphy 11 1 read-write OTG_WAKEUP_INT_ENABLE No description available 10 1 read-write OTG_POWER_MASK No description available 9 1 read-write OTG_OVER_CUR_POL No description available 8 1 read-write OTG_OVER_CUR_DIS No description available 7 1 read-write SER_MODE_SUSPEND_EN for naneng usbphy, only switch to serial mode when suspend 4 1 read-write PHY_CTRL0 No description available 0x210 32 0x00000000 0x02007007 GPIO_ID_SEL_N No description available 25 1 read-write ID_DIG_OVERRIDE No description available 14 1 read-write SESS_VALID_OVERRIDE No description available 13 1 read-write VBUS_VALID_OVERRIDE No description available 12 1 read-write ID_DIG_OVERRIDE_EN No description available 2 1 read-write SESS_VALID_OVERRIDE_EN No description available 1 1 read-write VBUS_VALID_OVERRIDE_EN No description available 0 1 read-write PHY_CTRL1 No description available 0x214 32 0x00000000 0x00100002 UTMI_CFG_RST_N No description available 20 1 read-write UTMI_OTG_SUSPENDM OTG suspend, not utmi_suspendm 1 1 read-write TOP_STATUS No description available 0x220 32 0x00000000 0x80000000 WAKEUP_INT_STATUS No description available 31 1 read-write PHY_STATUS No description available 0x224 32 0x00000000 0x800000F5 UTMI_CLK_VALID No description available 31 1 read-write LINE_STATE No description available 6 2 read-write HOST_DISCONNECT No description available 5 1 read-write ID_DIG No description available 4 1 read-write UTMI_SESS_VALID No description available 2 1 read-write VBUS_VALID No description available 0 1 read-write SEC SEC SEC 0xf3044000 0x0 0x18 registers SECURE_STATE Secure state 0x0 32 0x00000000 0x000300F0 ALLOW_NSC Non-secure state allow 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state 1: system is healthy to enter non-secure state 17 1 read-only ALLOW_SEC Secure state allow 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state 1: system is healthy to enter secure state 16 1 read-only PMIC_FAIL PMIC secure state one hot indicator 0: secure state is not in fail state 1: secure state is in fail state 7 1 read-write PMIC_NSC PMIC secure state one hot indicator 0: secure state is not in non-secure state 1: secure state is in non-secure state 6 1 read-write PMIC_SEC PMIC secure state one hot indicator 0: secure state is not in secure state 1: secure state is in secure state 5 1 read-write PMIC_INS PMIC secure state one hot indicator 0: secure state is not in inspect state 1: secure state is in inspect state 4 1 read-write SECURE_STATE_CONFIG secure state configuration 0x4 32 0x00000000 0x00000009 LOCK Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset 0: not locked, register can be modified 1: register locked, write access to the register is ignored 3 1 read-write ALLOW_RESTART allow secure state restart from fail state 0: restart is not allowed, only hardware reset can recover secure state 1: software is allowed to switch to inspect state from fail state 0 1 read-write VIOLATION_CONFIG Security violation config 0x8 32 0x00000000 0xFFFFFFFF LOCK_NSC Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored 31 1 read-write NSC_VIO_CFG configuration of non-secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation 16 15 read-write LOCK_SEC Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored 15 1 read-write SEC_VIO_CFG configuration of secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation 0 15 read-write ESCALATE_CONFIG Escalate behavior on security event 0xc 32 0x00000000 0xFFFFFFFF LOCK_NSC Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored 31 1 read-write NSC_VIO_CFG configuration of non-secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate 16 15 read-write LOCK_SEC Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored 15 1 read-write SEC_VIO_CFG configuration of secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate 0 15 read-write EVENT Event and escalate status 0x10 32 0x00000000 0xFFFF000C EVENT local event statue, each bit represents one security event 16 16 read-only PMIC_ESC_NSC PMIC is escalating non-secure event 3 1 read-only PMIC_ESC_SEC PMIC is escalting secure event 2 1 read-only LIFECYCLE Lifecycle 0x14 32 0x00000000 0x000000FF LIFECYCLE lifecycle status, bit7: lifecycle_debate, bit6: lifecycle_scribe, bit5: lifecycle_no_ret, bit4: lifecycle_return, bit3: lifecycle_secure, bit2: lifecycle_nonsec, bit1: lifecycle_create, bit0: lifecycle_unknow 0 8 read-only MON MON MON 0xf3048000 0x0 0x48 registers 4 0x8 glitch0,glitch1,clock0,clock1 MONITOR[%s] no description available 0x0 CONTROL Glitch and clock monitor control 0x0 32 0x00000000 0x00000011 ACTIVE select glitch works in active mode or passve mode. 0: passive mode, depends on power glitch destroy DFF value 1: active mode, check glitch by DFF chain 4 1 read-write ENABLE enable glitch detector 0: detector disabled 1: detector enabled 0 1 read-write STATUS Glitch and clock monitor status 0x4 32 0x00000000 0x00000001 FLAG flag for glitch detected, write 1 to clear this flag 0: glitch not detected 1: glitch detected 0 1 read-write IRQ_FLAG No description available 0x40 32 0x00000000 0x0000000F FLAG interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag 0: no monitor interrupt 1: monitor interrupt happened 0 4 read-write IRQ_ENABLE No description available 0x44 32 0x00000000 0x0000000F ENABLE interrupt enable, each bit represents for one monitor 0: monitor interrupt disabled 1: monitor interrupt enabled 0 4 read-write OTP OTP OTP 0xf3050000 0x0 0xc08 registers 128 0x4 SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 SHADOW[%s] no description available 0x0 32 0x00000000 0xFFFFFFFF SHADOW shadow register of fuse for pmic area for PMIC, index valid for 0-15, for SOC index valid for 16-128 0 32 read-write 8 0x4 LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 SHADOW_LOCK[%s] no description available 0x200 32 0x00000000 0xFFFFFFFF LOCK lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked 0 32 read-write 128 0x4 FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 FUSE[%s] no description available 0x400 32 0x00000000 0xFFFFFFFF FUSE fuse array, valid in PMIC part only read operation will read out value in fuse array write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) 0 32 read-write 8 0x4 LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 FUSE_LOCK[%s] no description available 0x600 32 0x00000000 0xFFFFFFFF LOCK lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked 0 32 read-write UNLOCK UNLOCK 0x800 32 0x00000000 0xFFFFFFFF UNLOCK unlock word for fuse array operation write "OPEN" to unlock fuse array, write any other value will lock write to fuse. Please make sure 24M crystal is running and 2.5V LDO working properly 0 32 read-write DATA DATA 0x804 32 0x00000000 0xFFFFFFFF DATA data register for non-blocking access this register hold dat read from fuse array or data to by programmed to fuse array 0 32 read-write ADDR ADDR 0x808 32 0x00000000 0x0000007F ADDR word address to be read or write 0 7 read-write CMD CMD 0x80c 32 0x00000000 0xFFFFFFFF CMD command to access fure array "BLOW" will update fuse word at ADDR to value hold in DATA "READ" will fetch fuse value in at ADDR to DATA register 0 32 read-write LOAD_REQ LOAD Request 0xa00 32 0x00000007 0x0000000F REQUEST reload request for 4 regions bit0: region0 bit1: region1 bit2: region2 bit3: region3 0 4 read-write LOAD_COMP LOAD complete 0xa04 32 0x00000007 0x0000000F COMPLETE reload complete sign for 4 regions bit0: region 0 bit1: region1 bit2: region2 bit3: region3 0 4 read-write 4 0x4 LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 REGION[%s] no description available 0xa20 32 0x00000800 0x00007F7F STOP stop address of load region, fuse word at end address will NOT be reloaded region0: fixed at 8 region1: fixed at 16 region2: fixed at 0, region3: usrer configurable 8 7 read-write START start address of load region, fuse word at start address will be reloaded region0: fixed at 0 region1: fixed at 8 region2: fixed at 16, region3: usrer configurable 0 7 read-write INT_FLAG interrupt flag 0xc00 32 0x00000000 0x00000007 WRITE fuse write flag, write 1 to clear 0: fuse is not written or writing 1: value in DATA register is programmed into fuse 2 1 read-write READ fuse read flag, write 1 to clear 0: fuse is not read or reading 1: fuse value is put in DATA register 1 1 read-write LOAD fuse load flag, write 1 to clear 0: fuse is not loaded or loading 1: fuse loaded 0 1 read-write INT_EN interrupt enable 0xc04 32 0x00000000 0x00000007 WRITE fuse write interrupt enable 0: fuse write interrupt is not enable 1: fuse write interrupt is enable 2 1 read-write READ fuse read interrupt enable 0: fuse read interrupt is not enable 1: fuse read interrupt is enable 1 1 read-write LOAD fuse load interrupt enable 0: fuse load interrupt is not enable 1: fuse load interrupt is enable 0 1 read-write KEYM KEYM KEYM 0xf3054000 0x0 0x50 registers 8 0x4 SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 SOFTMKEY[%s] no description available 0x0 32 0x00000000 0xFFFFFFFF KEY software symmetric key key will be scambled to 4 variants for software to use, and replicable on same chip. scramble keys are chip different, and not replicable on different chip must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 0 32 read-write 8 0x4 SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 SOFTPKEY[%s] no description available 0x20 32 0x00000000 0xFFFFFFFF KEY software asymmetric key key is derived from scrambles of fuse private key, software input key, SRK, and system security status. This key os read once, sencondary read will read out 0 0 32 read-write SEC_KEY_CTL secure key generation 0x40 32 0x00000000 0x80011117 LOCK_SEC_CTL block secure state key setting being changed 31 1 read-write SK_VAL session key valid 0: session key is all 0's and not usable 1: session key is valid 16 1 read-only SMK_SEL software symmetric key selection 0: use origin value in software symmetric key 1: use scramble version of software symmetric key 12 1 read-write ZMK_SEL batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key 8 1 read-write FMK_SEL fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use alnertave scramble of fuse symmetric key 4 1 read-write KEY_SEL secure symmtric key synthesize setting, key is a XOR of following bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected 0 3 read-write NSC_KEY_CTL non-secure key generation 0x44 32 0x00000000 0x80011117 LOCK_NSC_CTL block non-secure state key setting being changed 31 1 read-write SK_VAL session key valid 0: session key is all 0's and not usable 1: session key is valid 16 1 read-only SMK_SEL software symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key 12 1 read-write ZMK_SEL batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key 8 1 read-write FMK_SEL fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use origin value in fuse symmetric key 4 1 read-write KEY_SEL non-secure symmtric key synthesize setting, key is a XOR of following bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected 0 3 read-write RNG Random number interface behavior 0x48 32 0x00000000 0x00010001 BLOCK_RNG_XOR block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset 0: RNG_XOR can be changed by software 1: RNG_XOR ignore software change from software 16 1 read-write RNG_XOR control how SFK is accepted from random number generator 0: SFK value replaced by random number input 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG 0 1 read-write READ_CONTROL key read out control 0x4c 32 0x00000000 0x00010001 BLOCK_PK_READ asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out 16 1 read-write BLOCK_SMK_READ symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out 0 1 read-write ADC0 ADC0 ADC16 0xf3080000 0x0 0x1464 registers 12 0x4 trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c CONFIG[%s] no description available 0x0 32 0x00000000 0xFF3F3F7F TRIG_LEN length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 30 2 write-only INTEN3 interrupt enable for 4th conversion 29 1 read-write CHAN3 channel number for 4th conversion 24 5 read-write INTEN2 interrupt enable for 3rd conversion 21 1 read-write CHAN2 channel number for 3rd conversion 16 5 read-write INTEN1 interrupt enable for 2nd conversion 13 1 read-write CHAN1 channel number for 2nd conversion 8 5 read-write QUEUE_EN preemption queue enable control 6 1 read-write INTEN0 interrupt enable for 1st conversion 5 1 read-write CHAN0 channel number for 1st conversion 0 5 read-write trg_dma_addr No description available 0x30 32 0x00000000 0xFFFFFFFC TRG_DMA_ADDR buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) 2 30 read-write trg_sw_sta No description available 0x34 32 0x00000000 0x0000001F TRG_SW_STA SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. 4 1 read-write TRIG_SW_INDEX which trigger for the SW trigger 0 for trig0a, 1 for trig0b… 3 for trig1a, …11 for trig3c 0 4 read-write 16 0x4 chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 BUS_RESULT[%s] no description available 0x400 32 0x00000000 0x0001FFFF VALID set after conversion finished if wait_dis is set, cleared after software read. The first time read with 0 will trigger one new conversion. If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. the result may not realtime if software read once and wait long time to read again 16 1 read-only CHAN_RESULT read this register will trigger one adc conversion. If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long 0 16 read-only buf_cfg0 No description available 0x500 32 0x00000000 0x00000003 BUS_MODE_EN bus mode enable 1 1 read-write WAIT_DIS set to disable read waiting, get result immediately but maybe not current conversion result. 0 1 read-write seq_cfg0 No description available 0x800 32 0x00000000 0x80000F1F CYCLE current dma write cycle bit 31 1 read-only SEQ_LEN sequence queue length, 0 for one, 0xF for 16 8 4 read-write RESTART_EN if set together with cont_en, HW will continue process the whole queue after trigger once. If cont_en is 0, this bit is not used 4 1 read-write CONT_EN if set, HW will continue process the queue till end(seq_len) after trigger once 3 1 read-write SW_TRIG SW trigger, pulse signal, cleared by HW one cycle later 2 1 write-only SW_TRIG_EN set to enable SW trigger 1 1 read-write HW_TRIG_EN set to enable external HW trigger, only trigger on posedge 0 1 read-write seq_dma_addr No description available 0x804 32 0x00000000 0xFFFFFFFC TAR_ADDR dma target address, should be 4-byte aligned 2 30 read-write seq_wr_addr No description available 0x808 32 0x00000000 0x00FFFFFF SEQ_WR_POINTER HW update this field after each dma write, it indicate the next dma write pointer. dma write address is (tar_addr+seq_wr_pointer)*4 0 24 read-only seq_dma_cfg No description available 0x80c 32 0x00000000 0x0FFF3FFF STOP_POS if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet 16 12 read-write DMA_RST set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. SW should clear all cycle bit in buffer to 0 before clear dma_rst 13 1 read-write STOP_EN set to stop dma if reach the stop_pos 12 1 read-write BUF_LEN dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 0 for 4byte; 0xFFF for 16kbyte. 0 12 read-write 16 0x4 cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 SEQ_QUE[%s] no description available 0x810 32 0x00000000 0x0000003F SEQ_INT_EN interrupt enable for current conversion 5 1 read-write CHAN_NUM_4_0 channel number for current conversion 0 5 read-write seq_high_cfg No description available 0x850 32 0x00000000 0x00FFFFFF STOP_POS_HIGH No description available 12 12 read-write BUF_LEN_HIGH No description available 0 12 read-write 16 0x10 chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 PRD_CFG[%s] no description available 0xc00 prd_cfg No description available 0x0 32 0x00000000 0x00001FFF PRESCALE 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx 8 5 read-write PRD conver period, with prescale. Set to 0 means disable current channel 0 8 read-write prd_thshd_cfg No description available 0x4 32 0x00000000 0xFFFFFFFF THSHDH threshold high, assert interrupt(if enabled) if result exceed high or low. 16 16 read-write THSHDL threshold low 0 16 read-write prd_result No description available 0x8 32 0x00000000 0x0000FFFF CHAN_RESULT adc convert result, update after each valid conversion. it may be updated period according to config, also may be updated due to other queue convert the same channel 0 16 read-only 16 0x4 chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 SAMPLE_CFG[%s] no description available 0x1000 32 0x00000000 0x00000FFF SAMPLE_CLOCK_NUMBER_SHIFT shift for sample clock number 9 3 read-write SAMPLE_CLOCK_NUMBER sample clock number, base on clock_period, default one period 0 9 read-write conv_cfg1 No description available 0x1104 32 0x00000000 0x000001FF CONVERT_CLOCK_NUMBER convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). 4 5 read-write CLOCK_DIVIDER clock_period, N half clock cycle per half adc cycle 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3, ... 15 for 1:16 Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk 0 4 read-write adc_cfg0 No description available 0x1108 32 0x00000000 0xA0000001 SEL_SYNC_AHB set to 1 will enable sync AHB bus, to get better bus performance. Adc_clk must to be set to same as bus clock at this mode 31 1 read-write ADC_AHB_EN set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; 29 1 read-write PORT3_REALTIME set to enable trg queue stop other queues 0 1 read-write int_sts No description available 0x1110 32 0x00000000 0xFFE0FFFF TRIG_CMPT interrupt for one trigger conversion complete if enabled 31 1 read-write TRIG_SW_CFLCT No description available 30 1 read-write TRIG_HW_CFLCT No description available 29 1 read-write READ_CFLCT read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 read-write SEQ_SW_CFLCT sequence queue conflict interrupt, set if HW or SW trigger received during conversion 27 1 read-write SEQ_HW_CFLCT No description available 26 1 read-write SEQ_DMAABT dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 read-write SEQ_CMPT the whole sequence complete interrupt 24 1 read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 read-write DMA_FIFO_FULL DMA fifo full interrupt, user need to check clock frequency if it's set. 22 1 read-write AHB_ERR set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr 21 1 read-write WDOG set if one chanel watch dog event triggered 0 16 read-write int_en No description available 0x1114 32 0x00000000 0xFFE0FFFF TRIG_CMPT interrupt for one trigger conversion complete if enabled 31 1 read-write TRIG_SW_CFLCT No description available 30 1 read-write TRIG_HW_CFLCT No description available 29 1 read-write READ_CFLCT read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 read-write SEQ_SW_CFLCT sequence queue conflict interrupt, set if HW or SW trigger received during conversion 27 1 read-write SEQ_HW_CFLCT No description available 26 1 read-write SEQ_DMAABT dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 read-write SEQ_CMPT the whole sequence complete interrupt 24 1 read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 read-write DMA_FIFO_FULL DMA fifo full interrupt, user need to check clock frequency if it's set. 22 1 read-write AHB_ERR set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr 21 1 read-write WDOG set if one chanel watch dog event triggered 0 16 read-write ana_ctrl0 No description available 0x1200 32 0x00000000 0x80001004 MOTO_EN "set to enable moto_soc and moto_valid. Should use AHB clock for adc, this bit can be used avoid async output" 31 1 read-write ADC_CLK_ON set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. MUST set clock_period to 0 or 1 for adc16 reg access 12 1 read-write STARTCAL set to start the offset calibration cycle (Active H). user need to clear it after setting it. 2 1 read-write ana_status No description available 0x1210 32 0x00000000 0x00000080 CALON Indicates if the ADC is in calibration mode (Active H). 7 1 read-write 34 0x2 adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 ADC16_PARAMS[%s] no description available 0x1400 16 0x0000 0xFFFF PARAM_VAL No description available 0 16 read-write adc16_config0 No description available 0x1444 32 0x00000000 0x01F07FFF REG_EN set to enable regulator 24 1 read-write BANDGAP_EN set to enable bandgap. user should set reg_en and bandgap_en before use adc16. 23 1 read-write CAL_AVG_CFG for average the calibration result. 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; 4- 16 loops; 5-32 loops; others reserved 20 3 read-write PREEMPT_EN set to enable preemption feature 14 1 read-write CONV_PARAM conversion parameter 0 14 read-write adc16_config1 No description available 0x1460 32 0x00000000 0x00001F00 COV_END_CNT used for faster conversion, user can change it to get higher convert speed(but less accuracy). should set to (21-convert_clock_number+1). 8 5 read-write ACMP ACMP ACMP 0xf30b0000 0x0 0x80 registers 4 0x20 chn0,chn1,chn2,chn3 CHANNEL[%s] no description available 0x0 cfg Configure Register 0x0 32 0x00000000 0xFF7FFFFF HYST This bitfield configure the comparator hysteresis. 00: Hysteresis level 0 01: Hysteresis level 1 10: Hysteresis level 2 11: Hysteresis level 3 30 2 read-write DACEN This bit enable the comparator internal DAC 0: DAC disabled 1: DAC enabled 29 1 read-write HPMODE This bit enable the comparator high performance mode. 0: HP mode disabled 1: HP mode enabled 28 1 read-write CMPEN This bit enable the comparator. 0: ACMP disabled 1: ACMP enabled 27 1 read-write MINSEL PIN select, from pad_ai_acmp[7:1] and dac_out 24 3 read-write PINSEL MIN select, from pad_ai_acmp[7:1] and dac_out 20 3 read-write CMPOEN This bit enable the comparator output on pad. 0: ACMP output disabled 1: ACMP output enabled 19 1 read-write FLTBYPS This bit bypass the comparator output digital filter. 0: The ACMP output need pass digital filter 1: The ACMP output digital filter is bypassed. 18 1 read-write WINEN This bit enable the comparator window mode. 0: Window mode is disabled 1: Window mode is enabled 17 1 read-write OPOL The output polarity control bit. 0: The ACMP output remain un-changed. 1: The ACMP output is inverted. 16 1 read-write FLTMODE This bitfield define the ACMP output digital filter mode: 000-bypass 100-change immediately; 101-change after filter; 110-stalbe low; 111-stable high 13 3 read-write SYNCEN This bit enable the comparator output synchronization. 0: ACMP output not synchronized with ACMP clock. 1: ACMP output synchronized with ACMP clock. 12 1 read-write FLTLEN This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. 0 12 read-write daccfg DAC configure register 0x4 32 0x00000000 0x000000FF DACCFG 8bit DAC digital value output to analog block 0 8 read-write sr Status register 0x10 32 0x00000000 0x00000003 FEDGF Output falling edge flag. Write 1 to clear this flag. 1 1 read-write REDGF Output rising edge flag. Write 1 to clear this flag. 0 1 read-write irqen Interrupt request enable register 0x14 32 0x00000000 0x00000003 FEDGEN Output falling edge flag interrupt enable bit. 1 1 read-write REDGEN Output rising edge flag interrupt enable bit. 0 1 read-write dmaen DMA request enable register 0x18 32 0x00000000 0x00000003 FEDGEN Output falling edge flag DMA request enable bit. 1 1 read-write REDGEN Output rising edge flag DMA request enable bit. 0 1 read-write SYSCTL SYSCTL SYSCTL 0xf4000000 0x0 0x2c00 registers 105 0x4 cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_cpu0,rst_soc,rst_cpu0,rsv24,rsv25,rsv26,rsv27,rsv28,rsv29,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_clk2_pll1,clk_src_clk3_pll1,clk_src_pll0_ref,clk_src_pll1_ref,rsv44,rsv45,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,rsv70,rsv71,rsv72,rsv73,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1,clk_top_adc0,clk_top_adc1,clk_top_dac0,clk_top_dac1,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahb0,lmm0,mct0,rom0,can0,can1,can2,can3,ptpc,rsv265,rsv266,rsv267,rsv268,tmr0,tmr1,tmr2,tmr3,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,wdg0,wdg1,mbx0,tsns,crc0,adc0,adc1,dac0,dac1,acmp,opa0,opa1,mot0,rng0,sdp0,kman,gpio,hdma,xpi0,usb0,ref0,ref1 RESOURCE[%s] no description available 0x0 32 0x00000000 0xC0000003 GLB_BUSY global busy 0: no changes pending to any nodes 1: any of nodes is changing status 31 1 read-only LOC_BUSY local busy 0: no change is pending for current node 1: current node is changing status 30 1 read-only MODE resource work mode 0:auto turn on and off as system required(recommended) 1:always on 2:always off 3:reserved 0 2 read-write 2 0x10 link0,link1 GROUP0[%s] no description available 0x800 VALUE Group setting 0x0 32 0x00000000 0xFFFFFFFF LINK denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: peripheral is not needed 1: periphera is needed 0 32 read-write SET Group setting 0x4 32 0x00000000 0xFFFFFFFF LINK denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: add periphera into this group，periphera is needed 0 32 read-write CLEAR Group setting 0x8 32 0x00000000 0xFFFFFFFF LINK denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: delete periphera in this group，periphera is not needed 0 32 read-write TOGGLE Group setting 0xc 32 0x00000000 0xFFFFFFFF LINK denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: toggle the result that whether periphera is needed before 0 32 read-write 1 0x10 cpu0 AFFILIATE[%s] no description available 0x900 VALUE Affiliate of Group 0x0 32 0x00000000 0x0000000F LINK Affiliate groups of cpu0, each bit represents a group bit0: cpu0 depends on group0 bit1: cpu0 depends on group1 bit2: cpu0 depends on group2 bit3: cpu0 depends on group3 0 4 read-write SET Affiliate of Group 0x4 32 0x00000000 0x0000000F LINK Affiliate groups of cpu0，each bit represents a group 0: no effect 1: the group is assigned to CPU0 0 4 read-write CLEAR Affiliate of Group 0x8 32 0x00000000 0x0000000F LINK Affiliate groups of cpu0, each bit represents a group 0: no effect 1: the group is not assigned to CPU0 0 4 read-write TOGGLE Affiliate of Group 0xc 32 0x00000000 0x0000000F LINK Affiliate groups of cpu0, each bit represents a group 0: no effect 1: toggle the result that whether the group is assigned to CPU0 before 0 4 read-write 1 0x10 cpu0 RETENTION[%s] no description available 0x920 VALUE Retention Control 0x0 32 0x00000000 0x00007FFF LINK retention setting while CPU0 enter stop mode, each bit represents a resource bit00: soc_mem is kept on while cpu0 stop bit01: soc_ctx is kept on while cpu0 stop bit02: cpu0_mem is kept on while cpu0 stop bit03: cpu0_ctx is kept on while cpu0 stop bit04: xtal_hold is kept on while cpu0 stop bit05: pll0_hold is kept on while cpu0 stop bit06: pll1_hold is kept on while cpu0 stop 0 15 read-write SET Retention Control 0x4 32 0x00000000 0x00007FFF LINK retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: keep 0 15 read-write CLEAR Retention Control 0x8 32 0x00000000 0x00007FFF LINK retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: no keep 0 15 read-write TOGGLE Retention Control 0xc 32 0x00000000 0x00007FFF LINK retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: toggle the result that whether the resource is kept on while CPU0 stop before 0 15 read-write 1 0x14 cpu0 POWER[%s] no description available 0x1000 status Power Setting 0x0 32 0x80000000 0xC0031100 FLAG flag represents power cycle happened from last clear of this bit 0: power domain did not edurance power cycle since last clear of this bit 1: power domain enduranced power cycle since last clear of this bit 31 1 read-write FLAG_WAKE flag represents wakeup power cycle happened from last clear of this bit 0: power domain did not edurance wakeup power cycle since last clear of this bit 1: power domain enduranced wakeup power cycle since last clear of this bit 30 1 read-write MEM_RET_N memory info retention control signal 0: memory enter retention mode 1: memory exit retention mode 17 1 read-only MEM_RET_P memory info retention control signal 0: memory not enterexitretention mode 1: memory enter retention mode 16 1 read-only LF_DISABLE low fanout power switch disable 0: low fanout power switches are turned on 1: low fanout power switches are truned off 12 1 read-only LF_ACK low fanout power switch feedback 0: low fanout power switches are turned on 1: low fanout power switches are truned off 8 1 read-only lf_wait Power Setting 0x4 32 0x000000FF 0x000FFFFF WAIT wait time for low fan out power switch turn on, default value is 255 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz 0 20 read-write off_wait Power Setting 0xc 32 0x0000000F 0x000FFFFF WAIT wait time for power switch turn off, default value is 15 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz 0 20 read-write ret_wait Power Setting 0x10 32 0x0000000F 0x000FFFFF WAIT wait time for memory retention mode transition, default value is 15 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz 0 20 read-write 2 0x10 soc,cpu0 RESET[%s] no description available 0x1400 control Reset Setting 0x0 32 0x80000000 0xC0000011 FLAG flag represents reset happened from last clear of this bit 0: domain did not edurance reset cycle since last clear of this bit 1: domain enduranced reset cycle since last clear of this bit 31 1 read-write FLAG_WAKE flag represents wakeup reset happened from last clear of this bit 0: domain did not edurance wakeup reset cycle since last clear of this bit 1: domain enduranced wakeup reset cycle since last clear of this bit 30 1 read-write HOLD perform reset and hold in reset, until ths bit cleared by software 0: reset is released for function 1: reset is assert and hold 4 1 read-write RESET perform reset and release imediately 0: reset is released 1 reset is asserted and will release automatically 0 1 read-write config Reset Setting 0x4 32 0x00402003 0x00FFFFFF PRE_WAIT wait cycle numbers before assert reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M 16 8 read-write RSTCLK_NUM reset clock number(must be even number) 0: 0 cycle 1: 0 cycles 2: 2 cycles 3: 2 cycles . . . Note, clock cycle is base on 24M 8 8 read-write POST_WAIT time guard band for reset release 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M 0 8 read-write counter Reset Setting 0xc 32 0x00000000 0x000FFFFF COUNTER self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M 0 20 read-write 1 0x4 clk_top_cpu0 CLOCK_CPU[%s] no description available 0x1800 32 0x00000000 0xD00F07FF GLB_BUSY global busy 0: no changes pending to any clock 1: any of nodes is changing status 31 1 read-only LOC_BUSY local busy 0: a change is pending for current node 1: current node is changing status 30 1 read-only PRESERVE preserve function against global select 0: select global clock setting 1: not select global clock setting 28 1 read-write SUB0_DIV ahb bus divider, the bus clock is generated by cpu_clock/div 0: divider by 1 1: divider by 2 … 16 4 read-write MUX current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3 8 3 read-write DIV clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256 0 8 read-write 32 0x4 clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,rsv5,rsv6,rsv7,rsv8,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1 CLOCK[%s] no description available 0x1804 32 0x00000000 0xD00007FF GLB_BUSY global busy 0: no changes pending to any clock 1: any of nodes is changing status 31 1 read-only LOC_BUSY local busy 0: a change is pending for current node 1: current node is changing status 30 1 read-only PRESERVE preserve function against global select 0: select global clock setting 1: not select global clock setting 28 1 read-write MUX current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3 8 3 read-write DIV clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256 0 8 read-write 2 0x4 clk_top_adc0,clk_top_adc1 ADCCLK[%s] no description available 0x1c00 32 0x00000000 0xD0000100 GLB_BUSY global busy 0: no changes pending to any clock 1: any of nodes is changing status 31 1 read-only LOC_BUSY local busy 0: a change is pending for current node 1: current node is changing status 30 1 read-only PRESERVE preserve function against global select 0: select global clock setting 1: not select global clock setting 28 1 read-write MUX current mux 0: ahb0 clock N 1: ana clock 8 1 read-write 2 0x4 clk_top_dac0,clk_top_dac1 DACCLK[%s] no description available 0x1c08 32 0x00000000 0xD0000100 GLB_BUSY global busy 0: no changes pending to any clock 1: any of nodes is changing status 31 1 read-only LOC_BUSY local busy 0: a change is pending for current node 1: current node is changing status 30 1 read-only PRESERVE preserve function against global select 0: select global clock setting 1: not select global clock setting 28 1 read-write MUX current mux 0: ahb0 clock N 1: ana clock 8 1 read-write global00 Clock senario 0x2000 32 0x00000000 0x000000FF MUX global clock override request bit0: override to preset0 bit1: override to preset1 bit2: override to preset2 bit3: override to preset3 bit4: override to preset4 bit5: override to preset5 bit6: override to preset6 bit7: override to preset7 0 8 read-write 4 0x20 slice0,slice1,slice2,slice3 MONITOR[%s] no description available 0x2400 control Clock measure and monitor control 0x0 32 0x00000000 0x89FFD7FF VALID result is ready for read 0: not ready 1: result is ready 31 1 read-write DIV_BUSY divider is applying new setting 27 1 read-only OUTEN enable clock output 24 1 read-write DIV output divider 16 8 read-write HIGH clock frequency higher than upper limit 15 1 read-write LOW clock frequency lower than lower limit 14 1 read-write START start measurement 12 1 read-write MODE work mode, 0: register value will be compared to measurement 1: upper and lower value will be recordered in register 10 1 read-write ACCURACY measurement accuracy, 0: resolution is 1kHz 1: resolution is 1Hz 9 1 read-write REFERENCE reference clock selection, 0: 32k 1: 24M 8 1 read-write SELECTION clock measurement selection 0 8 read-write current Clock measure result 0x4 32 0x00000000 0xFFFFFFFF FREQUENCY self updating measure result 0 32 read-only low_limit Clock lower limit 0x8 32 0xFFFFFFFF 0xFFFFFFFF FREQUENCY lower frequency 0 32 read-write high_limit Clock upper limit 0xc 32 0x00000000 0xFFFFFFFF FREQUENCY upper frequency 0 32 read-write 1 0x400 cpu0 CPU[%s] no description available 0x2800 LP CPU0 LP control 0x0 32 0x00001000 0xFF013703 WAKE_CNT CPU0 wake up counter, counter satuated at 255, write 0x00 to clear 24 8 read-write HALT halt request for CPU0, 0: CPU0 will start to execute after reset or receive wakeup request 1: CPU0 will not start after reset, or wakeup after WFI 16 1 read-write WAKE CPU0 is waking up 0: CPU0 wake up not asserted 1: CPU0 wake up asserted 13 1 read-only EXEC CPU0 is executing 0: CPU0 is not executing 1: CPU0 is executing 12 1 read-only WAKE_FLAG CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit 0: CPU0 wakeup not happened 1: CPU0 wake up happened 10 1 read-write SLEEP_FLAG CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit 0: CPU0 sleep not happened 1: CPU0 sleep happened 9 1 read-write RESET_FLAG CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit 0: CPU0 reset not happened 1: CPU0 reset happened 8 1 read-write MODE Low power mode, system behavior after WFI 00: CPU clock stop after WFI 01: System enter low power mode after WFI 10: Keep running after WFI 11: reserved 0 2 read-write LOCK CPU0 Lock GPR 0x4 32 0x00000000 0x0000FFFE GPR Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset 2 14 read-write LOCK Lock bit for CPU_LOCK 1 1 read-write 14 0x4 GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 GPR[%s] no description available 0x8 32 0x00000000 0xFFFFFFFF GPR register for software to handle resume, can save resume address or status 0 32 read-write 4 0x4 STATUS0,STATUS1,STATUS2,STATUS3 WAKEUP_STATUS[%s] no description available 0x40 32 0x00000000 0xFFFFFFFF STATUS IRQ values 0 32 read-only 4 0x4 ENABLE0,ENABLE1,ENABLE2,ENABLE3 WAKEUP_ENABLE[%s] no description available 0x80 32 0x00000000 0xFFFFFFFF ENABLE IRQ wakeup enable 0 32 read-write IOC IOC IOC 0xf4040000 0x0 0xe40 registers 456 0x8 pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,rsv64,rsv65,rsv66,rsv67,rsv68,rsv69,rsv70,rsv71,rsv72,rsv73,rsv74,rsv75,rsv76,rsv77,rsv78,rsv79,rsv80,rsv81,rsv82,rsv83,rsv84,rsv85,rsv86,rsv87,rsv88,rsv89,rsv90,rsv91,rsv92,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,rsv424,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07 PAD[%s] no description available 0x0 FUNC_CTL ALT SELECT 0x0 32 0x00000000 0x0001011F LOOP_BACK force input on 0: disable 1: enable 16 1 read-write ANALOG select analog pin in pad 0: disable 1: enable 8 1 read-write ALT_SELECT alt select 0: ALT0 1: ALT1 ... 31:ALT31 0 5 read-write PAD_CTL PAD SETTINGS 0x4 32 0x01010056 0x01370177 HYS schmitt trigger enable 0: disable 1: enable 24 1 read-write PRS select pull up/down internal resistance strength: For pull down, only have 100 Kohm resistance For pull up: 00: 100 KOhm 01: 47 KOhm 10: 22 KOhm 11: 22 KOhm 20 2 read-write PS pull select 0: pull down 1: pull up 18 1 read-write PE pull enable 0: pull disable 1: pull enable 17 1 read-write KE keeper capability enable 0: keeper disable 1: keeper enable 16 1 read-write OD open drain 0: open drain disable 1: open drain enable 8 1 read-write SR slew rate 0: Slow slew rate 1: Fast slew rate 6 1 read-write SPD additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise 00: Slow frequency slew rate(50Mhz) 01: Medium frequency slew rate(100 Mhz) 10: Fast frequency slew rate(150 Mhz) 11: Max frequency slew rate(200Mhz) 4 2 read-write DS drive strength 1.8V Mode: 000: 260 Ohm 001: 260 Ohm 010: 130 Ohm 011: 88 Ohm 100: 65 Ohm 101: 52 Ohm 110: 43 Ohm 111: 37 Ohm 3.3V Mode: 000: 157 Ohm 001: 157 Ohm 010: 78 Ohm 011: 53 Ohm 100: 39 Ohm 101: 32 Ohm 110: 26 Ohm 111: 23 Ohm 0 3 read-write PIOC PIOC IOC 0xf4118000 PLLCTLV2 PLLCTLV2 PLLCTLV2 0xf40c0000 0x0 0x200 registers XTAL OSC configuration 0x0 32 0x0001FFFF 0xB00FFFFF BUSY Busy flag 0: Oscillator is working or shutdown 1: Oscillator is changing status 31 1 read-only RESPONSE Crystal oscillator status 0: Oscillator is not stable 1: Oscillator is stable for use 29 1 read-only ENABLE Crystal oscillator enable status 0: Oscillator is off 1: Oscillator is on 28 1 read-only RAMP_TIME Rampup time of XTAL oscillator in cycles of RC24M clock 0: 0 cycle 1: 1 cycle 2: 2 cycle 1048575: 1048575 cycles 0 20 read-write 3 0x80 pll0,pll1,pll2 PLL[%s] no description available 0x80 MFI PLL0 multiple register 0x0 32 0x00000010 0xB000007F BUSY Busy flag 0: PLL is stable or shutdown 1: PLL is changing status 31 1 read-only RESPONSE PLL status 0: PLL is not stable 1: PLL is stable for use 29 1 read-only ENABLE PLL enable status 0: PLL is off 1: PLL is on 28 1 read-only MFI loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) 0-15: invalid 16: divide by 16 17: divide by17 . . . 42: divide by 42 43~:invalid 0 7 read-write MFN PLL0 fraction numerator register 0x4 32 0x09896800 0x3FFFFFFF MFN Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. 0 30 read-write MFD PLL0 fraction demoninator register 0x8 32 0x0E4E1C00 0x3FFFFFFF MFD Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. 0 30 read-write SS_STEP PLL0 spread spectrum step register 0xc 32 0x00000000 0x3FFFFFFF STEP Step of spread spectrum modulator. This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. 0 30 read-write SS_STOP PLL0 spread spectrum stop register 0x10 32 0x00000000 0x3FFFFFFF STOP Stop point of spread spectrum modulator This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. 0 30 read-write CONFIG PLL0 confguration register 0x14 32 0x00000000 0x00000101 SPREAD Enable spread spectrum function. This field supports changing during PLL running. 8 1 read-write REFSEL Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. 0: XTAL24M 1: IRC24M 0 1 read-write LOCKTIME PLL0 lock time register 0x18 32 0x000009C4 0x0000FFFF LOCKTIME Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. 0 16 read-write STEPTIME PLL0 step time register 0x1c 32 0x000009C4 0x0000FFFF STEPTIME Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. 0 16 read-write ADVANCED PLL0 advance configuration register 0x20 32 0x00000000 0x11000000 SLOW Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. 0: fast lock enabled, lock time is 100us 1: fast lock disabled, lock time is 400us 28 1 read-write DITHER Enable dither function 24 1 read-write 3 0x4 DIV0,DIV1,DIV2 DIV[%s] no description available 0x40 32 0x00000000 0xB000003F BUSY Busy flag 0: divider is working 1: divider is changing status 31 1 read-only RESPONSE Divider response status 0: Divider is not stable 1: Divider is stable for use 29 1 read-only ENABLE Divider enable status 0: Divider is off 1: Divider is on 28 1 read-only DIV Divider factor, divider factor is DIV/5 + 1 0: divide by 1 1: divide by 1.2 2: divide by 1.4 . . . 63: divide by 13.6 0 6 read-write PPOR PPOR PPOR 0xf4100000 0x0 0x20 registers RESET_FLAG flag indicate reset source 0x0 32 0x00000000 0xFFFFFFFF FLAG reset reason of last hard reset, write 1 to clear each bit 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software 0 32 write-only RESET_STATUS reset source status 0x4 32 0x00000000 0xFFFFFFFF STATUS current status of reset sources 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software 0 32 read-only RESET_HOLD reset hold attribute 0x8 32 0x00000000 0xFFFFFFFF HOLD hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software 0 32 read-write RESET_ENABLE reset source enable 0xc 32 0xFFFFFFFF 0xFFFFFFFF ENABLE enable of reset sources 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software 0 32 read-write RESET_TYPE reset type triggered by reset 0x10 32 0x00000000 0xFFFFFFFF TYPE reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software 0 32 read-write SOFTWARE_RESET Software reset counter 0x1c 32 0x00000000 0xFFFFFFFF COUNTER counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset 0 32 read-write PCFG PCFG PMU 0xf4104000 0x0 0x70 registers BANDGAP BANGGAP control 0x0 32 0x00101010 0x801F1F1F VBG_TRIMMED Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: bandgap is not trimmed 1: bandgap is trimmed 31 1 read-write VBG_1P0_TRIM Banggap 1.0V output trim value 16 5 read-write VBG_P65_TRIM Banggap 1.0V output trim value 8 5 read-write VBG_P50_TRIM Banggap 1.0V output trim value 0 5 read-write LDO1P1 1V LDO config 0x4 32 0x0000044C 0x00000FFF VOLT LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. 700: 700mV 720: 720mV . . . 1320:1320mV 0 12 read-write LDO2P5 2.5V LDO config 0x8 32 0x000009C4 0x10010FFF READY Ready flag, will set 1ms after enabled or voltage change 0: LDO is not ready for use 1: LDO is ready 28 1 read-only ENABLE LDO enable 0: turn off LDO 1: turn on LDO 16 1 read-write VOLT LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. 2125: 2125mV 2150: 2150mV . . . 2900:2900mV 0 12 read-write DCDC_MODE DCDC mode select 0x10 32 0x0001047E 0x10070FFF READY Ready flag 0: DCDC is applying new change 1: DCDC is ready 28 1 read-only MODE DCDC work mode XX0: turn off 001: basic mode 011: generic mode 101: automatic mode 111: expert mode 16 3 read-write VOLT DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV 0 12 read-write DCDC_LPMODE DCDC low power mode 0x14 32 0x00000384 0x00000FFF STBY_VOLT DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV 0 12 read-write DCDC_PROT DCDC protection 0x18 32 0x00000010 0x11018191 ILIMIT_LP over current setting for low power mode 0:250mA 1:200mA 28 1 read-write OVERLOAD_LP over current in low power mode 0: current is below setting 1: overcurrent happened in low power mode 24 1 read-only POWER_LOSS_FLAG power loss 0: input power is good 1: input power is too low 16 1 read-only DISABLE_OVERVOLTAGE output over voltage protection 0: protection enabled, DCDC will shut down is output voltage is unexpected high 1: protection disabled, DCDC continue to adjust output voltage 15 1 read-write OVERVOLT_FLAG output over voltage flag 0: output is normal 1: output is unexpected high 8 1 read-only DISABLE_SHORT disable output short circuit protection 0: short circuits protection enabled, DCDC shut down if short circuit on output detected 1: short circuit protection disabled 7 1 read-write SHORT_CURRENT short circuit current setting 0: 2.0A, 1: 1.3A 4 1 read-write SHORT_FLAG short circuit flag 0: current is within limit 1: short circuits detected 0 1 read-only DCDC_CURRENT DCDC current estimation 0x1c 32 0x00000000 0x0000811F ESTI_EN enable current measure 15 1 read-write VALID Current level valid 0: data is invalid 1: data is valid 8 1 read-only LEVEL DCDC current level, current level is num * 50mA 0 5 read-only DCDC_ADVMODE DCDC advance setting 0x20 32 0x03120040 0x073F007F EN_RCSCALE Enable RC scale 24 3 read-write DC_C Loop C number 20 2 read-write DC_R Loop R number 16 4 read-write EN_FF_DET enable feed forward detect 0: feed forward detect is disabled 1: feed forward detect is enabled 6 1 read-write EN_FF_LOOP enable feed forward loop 0: feed forward loop is disabled 1: feed forward loop is enabled 5 1 read-write EN_AUTOLP enable auto enter low power mode 0: do not enter low power mode 1: enter low power mode if current is detected low 4 1 read-write EN_DCM_EXIT avoid over voltage 0: stay in DCM mode when voltage excess 1: change to CCM mode when voltage excess 3 1 read-write EN_SKIP enable skip on narrow pulse 0: do not skip narrow pulse 1: skip narrow pulse 2 1 read-write EN_IDLE enable skip when voltage is higher than threshold 0: do not skip 1: skip if voltage is excess 1 1 read-write EN_DCM DCM mode 0: CCM mode 1: DCM mode 0 1 read-write DCDC_ADVPARAM DCDC advance parameter 0x24 32 0x00006E1C 0x00007F7F MIN_DUT minimum duty cycle 8 7 read-write MAX_DUT maximum duty cycle 0 7 read-write DCDC_MISC DCDC misc parameter 0x28 32 0x00070100 0x13170317 EN_HYST hysteres enable 28 1 read-write HYST_SIGN hysteres sign 25 1 read-write HYST_THRS hysteres threshold 24 1 read-write RC_SCALE Loop RC scale threshold 20 1 read-write DC_FF Loop feed forward number 16 3 read-write OL_THRE overload for threshold for lod power mode 8 2 read-write OL_HYST current hysteres range 0: 12.5mV 1: 25mV 4 1 read-write DELAY enable delay 0: delay disabled, 1: delay enabled 2 1 read-write CLK_SEL clock selection 0: select DCDC internal oscillator 1: select RC24M oscillator 1 1 read-write EN_STEP enable stepping in voltage change 0: stepping disabled, 1: steping enabled 0 1 read-write DCDC_DEBUG DCDC Debug 0x2c 32 0x00005DBF 0x000FFFFF UPDATE_TIME DCDC voltage change time in 24M clock cycles, default value is 1mS 0 20 read-write DCDC_START_TIME DCDC ramp time 0x30 32 0x0001193F 0x000FFFFF START_TIME Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS 0 20 read-write DCDC_RESUME_TIME DCDC resume time 0x34 32 0x00008C9F 0x000FFFFF RESUME_TIME Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS 0 20 read-write POWER_TRAP SOC power trap 0x40 32 0x00000000 0x80010001 TRIGGERED Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. 0: low power trap is not triggered 1: low power trap triggered 31 1 read-write RETENTION DCDC enter standby mode, which will reduce voltage for memory content retention 0: Shutdown DCDC 1: reduce DCDC voltage 16 1 read-write TRAP Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered 0: trap not enabled, pmic side low power function disabled 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. 0 1 read-write WAKE_CAUSE Wake up source 0x44 32 0x00000000 0xFFFFFFFF CAUSE wake up cause, each bit represents one wake up source, write 1 to clear the register bit 0: wake up source is not active during last wakeup 1: wake up source is active furing last wakeup bit 0: pmic_enable bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit31: pin wakeup 0 32 read-write WAKE_MASK Wake up mask 0x48 32 0x00000000 0xFFFFFFFF MASK mask for wake up sources, each bit represents one wakeup source 0: allow source to wake up system 1: disallow source to wakeup system bit 0: pmic_enable bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit31: pin wakeup 0 32 read-write SCG_CTRL Clock gate control in PMIC 0x4c 32 0xFFFFFFFF 0xFFFFFFFF SCG control whether clock being gated during PMIC low power flow, 2 bits for each peripheral 00,01: reserved 10: clock is always off 11: clock is always on bit6-7:gpio bit8-9:ioc bit10-11: timer bit12-13:wdog bit14-15:uart 0 32 read-write RC24M RC 24M config 0x60 32 0x00000310 0x8000071F RC_TRIMMED RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: RC is not trimmed 1: RC is trimmed 31 1 read-write TRIM_C Coarse trim for RC24M, bigger value means faster 8 3 read-write TRIM_F Fine trim for RC24M, bigger value means faster 0 5 read-write RC24M_TRACK RC 24M track mode 0x64 32 0x00000000 0x00010011 SEL24M Select track reference 0: select 32K as reference 1: select 24M XTAL as reference 16 1 read-write RETURN Retrun default value when XTAL loss 0: remain last tracking value 1: switch to default value 4 1 read-write TRACK track mode 0: RC24M free running 1: track RC24M to external XTAL 0 1 read-write TRACK_TARGET RC 24M track target 0x68 32 0x00000000 0xFFFFFFFF PRE_DIV Divider for reference source 16 16 read-write TARGET Target frequency multiplier of divided source 0 16 read-write STATUS RC 24M track status 0x6c 32 0x00000000 0x0011871F SEL32K track is using XTAL32K 0: track is not using XTAL32K 1: track is using XTAL32K 20 1 read-only SEL24M track is using XTAL24M 0: track is not using XTAL24M 1: track is using XTAL24M 16 1 read-only EN_TRIM default value takes effect 0: default value is invalid 1: default value is valid 15 1 read-only TRIM_C default coarse trim value 8 3 read-only TRIM_F default fine trim value 0 5 read-only PGPR0 PGPR0 PGPR 0xf4110000 0x0 0x40 registers PMIC_GPR00 Generic control 0x0 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR01 Generic control 0x4 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR02 Generic control 0x8 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR03 Generic control 0xc 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR04 Generic control 0x10 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR05 Generic control 0x14 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR06 Generic control 0x18 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR07 Generic control 0x1c 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR08 Generic control 0x20 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR09 Generic control 0x24 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR10 Generic control 0x28 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR11 Generic control 0x2c 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR12 Generic control 0x30 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR13 Generic control 0x34 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR14 Generic control 0x38 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR15 Generic control 0x3c 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PGPR1 PGPR1 PGPR 0xf4114000 PDGO PDGO PDGO 0xf4134000 0x0 0x714 registers DGO_TURNOFF trunoff control 0x0 32 0x00000000 0xFFFFFFFF COUNTER trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. 0 32 write-only DGO_RC32K_CFG RC32K CLOCK 0x4 32 0x00000000 0x80C001FF IRC_TRIMMED IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: irc is not trimmed 1: irc is trimmed 31 1 read-write CAPEX7_TRIM IRC32K bit 7 23 1 read-write CAPEX6_TRIM IRC32K bit 6 22 1 read-write CAP_TRIM capacitor trim bits 0 9 read-write DGO_GPR00 Generic control 0 0x600 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write DGO_GPR01 Generic control 1 0x604 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write DGO_GPR02 Generic control 2 0x608 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write DGO_GPR03 Generic control 3 0x60c 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write DGO_CTR0 control register 0 0x700 32 0x00000000 0x00010000 RETENTION dgo register status retenion 16 1 read-write DGO_CTR1 control register 1 0x704 32 0x00000000 0x80010001 AOTO_SYS_WAKEUP software wakeup： 0 : wakeup once； 1：auto wakeup Continuously 31 1 read-write WAKEUP_EN permit wakeup pin or software wakeup 16 1 read-write PIN_WAKEUP_STATUS wakeup pin status 0 1 read-only DGO_CTR2 control register 2 0x708 32 0x00000000 0x01010000 RESETN_PULLUP_DISABLE resetn pin pull up disable 24 1 read-write WAKEUP_PULLDN_DISABLE wakeup pin pull down disable 16 1 read-write DGO_CTR3 control register 3 0x70c 32 0x00000000 0xFFFFFFFF WAKEUP_COUNTER software wakeup counter 0 32 read-write DGO_CTR4 control register 4 0x710 32 0x00000000 0x00000003 BANDGAP_LESS_POWER Banggap work in power save mode, banggap function normally 0: banggap works in high performance mode 1: banggap works in power saving mode 1 1 read-write BANDGAP_LP_MODE Banggap work in low power mode, banggap function limited 0: banggap works in normal mode 1: banggap works in low power mode 0 1 read-write