/*
 * Copyright 2018 NXP
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * o Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
 *
 * o Redistributions in binary form must reproduce the above copyright notice, this
 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
 *
 * o Neither the name of the copyright holder nor the names of its
 *   contributors may be used to endorse or promote products derived from this
 *   software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

_load_dcdc_trim()
{
  __var ocotp_base;
  __var ocotp_fuse_bank0_base;
  __var dcdc_base;
  __var reg;
  __var trim_value;
  __var dcdc_trim_loaded;
  __var index;

  ocotp_base = 0x401F4000;
  ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
  dcdc_base = 0x40080000;

  dcdc_trim_loaded = 0;

  reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory");
  if (reg & (1<<10))
  {
      // DCDC: REG0->VBG_TRM
      trim_value = (reg & (0x1F << 11)) >> 11;
      reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24);
      __writeMemory32(reg, dcdc_base + 0x4, "Memory");
      dcdc_trim_loaded = 1;
  }

  reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory");
  if (reg & (1<<30))
  {
    index = (reg & (3 << 28)) >> 28;
    if (index < 4)
    {
      // DCDC: REG3->TRG 
      reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index);
      __writeMemory32(reg, dcdc_base + 0xC, "Memory");
      dcdc_trim_loaded = 1;
    }
  }

  if (dcdc_trim_loaded)
  {
      // delay 1ms for dcdc to get stable
      __delay(1);
      __message "DCDC trim value loaded.\n";
  }

}

execUserPreload()
{
  _load_dcdc_trim();   
}

execUserReset()
{
  _load_dcdc_trim();   
}