#ifndef __SEP4020_H #define __SEP4020_H #include <rtthread.h> /*Core definations*/ #define SVCMODE #define Mode_USR 0x10 #define Mode_FIQ 0x11 #define Mode_IRQ 0x12 #define Mode_SVC 0x13 #define Mode_ABT 0x17 #define Mode_UND 0x1B #define Mode_SYS 0x1F /* * ¸÷Ä£¿é¼Ä´æÆ÷»ùÖµ */ #define ESRAM_BASE 0x04000000 #define INTC_BASE 0x10000000 #define PMU_BASE 0x10001000 #define RTC_BASE 0x10002000 #define WD_BASE 0x10002000 #define TIMER_BASE 0x10003000 #define PWM_BASE 0x10004000 #define UART0_BASE 0X10005000 #define UART1_BASE 0X10006000 #define UART2_BASE 0X10007000 #define UART3_BASE 0X10008000 #define SSI_BASE 0X10009000 #define I2S_BASE 0x1000A000 #define MMC_BASE 0x1000B000 #define SD_BASE 0x1000B000 #define SMC0_BASE 0x1000C000 #define SMC1_BASE 0x1000D000 #define USBD_BASE 0x1000E000 #define GPIO_BASE 0x1000F000 #define EMI_BASE 0x11000000 #define DMAC_BASE 0x11001000 #define LCDC_BASE 0x11002000 #define MAC_BASE 0x11003000 #define AMBA_BASE 0x11005000 /* * INTCÄ£¿é * »ùÖ·: 0x10000000 */ #define INTC_IER (INTC_BASE+0X000) /* IRQÖжÏÔÊÐí¼Ä´æÆ÷ */ #define INTC_IMR (INTC_BASE+0X008) /* IRQÖжÏÆÁ±Î¼Ä´æÆ÷ */ #define INTC_IFR (INTC_BASE+0X010) /* IRQÈí¼þÇ¿ÖÆÖжϼĴæÆ÷ */ #define INTC_IRSR (INTC_BASE+0X018) /* IRQδ´¦ÀíÖжÏ״̬¼Ä´æÆ÷ */ #define INTC_ISR (INTC_BASE+0X020) /* IRQÖжÏ״̬¼Ä´æÆ÷ */ #define INTC_IMSR (INTC_BASE+0X028) /* IRQÆÁ±ÎÖжÏ״̬¼Ä´æÆ÷ */ #define INTC_IFSR (INTC_BASE+0X030) /* IRQÖжÏ×îÖÕ״̬¼Ä´æÆ÷ */ #define INTC_FIER (INTC_BASE+0X0C0) /* FIQÖжÏÔÊÐí¼Ä´æÆ÷ */ #define INTC_FIMR (INTC_BASE+0X0C4) /* FIQÖжÏÆÁ±Î¼Ä´æÆ÷ */ #define INTC_FIFR (INTC_BASE+0X0C8) /* FIQÈí¼þÇ¿ÖÆÖжϼĴæÆ÷ */ #define INTC_FIRSR (INTC_BASE+0X0CC) /* FIQδ´¦ÀíÖжÏ״̬¼Ä´æÆ÷ */ #define INTC_FISR (INTC_BASE+0X0D0) /* FIQÖжÏ״̬¼Ä´æÆ÷ */ #define INTC_FIFSR (INTC_BASE+0X0D4) /* FIQÖжÏ×îÖÕ״̬¼Ä´æÆ÷ */ #define INTC_IPLR (INTC_BASE+0X0D8) /* IRQÖжÏÓÅÏȼ¶¼Ä´æÆ÷ */ #define INTC_ICR1 (INTC_BASE+0X0DC) /* IRQÄÚ²¿ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 */ #define INTC_ICR2 (INTC_BASE+0X0E0) /* IRQÄÚ²¿ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷2 */ #define INTC_EXICR1 (INTC_BASE+0X0E4) /* IRQÍⲿÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 */ #define INTC_EXICR2 (INTC_BASE+0X0E8) /* IRQÍⲿÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷2 */ /* * PMUÄ£¿é * »ùÖ·: 0x10001000 */ #define PMU_PLTR (PMU_BASE+0X000) /* PLLµÄÎȶ¨¹ý¶Éʱ¼ä */ #define PMU_PMCR (PMU_BASE+0X004) /* ϵͳÖ÷ʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ */ #define PMU_PUCR (PMU_BASE+0X008) /* USBʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ */ #define PMU_PCSR (PMU_BASE+0X00C) /* ÄÚ²¿Ä£¿éʱÖÓÔ´¹©¸øµÄ¿ØÖƼĴæÆ÷ */ #define PMU_PDSLOW (PMU_BASE+0X010) /* SLOW״̬ÏÂʱÖӵķÖƵÒò×Ó */ #define PMU_PMDR (PMU_BASE+0X014) /* оƬ¹¤×÷ģʽ¼Ä´æÆ÷ */ #define PMU_RCTR (PMU_BASE+0X018) /* Reset¿ØÖƼĴæÆ÷ */ #define PMU_CLRWAKUP (PMU_BASE+0X01C) /* WakeUpÇå³ý¼Ä´æÆ÷ */ /* * RTCÄ£¿é * »ùÖ·: 0x10002000 */ #define RTC_STA_YMD (RTC_BASE+0X000) /* Äê, ÔÂ, ÈÕ¼ÆÊý¼Ä´æÆ÷ */ #define RTC_STA_HMS (RTC_BASE+0X004) /* Сʱ, ·ÖÖÓ, Ãë¼Ä´æÆ÷ */ #define RTC_ALARM_ALL (RTC_BASE+0X008) /* ¶¨Ê±ÔÂ, ÈÕ, ʱ, ·Ö¼Ä´æÆ÷ */ #define RTC_CTR (RTC_BASE+0X00C) /* ¿ØÖƼĴæÆ÷ */ #define RTC_INT_EN (RTC_BASE+0X010) /* ÖжÏʹÄܼĴæÆ÷ */ #define RTC_INT_STS (RTC_BASE+0X014) /* ÖжÏ״̬¼Ä´æÆ÷ */ #define RTC_SAMP (RTC_BASE+0X018) /* ²ÉÑùÖÜÆڼĴæÆ÷ */ #define RTC_WD_CNT (RTC_BASE+0X01C) /* Watch-Dog¼ÆÊýÖµ¼Ä´æÆ÷ */ #define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog·þÎñ¼Ä´æÆ÷ */ #define RTC_CONFIG_CHECK (RTC_BASE+0X024) /* ÅäÖÃʱ¼äÈ·ÈϼĴæÆ÷ (ÔÚÅäÖÃʱ¼ä֮ǰÏÈд0xaaaaaaaa) */ #define RTC_KEY0 (RTC_BASE+0X02C) /* ÃÜÔ¿¼Ä´æÆ÷ */ /* * TIMERÄ£¿é * »ùÖ·: 0x10003000 */ #define TIMER_T1LCR (TIMER_BASE+0X000) /* ͨµÀ1¼ÓÔؼÆÊý¼Ä´æÆ÷ */ #define TIMER_T1CCR (TIMER_BASE+0X004) /* ͨµÀ1µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ #define TIMER_T1CR (TIMER_BASE+0X008) /* ͨµÀ1¿ØÖƼĴæÆ÷ */ #define TIMER_T1ISCR (TIMER_BASE+0X00C) /* ͨµÀ1ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define TIMER_T1IMSR (TIMER_BASE+0X010) /* ͨµÀ1ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ #define TIMER_T2LCR (TIMER_BASE+0X020) /* ͨµÀ2¼ÓÔؼÆÊý¼Ä´æÆ÷ */ #define TIMER_T2CCR (TIMER_BASE+0X024) /* ͨµÀ2µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ #define TIMER_T2CR (TIMER_BASE+0X028) /* ͨµÀ2¿ØÖƼĴæÆ÷ */ #define TIMER_T2ISCR (TIMER_BASE+0X02C) /* ͨµÀ2ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define TIMER_T2IMSR (TIMER_BASE+0X030) /* ͨµÀ2ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ #define TIMER_T3LCR (TIMER_BASE+0X040) /* ͨµÀ3¼ÓÔؼÆÊý¼Ä´æÆ÷ */ #define TIMER_T3CCR (TIMER_BASE+0X044) /* ͨµÀ3µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ #define TIMER_T3CR (TIMER_BASE+0X048) /* ͨµÀ3¿ØÖƼĴæÆ÷ */ #define TIMER_T3ISCR (TIMER_BASE+0X04C) /* ͨµÀ3ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define TIMER_T3IMSR (TIMER_BASE+0X050) /* ͨµÀ3ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ #define TIMER_T3CAPR (TIMER_BASE+0X054) /* ͨµÀ3²¶»ñ¼Ä´æÆ÷ */ #define TIMER_T4LCR (TIMER_BASE+0X060) /* ͨµÀ4¼ÓÔؼÆÊý¼Ä´æÆ÷ */ #define TIMER_T4CCR (TIMER_BASE+0X064) /* ͨµÀ4µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ #define TIMER_T4CR (TIMER_BASE+0X068) /* ͨµÀ4¿ØÖƼĴæÆ÷ */ #define TIMER_T4ISCR (TIMER_BASE+0X06C) /* ͨµÀ4ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define TIMER_T4IMSR (TIMER_BASE+0X070) /* ͨµÀ4ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ #define TIMER_T4CAPR (TIMER_BASE+0X074) /* ͨµÀ4²¶»ñ¼Ä´æÆ÷ */ #define TIMER_T5LCR (TIMER_BASE+0X080) /* ͨµÀ5¼ÓÔؼÆÊý¼Ä´æÆ÷ */ #define TIMER_T5CCR (TIMER_BASE+0X084) /* ͨµÀ5µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ #define TIMER_T5CR (TIMER_BASE+0X088) /* ͨµÀ5¿ØÖƼĴæÆ÷ */ #define TIMER_T5ISCR (TIMER_BASE+0X08C) /* ͨµÀ5ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define TIMER_T5IMSR (TIMER_BASE+0X090) /* ͨµÀ5ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ #define TIMER_T5CAPR (TIMER_BASE+0X094) /* ͨµÀ5²¶»ñ¼Ä´æÆ÷ */ #define TIMER_T6LCR (TIMER_BASE+0X0A0) /* ͨµÀ6¼ÓÔؼÆÊý¼Ä´æÆ÷ */ #define TIMER_T6CCR (TIMER_BASE+0X0A4) /* ͨµÀ6µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ #define TIMER_T6CR (TIMER_BASE+0X0A8) /* ͨµÀ6¿ØÖƼĴæÆ÷ */ #define TIMER_T6ISCR (TIMER_BASE+0X0AC) /* ͨµÀ6ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define TIMER_T6IMSR (TIMER_BASE+0X0B0) /* ͨµÀ6ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ #define TIMER_T6CAPR (TIMER_BASE+0X0B4) /* ͨµÀ6²¶»ñ¼Ä´æÆ÷ */ #define TIMER_T7LCR (TIMER_BASE+0X0C0) /* ͨµÀ7¼ÓÔؼÆÊý¼Ä´æÆ÷ */ #define TIMER_T7CCR (TIMER_BASE+0X0C4) /* ͨµÀ7µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ #define TIMER_T7CR (TIMER_BASE+0X0C8) /* ͨµÀ7¿ØÖƼĴæÆ÷ */ #define TIMER_T7ISCR (TIMER_BASE+0X0CC) /* ͨµÀ7ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define TIMER_T7IMSR (TIMER_BASE+0X0D0) /* ͨµÀ7ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ #define TIMER_T8LCR (TIMER_BASE+0X0E0) /* ͨµÀ8¼ÓÔؼÆÊý¼Ä´æÆ÷ */ #define TIMER_T8CCR (TIMER_BASE+0X0E4) /* ͨµÀ8µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ #define TIMER_T8CR (TIMER_BASE+0X0E8) /* ͨµÀ8¿ØÖƼĴæÆ÷ */ #define TIMER_T8ISCR (TIMER_BASE+0X0EC) /* ͨµÀ8ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define TIMER_T8IMSR (TIMER_BASE+0X0F0) /* ͨµÀ8ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ #define TIMER_T9LCR (TIMER_BASE+0X100) /* ͨµÀ9¼ÓÔؼÆÊý¼Ä´æÆ÷ */ #define TIMER_T9CCR (TIMER_BASE+0X104) /* ͨµÀ9µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ #define TIMER_T9CR (TIMER_BASE+0X108) /* ͨµÀ9¿ØÖƼĴæÆ÷ */ #define TIMER_T9ISCR (TIMER_BASE+0X10C) /* ͨµÀ9ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define TIMER_T9IMSR (TIMER_BASE+0X110) /* ͨµÀ9ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ #define TIMER_T10LCR (TIMER_BASE+0X120) /* ͨµÀ10¼ÓÔؼÆÊý¼Ä´æÆ÷ */ #define TIMER_T10CCR (TIMER_BASE+0X124) /* ͨµÀ10µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ #define TIMER_T10CR (TIMER_BASE+0X128) /* ͨµÀ10¿ØÖƼĴæÆ÷ */ #define TIMER_T10ISCR (TIMER_BASE+0X12C) /* ͨµÀ10ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define TIMER_T10IMSR (TIMER_BASE+0X130) /* ͨµÀ10ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ #define TIMER_TIMSR (TIMER_BASE+0X140) /* TIMERÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ #define TIMER_TISCR (TIMER_BASE+0X144) /* TIMERÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define TIMER_TISR (TIMER_BASE+0X148) /* TIMERÖжÏ״̬¼Ä´æÆ÷ */ /* * PWMÄ£¿é * »ùÖ·: 0x10004000 */ #define PWM0_CTRL (PWM_BASE+0X000) /* PWM0¿ØÖƼĴæÆ÷ */ #define PWM0_DIV (PWM_BASE+0X004) /* PWM0·ÖƵ¼Ä´æÆ÷ */ #define PWM0_PERIOD (PWM_BASE+0X008) /* PWM0ÖÜÆڼĴæÆ÷ */ #define PWM0_DATA (PWM_BASE+0X00C) /* PWM0Êý¾Ý¼Ä´æÆ÷ */ #define PWM0_CNT (PWM_BASE+0X010) /* PWM0¼ÆÊý¼Ä´æÆ÷ */ #define PWM0_STATUS (PWM_BASE+0X014) /* PWM0״̬¼Ä´æÆ÷ */ #define PWM1_CTRL (PWM_BASE+0X020) /* PWM1¿ØÖƼĴæÆ÷ */ #define PWM1_DIV (PWM_BASE+0X024) /* PWM1·ÖƵ¼Ä´æÆ÷ */ #define PWM1_PERIOD (PWM_BASE+0X028) /* PWM1ÖÜÆڼĴæÆ÷ */ #define PWM1_DATA (PWM_BASE+0X02C) /* PWM1Êý¾Ý¼Ä´æÆ÷ */ #define PWM1_CNT (PWM_BASE+0X030) /* PWM1¼ÆÊý¼Ä´æÆ÷ */ #define PWM1_STATUS (PWM_BASE+0X034) /* PWM1״̬¼Ä´æÆ÷ */ #define PWM2_CTRL (PWM_BASE+0X040) /* PWM2¿ØÖƼĴæÆ÷ */ #define PWM2_DIV (PWM_BASE+0X044) /* PWM2·ÖƵ¼Ä´æÆ÷ */ #define PWM2_PERIOD (PWM_BASE+0X048) /* PWM2ÖÜÆڼĴæÆ÷ */ #define PWM2_DATA (PWM_BASE+0X04C) /* PWM2Êý¾Ý¼Ä´æÆ÷ */ #define PWM2_CNT (PWM_BASE+0X050) /* PWM2¼ÆÊý¼Ä´æÆ÷ */ #define PWM2_STATUS (PWM_BASE+0X054) /* PWM2״̬¼Ä´æÆ÷ */ #define PWM3_CTRL (PWM_BASE+0X060) /* PWM3¿ØÖƼĴæÆ÷ */ #define PWM3_DIV (PWM_BASE+0X064) /* PWM3·ÖƵ¼Ä´æÆ÷ */ #define PWM3_PERIOD (PWM_BASE+0X068) /* PWM3ÖÜÆڼĴæÆ÷ */ #define PWM3_DATA (PWM_BASE+0X06C) /* PWM3Êý¾Ý¼Ä´æÆ÷ */ #define PWM3_CNT (PWM_BASE+0X070) /* PWM3¼ÆÊý¼Ä´æÆ÷ */ #define PWM3_STATUS (PWM_BASE+0X074) /* PWM3״̬¼Ä´æÆ÷ */ #define PWM_INTMASK (PWM_BASE+0X080) /* PWMÖжÏÆÁ±Î¼Ä´æÆ÷ */ #define PWM_INT (PWM_BASE+0X084) /* PWMÖжϼĴæÆ÷ */ #define PWM_ENABLE (PWM_BASE+0X088) /* PWMʹÄܼĴæÆ÷ */ /* * UART0Ä£¿é * »ùÖ·: 0x10005000 */ #define UART0_DLBL (UART0_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ #define UART0_RXFIFO (UART0_BASE+0X000) /* ½ÓÊÕFIFO */ #define UART0_TXFIFO (UART0_BASE+0X000) /* ·¢ËÍFIFO */ #define UART0_DLBH (UART0_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ #define UART0_IER (UART0_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ #define UART0_IIR (UART0_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ #define UART0_FCR (UART0_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ #define UART0_LCR (UART0_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ #define UART0_MCR (UART0_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ #define UART0_LSR (UART0_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ #define UART0_MSR (UART0_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ /* * UART1Ä£¿é * »ùÖ·: 0x10006000 */ #define UART1_DLBL (UART1_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ #define UART1_RXFIFO (UART1_BASE+0X000) /* ½ÓÊÕFIFO */ #define UART1_TXFIFO (UART1_BASE+0X000) /* ·¢ËÍFIFO */ #define UART1_DLBH (UART1_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ #define UART1_IER (UART1_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ #define UART1_IIR (UART1_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ #define UART1_FCR (UART1_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ #define UART1_LCR (UART1_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ #define UART1_MCR (UART1_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ #define UART1_LSR (UART1_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ #define UART1_MSR (UART1_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ /* * UART2Ä£¿é * »ùÖ·: 0x10007000 */ #define UART2_DLBL (UART2_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ #define UART2_RXFIFO (UART2_BASE+0X000) /* ½ÓÊÕFIFO */ #define UART2_TXFIFO (UART2_BASE+0X000) /* ·¢ËÍFIFO */ #define UART2_DLBH (UART2_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ #define UART2_IER (UART2_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ #define UART2_IIR (UART2_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ #define UART2_FCR (UART2_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ #define UART2_LCR (UART2_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ #define UART2_MCR (UART2_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ #define UART2_LSR (UART2_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ #define UART2_MSR (UART2_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ /* * UART3Ä£¿é * »ùÖ·: 0x10008000 */ #define UART3_DLBL (UART3_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ #define UART3_RXFIFO (UART3_BASE+0X000) /* ½ÓÊÕFIFO */ #define UART3_TXFIFO (UART3_BASE+0X000) /* ·¢ËÍFIFO */ #define UART3_DLBH (UART3_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ #define UART3_IER (UART3_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ #define UART3_IIR (UART3_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ #define UART3_FCR (UART3_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ #define UART3_LCR (UART3_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ #define UART3_MCR (UART3_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ #define UART3_LSR (UART3_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ #define UART3_MSR (UART3_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ /* * SSIÄ£¿é * »ùÖ·: 0x10009000 */ #define SSI_CONTROL0 (SSI_BASE+0X000) /* ¿ØÖƼĴæÆ÷0 */ #define SSI_CONTROL1 (SSI_BASE+0X004) /* ¿ØÖƼĴæÆ÷1 */ #define SSI_SSIENR (SSI_BASE+0X008) /* SSIʹÄܼĴæÆ÷ */ #define SSI_MWCR (SSI_BASE+0X00C) /* Microwire¿ØÖƼĴæÆ÷ */ #define SSI_SER (SSI_BASE+0X010) /* ´ÓÉ豸ʹÄܼĴæÆ÷ */ #define SSI_BAUDR (SSI_BASE+0X014) /* ²¨ÌØÂÊÉèÖüĴæÆ÷ */ #define SSI_TXFTLR (SSI_BASE+0X018) /* ·¢ËÍFIFOãÐÖµ¼Ä´æÆ÷ */ #define SSI_RXFTLR (SSI_BASE+0X01C) /* ½ÓÊÕFIFOãÐÖµ¼Ä´æÆ÷ */ #define SSI_TXFLR (SSI_BASE+0X020) /* ·¢ËÍFIFO״̬¼Ä´æÆ÷ */ #define SSI_RXFLR (SSI_BASE+0X024) /* ½ÓÊÕFIFO״̬¼Ä´æÆ÷ */ #define SSI_SR (SSI_BASE+0X028) /* ״̬¼Ä´æÆ÷ */ #define SSI_IMR (SSI_BASE+0X02C) /* ÖжÏÆÁ±Î¼Ä´æÆ÷ */ #define SSI_ISR (SSI_BASE+0X030) /* ÖжÏ×îÖÕ״̬¼Ä´æÆ÷ */ #define SSI_RISR (SSI_BASE+0X034) /* ÖжÏÔʼ״̬¼Ä´æÆ÷ */ #define SSI_TXOICR (SSI_BASE+0X038) /* ·¢ËÍFIFOÉÏÒçÖжÏÇå³ý¼Ä´æÆ÷ */ #define SSI_RXOICR (SSI_BASE+0X03C) /* ½ÓÊÕFIFOÉÏÒçÖжÏÇå³ý¼Ä´æÆ÷ */ #define SSI_RXUICR (SSI_BASE+0X040) /* ½ÓÊÕFIFOÏÂÒçÖжÏÇå³ý¼Ä´æÆ÷ */ #define SSI_ICR (SSI_BASE+0X02C) /* ÖжÏÇå³ý¼Ä´æÆ÷ */ #define SSI_DMACR (SSI_BASE+0X04C) /* DMA¿ØÖƼĴæÆ÷ */ #define SSI_DMATDLR (SSI_BASE+0X050) /* DMA·¢ËÍ״̬¼Ä´æÆ÷ */ #define SSI_DMARDLR (SSI_BASE+0X054) /* DMA½ÓÊÕ״̬¼Ä´æÆ÷ */ #define SSI_DR (SSI_BASE+0X060) /* Êý¾Ý¼Ä´æÆ÷ */ /* * I2SÄ£¿é * »ùÖ·: 0x1000A000 */ #define I2S_CTRL (I2S_BASE+0X000) /* I2S¿ØÖƼĴæÆ÷ */ #define I2S_DATA (I2S_BASE+0X004) /* I2SÊý¾Ý¼Ä´æÆ÷ */ #define I2S_INT (I2S_BASE+0X008) /* I2SÖжϼĴæÆ÷ */ #define I2S_STATUS (I2S_BASE+0X00C) /* I2S״̬¼Ä´æÆ÷ */ /* * SDÄ£¿é * »ùÖ·: 0x1000B000 */ #define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIOʱÖÓ¿ØÖƼĴæÆ÷ */ #define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIOÈí¼þ¸´Î»¼Ä´æÆ÷ */ #define SDC_ARGUMENT (SD_BASE+0X08) /* SDIOÃüÁî²ÎÊý¼Ä´æÆ÷ */ #define SDC_COMMAND (SD_BASE+0X0C) /* SDIOÃüÁî¿ØÖƼĴæÆ÷ */ #define SDC_BLOCK_SIZE (SD_BASE+0X10) /* SDIOÊý¾Ý¿é³¤¶È¼Ä´æÆ÷ */ #define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIOÊý¾Ý¿éÊýÄ¿¼Ä´æÆ÷ */ #define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO´«ÊäģʽѡÔñ¼Ä´æÆ÷ */ #define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIOÏìÓ¦¼Ä´æÆ÷0 */ #define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIOÏìÓ¦¼Ä´æÆ÷1 */ #define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIOÏìÓ¦¼Ä´æÆ÷2 */ #define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIOÏìÓ¦¼Ä´æÆ÷3 */ #define SDC_READ_TIMEOUT_CONTROL (SD_BASE+0X2c) /* SDIO¶Á³¬Ê±¿ØÖƼĴæÆ÷ */ #define SDC_INTERRUPT_STATUS (SD_BASE+0X30) /* SDIOÖжÏ״̬¼Ä´æÆ÷ */ #define SDC_INTERRUPT_STATUS_MASK (SD_BASE+0X34) /* SDIOÖжÏ״̬ÆÁ±Î¼Ä´æÆ÷ */ #define SDC_READ_BUFER_ACCESS (SD_BASE+0X38) /* SDIO½ÓÊÕFIFO */ #define SDC_WRITE_BUFER_ACCESS (SD_BASE+0X3c) /* SDIO·¢ËÍFIFO */ /* * SMC0Ä£¿é * »ùÖ·: 0x1000C000 */ #define SMC0_CTRL (SMC0_BASE+0X000) /* SMC0¿ØÖƼĴæÆ÷ */ #define SMC0_INT (SMC0_BASE+0X004) /* SMC0ÖжϼĴæÆ÷ */ #define SMC0_FD (SMC0_BASE+0X008) /* SMC0»ù±¾µ¥ÔªÊ±¼ä¼Ä´æÆ÷ */ #define SMC0_CT (SMC0_BASE+0X00C) /* SMC0×Ö·û´«Êäʱ¼ä¼Ä´æÆ÷ */ #define SMC0_BT (SMC0_BASE+0X010) /* SMC0¿é´«Êäʱ¼ä¼Ä´æÆ÷ */ /* * SMC1Ä£¿é * »ùÖ·: 0x1000D000 */ #define SMC1_CTRL (SMC1_BASE+0X000) /* SMC1¿ØÖƼĴæÆ÷ */ #define SMC1_INT (SMC1_BASE+0X004) /* SMC1ÖжϼĴæÆ÷ */ #define SMC1_FD (SMC1_BASE+0X008) /* SMC1»ù±¾µ¥ÔªÊ±¼ä¼Ä´æÆ÷ */ #define SMC1_CT (SMC1_BASE+0X00C) /* SMC1×Ö·û´«Êäʱ¼ä¼Ä´æÆ÷ */ #define SMC1_BT (SMC1_BASE+0X010) /* SMC1¿é´«Êäʱ¼ä¼Ä´æÆ÷ */ /* * USBDÄ£¿é * »ùÖ·: 0x1000E000 */ #define USBD_PROTOCOLINTR (USBD_BASE+0X000) /* USBÐÒéÖжϼĴæÆ÷ */ #define USBD_INTRMASK (USBD_BASE+0X004) /* USBÖжÏÆÁ±Î¼Ä´æÆ÷ */ #define USBD_INTRCTRL (USBD_BASE+0X008) /* USBÖжÏÀàÐÍ¿ØÖƼĴæÆ÷ */ #define USBD_EPINFO (USBD_BASE+0X00C) /* USB»î¶¯¶Ëµã״̬¼Ä´æÆ÷ */ #define USBD_BCONFIGURATIONVALUE (USBD_BASE+0X010) /* SET_CCONFIGURATION¼Ç¼ */ #define USBD_BMATTRIBUTES (USBD_BASE+0X014) /* µ±Ç°ÅäÖÃÊôÐԼĴæÆ÷ */ #define USBD_DEVSPEED (USBD_BASE+0X018) /* µ±Ç°É豸¹¤×÷ËٶȼĴæÆ÷ */ #define USBD_FRAMENUMBER (USBD_BASE+0X01C) /* ¼Ç¼µ±Ç°SOF°üÄÚµÄÖ¡ºÅ */ #define USBD_EPTRANSACTIONS0 (USBD_BASE+0X020) /* ¼Ç¼Ï´ÎÒªÇóµÄ´«Êä´ÎÊý */ #define USBD_EPTRANSACTIONS1 (USBD_BASE+0X024) /* ¼Ç¼Ï´ÎÒªÇóµÄ´«Êä´ÎÊý */ #define USBD_APPIFUPDATE (USBD_BASE+0X028) /* ½Ó¿ÚºÅ¿ìËÙ¸üмĴæÆ÷ */ #define USBD_CFGINTERFACE0 (USBD_BASE+0X02C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE1 (USBD_BASE+0X030) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE2 (USBD_BASE+0X034) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE3 (USBD_BASE+0X038) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE4 (USBD_BASE+0X03C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE5 (USBD_BASE+0X040) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE6 (USBD_BASE+0X044) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE7 (USBD_BASE+0X048) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE8 (USBD_BASE+0X04C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE9 (USBD_BASE+0X050) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE10 (USBD_BASE+0X054) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE11 (USBD_BASE+0X058) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE12 (USBD_BASE+0X05C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE13 (USBD_BASE+0X060) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE14 (USBD_BASE+0X064) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE15 (USBD_BASE+0X068) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE16 (USBD_BASE+0X06C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE17 (USBD_BASE+0X070) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE18 (USBD_BASE+0X074) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE19 (USBD_BASE+0X078) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE20 (USBD_BASE+0X07C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE21 (USBD_BASE+0X080) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE22 (USBD_BASE+0X084) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE23 (USBD_BASE+0X088) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE24 (USBD_BASE+0X08C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE25 (USBD_BASE+0X090) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE26 (USBD_BASE+0X094) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE27 (USBD_BASE+0X098) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE28 (USBD_BASE+0X09C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE29 (USBD_BASE+0X0A0) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE30 (USBD_BASE+0X0A4) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_CFGINTERFACE31 (USBD_BASE+0X0A8) /* ¼Ç¼½Ó¿ÚµÄÖµ */ #define USBD_PKTPASSEDCTRL (USBD_BASE+0X0AC) /* ¼Ç¼³É¹¦½ÓÊյİüÊý */ #define USBD_PKTDROPPEDCTRL (USBD_BASE+0X0B0) /* ¼Ç¼¶ªÊ§µÄ°üÊý */ #define USBD_CRCERRCTRL (USBD_BASE+0X0B4) /* ¼Ç¼CRC´íÎóµÄ°üÊý */ #define USBD_BITSTUFFERRCTRL (USBD_BASE+0X0B8) /* ¼Ç¼λÌî³ä´íÎóµÄ°üÊý */ #define USBD_PIDERRCTRL (USBD_BASE+0X0BC) /* ¼Ç¼PID´íÎóµÄ°üÊý */ #define USBD_FRAMINGERRCTL (USBD_BASE+0X0C0) /* ¼Ç¼ÓÐSYNCºÍEOPµÄ°üÊý */ #define USBD_TXPKTCTRL (USBD_BASE+0X0C4) /* ¼Ç¼·¢ËÍ°üµÄÊýÁ¿ */ #define USBD_STATCTRLOV (USBD_BASE+0X0C8) /* ¼Ç¼ͳ¼Æ¼Ä´æÆ÷Òç³öÇé¿ö */ #define USBD_TXLENGTH (USBD_BASE+0X0CC) /* ¼Ç¼ÿ´ÎIN´«ÊäÊÂÎñ°ü³¤¶È */ #define USBD_RXLENGTH (USBD_BASE+0X0D0) /* ¼Ç¼OUT´«ÊäÊÂÎñ°ü³¤¶È */ #define USBD_RESUME (USBD_BASE+0X0D4) /* USB»½ÐѼĴæÆ÷ */ #define USBD_READFLAG (USBD_BASE+0X0D8) /* ¶ÁÒ첽״̬¼Ä´æÆ÷±êÖ¾ */ #define USBD_RECEIVETYPE (USBD_BASE+0X0DC) /* ´«Êä״̬¼Ä´æÆ÷ */ #define USBD_APPLOCK (USBD_BASE+0X0E0) /* ËøÐźżĴæÆ÷ */ #define USBD_EP0OUTADDR (USBD_BASE+0X100) /* ¶Ëµã0¶ËµãºÅºÍ·½Ïò */ #define USBD_EP0OUTBMATTR (USBD_BASE+0X104) /* ¶Ëµã0ÀàÐͼĴæÆ÷ */ #define USBD_EP0OUTMAXPKTSIZE (USBD_BASE+0X108) /* ¶Ëµã0×î´ó°ü³ß´ç¼Ä´æÆ÷ */ #define USBD_EP0OUTIFNUM (USBD_BASE+0X10C) /* ¶Ëµã0½Ó¿ÚºÅ¼Ä´æÆ÷ */ #define USBD_EP0OUTSTAT (USBD_BASE+0X110) /* ¶Ëµã0״̬¼Ä´æÆ÷ */ #define USBD_EP0OUTBMREQTYPE (USBD_BASE+0X114) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóÀà */ #define USBD_EP0OUTBREQUEST (USBD_BASE+0X118) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóÄÚÈÝ */ #define USBD_EP0OUTWVALUE (USBD_BASE+0X11C) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóÖµ */ #define USBD_EP0OUTWINDEX (USBD_BASE+0X120) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóË÷Òý */ #define USBD_EP0OUTWLENGTH (USBD_BASE+0X120) /* ¶Ëµã0 SETUPÊÂÎñÇëÇó³¤¶È */ #define USBD_EP0OUTSYNCHFRAME (USBD_BASE+0X128) /* ¶Ëµã0ͬ²½°üÖ¡ºÅ */ #define USBD_EP1OUTADDR (USBD_BASE+0X12C) /* ¶Ëµã1Êä³ö¶ËµãºÅºÍ·½Ïò */ #define USBD_EP1OUTBMATTR (USBD_BASE+0X130) /* ¶Ëµã1Êä³öÀàÐͼĴæÆ÷ */ #define USBD_EP1OUTMAXPKTSIZE (USBD_BASE+0X134) /* ¶Ëµã1Êä³ö×î´ó°ü³ß´ç¼Ä´æÆ÷ */ #define USBD_EP1OUTIFNUM (USBD_BASE+0X138) /* ¶Ëµã1Êä³ö½Ó¿ÚºÅ¼Ä´æÆ÷ */ #define USBD_EP1OUTSTAT (USBD_BASE+0X13C) /* ¶Ëµã1Êä³ö״̬¼Ä´æÆ÷ */ #define USBD_EP1OUTBMREQTYPE (USBD_BASE+0X140) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÀàÐÍ */ #define USBD_EP1OUTBREQUEST (USBD_BASE+0X144) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÄÚÈÝ */ #define USBD_EP1OUTWVALUE (USBD_BASE+0X148) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÖµ */ #define USBD_EP1OUTWINDX (USBD_BASE+0X14C) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóË÷Òý */ #define USBD_EP1OUTWLENGH (USBD_BASE+0X150) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÓò³¤¶È */ #define USBD_EP1OUTSYNCHFRAME (USBD_BASE+0X154) /* ¶Ëµã1Êä³öͬ²½°üÖ¡ºÅ */ #define USBD_EP1INADDR (USBD_BASE+0X158) /* ¶Ëµã1ÊäÈë¶ËµãºÅºÍ·½Ïò */ #define USBD_EP1INBMATTR (USBD_BASE+0X15C) /* ¶Ëµã1ÊäÈëÀàÐͼĴæÆ÷ */ #define USBD_EP1INMAXPKTSIZE (USBD_BASE+0X160) /* ¶Ëµã1ÊäÈë×î´ó°ü³ß´ç¼Ä´æÆ÷ */ #define USBD_EP1INIFNUM (USBD_BASE+0X164) /* ¶Ëµã1ÊäÈë½Ó¿ÚºÅ¼Ä´æÆ÷ */ #define USBD_EP1INSTAT (USBD_BASE+0X168) /* ¶Ëµã1ÊäÈë״̬¼Ä´æÆ÷ */ #define USBD_EP1INBMREQTYPE (USBD_BASE+0X16C) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÀàÐÍ */ #define USBD_EP1INBREQUEST (USBD_BASE+0X170) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÄÚÈÝ */ #define USBD_EP1INWVALUE (USBD_BASE+0X174) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÖµ */ #define USBD_EP1INWINDEX (USBD_BASE+0X178) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóË÷Òý */ #define USBD_EP1INWLENGTH (USBD_BASE+0X17C) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÓò³¤¶È */ #define USBD_EP1INSYNCHFRAME (USBD_BASE+0X180) /* ¶Ëµã1ÊäÈëͬ²½°üÖ¡ºÅ */ #define USBD_EP2OUTADDR (USBD_BASE+0X184) /* ¶Ëµã2Êä³ö¶ËµãºÅºÍ·½Ïò */ #define USBD_EP2OUTBMATTR (USBD_BASE+0X188) /* ¶Ëµã2Êä³öÀàÐͼĴæÆ÷ */ #define USBD_EP2OUTMAXPKTSIZE (USBD_BASE+0X18C) /* ¶Ëµã2Êä³ö×î´ó°ü³ß´ç¼Ä´æÆ÷ */ #define USBD_EP2OUTIFNUM (USBD_BASE+0X190) /* ¶Ëµã2Êä³ö½Ó¿ÚºÅ¼Ä´æÆ÷ */ #define USBD_EP2OUTSTAT (USBD_BASE+0X194) /* ¶Ëµã2Êä³ö״̬¼Ä´æÆ÷ */ #define USBD_EP2OUTBMREQTYPE (USBD_BASE+0X198) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÀàÐÍ */ #define USBD_EP2OUTBREQUEST (USBD_BASE+0X19C) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÄÚÈÝ */ #define USBD_EP2OUTWVALUE (USBD_BASE+0X1A0) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÖµ */ #define USBD_EP2OUTWINDEX (USBD_BASE+0X1A4) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóË÷Òý */ #define USBD_EP2OUTWLENGTH (USBD_BASE+0X1A8) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÓò³¤¶È */ #define USBD_EP2OUTSYNCHFRAME (USBD_BASE+0X1AC) /* ¶Ëµã2Êä³öͬ²½°üÖ¡ºÅ */ #define USBD_EP2INADDR (USBD_BASE+0X1B0) /* ¶Ëµã2ÊäÈë¶ËµãºÅºÍ·½Ïò */ #define USBD_EP2INBMATTR (USBD_BASE+0X1B4) /* ¶Ëµã2ÊäÈëÀàÐͼĴæÆ÷ */ #define USBD_EP2INMAXPKTSIZE (USBD_BASE+0X1B8) /* ¶Ëµã2ÊäÈë×î´ó°ü³ß´ç¼Ä´æÆ÷ */ #define USBD_EP2INIFNUM (USBD_BASE+0X1BC) /* ¶Ëµã2ÊäÈë½Ó¿ÚºÅ¼Ä´æÆ÷ */ #define USBD_EP2INSTAT (USBD_BASE+0X1C0) /* ¶Ëµã2ÊäÈë״̬¼Ä´æÆ÷ */ #define USBD_EP2INBMREQTYPE (USBD_BASE+0X1C4) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÀàÐÍ */ #define USBD_EP2INBREQUEST (USBD_BASE+0X1C8) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÄÚÈÝ */ #define USBD_EP2INWVALUE (USBD_BASE+0X1CC) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÖµ */ #define USBD_EP2INWINDEX (USBD_BASE+0X1D0) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóË÷Òý */ #define USBD_EP2INWLENGTH (USBD_BASE+0X1D4) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÓò³¤¶È */ #define USBD_EP2INSYNCHFRAME (USBD_BASE+0X1D8) /* ¶Ëµã2ÊäÈëͬ²½°üÖ¡ºÅ */ #define USBD_RXFIFO (USBD_BASE+0X200) /* ½ÓÊÜFIFO */ #define USBD_TXFIFO (USBD_BASE+0X300) /* ·¢ËÍFIFO */ /* * GPIOÄ£¿é * »ùÖ·: 0x1000F000 */ #define GPIO_DBCLK_DIV (GPIO_BASE+0X000) /* ȥë´Ì²ÉÓÃʱÖÓ·ÖƵ±ÈÅäÖüĴæÆ÷ */ #define GPIO_PORTA_DIR (GPIO_BASE+0X004) /* A×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ #define GPIO_PORTA_SEL (GPIO_BASE+0X008) /* A×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ #define GPIO_PORTA_INCTL (GPIO_BASE+0X00C) /* A×é¶Ë¿ÚͨÓÃÓÃ;ÊäÈëʱÀàÐÍÅäÖüĴæÆ÷ */ #define GPIO_PORTA_INTRCTL (GPIO_BASE+0X010) /* A×é¶Ë¿ÚÖжϴ¥·¢ÀàÐÍÅäÖüĴæÆ÷ */ #define GPIO_PORTA_INTRCLR (GPIO_BASE+0X014) /* A×é¶Ë¿ÚͨÓÃÓÃ;ÖжÏÇå³ýÅäÖüĴæÆ÷ */ #define GPIO_PORTA_DATA (GPIO_BASE+0X018) /* A×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ #define GPIO_PORTB_DIR (GPIO_BASE+0X01C) /* B×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ #define GPIO_PORTB_SEL (GPIO_BASE+0X020) /* B×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ #define GPIO_PORTB_DATA (GPIO_BASE+0X024) /* B×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ #define GPIO_PORTC_DIR (GPIO_BASE+0X028) /* C×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ #define GPIO_PORTC_SEL (GPIO_BASE+0X02C) /* C×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ #define GPIO_PORTC_DATA (GPIO_BASE+0X030) /* C×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ #define GPIO_PORTD_DIR (GPIO_BASE+0X034) /* D×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ #define GPIO_PORTD_SEL (GPIO_BASE+0X038) /* D×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ #define GPIO_PORTD_SPECII (GPIO_BASE+0X03C) /* D×é¶Ë¿ÚרÓÃÓÃ;2Ñ¡ÔñÅäÖüĴæÆ÷ */ #define GPIO_PORTD_DATA (GPIO_BASE+0X040) /* D×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ #define GPIO_PORTE_DIR (GPIO_BASE+0X044) /* E×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ #define GPIO_PORTE_SEL (GPIO_BASE+0X048) /* E×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ #define GPIO_PORTE_DATA (GPIO_BASE+0X04C) /* E×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ #define GPIO_PORTF_DIR (GPIO_BASE+0X050) /* F×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ #define GPIO_PORTF_SEL (GPIO_BASE+0X054) /* F×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ #define GPIO_PORTF_INCTL (GPIO_BASE+0X058) /* F×é¶Ë¿ÚͨÓÃÓÃ;ÊäÈëʱÀàÐÍÅäÖüĴæÆ÷ */ #define GPIO_PORTF_INTRCTL (GPIO_BASE+0X05C) /* F×é¶Ë¿ÚÖжϴ¥·¢ÀàÐÍÅäÖüĴæÆ÷ */ #define GPIO_PORTF_INTRCLR (GPIO_BASE+0X060) /* F×é¶Ë¿ÚͨÓÃÓÃ;ÖжÏÇå³ýÅäÖüĴæÆ÷ */ #define GPIO_PORTF_DATA (GPIO_BASE+0X064) /* F×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ #define GPIO_PORTG_DIR (GPIO_BASE+0X068) /* G×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ #define GPIO_PORTG_SEL (GPIO_BASE+0X06C) /* G×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ #define GPIO_PORTG_DATA (GPIO_BASE+0X070) /* G×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ #define GPIO_PORTH_DIR (GPIO_BASE+0X07C) /* H×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ #define GPIO_PORTH_SEL (GPIO_BASE+0X078) /* H×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ #define GPIO_PORTH_DATA (GPIO_BASE+0X07C) /* H×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ #define GPIO_PORTI_DIR (GPIO_BASE+0X080) /* I×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ #define GPIO_PORTI_SEL (GPIO_BASE+0X084) /* I×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ #define GPIO_PORTI_DATA (GPIO_BASE+0X088) /* I×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ /* * EMIÄ£¿é * »ùÖ·: 0x11000000 */ #define EMI_CSACONF (EMI_BASE+0X000) /* CSA²ÎÊýÅäÖüĴæÆ÷ */ #define EMI_CSBCONF (EMI_BASE+0X004) /* CSB²ÎÊýÅäÖüĴæÆ÷ */ #define EMI_CSCCONF (EMI_BASE+0X008) /* CSC²ÎÊýÅäÖüĴæÆ÷ */ #define EMI_CSDCONF (EMI_BASE+0X00C) /* CSD²ÎÊýÅäÖüĴæÆ÷ */ #define EMI_CSECONF (EMI_BASE+0X010) /* CSE²ÎÊýÅäÖüĴæÆ÷ */ #define EMI_CSFCONF (EMI_BASE+0X014) /* CSF²ÎÊýÅäÖüĴæÆ÷ */ #define EMI_SDCONF1 (EMI_BASE+0X018) /* SDRAMʱÐòÅäÖüĴæÆ÷1 */ #define EMI_SDCONF2 (EMI_BASE+0X01C) /* SDRAMʱÐòÅäÖüĴæÆ÷2, SDRAM³õʼ»¯Óõ½µÄÅäÖÃÐÅÏ¢ */ #define EMI_REMAPCONF (EMI_BASE+0X020) /* Ƭѡ¿Õ¼ä¼°µØÖ·Ó³ÉäREMAPÅäÖüĴæÆ÷ */ #define EMI_NAND_ADDR1 (EMI_BASE+0X100) /* NAND FLASHµÄµØÖ·¼Ä´æÆ÷1 */ #define EMI_NAND_COM (EMI_BASE+0X104) /* NAND FLASHµÄ¿ØÖÆ×ּĴæÆ÷ */ #define EMI_NAND_STA (EMI_BASE+0X10C) /* NAND FLASHµÄ״̬¼Ä´æÆ÷ */ #define EMI_ERR_ADDR1 (EMI_BASE+0X110) /* ¶Á²Ù×÷³ö´íµÄµØÖ·¼Ä´æÆ÷1 */ #define EMI_ERR_ADDR2 (EMI_BASE+0X114) /* ¶Á²Ù×÷³ö´íµÄµØÖ·¼Ä´æÆ÷2 */ #define EMI_NAND_CONF1 (EMI_BASE+0X118) /* NAND FLASHµÄÅäÖÃÆ÷´æÆ÷1 */ #define EMI_NAND_INTR (EMI_BASE+0X11C) /* NAND FLASHÖжϼĴæÆ÷ */ #define EMI_NAND_ECC (EMI_BASE+0X120) /* ECCУÑéÍê³É¼Ä´æÆ÷ */ #define EMI_NAND_IDLE (EMI_BASE+0X124) /* NAND FLASH¿ÕÏмĴæÆ÷ */ #define EMI_NAND_CONF2 (EMI_BASE+0X128) /* NAND FLASHµÄÅäÖÃÆ÷´æÆ÷2 */ #define EMI_NAND_ADDR2 (EMI_BASE+0X12C) /* NAND FLASHµÄµØÖ·¼Ä´æÆ÷2 */ #define EMI_NAND_DATA (EMI_BASE+0X200) /* NAND FLASHµÄÊý¾Ý¼Ä´æÆ÷ */ /* * DMACÄ£¿é * »ùÖ·: 0x11001000 */ #define DMAC_INTSTATUS (DMAC_BASE+0X020) /* DAMCÖжÏ״̬¼Ä´æÆ÷¡£ */ #define DMAC_INTTCSTATUS (DMAC_BASE+0X050) /* DMAC´«ÊäÍê³ÉÖжÏ״̬¼Ä´æÆ÷ */ #define DMAC_INTTCCLEAR (DMAC_BASE+0X060) /* DMAC´«ÊäÍê³ÉÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define DMAC_INTERRORSTATUS (DMAC_BASE+0X080) /* DMAC´«Êä´íÎóÖжÏ״̬¼Ä´æÆ÷ */ #define DMAC_INTINTERRCLR (DMAC_BASE+0X090) /* DMAC´«Êä´íÎóÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ #define DMAC_ENBLDCHNS (DMAC_BASE+0X0B0) /* DMACͨµÀʹÄÜ״̬¼Ä´æÆ÷ */ #define DMAC_C0SRCADDR (DMAC_BASE+0X000) /* DMACµÀ0Ô´µØÖ·¼Ä´æÆ÷ */ #define DMAC_C0DESTADD (DMAC_BASE+0X004) /* DMACµÀ0Ä¿µÄµØÖ·¼Ä´æÆ÷ */ #define DMAC_C0CONTROL (DMAC_BASE+0X00C) /* DMACµÀ0¿ØÖƼĴæÆ÷ */ #define DMAC_C0CONFIGURATION (DMAC_BASE+0X010) /* DMACµÀ0ÅäÖüĴæÆ÷ */ #define DMAC_C0DESCRIPTOR (DMAC_BASE+0X01C) /* DMACµÀ0Á´±íµØÖ·¼Ä´æÆ÷ */ #define DMAC_C1SRCADDR (DMAC_BASE+0X100) /* DMACµÀ1Ô´µØÖ·¼Ä´æÆ÷ */ #define DMAC_C1DESTADDR (DMAC_BASE+0X104) /* DMACµÀ1Ä¿µÄµØÖ·¼Ä´æÆ÷ */ #define DMAC_C1CONTROL (DMAC_BASE+0X10C) /* DMACµÀ1¿ØÖƼĴæÆ÷ */ #define DMAC_C1CONFIGURATION (DMAC_BASE+0X110) /* DMACµÀ1ÅäÖüĴæÆ÷ */ #define DMAC_C1DESCRIPTOR (DMAC_BASE+0X114) /* DMACµÀ1Á´±íµØÖ·¼Ä´æÆ÷ */ #define DMAC_C2SRCADDR (DMAC_BASE+0X200) /* DMACµÀ2Ô´µØÖ·¼Ä´æÆ÷ */ #define DMAC_C2DESTADDR (DMAC_BASE+0X204) /* DMACµÀ2Ä¿µÄµØÖ·¼Ä´æÆ÷ */ #define DMAC_C2CONTROL (DMAC_BASE+0X20C) /* DMACµÀ2¿ØÖƼĴæÆ÷ */ #define DMAC_C2CONFIGURATION (DMAC_BASE+0X210) /* DMACµÀ2ÅäÖüĴæÆ÷ */ #define DMAC_C2DESCRIPTOR (DMAC_BASE+0X214) /* DMACµÀ2Á´±íµØÖ·¼Ä´æÆ÷ */ #define DMAC_C3SRCADDR (DMAC_BASE+0X300) /* DMACµÀ3Ô´µØÖ·¼Ä´æÆ÷ */ #define DMAC_C3DESTADDR (DMAC_BASE+0X304) /* DMACµÀ3Ä¿µÄµØÖ·¼Ä´æÆ÷ */ #define DMAC_C3CONTROL (DMAC_BASE+0X30C) /* DMACµÀ3¿ØÖƼĴæÆ÷ */ #define DMAC_C3CONFIGURATION (DMAC_BASE+0X310) /* DMACµÀ3ÅäÖüĴæÆ÷ */ #define DMAC_C3DESCRIPTOR (DMAC_BASE+0X314) /* DMACµÀ3Á´±íµØÖ·¼Ä´æÆ÷ */ #define DMAC_C4SRCADDR (DMAC_BASE+0X400) /* DMACµÀ4Ô´µØÖ·¼Ä´æÆ÷ */ #define DMAC_C4DESTADDR (DMAC_BASE+0X404) /* DMACµÀ4Ä¿µÄµØÖ·¼Ä´æÆ÷ */ #define DMAC_C4CONTROL (DMAC_BASE+0X40C) /* DMACµÀ4¿ØÖƼĴæÆ÷ */ #define DMAC_C4CONFIGURATION (DMAC_BASE+0X410) /* DMACµÀ4ÅäÖüĴæÆ÷ */ #define DMAC_C4DESCRIPTOR (DMAC_BASE+0X414) /* DMACµÀ4Á´±íµØÖ·¼Ä´æÆ÷ */ #define DMAC_C5SRCADDR (DMAC_BASE+0X500) /* DMACµÀ5Ô´µØÖ·¼Ä´æÆ÷ */ #define DMAC_C5DESTADDR (DMAC_BASE+0X504) /* DMACµÀ5Ä¿µÄµØÖ·¼Ä´æÆ÷ */ #define DMAC_C5CONTROL (DMAC_BASE+0X50C) /* DMACµÀ5¿ØÖƼĴæÆ÷ */ #define DMAC_C5CONFIGURATION (DMAC_BASE+0X510) /* DMACµÀ5ÅäÖüĴæÆ÷ */ #define DMAC_C5DESCRIPTOR (DMAC_BASE+0X514) /* DMACµÀ5Á´±íµØÖ·¼Ä´æÆ÷ */ /* * LCDCÄ£¿é * »ùÖ·: 0x11002000 */ #define LCDC_SSA (LCDC_BASE+0X000) /* ÆÁÄ»ÆðʼµØÖ·¼Ä´æÆ÷ */ #define LCDC_SIZE (LCDC_BASE+0X004) /* ÆÁÄ»³ß´ç¼Ä´æÆ÷ */ #define LCDC_PCR (LCDC_BASE+0X008) /* Ãæ°åÅäÖüĴæÆ÷ */ #define LCDC_HCR (LCDC_BASE+0X00C) /* ˮƽÅäÖüĴæÆ÷ */ #define LCDC_VCR (LCDC_BASE+0X010) /* ´¹Ö±ÅäÖüĴæÆ÷ */ #define LCDC_PWMR (LCDC_BASE+0X014) /* PWM¶Ô±È¶È¿ØÖƼĴæÆ÷ */ #define LCDC_LECR (LCDC_BASE+0X018) /* ʹÄÜ¿ØÖƼĴæÆ÷ */ #define LCDC_DMACR (LCDC_BASE+0X01C) /* DMA¿ØÖƼĴæÆ÷ */ #define LCDC_LCDISREN (LCDC_BASE+0X020) /* ÖжÏʹÄܼĴæÆ÷ */ #define LCDC_LCDISR (LCDC_BASE+0X024) /* ÖжÏ״̬¼Ä´æÆ÷ */ #define LCDC_LGPMR (LCDC_BASE+0X040) /* »Ò¶Èµ÷É«Ó³Éä¼Ä´æÆ÷×é (16¸ö32bit¼Ä´æÆ÷) */ /* * MACÄ£¿é * »ùÖ·: 0x11003000 */ #define MAC_CTRL (MAC_BASE+0X000) /* MAC¿ØÖƼĴæÆ÷ */ #define MAC_INTSRC (MAC_BASE+0X004) /* MACÖжÏÔ´¼Ä´æÆ÷ */ #define MAC_INTMASK (MAC_BASE+0X008) /* MACÖжÏÆÁ±Î¼Ä´æÆ÷ */ #define MAC_IPGT (MAC_BASE+0X00C) /* Á¬ÐøÖ¡¼ä¸ô¼Ä´æÆ÷ */ #define MAC_IPGR1 (MAC_BASE+0X010) /* µÈ´ý´°¿Ú¼Ä´æÆ÷ */ #define MAC_IPGR2 (MAC_BASE+0X014) /* µÈ´ý´°¿Ú¼Ä´æÆ÷ */ #define MAC_PACKETLEN (MAC_BASE+0X018) /* Ö¡³¤¶È¼Ä´æÆ÷ */ #define MAC_COLLCONF (MAC_BASE+0X01C) /* ÅöײÖØ·¢¼Ä´æÆ÷ */ #define MAC_TXBD_NUM (MAC_BASE+0X020) /* ·¢ËÍÃèÊö·û¼Ä´æÆ÷ */ #define MAC_FLOWCTRL (MAC_BASE+0X024) /* Á÷¿Ø¼Ä´æÆ÷ */ #define MAC_MII_CTRL (MAC_BASE+0X028) /* PHY¿ØÖƼĴæÆ÷ */ #define MAC_MII_CMD (MAC_BASE+0X02C) /* PHYÃüÁî¼Ä´æÆ÷ */ #define MAC_MII_ADDRESS (MAC_BASE+0X030) /* PHYµØÖ·¼Ä´æÆ÷ */ #define MAC_MII_TXDATA (MAC_BASE+0X034) /* PHYдÊý¾Ý¼Ä´æÆ÷ */ #define MAC_MII_RXDATA (MAC_BASE+0X038) /* PHY¶ÁÊý¾Ý¼Ä´æÆ÷ */ #define MAC_MII_STATUS (MAC_BASE+0X03C) /* PHY״̬¼Ä´æÆ÷ */ #define MAC_ADDR0 (MAC_BASE+0X040) /* MACµØÖ·¼Ä´æÆ÷ */ #define MAC_ADDR1 (MAC_BASE+0X044) /* MACµØÖ·¼Ä´æÆ÷ */ #define MAC_HASH0 (MAC_BASE+0X048) /* MAC HASH¼Ä´æÆ÷ */ #define MAC_HASH1 (MAC_BASE+0X04C) /* MAC HASH¼Ä´æÆ÷ */ #define MAC_TXPAUSE (MAC_BASE+0X050) /* MAC¿ØÖÆÖ¡¼Ä´æÆ÷ */ #define MAC_TX_BD (MAC_BASE+0X400) #define MAC_RX_BD (MAC_BASE+0X600) /* ************************************** * Error Codes: * IF SUCCESS RETURN 0, ELSE RETURN OTHER ERROR CODE, * parameter error return (-33)/E_PAR, * hardware error reture (-99)/E_HA ************************************** */ #define E_OK 0 /* Normal completion */ #define E_SYS (-5) /* System error */ #define E_NOMEM (-10) /* Insufficient memory */ #define E_NOSPT (-17) /* Feature not supported */ #define E_INOSPT (-18) /* Feature not supported by ITRON/FILE specification */ #define E_RSFN (-20) /* Reserved function code number */ #define E_RSATR (-24) /* Reserved attribute */ #define E_PAR (-33) /* Parameter error */ #define E_ID (-35) /* Invalid ID number */ #define E_NOEXS (-52) /* Object does not exist */ #define E_OBJ (-63) /* Invalid object state */ #define E_MACV (-65) /* Memory access disabled or memory access violation */ #define E_OACV (-66) /* Object access violation */ #define E_CTX (-69) /* Context error */ #define E_QOVR (-73) /* Queuing or nesting overflow */ #define E_DLT (-81) /* Object being waited for was deleted */ #define E_TMOUT (-85) /* Polling failure or timeout exceeded */ #define E_RLWAI (-86) /* WAIT state was forcibly released */ #define E_HA (-99) /* HARD WARE ERROR */ /* ************************************** * PMU Ä£¿éʱÖÓ ************************************** */ #define CLK_SGPT (1 << 16) #define CLK_SI2S (1 << 15) #define CLK_SSMC (1 << 14) #define CLK_SMAC (1 << 13) #define CLK_SUSB (1 << 12) #define CLK_SUART3 (1 << 11) #define CLK_SUART2 (1 << 10) #define CLK_SUART1 (1 << 9) #define CLK_SUART0 (1 << 8) #define CLK_SSSI (1 << 7) #define CLK_SAC97 (1 << 6) #define CLK_SMMCSD (1 << 5) #define CLK_SEMI (1 << 4) #define CLK_SDMAC (1 << 3) #define CLK_SPWM (1 << 2) #define CLK_SLCDC (1 << 1) #define CLK_SESRAM (1) /*Interrupt Sources*/ #define INTSRC_RTC 31 #define INTSRC_DMAC 30 #define INTSRC_EMI 29 #define INTSRC_MAC 28 #define INTSRC_TIMER1 27 #define INTSRC_TIMER2 26 #define INTSRC_TIMER3 25 #define INTSRC_UART0 24 #define INTSRC_UART1 23 #define INTSRC_UART2 22 #define INTSRC_UART3 21 #define INTSRC_PWM 20 #define INTSRC_LCDC 19 #define INTSRC_I2S 18 #define INTSRC_SSI 17 #define INTSRC_USB 15 #define INTSRC_SMC0 14 #define INTSRC_SMC1 13 #define INTSRC_SDIO 12 #define INTSRC_EXINT10 11 #define INTSRC_EXINT9 10 #define INTSRC_EXINT8 9 #define INTSRC_EXINT7 8 #define INTSRC_EXINT6 7 #define INTSRC_EXINT5 6 #define INTSRC_EXINT4 5 #define INTSRC_EXINT3 4 #define INTSRC_EXINT2 3 #define INTSRC_EXINT1 2 #define INTSRC_EXINT0 1 #define INTSRC_NULL 0 /*Sereral useful macros*/ #define set_plevel(plevel) *(RP)INTC_IPLR = plevel //ÉèÖÃÆÕͨÖжϵÄÓÅÏȼ¶ÃÅÏÞ£¬Ö»ÓÐÓÅÏȼ¶´óÓÚ´ËÖµµÄÖжϲÅÄÜͨ¹ý #define set_int_force(intnum) *(RP)INTC_IFR = (1 << intnum) //ÖÃ1ºó£¬Èí¼þÇ¿ÖƸÃλ¶ÔÓ¦µÄÖжÏÔ´·¢³öÖжÏÐźŠ#define enable_irq(intnum) *(RP)INTC_IER |= (1 << intnum) //ÖÃ1ºó£¬ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ#define disable_irq( intnum) *(RP)INTC_IER &= ~(1<< intnum) //ÖÃ0ºó£¬²»ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //ÖÃ1ºó£¬ÆÁ±Î¶ÔÓ¦µÄIRQ ÖжÏÐźŠ#define unmask_irq(intnum) *(RP)INTC_IMR &= ~(1 << intnum) //ÖÃ0ºó£¬Í¨¹ý¶ÔÓ¦µÄIRQ ÖжÏÐźŠ#define mask_all_irq() *(RP)INTC_IMR = 0xFFFFFFFF //ÆÁ±Î¶ÔÓ¦µÄIRQ ÖжÏÐźŠ#define unmask_all_irq() *(RP)INTC_IMR = 0x00000000 //ͨ¹ý¶ÔÓ¦µÄIRQ ÖжÏÐźŠ#define enable_all_irq() *(RP)INTC_IER = 0XFFFFFFFF //ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ#define disable_all_irq() *(RP)INTC_IER = 0X00000000 //²»ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ#define InitInt() do{mask_all_irq(); enable_all_irq();}while(0) /* ************************************** * ËùÓгÌÐòÖÐÓõ½µÄTypedef ************************************** */ typedef char S8; /* signed 8-bit integer */ typedef short S16; /* signed 16-bit integer */ typedef long S32; /* signed 32-bit integer */ typedef unsigned char U8; /* unsigned 8-bit integer */ typedef unsigned short U16; /* unsigned 16-bit integer */ typedef unsigned long U32; /* unsigned 32-bit integer */ typedef volatile U32 * RP; typedef volatile U16 * RP16; typedef volatile U8 * RP8; typedef void *VP; /* pointer to an unpredictable data type */ typedef void (*FP)(); /* program start address */ #ifndef _BOOL_TYPE_ #define _BOOL_TYPE_ typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ #endif typedef int ER; /* Error code. A signed integer. */ /** * IO definitions * * define access restrictions to peripheral registers */ #define __I volatile const /*!< defines 'read only' permissions */ #define __O volatile /*!< defines 'write only' permissions */ #define __IO volatile /*!< defines 'read / write' permissions */ #define __iomem volatile /*Macros for debug*/ #define EOUT(fmt,...) \ do \ { \ rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ rt_kprintf(fmt,##__VA_ARGS__); \ }while(0) #define RT_DEBUG #ifdef RT_DEBUG #define DBOUT(fmt,...) \ do \ { \ rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ rt_kprintf(fmt,##__VA_ARGS__); \ }while(0) #else #define DBOUT(fmt,...) \ do{}while(0) #endif #ifdef RT_DEBUG #define ASSERT(arg) \ if((arg) == 0) \ { \ while(1) \ { \ rt_kprintf("have a assert failure\n"); \ } \ } #else #define ASSERT(arg) \ do \ { \ }while(0) #endif #define write_reg(reg,value) \ do \ { \ *(RP)(reg) = value; \ }while(0) #define read_reg(reg) (*(RP)reg) struct rt_hw_register { rt_uint32_t r0; rt_uint32_t r1; rt_uint32_t r2; rt_uint32_t r3; rt_uint32_t r4; rt_uint32_t r5; rt_uint32_t r6; rt_uint32_t r7; rt_uint32_t r8; rt_uint32_t r9; rt_uint32_t r10; rt_uint32_t fp; rt_uint32_t ip; rt_uint32_t sp; rt_uint32_t lr; rt_uint32_t pc; rt_uint32_t cpsr; rt_uint32_t ORIG_r0; }; /*@}*/ #endif