228a6be077
cortex-r4: add __rt_ffs
2013-06-05 23:20:39 +08:00
e74befca44
move libcpu/arm/rm48x50/ to libcpu/arm/cortex-r4
2013-05-31 21:06:26 +08:00
24fc6e6ebb
rm48x50: VFP lazy stacking
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You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT
will turn on VFP for all threads and stack all the VFP registers. When
doing lazy stacking, VFP will only be turned on for the thread who
issued VFP instructions.
Currently, if a thread turned on VFP, it cannot be turned off. RTT will
never know what time the thread doesn't need VFP any more. The thread
might could turn off the VFP for it self in proper time.
2013-05-31 20:58:08 +08:00
8bbfd45ce3
rm48x50: change STMFD/LDMFD to STMDB/LDMIA
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VFP instructions only have IA(Increment After)/DB(Decrement Before)
mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
ec1203bfab
rm48x50: turn on VFP support
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This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
83ea4dd628
rm48x50: small cleanup on context_ccs.asm
2013-05-30 17:37:50 +08:00
810311b624
rm48x50: fix bug in rt_hw_interrupt_{mask,unmask}
2013-05-29 23:36:32 +08:00
f08df08897
rm48x50: optimize a BEQ
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Use condition flag in the ORR. This could eliminate a BEQ.
2013-05-26 23:37:56 +08:00
19fe6251e7
rm48x50: optimize context_switch_interrupt_to by reuse registers
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When saving thread registers in context_switch_interrupt_to, we don't
change them, just move them. So there is no need to always r0-r3 from
stack to the real r0-r3. So just use the intermediate registers and
eliminate 2 MOV.
2013-05-26 22:37:49 +08:00
3d0647efb3
rm48x50: optimize context_switch_interrupt_do
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Substitude STMFD, MOV, ADD with STMFD, SUB. It reduce one instruction.
Tested on board and it works like a charm.
2013-05-26 17:22:36 +08:00
b39d038cf0
rm48x50: utilize CPS instruction and remove some useless code
2013-05-26 16:55:39 +08:00
f51bce3fed
add rm48x50 bsp and libcpu
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We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
2013-05-24 22:55:13 +08:00
db548a1b37
fixed compiling error related to the RT_USING_INTERRUPT_INFO in mini4020
2013-04-10 00:49:18 +08:00
d9d39a8d21
Use SRAM as EMAC transmit buffer, to avoid the underrun error, especially in the large amount of data communication.
2013-04-08 21:57:24 +08:00
0594734d8d
clean up code
2013-04-02 20:33:56 +08:00
03aa76155e
fixed context thread issue when using armcc compile
2013-04-02 20:27:08 +08:00
fb9ea5eada
enable at91sam9260 mmu, update SDIO and EMAC drivers
2013-04-02 20:24:51 +08:00
92d4c1939b
fixed at91sam9260 context thread issue, avoid idle thread stack overflow
2013-04-02 20:23:11 +08:00
edef109d76
fix interrupt compiling issue in PPC
2013-03-31 22:58:36 -04:00
c1b600644f
Merge pull request #56 from aozima/aozima
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Modify the interrupt interface implementations.
2013-03-31 04:14:40 -07:00
2ccb3c7589
update LPC2478: Modify the interrupt interface implementations.
2013-03-31 18:25:51 +08:00
710a0fc4a5
fix issue when print interrupt info
2013-03-31 18:24:51 +08:00
1549b7db90
update LPC214X: Modify the interrupt interface implementations.
2013-03-31 17:58:26 +08:00
eab20a9975
update AT91SAM7X: Modify the interrupt interface implementations.
2013-03-31 17:43:09 +08:00
83ce430902
update loongson 1B dev: Modify the interrupt interface implementations.
2013-03-31 17:32:25 +08:00
93e04a1366
update loongson dev3210: Modify the interrupt interface implementations.
2013-03-31 17:32:20 +08:00
6058efbd9b
update Jz47xx: Modify the interrupt interface implementations.
2013-03-31 17:32:16 +08:00
29a3ae4368
update sep4020: Modify the interrupt interface implementations.
2013-03-31 17:32:04 +08:00
fbc1b05dd8
update mini2440: Modify the interrupt interface implementations.
2013-03-31 17:30:30 +08:00
608074deaf
update to interrupt description
2013-03-30 08:15:27 +08:00
8e6a534fa3
fix compiling issue in Jz47XX
2013-03-26 09:08:25 +08:00
bb72be94b2
code cleanup for interrupt description
2013-03-26 08:52:33 +08:00
5639c5daed
implement __rt_ffs for armv5
2013-03-24 16:03:23 +08:00
1abaa0492d
implement __rt_ffs in kernel service library
2013-03-23 11:27:29 +08:00
7917cf09e7
remain the old handler to keep forward compatibility
2013-03-19 11:25:46 +08:00
9678ee67e9
Modified the interrupt function comments
2013-03-19 11:25:33 +08:00
b21028474b
Modify the interrupt interface implementations, changes in the part of the parameter definition.
2013-03-19 11:25:12 +08:00
be59c9287f
fixed cache initial bug.
2013-03-08 11:23:40 +08:00
9ccdf4172e
basic mingw support for simulator: kernel and finsh
2013-02-26 16:03:08 +08:00
d80888a194
port stm32f0x to gcc.
2013-02-20 22:03:31 +08:00
b8aaa6e730
clean code in cpu_port.c, add some comments
2013-01-16 18:49:07 +08:00
b8bd5c8309
fix bug in cpu_port.c(can work very well)
2013-01-15 23:59:14 +08:00
395178ebfa
rewrite cpu_port.c (but still has bug)
2013-01-15 21:38:54 +08:00
07da6caafd
surport finsh
2013-01-14 22:38:54 +08:00
8f70786c30
add finsh, but still cannot work, only can be built with gcc
2013-01-14 16:50:40 +08:00
7b42f926a0
re-write the rt_hw_interrupt_enable/disable
2013-01-14 14:14:40 +08:00
5685a395be
add some comments and clean code in cpu_port.c
2013-01-14 01:23:08 +08:00
7b58dd92fa
add libcpu/sim/posix/cpu_port.c
2013-01-13 22:58:45 +08:00
72782e9203
convert end of line
2013-01-08 05:05:02 -08:00
ecd66612cf
remove lpc122x because there is a common cortex-m0 porting.
2013-01-04 06:03:03 -08:00
68fadd9edc
Add exception hook function.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2551 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-29 09:36:16 +00:00
ac9c373d7f
Add thread name to Win32Thread.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2541 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-29 03:28:31 +00:00
8df650d861
clean code in sim/win32/cpu_port.c
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2536 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-27 08:31:53 +00:00
468ade5e98
fixed the coding style in libcpu/arm
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2518 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-24 06:59:14 +00:00
f6629a1e4c
rename the file name using low case
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2514 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-24 03:50:42 +00:00
eab30ebbda
fixed the fixed the gcc compiling error in ubuntu host OS
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2512 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-24 03:34:04 +00:00
5be0c53dd8
stack addr align to 8byte.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2509 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-23 07:40:31 +00:00
2955dbfcda
add LPC4330 BSP based on NGX xplorer development board
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2487 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-17 08:21:29 +00:00
6ae9a5d95c
revert wrongly commit.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2408 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-11-13 08:10:23 +00:00
f78a50883b
remove nuc1xx because there is a cortex-m0 branch.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2407 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-11-13 07:59:28 +00:00
ec0cb881d8
remove lpc1100 because there is a cortex-m0 branch.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2406 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-11-13 07:56:40 +00:00
6fe2afed8c
for rt-thread 1.1.0
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2372 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-10-26 03:36:13 +00:00
20352571e2
add libcpu/sim/win32 to support the win32 bsp (compiled by visual studio)
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2359 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-10-21 04:46:24 +00:00
806ecbbb2b
update libcpu/SConscript to support cl(c compiler of visual studio)
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2358 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-10-21 04:42:49 +00:00
0c13711396
Add taihu bsp (PPC405)
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2350 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-10-14 23:28:37 +00:00
0057604ad2
update hdisr_gcc.S: push argument for ISR.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2341 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-10-10 16:39:49 +00:00
e0a5c0ae81
save texit address in to thread stack in m16c
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2308 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-09-26 06:43:35 +00:00
c784dd2ed8
update V850 BSP, now supporting scons + IAR
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2306 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-09-25 04:18:24 +00:00
6dcb1207b1
initialize register r31(LP) with texit in V850/cpuport.c
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2305 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-09-25 03:19:43 +00:00
056228cce6
fixed bug: store r8 - r11.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2258 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-08-22 15:53:54 +00:00
4455768b92
fixed s3c2440a context thread bug,patch contributor
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:yuxun2k
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2192 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-06-28 14:04:20 +00:00
a9aa8d503e
add libcpu/cortex-m0.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2142 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-05-31 17:41:58 +00:00
5684d15916
add bf533 bsp and cpu files.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2138 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-05-30 11:29:34 +00:00
0ce3aa056d
update CMSIS RTOS API in MB9BF506R
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2117 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-05-15 06:16:37 +00:00
04a79d24cf
fix extern list_thread return type by arda.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2104 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-04-29 02:11:40 +00:00
090553f768
delete PK40X256VLQ100 branch.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2081 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-04-16 05:04:30 +00:00
a321f3da64
support GNUC cross compiler(GNUM16CM32Cv1101-ELF) for renesas M16C porting
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2047 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-04-14 07:04:27 +00:00
8d4938ae70
delete libcpu/arm/at91sam926x/rt_list.h
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2008 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-03-23 15:07:21 +00:00
38ba67a867
update libcpu cortex-m4.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1967 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-02-18 17:46:08 +00:00
68bee363ff
update IA32 branch for new rt-thread platform.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1948 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-02-16 04:19:20 +00:00
7906287cfe
IAR not support VSTMFD and VLDMFD, use VSTMDB and VLDMIA.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1947 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-02-16 03:45:50 +00:00
645260a1c9
fixed a compiling error while not defined RT_USING_FINSH
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1906 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-01-03 09:08:47 +00:00
aad32f8546
support context switch load/store FPU register.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1901 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-31 20:25:44 +00:00
1097104c7f
fixed stack align issues.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1900 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-31 20:21:46 +00:00
3df72cc21f
update file header.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1891 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-31 04:08:12 +00:00
701df33436
remove libcpu/arm/lm3s libcpu/arm/lpc176x , update bsp lm3s lpc176x.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1865 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-23 01:36:10 +00:00
d6892fb441
all FM3 cortex-m3 branches using /libcpu/arm/cortex-m3 instead of /libcpu/arm/fm3
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1861 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-22 00:46:34 +00:00
8b64d24bd4
all STM32 cortex-m3 branches using /libcpu/arm/cortex-m3 instead of /libcpu/arm/stm32
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1858 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-21 09:44:52 +00:00
9c8398a10b
fixed scons + IAR compiling error for stm32f107
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1855 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-21 07:20:51 +00:00
2622f51496
add thumb mode porting.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1854 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-20 16:06:20 +00:00
f1b07348c2
update libcpu lpc2478.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1852 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-20 09:03:46 +00:00
c808894735
update libcpu lpc2148.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1850 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-20 08:45:01 +00:00
212d828d3f
change thread return address.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1848 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-19 01:46:19 +00:00
da542ee0ca
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1847 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-18 05:36:26 +00:00
c66c182894
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1846 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-18 05:16:43 +00:00
90c43598fc
delete microbalze.inc
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此行及以下内容将会被忽略--
D microblaze/microbalze.inc
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1845 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-18 05:16:01 +00:00
ae73bd59bc
modify format
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1844 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-18 05:13:10 +00:00
08f25161d9
porting for microblaze. nl1031
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1843 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-12-17 04:14:22 +00:00
462cfdc3e0
add fatal event handler in ARM7TDMI.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1819 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-11-29 10:17:51 +00:00
ed9828226a
*** EFM32 branch ***
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1. Move file, "start_gcc.S", from "libcpu/arm/cortex-m3/" to "bsp/efm32/"
2. Upgrade EFM32 driver libraries (CMSIS and efm32lib) to version 2.2.2
3. Upgrade EFM32 G2xx development kit drivers (EFM32_Gxxx_DK) to version 1.7.2 (from version 1.6.0)
4. Modify the files ("drv_usart.c" and "drv_iic.c") according to the driver libraries upgrading
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1818 bbd45198-f89e-11dd-88c7-29a3b14d5316
2011-11-29 09:15:10 +00:00
Grissiom
yiyue.fang
weety
Bernard Xiong
aozima
prife
prife
Ubuntu
nongli1031@gmail.com
iamyhw@gmail.com
mok.jingxian@gmail.com
onelife.real