ardafu
39452b67b0
1. [cpu] split ARM926 cpu code from AT91SAM9260 BSP
2015-04-14 21:56:34 +08:00
ItsEddy
ced7d5a34f
[DeviceDriver] stm32: Remove explicity clear of RXNE flag
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According to STM32 Manual, the USART RXNE flag will be clear automatically after
read to the USART_DR register[1], so the call to USART_ClearITPendingBit is
unnecessary.
[1]: See RM0090 Reference Manual p.992, Bit 5
2015-04-07 21:09:22 +08:00
yangfasheng
75ede181aa
update nrf51822 in bsp
2015-04-06 14:21:25 +08:00
yangfasheng
3dc20907c3
add nrf51822 to bsp
2015-04-06 13:46:14 +08:00
heyuanjie87
d4ec1ed5f9
[bsp]stm32f107/.uvprojx:fix mcu type error
2015-04-03 21:18:10 +08:00
Bright Pan
93122aaa19
[BSP]stm32f10x: Fix gpio driver for 144pins and 64pins
2015-03-25 10:44:02 +08:00
Bright Pan
c377690989
[BSP]stm32f10x: Add gpio driver for pin driver frame
2015-03-24 16:30:37 +08:00
unknown
351dd923e3
bsp stm32f10x add uart4 drive
2015-03-11 15:24:09 +08:00
Bernard Xiong
a2fbc5f5a8
Merge pull request #431 from ArdaFu/master
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[BSP] TM4C129X Fix bugs and errors.
2015-03-11 00:03:53 +08:00
Bright Pan
a61d228b76
Nanopb is a plain-C implementation of Google's Protocol Buffers data
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format. It is targeted at 32 bit microcontrollers, but is also fit for
other embedded systems with tight (2-10 kB ROM, <1 kB RAM) memory
constraints.(http://koti.kapsi.fi/jpa/nanopb/ )
How to use the example:
1. move examples/nanopb to bsp/xxxx/
2. enable macro RT_USING_NANOPB in rtconfig.h
3. regenerate the project file (scons --target=xxxx)
4. rebuild the project
2015-03-10 18:24:17 +08:00
ardafu
1daa96a214
1. [BSP] TM4C129x : Fix the bug that enable global INT before OS scheduler start the fist thread.
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2. [BSP] TM4C129x : According to LunchPad, change device id from TM4C1294XCNZAD to TM4C1294NCPDT
2015-03-10 12:13:14 +08:00
Arda
4a9c3fae29
Merge pull request #3 from RT-Thread/master
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sync with official source
2015-03-10 12:01:25 +08:00
Bernard Xiong
584efccad1
Update application.c
2015-03-04 10:32:48 +08:00
prife
c6f88ef726
dfs_win32: add seekdir support
2015-02-02 01:21:40 +08:00
armink
79c37cb30f
[BSP]changed stm32f10x uart driver. make sure the serial transmit
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complete in putc().
2015-01-31 11:18:59 +08:00
armink
131c41d182
[BSP]support 9 data bits and parity config for stm32f10x uart driver.
2015-01-31 11:14:10 +08:00
armink
1213dec3c9
fix #347
2015-01-31 11:05:00 +08:00
bernard
71930b0995
[BSP] Fix the interrupt issue in USART driver of STM32F4.
2015-01-25 16:41:05 +08:00
Bernard Xiong
c1f47af9f1
[BSP] remove RT_USING_VMM in default and let it run in QEMU.
2015-01-21 14:17:36 +08:00
Bernard Xiong
86358d0830
[BSP] code cleanup for usart and gpio driver in STM32F4
2015-01-21 12:36:34 +08:00
Bernard Xiong
756f2c67ab
[BSP] rename the rt_hw_usart_init to stm32_hw_usart_init
2015-01-20 16:02:33 +08:00
Bernard Xiong
bff1bb3d7b
[BSP] update MDK project file for STM32F4
2015-01-20 15:58:37 +08:00
Bernard Xiong
080c8912ea
Merge remote-tracking branch 'upstream/master'
2015-01-20 15:56:52 +08:00
Bernard Xiong
9261c37e0e
[BSP] Add GPIO driver for STM32F4
2015-01-20 07:55:52 +00:00
Bernard Xiong
2b7600bdf3
[BSP] update MDK project file for STM32F4
2015-01-20 15:52:39 +08:00
Bernard Xiong
6acf4a4528
[BSP] Update UART and GPIO driver with framework in STM32F4
2015-01-20 07:23:59 +00:00
Grissiom
c565925169
bsp/{cortex-M}: fix the SysTick_Config
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SysTick_Config substract one inside the function. So there is no need to
substract one when passing the parameter.
2015-01-09 15:26:06 +08:00
Bernard Xiong
56ab0995c1
Merge pull request #409 from grissiom/lpc43xx
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Lpc43xx
2015-01-09 10:00:25 +08:00
Grissiom
81b37fb1f9
lpc43xx: add copy-right info in vbus drivers
2015-01-08 17:16:26 +08:00
Grissiom
05a01884e6
lpc43xx: fix clock configure
2015-01-07 17:15:50 +08:00
Grissiom
11026d0579
lpc43xx: clean the .o before building M0 and M4
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SCons will omit the file in parent dir of SConstruct somehow and build
the object files in that dir instead of in variant dir. This cause
problem because we cannot mix the object files between M0 and M4 which
SCons failed to rebuild. So we have to manually remove the files before
building.
2015-01-07 17:15:49 +08:00
Grissiom
17a75eaa02
lpc43xx: remove the fpu settings in startup_LPC43xx_M0
2015-01-07 17:15:49 +08:00
Grissiom
22938a93ef
lpc43xx: fix some compile warnings
2015-01-07 17:15:49 +08:00
Grissiom
f7415e595e
VBus: added
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Currently only lpc43xx is supported.
2015-01-07 17:15:49 +08:00
Grissiom
fcff552626
lpc43xx: fix the SConscripts
2015-01-07 10:25:44 +08:00
Grissiom
03a2847f12
lpc43xx: fix some compile warnings
2015-01-07 10:25:44 +08:00
Grissiom
7965708050
lpc43xx: add -Wall
2015-01-07 10:25:44 +08:00
Grissiom
df31744178
lpc43xx: fix the M0 project template
2015-01-07 10:25:43 +08:00
Coing
70aaf4237f
fix project.uvoptx can't open,recreate the project.uvoptx. this commit is for post
2015-01-06 21:54:47 +08:00
Grissiom
0ca281c162
lpc43xx: add flash linker script for GCC
2015-01-06 13:40:46 +08:00
Grissiom
bcbe180886
lpc43xx: fix the default RTT_ROOT in SConstruct
2015-01-06 13:39:54 +08:00
Grissiom
fca84daa9d
lpc43xx: fix the startup code for GCC
2015-01-06 12:42:12 +08:00
Grissiom
833339e1c6
lpc43xx: output a newline in the header file
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Some compiler is brain-damaged that it will yeild a warning for headers
not ended with a newline. Yes, I mean you, Keil.
2015-01-06 11:03:01 +08:00
Grissiom
ff3ab9c0ab
lpc43xx: add readme
2015-01-06 10:46:32 +08:00
Grissiom
090adcf4c0
lpc43xx: don't set the Clock again in M0 core
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M0 core is always booted by the M4 core. It means that if we are running
in M0, the clock is always configured.
2015-01-06 10:46:32 +08:00
Grissiom
21ef733251
lpc43xx: use the RIT timer as SysTick in M0 core
2015-01-06 10:46:31 +08:00
Grissiom
773a884a4b
lpc43xx: move board.c into M0/M4
2015-01-06 10:46:31 +08:00
Grissiom
d2e4050a70
lpc43xx: update template.uvproj and add sct files
2015-01-06 10:46:31 +08:00
Grissiom
959f6c695f
lpc43xx: move the application code into its own space
2015-01-06 10:46:31 +08:00
Grissiom
5542af8b7c
lpc43xx/driver: fix the VTOR setting
2015-01-06 10:25:43 +08:00