* [Feature] Power domain for device
1.Support device power on/off.
2.Support attach/detach device.
3.Support power domain driver api.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* [DM/platform] Enhanced platform bus
1.Add power domain for device.
2.Support `remove` and `shutdown` bus interface.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
---------
Signed-off-by: GuEe-GUI <2991707448@qq.com>
Correct `sched_setaffinity()` to use the thread IDs (TIDs) instead of
process IDs (PIDs). The previous implementation used PIDs, which
caused issues since affinity settings need to be applied at the
thread level.
As the manual documented, the signature is:
> int sched_setaffinity(pid_t pid, size_t cpusetsize,
> const cpu_set_t *mask);
Yes, it's tricky, the identification passing in is called **'PID'**.
But when we talk about 'pid' from GNU libc, it's the **'task-id'**,
aka, `thread->tid` known in kernel.
Changes were made by updating the function signatures and logic in
`lwp.h`, `lwp_pid.c`, and `lwp_syscall.c` to accept TIDs. Specifically,
the `lwp_setaffinity` function and related internal functions now
operate using thread IDs and adjust thread affinity settings accordingly
Signed-off-by: Shell <smokewood@qq.com>
* [libcpu] arm64: Add hardware thread_self support
This patch introduces hardware-based thread self-identification
for the AArch64 architecture. It optimizes thread management by
using hardware registers to store and access the current thread's
pointer, reducing overhead and improving overall performance.
Changes include:
- Added `ARCH_USING_HW_THREAD_SELF` configuration option.
- Modified `rtdef.h`, `rtsched.h` to conditionally include
`critical_switch_flag` based on the new config.
- Updated context management in `context_gcc.S`, `cpuport.h`
to support hardware-based thread self.
- Enhanced `scheduler_mp.c` and `thread.c` to leverage the new
hardware thread self feature.
These modifications ensure better scheduling and thread handling,
particularly in multi-core environments, by minimizing the
software overhead associated with thread management.
Signed-off-by: Shell <smokewood@qq.com>
* fixup: address suggestion
* fixup: rt_current_thread as global
* scheduler: add cpu object for UP scheduler
Also, maintain the rt_current_thread in cpu object on UP scheduler.
---------
Signed-off-by: Shell <smokewood@qq.com>
[OFW] io ranges use ptr array to storage without ofw data
ofw data is private data for every ofw node that
the drivers of ofw node will use item.
replace the ranges supported to a ptr array.
the ptr array size is config by `RT_USING_OFW_BUS_RANGES_NUMBER`
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* [PIC] Make affinity helper interface
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* [PIC/GIC] Fixup GIC affinity init
GICv2 is not support if current CPU is not startup,
but RT-Thread SMP is startup after the devices init
in the `main` thread.
This patch fixup the cpumask to init once and check
the init status in affinity interface.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
---------
Signed-off-by: GuEe-GUI <2991707448@qq.com>
The OFW map id is always use in DMA, PCI, IOMMU
bus system to find the device identity. this is
a access interface.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
DFS mount auto by kernel parameters
1.Mount the rootfs options by parameters:
- root=: root device, like vda1, sda1, sd0p1, nvme0n0p1...
- rootfstype=: root file system type, like elm, ext, crom...
- rw/ro: root is readonly or all enable, if not have 'rw' flag,
the 'ro' flag is default.
- rootwait: always wait for root device status is OK.
- rootdelay=: mount rootfs delay amount of time (millisecond).
2.Mount the other fs options by `fstab.sh`, it will read the script
after root mount is OK, it's format is a list of mount cmds in MSH:
mount vda2 /mnt elm
mount 192.168.1.1:/ /mnt/remote nfs
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* bsp: cvitek: kconfig: add wdt for cv18xx_riscv
Add Watchdog timer in Kconfig.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* drv: cvitek: remove using macro from source file
Building of source file should be controlled by SConscript,
but not in source file itself.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp: cvitek: kconfig: add i2c for cv18xx_riscv
Add I2C in Kconfig for c906B.
Note, the IRQ# is different from that of c906L.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp: cvitek: kconfig: add rtc for cv18xx_riscv
Add RTC in Kconfig for c906B.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp: cvitek: fix channel issue for pwm driver
The original code confuses the concepts of controllers and channels.
Fixed it and do some code cleanup.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp:cvitek: add i2c pinmux config for cv18xx_riscv
Pinmux in driver code is controlled by SOC type, bcos driver
code should be general and support all pins defined by SoC.
Pinmux configuration in Kconfig is controlled by BOARD type,
bcos when we operate on board, it does not expose all chip-level
pin signals and we can only use part of them.
Following is I2C signals exported by duo family. Details see
https://milkv.io/docs/duo/overview.
Note: we have not added support for duo-S.
Duo
===
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL
GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo 256m
========
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL
GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo S
=====
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL
J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL
J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA
J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL
J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL
J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA
J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA
J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL
J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL
J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA
J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: flyingcys <flyingcys@163.com>
* bsp:cvitek: remove using macro from source file for i2c
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp:cvitek: unify menu message text for i2c as other drivers
Other dirvers has no extra word "HW".
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp:cvitek: add i2c pinmux config for c906_little
Porting what we have done in commit "bsp:cvitek: add i2c pinmux config
for cv18xx_riscv" to c906_little.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---------
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: flyingcys <flyingcys@163.com>
Co-authored-by: flyingcys <flyingcys@163.com>
This change addresses a potential out-of-memory access issue in the
devfs filesystem component. The issue arises when the `rt_malloc`
function allocates memory for a path string without accounting for
the null terminator, leading to undefined behavior.
As the manual documented:
> DESCRIPTION
> The strlen() function calculates the length of the string pointed to
> by s, excluding the terminating null byte ('\0').
To fix this, the memory allocation size was increased by one byte
to ensure space for the null terminator. This prevents potential
out-of-memory access and ensures proper string termination.
Signed-off-by: Shell <smokewood@qq.com>
* [libcpu/arm64] add C11 atomic ticket spinlock
Replace the former implementation of flag-based spinlock which is unfair
Besides, C11 atomic implementation is more readable (it's C anyway),
and maintainable. Cause toolchain can use their builtin optimization and
tune for different micro-architectures. For example armv8.5 introduces a
better instruction. The compiler can help with that when it knows your
target platform in support of it.
Signed-off-by: Shell <smokewood@qq.com>
* fixup: RT_CPUS_NR
---------
Signed-off-by: Shell <smokewood@qq.com>
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