Commit Graph

8 Commits

Author SHA1 Message Date
Meco Man bd80b7a4a1 对finsh_set_device调用增加宏定义限制 2021-11-24 08:57:12 -05:00
yangjie 75e4c9dd0a [bsp]update GPL license to Apache-2.0, and format files 2021-04-09 10:52:34 +08:00
guozhanxin a22decb71b 【优化】在代码中移除 rt_system_object_init/rt_system_tick_init 的调用。 2020-11-23 11:39:38 +08:00
Grissiom 9568669109 rm48x50: add GCC support 2013-10-20 18:51:45 +08:00
Grissiom 6bcf1bc48b rm48x50: fix the prototype of finsh_system_init 2013-10-19 21:10:49 +08:00
Grissiom 2df7fc310f RM48 does not have cache implemented 2013-06-12 23:48:29 +08:00
Grissiom 4d40978a70 rm48x50: add finsh support 2013-05-29 23:39:09 +08:00
Grissiom f51bce3fed add rm48x50 bsp and libcpu
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:

    1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
    channel 5 in enabled and connected to IRQ.

    2, RTI driver is enabled and compare3 source is selected to counter1
    and the compare3 will generate tick in the period of 10ms. This
    value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.

In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
2013-05-24 22:55:13 +08:00