When saving thread registers in context_switch_interrupt_to, we don't
change them, just move them. So there is no need to always r0-r3 from
stack to the real r0-r3. So just use the intermediate registers and
eliminate 2 MOV.
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
printf("%s") will print a NULL terminated string, while rt_serial_write
should print buffer for size length. This also fix segfault when the
string is not null terminated but specified by size.
Although currently the only message send to the queue is struct
udev_msg, in order to keep backward compacity and for extention in the
future, we set the size of message to 32.
It also add two configurations for the USB device even loop thread:
RT_USBD_THREAD_STACK_SZ to set the stack size, default to 2048
RT_USBD_THREAD_PRIO to set the priority, default to 8
You can overwrite the default values in rtconfig.h
We start the sending transaction in SOF handler. But if the data is
already sending, start an other transaction will cause data lose.
Implement a state machine is cdc_vcom and avoid that.
This commit set the buffer for packet to CDC_MaxPacketSize which is a
reasonable value for it. However, maybe we should make
CDC_{RX,TX}_BUFSIZE configurable as well.
Grissiom
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