rt-thread

Commit Graph

Author	SHA1	Message	Date
shandianchengzi	e49140b513	[HUST CSE IoTS&P Lab][bsp] add missing UL suffix to BIT macro to prevent undefined behavior (#7153 ) * [bsp] add missing UL suffix to BIT macro to prevent undefined behavior. * [bsp] add UL suffix to BIT macro for consistency and readability. * fix toUppercase. * fix the abnormal character. * format the file.	2023-04-03 23:05:42 +08:00
guo	ecf2d82159	sync branch rt-smart. (#6641 ) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>	2022-12-03 12:07:44 +08:00

Author

SHA1

Message

Date

shandianchengzi

e49140b513

[HUST CSE IoTS&P Lab][bsp] add missing UL suffix to BIT macro to prevent undefined behavior (#7153 )

* [bsp] add missing UL suffix to BIT macro to prevent undefined behavior.

* [bsp] add UL suffix to BIT macro for consistency and readability.

* fix toUppercase.

* fix the abnormal character.

* format the file.

2023-04-03 23:05:42 +08:00

guo

ecf2d82159

sync branch rt-smart. (#6641 )

* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>

2022-12-03 12:07:44 +08:00

2 Commits