6 Commits

Author	SHA1	Message	Date
michael	3d0bdf4bb6	MIPS:improvement FPU support	2020-08-25 11:52:07 +08:00
bigmagic	c024e2e485	add ls2k bsp config	2020-04-07 14:39:20 +08:00
bigmagic	990f731b77	fix mips64 some bug	2020-04-07 14:39:12 +08:00
Jiaxun Yang	7c66501861	[libcpu] Refine MIPS common code ... MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>	2019-12-11 15:24:04 +08:00
Bernard Xiong	72782e9203	convert end of line	2013-01-08 05:05:02 -08:00
bernard.xiong	e94adf07ca	add init Jz47xx porting. ... git-svn-id: https://rt-thread.googlecode.com/svn/trunk@792 bbd45198-f89e-11dd-88c7-29a3b14d5316	2010-07-14 09:51:49 +00:00