Commit Graph

2 Commits

Author SHA1 Message Date
Yaochenger b77241935c
[bsp][ch32v208]添加ch32v208BSP,合并libcpu/riscv 中ch系列的port文件 (#6780)
【1】添加ch32v208-r0 bsp
【2】合并libcpu/riscv 下ch系列mcu的port文件
2022-12-27 13:24:02 -05:00
blta 99526cc047 [bsp/ch32v103r-evt] add ch32v103r-evt bsp
feat: move MRS demo source to bsp and libraries folder

feat: update Sconscript

feat: modify SConstruct in the bsp

feat: use the rtconfig.py of gd32vf103v-eval bsp to modify

feat: use the MRS's rtconfig.h temoporarily

feat: update Kconfig files

feat: use the MRS's .ld and rename as link.lds

feat: add ch32v1 porting folder

perf: remove board/system_ch32v10x.c

fix: define SOC_ARM_SERIES_CH32V103 in rtconfig.h

fix: add some neccessary macros in rtconfig.h

perf: use the menuconfig to generate rtconfig.h

feat: add readme.md

fix: correct the bad encode in main.c

fix: include board.h in main.c

perf: check and update README.md

perf: remove ch32f10x_port_cn.md

feat: ignore the standard libraries's CI checking

feat: add sdk_dist.py

fix: correct some style errors again

perf: simply the board/kconfig

fix: format ch32v103r-evt

fix: format drvs and libcpu
2022-04-06 11:06:55 +08:00