Commit Graph

7279 Commits

Author SHA1 Message Date
Bernard Xiong bde4817b9e
Merge pull request #9228 from messigogogo/master
[BSP/Phytium]适配最新驱动
2024-07-25 19:03:37 +08:00
Bernard Xiong 30f995dfb4
Merge pull request #9221 from Z8MAN8/cvitek_arm_uart
bsp: cvitek: add missing soc type for aarch64
2024-07-25 18:58:34 +08:00
Bernard Xiong 660f3aa205
Merge pull request #9247 from Z8MAN8/cvitek_arm_board_init
bsp: cviteK: update board init for aarch64
2024-07-25 09:11:05 +08:00
sheltonyu d1c7712bfb
[bsp/at32] 1.add support hwi2c driver, 2.update all firmware libraries. (#9241)
* 1.add support hwi2c driver, 2.update all firmware libraries

* update some files and fixed errors

* add support a423 at hwi2c driver

* add .ignore_format.yml
2024-07-24 23:22:50 +08:00
Chen Wang c8914c7f2b bsp: cvitek: fixed stacksize issue
In the original Sconstruct script, `GetDepend('__STACKSIZE__')`
is placed before the call to `PrepareBuilding()`, which causes
the value of `GetDepend('__STACKSIZE__')` to always be False,
and the value of `__STACKSIZE__` in `link_stacksize.lds` will
not be updated.

Solution: move the call if `PrepareBuilding()` ahead.

Also sync and update the .config and rtconfig.h, plus the
link_stacksize.lds.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-24 23:18:25 +08:00
Z8MAN8 84eea6c654 bsp: cviteK: update board init for aarch64
When compiling CV18xx_arch64, have a error:
can not find "rt_fdt_commit_memregion_early"

Analysis: b785ef9 ("[libcpu][aarch64]memory setup using memblock ")
no longer support  "rt_fdt_commit_memregion_early", become use
"rt_memblock_reserve_memory"

Solution: Refer to the bsp/qemu-virt64-aarch64/drivers/board.c
delete "rt_fdt_commit_memregion_early"

Signed-off-by: Shicheng Chu <1468559561@qq.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-24 19:44:52 +08:00
Z8MAN8 4c2fe22cbe bsp: cvitek: add missing soc type for aarch64
When compiling CV18xx_arch64, there are the following errors:
1. missing soc type for aarch64
2. uart device objects defined but not used

Analysis: a63c07f ("bsp: cvitek: new design for pinmux") and
114e143("bsp:cvitek: add pinmux for uart"), CV18xx_arch64 is not
considered.

Solution: Refer to the cv18xx_riscv format to add the corresponding
chip type SOC_Type_SG2002, as well as the corresponding macro
for the serial port pins and interrupts

Signed-off-by: Shicheng Chu <1468559561@qq.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-24 19:29:46 +08:00
Bernard Xiong 8dc166b16c
Merge pull request #9242 from heyuanjie87/hyj724
[bsp/cvitek]添加ioremap兼容定义以适应smart运行
2024-07-24 13:36:11 +08:00
heyuanjie87 5b82841748 [feat]添加ioremap兼容定义以适应smart运行 2024-07-24 12:28:50 +08:00
Chen Wang 04cad7f9c6 bsp: cvitek: improve documentation
Currently, the documents under bsp/cvitek are a bit
messy. There are currently four readme files:

- bsp/cvitek/README.md (Chinese)
- bsp/cvitek/c906_little/README.md (Chinese/English)
- bsp/cvitek/cv18xx_aarch64/README.md (Chinese)
- bsp/cvitek/cv18xx_risc-v/README.md (Chinese/English)

Regarding the working mode of the big + small cores, it
is meaningless to describe the small core alone, or the
large core alone. This can also be seen in the existing
files. The readme of the small core will also introduce
the programming of the large core, and vice versa.

Considering that the official default mode is
C906B + C906L. ARM large core can be treataed as a
special case. So the document structure is modified as
follows:
- Remove `bsp/cvitek/c906_little/README.md` and
  `bsp/cvitek/cv18xx_risc-v/README.md`, merge them all
  into `bsp/cvitek/README.md`
- Add a link to `bsp/cvitek/cv18xx_aarch64/README.md`
  in `bsp/cvitek/README.md`

FIXME: The modified document does not provide English
version. Is it really necessary?

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-22 22:54:56 +08:00
zhangyan 1202d51bd6 format check 2024-07-22 10:42:30 +08:00
张衍 0e3c4bd26b [BSP/Phytium]适配最新裸机驱动 2024-07-22 02:33:39 +00:00
Z8MAN8 78f3ebfb33 [bsp][cvitek] 修复 cv18xx_aarch64 gpio 驱动相关宏配置 2024-07-21 17:37:56 +08:00
Z8MAN8 2a3bb2bf95 [bsp][cvitek]: 将adc wdt驱动的局部函数移至源文件 2024-07-21 17:37:09 +08:00
Rbb666 6b3ef17830 删除stm32/drv_pm.c不必要的头文件 2024-07-19 11:51:39 +08:00
Rbb666 1a596607ed 删除bsp:stm32l476的pm组件依赖 2024-07-19 11:51:39 +08:00
wdfk-prog 568356cc48 [stm32][pm]lptimer is supported 2024-07-19 11:51:39 +08:00
wdfk-prog fccd98747e [stm32][lptim]lptimer is register with hwtimer, only supports pm calls,the timer function is not supported 2024-07-19 11:51:39 +08:00
Chen Wang 7c1d205a4e bsp: cvitek: switch to device init function for some drivers
Some drivers use INIT_BOARD_EXPORT, it is not necessary,
it is enough to use INIT_DEVICE_EXPORT for genearl drivers.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-18 21:35:35 +08:00
MuChenger 0efc408a00 adapt to rv64ilp32 toolchain 2024-07-18 15:59:40 +08:00
Bernard Xiong a974cde8f9
Merge pull request #9201 from unicornx/dev-wdt-bugfix
bsp: cvitek:  accuulated bugfixes for wdt driver
2024-07-17 22:26:05 +08:00
Bernard Xiong a2f4e120c3
Merge pull request #9200 from unicornx/dev-spi-new
bsp: cvitek: re-wrote spi driver
2024-07-17 22:25:26 +08:00
Bernard Xiong 4e630fed08
Merge pull request #9199 from unicornx/dev-i2c-new
bsp: cvitek: re-wrote i2c driver
2024-07-17 22:24:24 +08:00
Chen Wang 1bcf232d12 bsp: cvitek: fix the wdt timeout unit problem
See `components/drivers/include/drivers/watchdog.h`

maco definition of
RT_DEVICE_CTRL_WDT_GET_TIMEOUT
RT_DEVICE_CTRL_WDT_SET_TIMEOUT
RT_DEVICE_CTRL_WDT_GET_TIMELEFT

The wdt timeout time unit is defined as seconds in the API, but
the code incorrectly uses ms.

Correct this and comply with the API definition.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Yuanjie He <943313837@qq.com>
Reviewed-by: Shell <smokewood@qq.com>
2024-07-17 16:56:07 +08:00
flyingcys 1ef2afbc93 bsp: cvitek: re-wrote spi driver
Rewrote the spi driver.

Reuse the driver code from https://github.com/sophgo/cvi_alios_open,
which is Apache 2.0 licenced.

Signed-off-by: flyingcys <flyingcys@163.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-17 11:52:27 +08:00
Shell f6f570df74
Merge branch 'master' into shell/rv64-tick 2024-07-17 09:39:54 +08:00
Chen Wang 2d5eb2669f bsp: cvitek: remove warning when building wdt driver
```
./bsp/cvitek/drivers/drv_wdt.c: In function '_wdt_control':
warning: assignment to 'void *' from 'unsigned int' makes pointer
from integer without a cast [-Wint-conversion]
  119 |         wdt_device->parent.user_data = (rt_uint32_t)(*(rt_uint32_t *)arg);
      |                                      ^
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
  122 |         *(rt_uint32_t *)arg = (rt_uint32_t)wdt_device->parent.user_data;
      |                               ^
```

Rootcasue: It's not portable to store integar in a pointer.

Solution: use global _wdt_dev to store the timeout value.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-17 09:05:26 +08:00
flyingcys dda79ad6bc bsp: cvitek: re-wrote i2c driver
Optimize the original i2c driver code.

Signed-off-by: flyingcys <flyingcys@163.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-17 08:19:03 +08:00
Chen Wang d8294de640 bsp:cvitek: add pinmux for adc
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
Chen Wang 2c85bcb463 bsp:cvitek: add pinmux for spi
Board level pin available info:

duo & duo256:

NAME    SPI         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP6     SPI2_SCK    PWR_GPIO[23]    SD1_CLK__SPI2_SCK
GP7     SPI2_SDO    PWR_GPIO[22]    SD1_CMD__SPI2_SDO
GP8     SPI2_SDI    PWR_GPIO[21]    SD1_D0__SPI2_SDI
GP9     SPI2_CS_X   PWR_GPIO[18]    SD1_D3__SPI2_CS_X

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
Chen Wang 51825a5b5c bsp:cvitek: add pinmux for pwm
Board level pin available info is summarized and list here for memo:

Duo:

NAME    PWM         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
PWM-1
GP9     PWM4        PWR_GPIO[18]    SD1_D3__PWM_4
GP12    PWM4        XGPIOA[16]      UART0_TX__PWM_4

GP4     PWM5        PWR_GPIO[19]    SD1_D2__PWM_5
GP13    PWM5        XGPIOA[17]      UART0_RX__PWM_5

GP5     PWM6        PWR_GPIO[20]    SD1_D1__PWM_6

GP8     PMW7        PWR_GPIO[21]    SD1_D0__PWM_7

PWM-2
GP7     PWM8        PWR_GPIO[22]    SD1_CMD__PWM_8
GP6     PWM9        PWR_GPIO[23]    SD1_CLK__PWM_9
GP2     PWM10       PWR_GPIO[26]    SD1_GPIO1__PWM_10
GP3     PWM11       PWR_GPIO[25]    SD1_GPIO0__PWM_11

Duo256:

NAME    PWM         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
PWM-1
GP9     PWM4        PWR_GPIO[18]    SD1_D3__PWM_4
GP12    PWM4        XGPIOA[16]      UART0_TX__PWM_4

GP4     PWM5        PWR_GPIO[19]    SD1_D2__PWM_5
GP13    PWM5        XGPIOA[17]      UART0_RX__PWM_5

GP3     PWM6        XGPIOA[18]      JTAG_CPU_TCK__PWM_6
GP5     PWM6        PWR_GPIO[20]    SD1_D1__PWM_6

GP2     PWM7        XGPIOA[19]      JTAG_CPU_TMS__PWM_7
GP8     PMW7        PWR_GPIO[21]    SD1_D0__PWM_7

PWM-2
GP7     PWM8        PWR_GPIO[22]    SD1_CMD__PWM_8
GP6     PWM9        PWR_GPIO[23]    SD1_CLK__PWM_9
GP10    PWM10       XGPIOC[14]      PAD_MIPI_TXM1__PWM_10
GP11    PWM11       XGPIOC[15]      PAD_MIPI_TXP1__PWM_11

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
Chen Wang 114e143d56 bsp:cvitek: add pinmux for uart
Board level UART pinmux summary, following capability
should be controlled by pinname whitelist.

Duo:

NAME    UART        CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP13    UART0_RX    XGPIOA[17]      UART0_RX__UART0_RX
GP12    UART0_TX    XGPIOA[16]      UART0_TX__UART0_TX

GP1     UART1_RX    XGPIOA[29]      IIC0_SDA__UART1_RX
GP13    UART1_RX    XGPIOA[17]      UART0_RX__UART1_RX
GP0     UART1_TX    XGPIOA[28]      IIC0_SCL__UART1_TX
GP12    UART1_TX    XGPIOA[16]      UART0_TX__UART1_TX

GP1     UART2_RX    XGPIOA[29]      IIC0_SDA__UART2_RX
GP5     UART2_RX    PWR_GPIO[20]    SD1_D1__UART2_RX
GP0     UART2_TX    XGPIOA[28]      IIC0_SCL__UART2_TX
GP4     UART2_TX    PWR_GPIO[19]    SD1_D2__UART2_TX

GP5     UART3_RX    PWR_GPIO[20]    SD1_D1__UART3_RX
GP4     UART3_TX    PWR_GPIO[19]    SD1_D2__UART3_TX

GP3     UART4_RX    PWR_GPIO[25]    SD1_GPIO0__UART4_RX
GP2     UART4_TX    PWR_GPIO[26]    SD1_GPIO1__UART4_TX

Duo 256m:

NAME    UART        CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP13    UART0_RX    XGPIOA[17]      UART0_RX__UART0_RX
GP12    UART0_TX    XGPIOA[16]      UART0_TX__UART0_TX

GP1     UART1_RX    XGPIOA[29]      IIC0_SDA__UART1_RX
GP3     UART1_RX    XGPIOA[18]      JTAG_CPU_TCK__UART1_RX
GP13    UART1_RX    XGPIOA[17]      UART0_RX__UART1_RX
GP0     UART1_TX    XGPIOA[28]      IIC0_SCL__UART1_TX
GP2     UART1_TX    XGPIOA[19]      JTAG_CPU_TMS__UART1_TX
GP12    UART1_TX    XGPIOA[16]      UART0_TX__UART1_TX

GP1     UART2_RX    XGPIOA[29]      IIC0_SDA__UART2_RX
GP5     UART2_RX    PWR_GPIO[20]    SD1_D1__UART2_RX
GP0     UART2_TX    XGPIOA[28]      IIC0_SCL__UART2_TX
GP4     UART2_TX    PWR_GPIO[19]    SD1_D2__UART2_TX

GP5     UART3_RX    PWR_GPIO[20]    SD1_D1__UART3_RX
GP4     UART3_TX    PWR_GPIO[19]    SD1_D2__UART3_TX

Note: this patch also update the .config and rtconfig.h
because this patch modify some configuration items's name,
for example: RT_USIMG_UART0 -> BSP_USING_UART0.

FIXME: only handle RISC-V related, no ARM.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
Chen Wang e1eb3d3217 bsp:cvitek: add pinmux for i2c
Based on new pinmux framework, add configuration for uart.

Board level pin available info is summarized and should be
controlled by pin whitelist.

Duo

NAME    I2C         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP0     I2C0_SCL    XGPIOA[28]      IIC0_SCL__IIC0_SCL
GP1     I2C0_SDA    XGPIOA[29]      IIC0_SDA__IIC0_SDA

GP4     I2C1_SCL    PWR_GPIO[19]    SD1_D2__IIC1_SCL
GP9     I2C1_SCL    PWR_GPIO[18]    SD1_D3__IIC1_SCL
GP11    I2C1_SCL    XGPIOC[10]      PAD_MIPIRX0N__IIC1_SCL
GP5     I2C1_SDA    PWR_GPIO[20]    SD1_D1__IIC1_SDA
GP8     I2C1_SDA    PWR_GPIO[21]    SD1_D0__IIC1_SDA
GP10    I2C1_SDA    XGPIOC[9]       PAD_MIPIRX1P__IIC1_SDA

GP7     I2C3_SCL    PWR_GPIO[22]    SD1_CMD__IIC3_SCL
GP6     I2C3_SDA    PWR_GPIO[23]    SD1_CLK__IIC3_SDA

Duo256m

NAME    I2C         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP4     I2C1_SCL    PWR_GPIO[19]    SD1_D2__IIC1_SCL
GP9     I2C1_SCL    PWR_GPIO[18]    SD1_D3__IIC1_SCL
GP5     I2C1_SDA    PWR_GPIO[20]    SD1_D1__IIC1_SDA
GP8     I2C1_SDA    PWR_GPIO[21]    SD1_D0__IIC1_SDA

GP11    I2C2_SCL    XGPIOC[15]      PAD_MIPI_TXP1__IIC2_SCL
GP10    I2C2_SDA    XGPIOC[14]      PAD_MIPI_TXM1__IIC2_SDA

GP7     I2C3_SCL    PWR_GPIO[22]    SD1_CMD__IIC3_SCL
GP6     I2C3_SDA    PWR_GPIO[23]    SD1_CLK__IIC3_SDA

Duo S(Note, we have not supported duo S, just list for memo)

NAME    I2C         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------

J3-B18  I2C1_SCL    XGPIOB[18]      VIVO_D3__IIC1_SCL
J3-B12  I2C1_SCL    XGPIOB[12]      VIVO_D9__IIC1_SCL
J3-B11  I2C1_SDA    XGPIOB[11]      VIVO_D10__IIC1_SDA

J3-B13  I2C2_SCL    XGPIOB[13]      VIVO_D8__IIC2_SCL
J4-E1   I2C2_SCL    PWR_GPIO[1]     PWR_GPIO1__IIC2_SCL
J3-B14  I2C2_SDA    XGPIOB[14]      VIVO_D7__IIC2_SDA
J4-E2   I2C2_SDA    PWR_GPIO[2]     PWR_GPIO2__IIC2_SDA

J3-B20  I2C4_SCL    XGPIOB[20]      VIVO_D1__IIC4_SCL
J4-B1   I2C4_SCL    XGPIOB[1]       ADC3__IIC4_SCL
J3-B21  I2C4_SDA    XGPIOB[21]      VIVO_D0__IIC4_SDA
J4-B2   I2C4_SDA    XGPIOB[2]       ADC2__IIC4_SDA

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
Chen Wang d8d0af9143 bsp:cvitek: add calibration for adc
The ADC controller needs to be calibrated during the initialization
phase, otherwise the measured voltage value will be inaccurate.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 11:47:22 +08:00
Chen Wang a63c07fd75 bsp: cvitek: new design for pinmux
In the new design, we require the user to manually enter the
PinName (as a string) in menuconfig instead of being given
menu items to select.

The original method will lead to too many menu item-related
macros being defined in the code, causing ifdef and other
codes scatter everywhere in the driver code, which is
inconvenient to maintain.

The new design adds a pinmux driver module to manage the
multiplexing of pins. This patch provides this driver module.

P.S., the reason why users are allowed to specify pinname
in a string instead of the pin number is mainly because
the technical manual provided by the SOC manufacturer
does not have numbers for some pins, only names.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Yuanjie He <943313837@qq.com>
Reviewed-by: Shell <smokewood@qq.com>
2024-07-16 11:37:23 +08:00
Chen Wang 80668e0ba2 bsp:cvitek: revert add i2c pinmux config for c906
The contents of the SOC type part in the Kconfig configuration
are retained, and other parts related to I2C pin multiplexing
selection have been rolled back.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Yuanjie He <943313837@qq.com>
Reviewed-by: Shell <smokewood@qq.com>
2024-07-16 11:37:23 +08:00
Fan Yang 96ba787e25
Bugfix/fix weak handle trap in riscv common crash rv64 trap handling (#9189)
* [bsp][hpmicro] add weak handle_trap implementation

- added weak handle_trap implementation

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

* [libcpu][risc-v][common] remove weak handle_trap function

- removed weak handle_trap function from trap_common.c

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

---------

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
2024-07-15 17:51:32 +08:00
Shell 65ffe4e13e [libcpu/rv64] feat: unify tick.c
The changes unify the tick.c implementations for all risc-v64
architectures, leveraging the CPUTIME feature. This refactoring was
necessary to streamline the codebase, and ensure consistent timer
handling across different platforms.

Changes:
- Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues.
- Updated .config for BSPs to update `CPUTIME_TIMER_FREQ`
- Updated header of for API `riscv_cputime_init`
- Initialized riscv timer on `rt_hw_tick_init`
- Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`:
  - Replaced direct use of `rdtime` with `clock_cpu_gettime`.
  - Removed redundant timer frequency definitions.
  - Added static assertions to check the value of `CPUTIME_TIMER_FREQ`.
  - Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`.
  - Integrated `ktime` support for tick initialization.

Signed-off-by: Shell <smokewood@qq.com>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-15 12:06:39 +08:00
wdfk-prog df948ad603 [STM32][SPI]移除内部编写的延时函数使用统一延时接口 2024-07-12 17:48:17 +08:00
heyuanjie87 6180dabab3
[bsp/cvitek]将eth驱动中地址类型改为指针以适应ioremap (#9137)
ioremap后地址可能超32位
2024-07-11 10:28:02 +08:00
LZerro befa478073 [bsp][stm32_rt_spark]Add README_EN 2024-07-09 20:18:53 +08:00
Shell b73396681a
[bsp/allwinner] feat: porting to RT_USING_DEVICE_OPS (#9142)
* [bsp/allwinner] feat: porting to RT_USING_DEVICE_OPS

This patch ports the codebase to use the RT_USING_DEVICE_OPS structure,
which is required by v5.1.0 Smart kernel, improves modularity and makes
it easier to manage device operations by consolidating them into a
single structure, enhancing maintainability and future scalability.

Changes:
- Added RT_USING_DEVICE_OPS conditionals to partition.c and drv_sdmmc.c.
- Defined rt_device_ops structures for partition and sdmmc drivers.
- Updated device initialization to use the ops structure if defined.
- Replaced direct function calls with rt_dev_control, rt_dev_read, and
  rt_dev_write macros where applicable.
- Removed redundant us_delay function from os.c.

Signed-off-by: Shell <smokewood@qq.com>

* feat: update configuration

* feat: fixup compiler warning

---------

Signed-off-by: Shell <smokewood@qq.com>
2024-07-09 13:35:03 +08:00
Shell 66ff62413e document: add ref to gpio pinout 2024-07-08 22:09:35 +08:00
LZerro 04b77e409e [bsp][NXP]Fix .md picture mistakes 2024-07-08 22:06:53 +08:00
LZerro b47b6df927 [bsp][Infineon]&[NXP] Add README_EN 2024-07-08 22:06:53 +08:00
Rbb666 b171877139 [bsp][qemu]修复qemu-a9使能lcd缺失依赖问题. 2024-07-07 22:24:09 +08:00
heyuanjie87 776764c4d6 [bsp/cvitek/eth]解决编译警告 2024-07-04 00:33:32 +08:00
Rbb666 5f70f974d5 [bsp][stm32]Increase the serial_v1 tx timeout. 2024-07-04 00:33:06 +08:00
heyuanjie87 017c31a062 [bsp/cvitek]解决eth编译报错 2024-07-02 22:54:58 +08:00
Rbb666 8487e774a3 [bsp][stm32]fix stm32h7 spi transmit fail probelm. 2024-07-02 22:54:23 +08:00