4813 Commits

Author SHA1 Message Date
Meco Man
a992226863 [libc] uncomment wcwidth for win32 2024-12-24 13:42:04 +08:00
kurisaw
b23d667ba4 Specification of rtc synchronization functions 2024-12-23 19:40:11 -05:00
zhujiale
2d78d8cad1 [dm2.0] add general sdhci driver it support pio&&sdma 2024-12-22 19:35:34 +08:00
Meco Man
a9746edc08 [utest] optimize the utest to support new CI 2024-12-21 14:57:17 -05:00
Meco Man
7772d4619a [klibc] format code 2024-12-21 14:57:17 -05:00
Chen Wang
7c7ff6e532 kernel: cleanup debug APIs
- `dbg_log` is a “NOT RECOMMENDED API”, convert the calling of this
  API to LOG_x and remove this API.

- `dbg_here`/`dbg_enter`/`dbg_exit`: no one use these APIs, remove
  them directly.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-12-20 17:50:00 -05:00
ligr
1499dbda00 [components][libc/io]add comments for timer fd APIs. 2024-12-18 21:07:42 -05:00
GuEe-GUI
b294fba565 [DM/PIC] Support AMP mode
Only support on >= ARM GICv2

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-18 21:42:12 +08:00
GuEe-GUI
c9ab55f7a5 [DM/MAILBOX] Support PIC mailbox in AMP
Should registers clean by master in AMP.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-18 21:42:12 +08:00
GuEe-GUI
07b114ae73 [DFS/FIXUP] Fixup ISO9660 build
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-18 21:37:51 +08:00
zhujiale
e4760364f1 [serial] add bypass testcase in utest 2024-12-17 11:08:14 +08:00
zhujiale
27cf024585 [serial] add bypass hook to direct processing char when uart irq coming 2024-12-17 11:08:14 +08:00
wumingzi
c1166e0bf1 [OFW] Delete redundant strcasecmp function 2024-12-14 12:40:39 -05:00
kurisaw
23256d35bc [drivers][rtc] Fixed software and hardware rtc device naming as rtc 2024-12-13 17:41:44 -05:00
GuEe-GUI
1c54ff4de6 [DM/FIXUP] Fixup block value init
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-13 10:39:20 +08:00
GuEe-GUI
ec4f375bbc [DM/FIXUP] Fixup PIC ktime depends
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-13 10:39:20 +08:00
GuEe-GUI
a729a82706 [BSP/FIXUP] remove old reset drivers for RK3500
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-13 10:39:20 +08:00
GuEe-GUI
0ede1d6c65 [DM/FIXUP] Fixup NVME build
1. Fixup Kconfig show order.
2. Fix `RT_DECLARE_IRQ_AFFINITY` to `RT_IRQ_AFFINITY_DECLARE`
3. Remove warning.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-13 10:39:20 +08:00
GuEe-GUI
d248a3a288 [DM/FIXUP] Fixup PCI build
1. Add PCI include in rtdevice.h
2. Fixup `RT_KEY_ENABLED` loss.
3. remove waring type of `dw_pcie_ep_get_func_from_ep` return.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-13 10:39:20 +08:00
GuEe-GUI
76d3cf3b86 [DM/FIXUP] Fixup bitmap to new type
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-13 10:39:20 +08:00
GuEe-GUI
63bbce1c1f [DM/FIXUP] include name default
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-13 10:39:20 +08:00
zhujiale
ee5b7f1de9 [lwp] fix TTYSUP_CFLAG did not include CBAUD flag 2024-12-12 18:54:30 -05:00
zhujiale
e7b30ed2cc [componets] fix when printf 0 addr by %p will return nil 2024-12-09 19:45:40 -05:00
Supper Thomas
5b75e1c8bf doc(doxyge):fix doxygen path 2024-12-09 17:12:59 -05:00
wycwyhwyq
6876cb6f73
[components] When rtc is not enabled, use other clock sources instead (#9747)
When rtc is not enabled, use other clock sources instead

Signed-off-by: wycwyhwyq <5f20.6d9b@gmail.com>
2024-12-06 20:13:03 +08:00
kurisaw
3f1a62cfe3 [libcpu][drivers] cortex-r52 abnormal takeover and software rtc naming change 2024-12-04 10:11:04 +08:00
ligr
1cf97d8565 [components][dfs]add some comments and fix some former comments error for dfs v1. 2024-12-03 19:10:21 -05:00
GuEe-GUI
0de160f418 [DM/THERMAL] Add PWM cool fan
PWM fan is the most populate cool device.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-02 21:17:24 +08:00
GuEe-GUI
429c0c5257 [DM/FEATURE] Support thermal
Thermal drivers offer a generic mechanism for thermal management.
Usually it's made up of one or more thermal zones and cooling devices.
Each thermal zone contains its own temperature, trip points, and cooling devices.
All platforms with ACPI or OFW thermal support can use this driver.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-02 21:17:24 +08:00
GuEe-GUI
8c0a6c934b [DM/FEATURE] Support import SoC PIN config
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-02 21:15:17 +08:00
GuEe-GUI
e3340eca34 [DM/FEATURE] Support virtual pin
1. There is only one GPIO device in System.
2. For Pin API input is pin number
3. Add sets pin debounce time API.

So we need a virtual pin for multi gpio chip.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-02 21:15:17 +08:00
GuEe-GUI
16608279db [DM/FIXUP] Fixup pin propname check
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-02 21:15:17 +08:00
GuEe-GUI
7c59bb01ed [DM/FIXUP] Fixup pin flags get from OFW
Only check HIGH or LOW

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-02 21:15:17 +08:00
GuEe-GUI
aa30e9804a [DM/FIXUP] Fixup pin depend auto
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-02 21:15:17 +08:00
GuEe-GUI
7b7e4686af [DM/MAILBOX] Fixup platform request will deadlock
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-02 21:14:34 +08:00
GuEe-GUI
72a78a268f [DM/DMA] merge ofw_parse and request_chan
Work together can make DMA engine device drivers
knows how want a chan easy.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-02 21:14:13 +08:00
GuEe-GUI
8f392779ef [DM/DMA] Use strict mode for device DMA pool
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-12-02 21:14:13 +08:00
ligr
e9452ee98f [documentation][dfs]add some comments to dfs posix APIs for supplement. 2024-11-30 21:09:58 -05:00
GuEe-GUI
88b8310d16 [DM/PCI] Add DesignWare PCIe RC/EP base drivers
Too many PCI controllers base on DesignWare PCIe.
This is a modules.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-28 09:46:58 +08:00
GuEe-GUI
50982cd970 [DM/PCI] Add memory window pool for EP
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-28 09:46:58 +08:00
GuEe-GUI
0d2e677f07 [DM/LED] Add GPIO LED driver
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-28 09:46:02 +08:00
GuEe-GUI
175a7d26bf [DM/FEATURE] Support LED
Provides general LED control API and drivers.
It can work on PWM, GPIO and Syscon...

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-28 09:46:02 +08:00
GuEe-GUI
6f68ca7c71 [DM/SPI] Support DM mode in SPI
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-27 18:04:07 +08:00
GuEe-GUI
49d18ec0a9 [DM/REGULATOR] Add populate drivers
1. Fixed regulator.
2. GPIO regulator.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-27 18:02:23 +08:00
GuEe-GUI
56614a4cb9 [DM/FEATURE] Support regulator
1. Add the regulator driver framework.
2. Add the generic voltage and current regulator API support
  for drivers.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-27 18:02:23 +08:00
Meco Man
443ade4c29 [sscanf] use rt_sscanf to replace sscanf 2024-11-27 10:59:15 +08:00
ligr
ca1d4e6dea [components][ulog]add some comments to ulog for supplement. 2024-11-26 20:05:09 +08:00
GUI
d025072837
[DM/FEATURE] Support ATA AHCI (#9683)
Add ACHI drivers to support some old platform
driver such as SATA.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-26 11:22:09 +08:00
GuEe-GUI
71520fa9f1 [DM/FIXUP] Add ms sleep for link status change
We should wait a while for success or failure
after link status change or will communicate
fail with the endpoint.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-26 11:14:51 +08:00
GuEe-GUI
1ac8044294 [DM/FIXUP] Fixup PCI device ofw private node for MSI
Some PCI device devicetree is like:
```dts
pcie@fe270000 {
    device_type = "pci";
    msi-map = <0x1000 0x9c 0x1000 0x1000>;

    pcie@10 {
        reg = <0x100000 0x00 0x00 0x00 0x00>;
        #address-cells = <0x03>;
        #size-cells = <0x02>;

        pcie@10,0 {
            reg = <0x00 0x00 0x00 0x00 0x00>;
        };
    };
};
```

that the pcie@10,0 have a private ofw node, it will find
property name `msi-map` or `msi-parent` fail.
We should only find the property in host bridge's ofw node.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-26 11:14:51 +08:00