charlown
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9ec326f931
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[bsp/wch/arm/Libraries/ch32_drivers/drv_pwm_ch32f10x.c]:support pwm.
[bsp/wch/arm/ch32f103c8-core]:add timer1~4(include 4 channel) pwm.
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2021-09-23 23:20:16 +08:00 |
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charlown
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5ce84153f3
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[bsp/wch/arm/Libraries/ch32_drivers/drv_hwtimer_ch32f10x.c]:rename func: ch32f1_hwtimer_clock_init, ch32f1_hwtimer_clock_get, hwtimer and pwm will be use it. change some code annotation.
[bsp/wch/arm/ch32f103c8-core]: rename func.
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2021-09-10 17:12:31 +08:00 |
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charlown
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84111766f9
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[bsp/wch/arm/Libraries/ch32_drivers]: support ch32f10x hwtimer.
[bsp/wch/arm/ch32f103c8-core]: add hwtimer1~4.
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2021-09-08 16:45:55 +08:00 |
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charlown
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7aa4dfec8b
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[wch/arm/ch32f103c8-core]:format board/Kconfig, format README.md.
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2021-09-07 16:11:07 +08:00 |
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charlown
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abeb9500d0
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fix rtconfig.py param: DEVICE = cortex-m3 in other platform.
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2021-09-06 13:42:48 +08:00 |
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charlown
|
5169360e21
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support gcc for ch32f10x.
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2021-09-03 15:44:19 +08:00 |
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charlown
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02a3ac4036
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format wch bsp code.
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2021-09-02 22:49:01 +08:00 |
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charlown
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2e74dd8e2d
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support ch32f10x family, add ch32f103c8-core bsp
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2021-08-31 14:41:35 +08:00 |