* [libcpu] support for ARCH_REMAP_KERNEL
These changes introduce support for the ARCH_REMAP_KERNEL configuration,
which isolates kernel space in high virtual address regions. This feature
is necessary to enhance memory protection and management by segregating
user and kernel spaces more effectively.
Changes:
- Updated conditional macros to check for ARCH_REMAP_KERNEL instead of
ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new
configuration option.
- Modified qemu-virt64-riscv Kconfig and SConstruct files to include and
utilize ARCH_REMAP_KERNEL.
- Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv.
- Updated rtconfig.py to use a more flexible execution path setup.
- Enhanced user address space definitions in `lwp_arch.h` to support the
new virtual address mappings.
- Adjusted kernel memory initialization and mapping logic in `c906/mmu.c`
and `virt64/mmu.c` to account for high virtual address regions.
- Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures.
- Enhanced memory setup functions to support new mapping scheme, including
updates to early page table setup and address relocation logic.
These modifications ensure that the system can utilize high memory
addresses for the kernel, improving memory isolation and system stability.
Signed-off-by: Shell <smokewood@qq.com>
* fixup: CI run failed
* bsp: default config without using smart
* fixup: static checks
* restore rt_hw_mmu_kernel_map_init for D1
---------
Signed-off-by: Shell <smokewood@qq.com>
- added new boards: hpm5300evk, hpm5301evklite and hpm6800evk
- upgaded hpm_sdk
- driver updates and bugfixes
- add hpmicro BSPs to CI
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
* bsp: cvitek: kconfig: add wdt for cv18xx_riscv
Add Watchdog timer in Kconfig.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* drv: cvitek: remove using macro from source file
Building of source file should be controlled by SConscript,
but not in source file itself.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp: cvitek: kconfig: add i2c for cv18xx_riscv
Add I2C in Kconfig for c906B.
Note, the IRQ# is different from that of c906L.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp: cvitek: kconfig: add rtc for cv18xx_riscv
Add RTC in Kconfig for c906B.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp: cvitek: fix channel issue for pwm driver
The original code confuses the concepts of controllers and channels.
Fixed it and do some code cleanup.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp:cvitek: add i2c pinmux config for cv18xx_riscv
Pinmux in driver code is controlled by SOC type, bcos driver
code should be general and support all pins defined by SoC.
Pinmux configuration in Kconfig is controlled by BOARD type,
bcos when we operate on board, it does not expose all chip-level
pin signals and we can only use part of them.
Following is I2C signals exported by duo family. Details see
https://milkv.io/docs/duo/overview.
Note: we have not added support for duo-S.
Duo
===
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL
GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo 256m
========
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL
GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo S
=====
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL
J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL
J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA
J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL
J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL
J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA
J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA
J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL
J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL
J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA
J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: flyingcys <flyingcys@163.com>
* bsp:cvitek: remove using macro from source file for i2c
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp:cvitek: unify menu message text for i2c as other drivers
Other dirvers has no extra word "HW".
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp:cvitek: add i2c pinmux config for c906_little
Porting what we have done in commit "bsp:cvitek: add i2c pinmux config
for cv18xx_riscv" to c906_little.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---------
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: flyingcys <flyingcys@163.com>
Co-authored-by: flyingcys <flyingcys@163.com>
为什么提交这份PR (why to submit this PR)
ps：在设备初始化阶段不应该存在对硬件的操作
你的解决方案是什么 (what is your solution)
ps：添加一个pin_init函数，在spi设备使用时调用该函数来完成硬件引脚的状态初始化，而不是在设备初始化阶段对硬件进行操作，已经在瑞萨HMI上通过验证
* [bsp][nxp] add missing drv_spi.h
Otherwise when building spi users such as u8g2, gcc will complain can't
find the drv_spi.h.
* [bsp][nxp] enable spi6
* [bsp][nxp] add spi sample code which uses spi6 to loopback
Connect spi6's MISO <--> MSIO, I.E P3_20 and P3_22 with Dupont Line
The sample usage and output would be:
msh >spi_sample
spi rbuf : 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
spi loopback mode test over!
/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/bin/ld: rt-thread/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.o: in function `spixfer':
rt-thread/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.c:150:(.text.spixfer+0x102): undefined reference to `LPSPI_MasterTransferEDMA'
/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/bin/ld: rt-thread/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.c:160:(.text.spixfer+0x16c): undefined reference to `LPSPI_MasterTransferEDMA'
/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/bin/ld: rt-thread/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.o: in function `rt_hw_spi_init':
rt-thread/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.c:211:(.text.rt_hw_spi_init+0x22e): undefined reference to `LPSPI_MasterTransferCreateHandleEDMA'
This patch adds support for PWM generation using CTIMER on MCXN devices.
Each CTIMER provides 4 PWM channels, channels sharing the same
CTIMER instance will have the same period settings, and the duty
cycle will be maintained if period is changed through one of the four
channels.
The period channel is automatically assigned and will be transferred
to one of the other available channels if that channel is used for PWM
generation, no glitches should be expected during the transition.
The patch also provides a sample PWM output configuration connected to
the on-board green LED which can be enabled through Kconfig.
Signed-off-by: Yilin Sun <imi415@imi.moe>
This patch adds support for hwtimer using MRT0 instance which simulates
4 independent timers. The frequency is fixed to AHB bus frequency and
not adjustable.
Signed-off-by: Yilin Sun <imi415@imi.moe>
1 - The current linker flags undefines `Reset_Handler' and uses `entry()' as
default entry point (specified by `-e'), which will cause a invalid reset
vector in the image without proper crt0 init assembly routine.
2 - The default startup files provided by NXP violate the crt0 assumption
that bss section will be filled with zero unless macro `__STARTUP_CLEAR_BSS'
is defined. This will cause RTT hook funtion pointers set to non-NULL values at
kernel start, thus successfully passes the `RT_nnnn_HOOK_CALL` checks
and jumps to an invalid pointer.
3 - The default heap size used by TCB and kernel objects are set by
linker file macros, which is 0x400 (1024 bytes). The size is too small
for main task and the allocation will fail before the first task being created.
This patch restores Reset_Handler as default reset vector and executes
entry by replacing __START from newlib, defines the
`__STARTUP_CLEAR_BSS` macro to forcibly zeroize the bss section to avoid
unexpected hard faults, set proper heap sizes based on the SRAM sizes.
Some unused compiler/linker flags are also removed or replaced to avoid
future confusion.
The heap sizes for different devices are:
* LPC55(S)69/LPC55(S)28: 64kB
* LPC55(S)06/LPC55(S)16/LPC55(S)36: 32kB
Signed-off-by: Yilin Sun <imi415@imi.moe>
The following RTT constant table sections are missing from the linker
script which will cause non-functional image:
* .rti_fn*
* FSymTab
* VSymTab
Add these sections after .text sections.
Signed-off-by: Yilin Sun <imi415@imi.moe>
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