Commit Graph

930 Commits

Author SHA1 Message Date
MuChenger 0efc408a00 adapt to rv64ilp32 toolchain 2024-07-18 15:59:40 +08:00
Shell 2d1eba8bf3 [libcpu] quality: call PV_OFFSET on entry for once
This patch improves the efficiency and readability of the AArch64 common setup
code by calculating the `PV_OFFSET` once at the start and reusing the value.
This change reduces redundant calculations.

Signed-off-by: Shell <smokewood@qq.com>
2024-07-17 05:23:52 +00:00
Shell f6f570df74
Merge branch 'master' into shell/rv64-tick 2024-07-17 09:39:54 +08:00
zms123456 23fc7bfa4d
[libcpu][setup]fix fdt_ptr error (#9138)
fix fdt_ptr error
2024-07-16 17:04:55 +08:00
rcitachi 14fb55933b
[lwp][vdso] Add VDSO functionality under the aarch64 architecture (#9176)
Add VDSO functionality under the aarch64 architecture
2024-07-15 17:58:29 +08:00
Fan Yang 96ba787e25
Bugfix/fix weak handle trap in riscv common crash rv64 trap handling (#9189)
* [bsp][hpmicro] add weak handle_trap implementation

- added weak handle_trap implementation

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

* [libcpu][risc-v][common] remove weak handle_trap function

- removed weak handle_trap function from trap_common.c

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

---------

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
2024-07-15 17:51:32 +08:00
Shell 65ffe4e13e [libcpu/rv64] feat: unify tick.c
The changes unify the tick.c implementations for all risc-v64
architectures, leveraging the CPUTIME feature. This refactoring was
necessary to streamline the codebase, and ensure consistent timer
handling across different platforms.

Changes:
- Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues.
- Updated .config for BSPs to update `CPUTIME_TIMER_FREQ`
- Updated header of for API `riscv_cputime_init`
- Initialized riscv timer on `rt_hw_tick_init`
- Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`:
  - Replaced direct use of `rdtime` with `clock_cpu_gettime`.
  - Removed redundant timer frequency definitions.
  - Added static assertions to check the value of `CPUTIME_TIMER_FREQ`.
  - Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`.
  - Integrated `ktime` support for tick initialization.

Signed-off-by: Shell <smokewood@qq.com>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-15 12:06:39 +08:00
childerxxx d7914defdd Correct ".cpu cortex-m4" to ".cpu cortex-m7" 2024-07-11 20:42:50 +08:00
Shell beee77f372
feat: support ARCH_REMAP_KERNEL on libcpu/c906 (#9123)
feat: [libcpu/c906] support ARCH_REMAP_KERNEL

This change was necessary to enable the remapping of the kernel image to
a high virtual address region on the c906 platform.

Changes:
- Introduced new configuration options `ARCH_REMAP_KERNEL`, and
  `ARCH_USING_ASID` under the `ARCH_RISCV64` section.
- Updated MMU initialization and switching functions to incorporate
  remapping handling.
- Modified page table setup for proper memory attribute settings.
- Added support for early memory setup, kernel remapping
- Added conditional compilation for ASID support in the `rt_aspace` struct,
  since this is not enable currently for most architecture.

Signed-off-by: Shell <smokewood@qq.com>
2024-07-11 11:00:04 +08:00
Shell 90917cc75a
[format] cleanup libcpu/aarch64 (#8950)
* [dfs] fixup compiler warning

Signed-off-by: Shell <smokewood@qq.com>

* [format] libcpu/arm64: separate context switching codes

Signed-off-by: Shell <smokewood@qq.com>

* [format] libcpu/arm64: separate vector

Signed-off-by: Shell <smokewood@qq.com>

* [format] libcpu/arm64: separate context_gcc.S

Signed-off-by: Shell <smokewood@qq.com>

* [format] libcpu/arm64: moving headers to include directory

Signed-off-by: Shell <smokewood@qq.com>

* style: replace tab with space

---------

Signed-off-by: Shell <smokewood@qq.com>
2024-06-28 00:23:09 +08:00
zms123456 ca35f6692c
[libcpu][aarch64]mmu log fixup (#9078)
mmu log fixup
2024-06-26 14:37:05 +08:00
zms123456 b785ef9ed7
[libcpu][aarch64]memory setup using memblock (#9092)
* memory setup using memblock

* map pages later
2024-06-26 14:36:49 +08:00
heyuanjie87 b09a9784f9
[libcpu/c906]与virt同步 (#9095) 2024-06-26 12:16:37 +08:00
heyuanjie87 a5a89c439f
[rv]修正signal退出后用户态sp少8的问题 (#9080) 2024-06-24 21:36:32 +08:00
heyuanjie87 06ad67d549
[rv]信号处理进入用户态前恢复gp (#9072)
* [rv/virt/stackframe.h]添加GP寄存器保存偏移量宏

* 【rv/c906/stackframe.h]定义GP寄存器存储偏移量

* [rv]信号处理切换到用户态前恢复gp
2024-06-21 09:09:41 +08:00
Shell 65c9947225
[libcpu] rv64: support for ARCH_REMAP_KERNEL (#9067)
* [libcpu] support for ARCH_REMAP_KERNEL

These changes introduce support for the ARCH_REMAP_KERNEL configuration,
which isolates kernel space in high virtual address regions. This feature
is necessary to enhance memory protection and management by segregating
user and kernel spaces more effectively.

Changes:
- Updated conditional macros to check for ARCH_REMAP_KERNEL instead of
  ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new
  configuration option.
- Modified qemu-virt64-riscv Kconfig and SConstruct files to include and
  utilize ARCH_REMAP_KERNEL.
- Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv.
- Updated rtconfig.py to use a more flexible execution path setup.
- Enhanced user address space definitions in `lwp_arch.h` to support the
  new virtual address mappings.
- Adjusted kernel memory initialization and mapping logic in `c906/mmu.c`
  and `virt64/mmu.c` to account for high virtual address regions.
- Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures.
- Enhanced memory setup functions to support new mapping scheme, including
  updates to early page table setup and address relocation logic.

These modifications ensure that the system can utilize high memory
addresses for the kernel, improving memory isolation and system stability.

Signed-off-by: Shell <smokewood@qq.com>

* fixup: CI run failed

* bsp: default config without using smart

* fixup: static checks

* restore rt_hw_mmu_kernel_map_init for D1

---------

Signed-off-by: Shell <smokewood@qq.com>
2024-06-18 11:15:59 +08:00
zhangyan 842b555358
[bsp/phytium]c++支持,gpio,qspi驱动修改 (#9059)
* GPIO驱动与QSPI驱动适配

* C++支持

* update

---------

Co-authored-by: 张衍 <zhangyan1491@phytium.com.cn>
2024-06-16 15:42:37 +08:00
Shell e5b7f3fdd8
[kservice] Enhance support for backtrace service (#9037)
[feat] Enhance support for backtrace service

rt_backtrace_formatted_print() and rt_backtrace_to_buffer() to help
debug routines.

Also, following modification are included:
- make rt_backtrace_frame patchable with weak attr
- replace lwp backtrace with sync output

Signed-off-by: Shell <smokewood@qq.com>
2024-06-13 08:55:53 +08:00
Shell a12736e4c8
[libcpu] arm64: implement cpuid get by assembly (#9052) 2024-06-11 17:21:47 +08:00
Shell f00db6381a
[mm] precise & readable mm fault type (#9047)
* [smart] fixup: precise mm fault type

Also, fixup arm64 read access fault

* arm64: using meaningful macro on trap

* fixup: renaming macro
2024-06-07 21:34:03 +08:00
Shell f17f994f8c
[arm64] add hw thread self (#8942)
* [libcpu] arm64: Add hardware thread_self support

This patch introduces hardware-based thread self-identification
for the AArch64 architecture. It optimizes thread management by
using hardware registers to store and access the current thread's
pointer, reducing overhead and improving overall performance.

Changes include:
- Added `ARCH_USING_HW_THREAD_SELF` configuration option.
- Modified `rtdef.h`, `rtsched.h` to conditionally include
  `critical_switch_flag` based on the new config.
- Updated context management in `context_gcc.S`, `cpuport.h`
  to support hardware-based thread self.
- Enhanced `scheduler_mp.c` and `thread.c` to leverage the new
  hardware thread self feature.

These modifications ensure better scheduling and thread handling,
particularly in multi-core environments, by minimizing the
software overhead associated with thread management.

Signed-off-by: Shell <smokewood@qq.com>

* fixup: address suggestion

* fixup: rt_current_thread as global

* scheduler: add cpu object for UP scheduler

Also, maintain the rt_current_thread in cpu object on UP scheduler.

---------

Signed-off-by: Shell <smokewood@qq.com>
2024-05-28 14:27:55 +08:00
Shell 397cdcd132
[libcpu] discard rt_current_thread (#8976)
* [libcpu] rv64: discard rt_current_thread

* arm: using rt_thread_self to fetch current TCB
2024-05-26 22:00:17 +08:00
Shell e25fc8b511
[libcpu/arm64] add C11 atomic ticket spinlock (#8882)
* [libcpu/arm64] add C11 atomic ticket spinlock

Replace the former implementation of flag-based spinlock which is unfair

Besides, C11 atomic implementation is more readable (it's C anyway),
and maintainable. Cause toolchain can use their builtin optimization and
tune for different micro-architectures. For example armv8.5 introduces a
better instruction. The compiler can help with that when it knows your
target platform in support of it.

Signed-off-by: Shell <smokewood@qq.com>

* fixup: RT_CPUS_NR

---------

Signed-off-by: Shell <smokewood@qq.com>
2024-05-16 15:45:12 +08:00
Shell 017b2a5a44
[smart] fixup arm64 aspace switch (#8925)
* [smart] fixup arm64 aspace switch

Signed-off-by: Shell <smokewood@qq.com>

* fixup: arm add arch_kernel_mmu_table_get

---------

Signed-off-by: Shell <smokewood@qq.com>
2024-05-10 09:17:19 +08:00
liYangYang dbf8a26e6c
[libcpu][aarch64] Fixed the rt_hw_secondary_cpu_bsp_start() bug (#8898)
* fix rt_hw_secondary_cpu_bsp_start() bug

* timer init

* comment
2024-05-08 19:48:17 +08:00
Shell 48bd0e49f2
[ipc] support of lockless rt_completion (#8887)
* [ipc] lockless rt_completion implementation

The new rt_completion implemented by lockless algorithm can improve timer resolution for up to ~12%, compare to sem IPC.

Signed-off-by: Shell <smokewood@qq.com>

* fixup: error

* remove useless changes

---------

Signed-off-by: Shell <smokewood@qq.com>
2024-05-08 09:25:57 +08:00
Shell 9ba6cec663
[libcpu/arm64] dealing with mem region out of kernel space (#8847)
* [ofw] dealing with mem region out of kernel space

- Fix parameter checking in _out_of_range() that NULL is excluded for
  fixed mapping
- Split page install with a deferred stage to avoid mapping over
  ARCH_EARLY_MAP_SIZE

Signed-off-by: Shell <smokewood@qq.com>

* fixup: restrict vstart for using of RT_NULL

---------

Signed-off-by: Shell <smokewood@qq.com>
2024-05-08 09:23:31 +08:00
Fan Yang c21ba6985d
Fix compiling eror in hpmicro bsp (#8889)
- added 'DEVICE' to rtconfig.py
- fixed compiling error cuased by change in interrupt_gcc.S

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
2024-04-30 20:11:47 +08:00
flyingcys 2c8c4ccc47
[bsp]support cvitek sdhci drvier (#8849)
support cvitek sdhci drvier
2024-04-24 05:40:22 +08:00
wirano 202bacb44d [cpu_cache] fix function replaced by macro 2024-04-18 20:40:55 -04:00
Meco Man a841091827 [libcpu] remove .asm files in cortex-r52 2024-04-18 20:32:47 -04:00
Rbb666 9a3172540f Delete unnecessary configurations in cortex-r52 2024-04-18 20:32:47 -04:00
zms123456 cc47212b53
[libcpu][aarch64]fix memheap search in setup of aarch64 2024-04-16 19:56:01 -04:00
Rbb666 1497a3117a
[bsp][renesas]Add cortex-r52 rzt2m adaptation 2024-04-10 20:47:53 -04:00
zhangyan 81df7bcdde
[bsp/phytium]中断相关修改 (#8742)
* update smp 4
2024-04-11 00:09:17 +08:00
Shell b14e0c08e1
[bsp/rpi4] fixup startup failure (#8754)
[bsp/rpi4] fixup startup issues

Signed-off-by: Shell <smokewood@qq.com>
2024-04-11 00:02:49 +08:00
zhao maosheng 687eb87a2b fix: code format of serial.c and compile error in aarch64 context_gcc 2024-04-02 08:07:21 -04:00
zms123456 d856f77a55
[components][drivers] fix posix tty, and add more baudrate (#8683)
* serial-tty fix

* v2
2024-04-01 21:23:04 +08:00
Shell 864055bf18
[fixup] aarch64 UMP compiler error (#8677)
Signed-off-by: Shell <smokewood@qq.com>
2024-03-30 17:58:38 +08:00
liYangYang 9a1996ef59
[bsp][art-pi-smart] 关闭内存对齐检查来避免数据访问异常 2024-03-29 21:43:57 -04:00
Shell 83e95bdff4
sync smart & dfs (#8672)
Signed-off-by: xqyjlj <xqyjlj@126.com>
Signed-off-by: Shell <smokewood@qq.com>
Co-authored-by: xqyjlj <xqyjlj@126.com>
2024-03-28 23:42:56 +08:00
Shell 751c2ada43
[libcpu/aarch64] improve performance of IRQ dis/en-able (#8687)
Signed-off-by: Shell <smokewood@qq.com>
2024-03-28 23:32:05 +08:00
Shell ea63dd6c57
[libcpu/rv64] fixup for parameter passing on backtrace (#8655)
Signed-off-by: Shell <smokewood@qq.com>
2024-03-21 20:23:36 +08:00
LiuLingze 8120fa5e31 [bsp][cv1800b] fix a implicit-function-declaration warning
Signed-off-by: LiuLingze <luiyanbing@foxmail.com>
2024-03-19 08:10:43 -04:00
LiuLingze 26b40d534c [bsp][cv1800b] fix a int-conversion warning
Signed-off-by: LiuLingze <luiyanbing@foxmail.com>
2024-03-19 08:10:43 -04:00
zhangyan fad78950ea
[bsp/phytium]Adapter aarch64/aarch32 (#8580) 2024-03-13 18:07:03 +08:00
zhangyan 76202e2141
🎯 [libcpu/arm/cortex-a]修改arm/cortex-a启动方式,解决cortex-a开启SMP工作异常问题 (#8517)
Co-authored-by: wangzongqiang <wangzongqiang1322@phytium.com.cn>
2024-03-02 16:06:07 +08:00
Shell 53754ff50a
[fixup] check NULL pointer before access (#8573)
Signed-off-by: Shell <smokewood@qq.com>
2024-03-02 16:05:19 +08:00
fangjianzhou 00c6800e4e
[components/driver] update serial (#8567) 2024-03-01 10:29:21 +08:00
zms123456 6b5058ba5c
[components/drivers]update hwtimer (#8565) 2024-02-29 22:27:38 +08:00