26fab3e792
[wch][spi] 修改ch32 risc-v spi底层驱动函数返回值类型 ( #6979 )
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* [wch][spi] 修改ch32 risc-v spi底层驱动函数返回值类型
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Co-authored-by: Zxy <1308465141@qq.com>
Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-02-27 18:26:16 -05:00
e63e33a3c6
[ch32][bsp] fix warning: rt_size_t to rt_ssize_t
2023-02-25 13:50:33 -05:00
7c6c12cbff
[RTduino][ch32v208w-r0]ch32v208w-r0适配RTduino ( #6917 )
2023-02-08 23:01:20 -05:00
f58d3c5200
rt_device_write/read return data type as rt_ssize_t
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rt_ssize_t can give negative error code, which follows the unix style correctly
2023-02-07 21:43:57 -05:00
9bc68d26a4
format Kconfig and sconscript
2023-01-08 22:52:13 -05:00
6618293dc5
[bsp][ch32]pwm避免警告 ( #6818 )
2023-01-05 23:10:46 -05:00
b99769f686
[libcpu][riscv]移除ch32中的冗余文件,使用common下的文件 ( #6813 )
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* [libcpu][riscv]移除ch32中的冗余文件,使用common下的文件
* 修正cpuport.h宏定义
* 规范宏定义格式
2023-01-04 21:06:09 -05:00
882a0af94e
[libcpu][riscv] 添加宏用于区别是否开启FPU，更新ch32v208v-r0 ->ch32v208w-r0，更新注释
2022-12-28 18:47:39 -05:00
b77241935c
[bsp][ch32v208]添加ch32v208BSP,合并libcpu/riscv 中ch系列的port文件 ( #6780 )
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【1】添加ch32v208-r0 bsp
【2】合并libcpu/riscv 下ch系列mcu的port文件
2022-12-27 13:24:02 -05:00
e8504c7cf1
[smart/aarch64] code sync ( #6750 )
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* [smart/aarch64] sync aarch64
2022-12-20 17:49:37 +08:00
99bdf978d7
[rtdef] use lower-case to define attributes ( #6728 )
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* [rtdef] rename RT_WEAK attribute as rt_weak
* [rtdef] rename RT_USED attribute as rt_used
* [rtdef] rename RT_SECTION attribute as rt_section
* [rtdef] rename ALIGN attribute as rt_align
* [legacy] add RT_USED ALIGN RT_SECTION RT_WEAK as legacy support
2022-12-11 13:12:03 -05:00
aaf5462c6d
更改了函数名
2022-12-02 13:03:59 -05:00
1805ca5e2e
[ch32v307]添加了硬件spi驱动 ( #6654 )
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* 添加了硬件spi驱动
2022-11-26 15:00:11 -05:00
569e2ae1e8
[CAN]update struct can_filter_item and rt_can_msg ( #6556 )
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* 修改ry命令，已便于自定义保存路径
* modified: components/utilities/ymodem/ry_sy.c
* 修复从被动错误恢复后发送返回异常
* 修复在自动重传模式下,ACK异常阻塞线程
- 删除TX中断函数else分支。仅当RQCP位 置一才进入该中断
- 添加SCE中断函数中关于ACK_ERR的else判断。自动重传模式下会进入该判断,打断自动重传释放完成量。
* 增加对于CAN1与CAN2的SCE中断和TX中断的公共处理函数
* formatting格式化代码
* update struct can_filter_item and rt_can_msg
1. 对过滤器号和索引号结构体定义中同一名称hdr进行重命名hdr_bank和hdr_index,
以便准确区分.采用宏定义兼容以前变量名.
2. 添加接收标识rxfifo,已指明是哪个RXFIFO.
* 更正42M下的波特率
* 修复接收获取索引号错误
* 添加接收标识
* 更新注释
* 取消CANFD限制
* update struct can_filter_item and rt_can_msg
2022-11-21 21:45:51 -05:00
aa15f7cd56
修改ch32v307软件spi的宏
2022-11-20 13:16:21 -05:00
fd6cfa3bbd
replaced the judgement of RT_USING_XXX with BSP_USING, and add some… ( #6554 )
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* replaced the judgement of RT_USING_XXX with BSP_USING, and add some tips in Konfig about soft_i2c
2022-10-23 23:08:20 -04:00
11f52eebcf
[bsp][ch32v307]补全PWM设备，并为每个PWM设备添加条件编译，减少代码量 ( #6548 )
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* 新增硬件定时器功能
* 新增定时器功能
* Update Kconfig
* Update bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.h
Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
* Update Kconfig
* 添加剩余的PWM设备，并为每个PWM设备添加条件编译，减少代码量
* Update drv_pwm.c
* 根据建议进行修改
* 已根据建议修改
* Update bsp/wch/risc-v/Libraries/ch32_drivers/drv_pwm.c
Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
* Update bsp/wch/risc-v/Libraries/ch32_drivers/drv_pwm.h
Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
* Update bsp/wch/risc-v/Libraries/ch32_drivers/drv_pwm.c
Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2022-10-22 11:07:04 -04:00
642ba3bc93
新增CH32V307的硬件定时器功能 ( #6545 )
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新增CH32V307的硬件定时器功能，并在CH32V307V-R1-1V0板卡上进行了测试。
2022-10-21 20:12:17 -04:00
88179b75a1
[bsp][ch32v307]增加软件spi驱动 ( #6532 )
2022-10-19 00:23:25 -04:00
fddc522d9c
[bsp][ch32v307]添加了pwm驱动 ( #6519 )
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* [bsp][ch32v307]添加了 pwm 驱动
2022-10-16 20:14:08 -04:00
90d566308d
[bsp][ch32v307]修复了模拟iic的BUG ( #6505 )
2022-10-11 21:35:37 -04:00
c17d5d509f
[bsp][ch32v307] 添加can驱动 ( #6484 )
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CH32V307 添加can驱动。
CAN1和CAN2均可以使用，而且调整好波特率
2022-10-08 22:32:29 -04:00
de48b65b0d
[ch32v3] 修改RT_USING为BSP_USING ( #6482 )
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* 修改RT_USING为BSP_USING
* Update SConscript
* Update SConscript
Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2022-09-30 11:07:52 -04:00
ee57f2d0da
[ch32v307][bsp]添加了看门狗驱动 ( #6474 )
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添加了 ch32v307 看门狗驱动，已在 ch32v307评估板验证；
修改了 rt-thread\bsp\wch\risc-v\ch32v307v-r1\board 目录下的 Kconfig 文件；
修改了 rt-thread\bsp\wch\risc-v\Libraries\ch32_drivers 目录下的 SConscript 文件；
添加了 rt-thread\bsp\wch\risc-v\Libraries\ch32_drivers 目录下的 drv_iwdt.c 文件；
2022-09-28 21:09:53 -04:00
714b93cc3d
添加了 rtc 驱动
2022-09-22 23:25:27 -04:00
90d9b449b1
[ch32v307v-r1] 添加了模拟iic驱动 ( #6447 )
2022-09-19 10:33:55 -04:00
60d6e42941
[ch32v307v-r1] 添加dac驱动 ( #6440 )
2022-09-18 09:32:56 -04:00
fdcee2da20
[BSP] CH32V307 add drv_adc ( #6431 )
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添加了ch32v307的adc驱动，已在ch32v307评估班上对adc1ch5进行了验证，并修改了kconfig以及scons脚本，可以成功编译以及使用
2022-09-16 22:50:57 -04:00
ae62b57632
add drv_ulog.h so that the project can built successfully
2022-09-06 00:29:51 -04:00
6da3b2b4b6
完善CH32V307的串口BSP ( #6359 )
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* Update drv_usart.h
CH32V307的串口1外设是对接在APB2桥上，其他串口均对接在APB1桥上
已完全测试，并发现一个问题，已修正。
2022-09-01 12:35:11 -04:00
ef8ae7963c
[drv_usart]完善ch32的串口驱动。 ( #6336 )
2022-08-27 00:34:27 -04:00
c67cbdb30c
[drv_gpio]为ch32完善gpio驱动 ( #6334 )
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* 修改Kconfig的不足
* update gpio driver
* formatting code
2022-08-25 10:24:53 -04:00
a38b39ac25
ch569w-evt: add usbhs device mode driver ( #6330 )
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ch569w-evt: add usbhs device mode driver
* usbd driver tested with cdc_vcom, internal loopback
(can't run both MSH & usbd due to 16KB RAM limitation)
* reduce usrstack & main thread stack size for usbd test
* ch56x_uart.c : iron out UART0_PIN_ALT assignment
2022-08-24 07:59:37 -04:00
0ff905ce43
[bsp]添加ch32v307需要的库文件 ( #6329 )
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* add ch32v307 lib
* fix scons
2022-08-23 02:13:33 -04:00
77067f8729
ch569w-evt : add pwm driver, and spi_xfer bug fix ( #6240 )
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add PWM driver, output checked with logic analyzer
spi_xfer() bug fix for cs_pin and message looping
uart pin_mode init moved to uart driver
2022-08-09 12:18:20 -04:00
a881c05e58
ch569w-evt : add spi master driver, SPI0 tested ( #6205 )
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* ch569w-evt : add spi master driver, SPI0 tested
* Update bsp/wch/risc-v/ch569w-evt/board/Kconfig
* Update bsp/wch/risc-v/ch569w-evt/board/Kconfig
Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2022-08-01 22:36:49 -04:00
c802fcdcf8
WCH CH569W-R0-1v0 evt board bsp port, first version ( #6167 )
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WCH CH569W-R0-1v0 evt board bsp port, first version
dev/test under Ubuntu 20.04
toolchain from MounRiver_Studio_Community_Linux_x64_V120
tested drivers : SysTick, gpio, gpio interrupt, uart1 (RX interrupt, TX polling)
libcpu/risc-v/SConscript :
group includes rtconfig.CPU only if folder exists
libcpu/risc-v/common/cpuport.c/rt_hw_context_switch_interrupt() :
make it RT_WEAK for customization
2022-07-30 02:10:51 -04:00
99526cc047
[bsp/ch32v103r-evt] add ch32v103r-evt bsp
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feat: move MRS demo source to bsp and libraries folder
feat: update Sconscript
feat: modify SConstruct in the bsp
feat: use the rtconfig.py of gd32vf103v-eval bsp to modify
feat: use the MRS's rtconfig.h temoporarily
feat: update Kconfig files
feat: use the MRS's .ld and rename as link.lds
feat: add ch32v1 porting folder
perf: remove board/system_ch32v10x.c
fix: define SOC_ARM_SERIES_CH32V103 in rtconfig.h
fix: add some neccessary macros in rtconfig.h
perf: use the menuconfig to generate rtconfig.h
feat: add readme.md
fix: correct the bad encode in main.c
fix: include board.h in main.c
perf: check and update README.md
perf: remove ch32f10x_port_cn.md
feat: ignore the standard libraries's CI checking
feat: add sdk_dist.py
fix: correct some style errors again
perf: simply the board/kconfig
fix: format ch32v103r-evt
fix: format drvs and libcpu
2022-04-06 11:06:55 +08:00
liYangYang
linshire
Yaochenger
Meco Man
Yaochenger
Shell
linshire
wdfk-prog
Harrypotter-zhs
self-confident neko
zhaohaisheng
hg0720
chenbin182
hg0720
emuzit
blta