a8928c881e
MIPS:fix the RT_EXCEPTION_MAX value
...
from <see mips run> know that cp0_cause's ExcCode have 5 bit filed and
the max exception is 32.
2020-09-14 11:10:44 +08:00
a97b0a0d39
code format
2020-09-11 11:44:49 +08:00
c66314a8b6
fixed loongson bsp build on windows
2020-09-04 11:57:35 +08:00
1556ba8e7f
add ls2k mmu
2020-09-04 10:16:34 +08:00
bd95f3a94f
fix mips stackframe and exception
2020-09-04 10:16:34 +08:00
3d0bdf4bb6
MIPS:improvement FPU support
2020-08-25 11:52:07 +08:00
3ce53f9c79
MIPS:remove redundant #ifdef ARCH_MIPS64
...
there exist redundant #ifdef ARCH_MIPS64 in asm.h, remove it
2020-08-24 09:35:10 +08:00
1ec681a551
fix ls2k libc and irq
2020-06-21 23:28:11 +08:00
f295149f20
MIPS: fix inline assembly for FPU
...
Signed-off-by: duhuanpeng <548708880@qq.com>
2020-04-10 15:07:39 +08:00
ee61d78b18
MIPS: inline routine should be static here
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gcc will remove this "unused" routine and cause a linking error.
symbol not found when linking.
Signed-off-by: duhuanpeng <548708880@qq.com>
2020-04-10 15:07:34 +08:00
c27f13c6c9
[mips]fix a bug
2020-04-07 19:01:54 +08:00
dff04ffdc6
fix mips stackframe point
2020-04-07 14:49:20 +08:00
3c5329a9b7
mips repair constraint
2020-04-07 14:43:20 +08:00
c024e2e485
add ls2k bsp config
2020-04-07 14:39:20 +08:00
990f731b77
fix mips64 some bug
2020-04-07 14:39:12 +08:00
0f26ffa7a2
add ls2k bsp
2020-04-07 14:38:58 +08:00
9ef986929c
[libcpu] mips: Merge loongson_1 into gs232
...
Previously Loongson 1B and Loongson 1C have their own libcpu
implemention, but they're almost identical. So we merge them
into gs232 and adapt to new common code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2019-12-11 15:24:42 +08:00
7c66501861
[libcpu] Refine MIPS common code
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MIPS common code was highly duplicated, This commit
is a attempt to clean-up and refine these code.
The context and exception handle flow is mostly identical
with Linux, but a notable difference is that when FPU enabled,
we save FP registers in stackframe unconditionally.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2019-12-11 15:24:04 +08:00
a972fcc0b5
[BSP] move libcpu/mips/x1000 to bsp/x1000/cpu
2019-12-11 11:01:40 +08:00
ab818cda30
参照龙芯1c手册更正看门狗寄存器宏定义
2019-08-21 13:44:55 +08:00
d45efced1c
libcpu: MIPS: 更新版权信息/Update copyright information.
...
更新版权信息。
Update copyright information.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
2019-07-19 21:05:00 +08:00
d6b2f56f15
libcpu: MIPS: 清理代码/Clean up code.
...
清理内容重复的头文件。
Clean up duplicate header files.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
2019-07-19 21:00:34 +08:00
bd8f0d0423
[libcpu] Fix the build directory issue
2019-03-26 13:36:01 +00:00
e6d1537327
移除 SConscript.1 临时文件
2019-03-25 15:18:09 +08:00
3a3c6c51f8
[libcpu] remove cache.h from mips/common folder.
2019-01-07 21:16:05 +08:00
4c0aafb57f
[libcpu] Fix the SCoscript issue in cpu/MIPS.
2019-01-07 09:20:30 +08:00
bde47018b8
[libcpu] Add SConscript in libcpu.
2019-01-07 06:09:45 +08:00
2502114e34
[libcpu/mips/xburst]rt_hw_interrupt_install函数name参数增加const限定
2018-12-05 20:43:38 +08:00
da9bc3d677
[libcpu/mips/x1000]rt_hw_interrupt_install函数name参数增加const限定
2018-12-05 20:43:35 +08:00
33c6a9c795
[libcpu/mips/longson_1c]rt_hw_interrupt_install函数name参数增加const限定
2018-12-05 20:43:33 +08:00
2ce284c4b3
[libcpu/mips/longson_1b]rt_hw_interrupt_install函数name参数增加const限定
2018-12-05 20:43:26 +08:00
330bdf6989
[bsp/ls1cdev]跟上一提交，漏提两个文件
2018-05-12 19:36:08 +08:00
9a7caed323
[bsp/ls1cdev]添加自引导特性，添加配置选项
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1、添加自引导特性，添加配置选项
2、修复cpuport.c的bug
3、修复ls1c_pin.c不能默认复用的bug
2018-05-12 19:33:32 +08:00
afc2256d01
[libcpu]Support x1000 CPU
2017-11-10 19:50:14 +08:00
574e22bdbd
在配置文件“rtconfig.h”中增加硬浮点FPU的配置项，
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浮点经常会用到，所以默认使用硬浮点。
2017-09-13 15:21:09 +08:00
838c63f365
添加龙芯1C片内网卡的驱动（原创作者是chinesebear， https://github.com/chinesebear/rtt-net）
2017-08-23 15:46:51 +08:00
7129d77bee
增加龙芯1c硬浮点的支持（可以使用硬浮点了）
2017-08-10 15:35:03 +08:00
358612c8a2
支持GPIO中断（外部中断）
2017-07-20 17:35:03 +08:00
d1bb7c61f4
将支持的中断个数从32个扩展到160个，至此可以支持所有中断
2017-07-20 17:05:59 +08:00
f39164203e
修正龙芯1c的中断号
2017-07-18 17:04:32 +08:00
b96f07e477
flush cache after exception code install
2016-06-15 08:09:56 -07:00
255f8b7c34
[BSP] Add BSP for Ingenic X1000 CPU
2016-04-24 19:34:41 +08:00
86216ceecc
start exception by chinesebear
2016-04-19 22:08:23 +08:00
4ad1b35537
chinesebear add bsp & libcpu
2015-07-09 07:38:07 +08:00
11fb9060e0
mips/loongson_1b: format code
2014-08-18 15:24:21 +08:00
0ee101ccb0
mips/loongson_1b: install NULL handler is OK
2014-08-18 15:22:16 +08:00
1d928f7daf
mips/loongson_1b: fix rt_interrupt_dispatch
2014-08-18 15:21:09 +08:00
2604440ceb
[bsp] Remove none-released porting
2014-07-12 11:08:38 +08:00
83ce430902
update loongson 1B dev: Modify the interrupt interface implementations.
2013-03-31 17:32:25 +08:00
93e04a1366
update loongson dev3210: Modify the interrupt interface implementations.
2013-03-31 17:32:20 +08:00
michael
bigmagic
duhuanpeng
Jiaxun Yang
Bernard Xiong
liufeilong
Zhou Yanjie
tangyuxin
liruncong
zhuangwei123
勤为本
kontais
chinesebear
chinesebear
Grissiom
aozima