08521ceaa5
[libcpu] Fix the E310 compiling issue.
2018-12-08 17:08:52 +08:00
c9576c3e53
[BSP] Add RV32M1_VEGA BSP.
2018-12-08 10:44:56 +08:00
36b194aeb6
[BSP] Update Hifive1 BSP with unified RV porting.
2018-12-08 10:42:40 +08:00
2a7d814f77
[libcpu] Add unified RISC-V libcpu porting.
2018-12-08 10:41:38 +08:00
32c5b2515f
[libcpu] add risc-v e310 porting
2018-05-31 14:53:26 +08:00
5faae3350c
[libcpu] remove libcpu/risc-v
2018-05-29 12:59:13 +08:00
2ac493698b
[BSP] cleanup for hifive1 bsp.
2017-08-26 11:02:39 +08:00
72cfe9dd68
modify： drivers/cpuusage.c
...
modify： ../../libcpu/risc-v/e310/stack.c
rmove unused macro definition
modify： ../../src/idle.c
Return to the original version
2017-07-31 12:05:45 +08:00
e9f1bdf2da
new file： ../../libcpu/risc-v/e310/trap.c
...
add file that forget to submit before
auto change timer mtimercmp register on the base of RT_TICK_PER_SECOND in rtconfig.h
no flashing led
new file： ../../src/idle.c
recover old file
2017-07-31 11:12:28 +08:00
a5305c05df
fix bug in context_gcc.s and start_gcc.s:
...
save mie into stack
msh running normaly
2017-07-31 10:59:59 +08:00
b032dff161
fix bug in rt_hw_context_switch_interrupt_do
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save sp to old thread
clear rt_thread_switch_interrupt_flag
always enable interrupt after rt_hw_context_switch
judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt)
2017-07-30 19:46:28 +08:00
2d56a27c20
修改： ../../libcpu/risc-v/e310/context_gcc.S
...
enable interrupt after return form rt_hw_context_switch
2017-07-30 15:34:32 +08:00
3c51848d33
fix trap_entry
2017-07-29 15:37:20 +08:00
b80f83f360
modified: ../../libcpu/risc-v/e310/context_gcc.S
...
fix open timer intrrupt
2017-07-26 16:27:54 +08:00
98a6896cfa
remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();
...
it will lead to interrupt again in interrupt
2017-07-26 16:07:01 +08:00
b334347a24
deleted: rtthread.s /*just for debug*/
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modified: ../../libcpu/risc-v/e310/context_gcc.S
change ret to mret and switch to new task with mepc
2017-07-17 16:55:33 +08:00
e01455155a
add context_gcc.s
2017-07-17 15:44:00 +08:00
Bernard Xiong
liang yongxiang
zhangjun