aozima
2c47f2e683
Fix some spell error;
2014-07-31 13:59:25 +08:00
Bernard Xiong
2604440ceb
[bsp] Remove none-released porting
2014-07-12 11:08:38 +08:00
Grissiom
97fb91dcc6
bsp: add zynq7000
2014-06-27 14:12:36 +08:00
Grissiom
2b7be29cad
[bsp/rva8] enable group{0,1} interrupt forwarding in gic initialization
...
When RT-Thread is running stand alone, it forgot to enable the
distributor of GIC.
2014-04-08 11:54:03 +08:00
Grissiom
c0f0c2322f
[libcpu/arm] remove useless cpsr updating in rt_hw_context_switch_to
...
This piece of code will enable the interrupt early before switching to
the first thread. Although it is harmless, but not prefect.
2014-04-08 11:24:04 +08:00
Grissiom
28f11fdd7b
[vmm] add realview-pb-a8 VMM support
2014-04-03 17:59:14 +08:00
RTsien
9382a7105f
add CM_PER_UARTx_CLKCTRL
2014-01-11 15:14:36 +08:00
Grissiom
0c9b9ced31
cortex-r4: use byte to allocate the stack
...
Unit of "byte" is more intuitive than "long".
2013-11-17 12:49:08 +08:00
Grissiom
a8520ed383
cortex-r4: let svc mode reuse the stack of IRQ on startup
...
As the svc stack is the stack of threads, there is no need to allocate a
separate stack for the startup. Reuse the IRQ stack should be OK.
Tested on rm48 board.
2013-11-17 12:49:07 +08:00
Bright Pan
06987e72e5
Fix hardfault bug for gcc port
...
for 2013-02-20 aozima commmit "port for gcc", but the commit is
not tested,and the kernel is breakdown in context_gcc.S, the file
is a copy from cortex-m3,but not port for cortex-m0, so i complete
this port for aozima, test it in stm32f0discovery board ,
and it works fine.
2013-11-04 16:10:11 +08:00
Grissiom
377c6e6cc9
cortex-r4: dump register on traps
...
We could not handle any traps except IRQ/FIQ.
2013-10-20 23:46:50 +08:00
Grissiom
e1e563e85c
cortex-r4: remove RM48x50.h and add armv7.h
2013-10-20 21:10:26 +08:00
Grissiom
81ab083ae5
rm48: move some asm file to libcpu
2013-10-20 18:51:46 +08:00
Grissiom
9568669109
rm48x50: add GCC support
2013-10-20 18:51:45 +08:00
Bernard Xiong
7bdb082c91
Delete SConscript
2013-09-22 06:59:52 +08:00
bernard
9d09cd9f23
Import beaglebone porting
2013-09-20 21:20:51 +08:00
Grissiom
3ebc766521
sim/posix: move rt_hw_context_switch_interrupt after it's definition
...
This fix a compile error in Clang.
2013-09-04 00:05:03 +08:00
Bernard Xiong
e301d14979
Merge pull request #132 from MrVan/sep6200
...
SEP6200 Support
2013-07-29 22:35:31 -07:00
weety
37ac4855da
Embedded GPLv2 license.
2013-07-21 20:01:24 +08:00
weety
36c4604a36
fix compiling error
2013-07-21 19:39:21 +08:00
weety
42f9840653
commit again
2013-07-21 17:32:55 +08:00
weety
3bdbf640b7
update at91sam9260 project directory structure.
2013-07-21 17:19:30 +08:00
weety
885301bb14
update AT91SAM9260 usart driver, using serial driver component.
2013-07-21 15:01:42 +08:00
Peng Fan
82bc21ff7b
Cleanup and add licencse
2013-07-17 18:42:19 +08:00
Peng Fan
73beced22a
SEP6200 Support
2013-07-17 13:37:31 +08:00
aozima
ce4f0329db
enhancement hard fault exception handler.
2013-07-09 22:02:12 +08:00
aozima
5120f54a29
fix spelling error.
2013-06-24 22:57:27 +08:00
aozima
34d59ccb0f
update libcpu/arm/cortex-m4: support lazy stack optimized.
2013-06-23 18:10:46 +08:00
aozima
b045f93b47
fixed bug: correct cortex-m SCB->VTOR address.
2013-06-23 18:08:16 +08:00
aozima
93b9b28297
format code by Astyle.
2013-06-23 18:07:10 +08:00
aozima
a2ff85c03f
update libcpu/arm/cortex-m0: restore MSP.
2013-06-22 18:59:51 +08:00
aozima
4d421cad73
update libcpu/arm/cortex-m3: restore MSP.
2013-06-22 18:59:50 +08:00
aozima
f9e673354a
update libcpu/arm/cortex-m4: restore MSP.
2013-06-22 18:59:49 +08:00
Bernard Xiong
3071e35c54
Merge pull request #109 from grissiom/rm48x50
...
Rm48x50
2013-06-19 01:29:12 -07:00
visitor83
c986754c49
Signed-off-by: visitor83 <wolflouiswang@gmail.com>
...
format the s3c24x0 serial.c and mini2440 rtconfig.py
2013-06-18 12:51:55 +08:00
visitor83
c56fa7c907
ident format
...
Signed-off-by: visitor83 <root@wolflouis.(none)>
2013-06-16 10:00:34 +08:00
Grissiom
009239ceed
rm48x50: rt_interrupt_nest should be `volatile rt_uint8_t`
2013-06-12 23:56:10 +08:00
Grissiom
9b949c28b7
rm48x50: add cache_{enable, disable}
2013-06-12 21:03:04 +08:00
Grissiom
e8bbbe6788
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-06-05 23:21:06 +08:00
Grissiom
228a6be077
cortex-r4: add __rt_ffs
2013-06-05 23:20:39 +08:00
Grissiom
e74befca44
move libcpu/arm/rm48x50/ to libcpu/arm/cortex-r4
2013-05-31 21:06:26 +08:00
Grissiom
24fc6e6ebb
rm48x50: VFP lazy stacking
...
You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT
will turn on VFP for all threads and stack all the VFP registers. When
doing lazy stacking, VFP will only be turned on for the thread who
issued VFP instructions.
Currently, if a thread turned on VFP, it cannot be turned off. RTT will
never know what time the thread doesn't need VFP any more. The thread
might could turn off the VFP for it self in proper time.
2013-05-31 20:58:08 +08:00
Grissiom
8bbfd45ce3
rm48x50: change STMFD/LDMFD to STMDB/LDMIA
...
VFP instructions only have IA(Increment After)/DB(Decrement Before)
mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
Grissiom
ec1203bfab
rm48x50: turn on VFP support
...
This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
Grissiom
83ea4dd628
rm48x50: small cleanup on context_ccs.asm
2013-05-30 17:37:50 +08:00
Grissiom
810311b624
rm48x50: fix bug in rt_hw_interrupt_{mask,unmask}
2013-05-29 23:36:32 +08:00
Grissiom
f08df08897
rm48x50: optimize a BEQ
...
Use condition flag in the ORR. This could eliminate a BEQ.
2013-05-26 23:37:56 +08:00
Grissiom
19fe6251e7
rm48x50: optimize context_switch_interrupt_to by reuse registers
...
When saving thread registers in context_switch_interrupt_to, we don't
change them, just move them. So there is no need to always r0-r3 from
stack to the real r0-r3. So just use the intermediate registers and
eliminate 2 MOV.
2013-05-26 22:37:49 +08:00
Grissiom
3d0647efb3
rm48x50: optimize context_switch_interrupt_do
...
Substitude STMFD, MOV, ADD with STMFD, SUB. It reduce one instruction.
Tested on board and it works like a charm.
2013-05-26 17:22:36 +08:00
Grissiom
b39d038cf0
rm48x50: utilize CPS instruction and remove some useless code
2013-05-26 16:55:39 +08:00