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125 Commits

Author SHA1 Message Date
Meco Man bd228eb9c5 [ci] fix errors under strick compiling mode 2024-02-20 08:39:05 +08:00
Meco Man 6d4503363a [libcpu][SConscript]规范group名为libcpu 2024-02-20 08:39:05 +08:00
flyingcys 3f41bd95d1
add libcpu/risc-v/rv64 (#8511) 2024-01-28 13:39:39 +08:00
xqyjlj 1b6f0e88a3
🐞 fix: fix d1s smart build (#8212) 2023-11-02 20:16:02 +08:00
Shell 70a8d1d465
[kservice] improve backtrace service in kernel (#8144) 
Signed-off-by: Shell <smokewood@qq.com>
 2023-10-21 20:14:45 +08:00
Shell 1d678e5596
[smart] fixup: mmap support (#8154) 
Signed-off-by: Shell <smokewood@qq.com>
 2023-10-20 13:28:20 +08:00
geniusgogo ecd29fda60
Sync dfs lwp (#8123) 2023-10-17 13:07:59 +08:00
Shell 47b183a297
[smart/syscall] fix exit(2) and add exit_group(2) (#8005) 
Signed-off-by: shell <smokewood@qq.com>
Signed-off-by: shell <wangxiaoyao@rt-thread.com>
Signed-off-by: Shell <smokewood@qq.com>
 2023-09-09 09:35:56 +08:00
Shell d862816a51
[components/mm] add unmap page API (#7834) 
Signed-off-by: Shell <smokewood@qq.com>
 2023-08-16 15:38:59 +08:00
Fan YANG 5308cc4716 [libcpu][risc-v][common] Fix application crash on risc-v soc if FPU is 
enabled

- Defined ARCH_RISCV_FPU once the __riscv_flen macro was detected

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
 2023-08-11 21:20:28 -04:00
Fan YANG 5ac509b6d0 [libcpu][risc-v][common] Avoid using t0 before being saved 
- Fixed the issue that t0 was modified unexpectedly before being saved

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
 2023-08-09 01:07:11 -04:00
Meco Man c6a2f5b7bd rt_hw_cpu_shutdown: implement default weak function 
and remvoe duplicated default functions in each cpu/bsp level
 2023-08-08 22:34:25 -04:00
xqyjlj d23dd56692 🐞 fix(ktime): fix wrong boottime 
因为tick从中断到设置中间的时延特别大，因此暂不采用tick做基准时间，直接取gtime的cnt做基准时间
 2023-07-27 11:35:29 +08:00
xqyjlj 0eb75ced70
[time]时钟框架重构 (#7794) 2023-07-17 20:11:58 +08:00
flyingcys c78f646891
[bsp]add cv1800b (#7753) 2023-06-30 00:05:55 +08:00
Liu,Yuan 1d8165851b
[risc-v][libcpu] 删去无用局部变量 (#7634) 2023-06-07 17:04:12 -04:00
Bernard Xiong 4b4c3c85f2
[atomic] add stdc atomic detection. (#7536) 2023-05-20 23:41:29 +08:00
Shell b7554a70d2
[libcpu][component][debug] add debug info for gdb (#7033) 2023-05-14 23:48:16 +08:00
flyingcys cbedb6b40b
[libcpu/risc-v/c906] add ioremap && default param (#7345) 2023-04-24 09:21:15 +08:00
Shicheng Chu 93f3cb30e4
[kernel] 将rt_thread结构体改为显式继承rt_object (#7131) 2023-04-04 09:06:27 -04:00
Yaochenger 38eb3fc40f
[utest][atomic]添加返回值测试 (#7124) 
* [utest][atomic]添加返回值测试
 2023-03-30 11:06:21 +08:00
Shell eec78d9f5d
[rt-smart] testcase & improvements for memory management (#7099) 
* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format & modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch
 2023-03-30 08:25:15 +08:00
flyingcys 0cf3bcf495
[bsp]fix esp32_c3 compile error (#7107) 
* fix rt_hw_interrupt_install return value

* add __rt_rvstack
 2023-03-29 19:01:26 +08:00
Yaochenger de4f237482
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053) 
* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构

* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
  * 1.规范代码风格
  * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试

---------

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
 2023-03-23 20:06:50 +08:00
flyingcys a538b26858
[bsp] add bl808 lp core (#7069) 
* Add riscv_32e support

* add bl808 lp core

* update README.md
 2023-03-19 23:16:12 +08:00
flyingcys c11f5bb251
add bl60x/bl70x/bl61x/bl808 (#7063) 
Co-authored-by: flyingcys <flyingcys!163.com>
 2023-03-19 14:41:18 +08:00
Shell 18a14cc935
[rt-smart] move sys_cacheflush to lwp_syscall.c (#7048) 
* [syscall] move sys_cacheflush to lwp_syscall.c

* [syscall] improve assertion

* [format] rename to rt_ctassert

* [debug] modified ct assertion on mm_page.c
 2023-03-17 15:11:38 +08:00
Shell 2394e75265
[libcpu/risc-v] support noncached normal memory (#7051) 
* [libcpu/risc-v] support noncached normal memory

* [mm] check before dereference in _fetch_page

* [mm] add comments on ioremap

* [ioremap] report more info on failed
 2023-03-16 10:26:55 +08:00
zilong 50e1f6327d
[libcpu/riscv/virt64] fix (#5979) (#7040) 2023-03-11 12:34:14 +08:00
chenhy0106 f6847af0cd
[libcpu/riscv/c906] fix "next_asid" type error (#7031) 
MAX_ASID最大为0x10000，在next_asid==MAX_ASID时进入下一个generation。因此next_asid不能只有16位，否则将不能进入下一个generation。修改rt_uint16_t为rt_uint32_t。
 2023-03-09 07:25:54 -05:00
Yaochenger cfc6bf9b12 [libcpu/risc-v]更新移植readme 2023-03-07 22:04:26 -05:00
Yaochenger 922e6e40d3
[libcpu/risc-v]迁移libcpu/risc-v/e310与rv32m1文件中内容至bsp (#7015) 2023-03-05 19:43:58 -05:00
Yaochenger 95540854a6
[libcpu/riscv]迁移libcpu/riscv/ch32中文件至bsp (#7004) 2023-03-02 09:17:43 -05:00
Yaochenger fc2e122ee2 [libcpu/risc-v]迁移libcpu/risc-v/hpmicro中的文件至bsp 2023-03-02 09:16:59 -05:00
Yaochenger 6aa2445522 [libcpu/risc-v]移除bumblebee文件夹与nuclei文件夹中的内容至bsp 2023-03-02 09:16:12 -05:00
Yaochenger 892ef3dc5b
[libcpu/risc-v]将cv32e40p文件夹中文件移至BSP (#7002) 2023-03-01 21:34:35 -05:00
Yaochenger b9e4fcfc68
[libcpu][riscv]整合libcpu/riscv中的移植文件 提供一份公共代码于common (#6941) 
整合libcpu/riscv中的移植文件 提供一份公共代码于common

在提交本pr时，除hpmicro的内核，rv32内核bsp已完成去除大部分的冗余，大部分代码采用common中的实现。本pr的作用是进一步统一common中的文件，从而提供一份公用代码，新移植的RV32内核的BSP可以全部使用common代码。

- 在common中提供一份公用文件：interrupt_gcc.S
- 修改原有的文件，将原有的中断中上下文切换代码替换为interrupt_gcc.S
- 基于上述修改，修改仓库中risc-v内核的BSP与移植相关的部分 (主要包含中断入口函数 中断栈等)
- 在common中提供一份公用文件：trap_common.c；提供统一中断入口函数，中断入口函数初始化，中断入口注册等函数，并完善异常时的信息输出

- 在common中提供一份公用文件：rt_hw_stack_frame.h；将栈帧结构体剥离，供用户使用

- 在上述工作完成后，在上述工作的基础上测试仓库中risc-v内核的BSP

- 完善函数中的命名，完善中断栈的获取

- 提供一份详细的基于现有common文件的移植指南

  #### 在什么测试环境下测试通过 

- 1.CH32V307V-R1-R0
- 2.CH32V208W-R0-1V4
- 3.HPM6750EVKMINI
- 4.GD32VF103V-EVAL
- 5.qemu(CORE-V-MCU )

> 与上述开发板使用同样芯片的BSP均测试通过

在CH32V307V-R1-R0与HPM6750EVKMINI上基于现有移植文件进行多线程复杂场景下的长时间测试，测试过程系统运行正常。
 2023-03-01 01:32:43 -05:00
Shell 382e9bcac7
[rt-smart] handling kernel from accessing unmapped user stack (#6957) 
[rt-smart] handling kernel from accessing unmapped user stack
 2023-02-24 14:52:16 +08:00
wangxiaoyao 484a0d602e [fixup] add cache maintenance ops; 
fix bugs on cache maintenance when starting user app
 2023-02-21 08:48:49 +08:00
Shell 2d09749086
[rt-smart] PV_OFFSET as a variable (#6904) 
* [rt-smart/mem] remove pv_offset

* [rt-smart] list kernel space command

* [rt-smart] restore ioremap region

* [revert] restore kernel space isolation

* [rt-smart/pv_off] code format

* [rt-smart] add get_pvoff()

* [pvoffset] pvoff as constant for C codes

* [pvoff] pvoff as interfaces
 2023-02-14 23:08:32 +08:00
chenhy0106 9db73a47c4
为c906添加asid支持 (#6870) 
* [rt-smart] asid for c906
 2023-01-28 13:08:40 -05:00
Shell f0dadcb3c3
[rt-smart] porting c906 and D1s to mm (#6848) 
* [rv64/bsp] porting to mm

* [mm] report more info for debugging

* [fix] code format

* [libcpu/c906] porting to RTOS

* [fix] using rtdbg api

* [fix] add return

* [fix] report more information for debugging

* [fix] use assert 0 for unrecoverable error
 2023-01-16 08:24:03 +08:00
Meco Man 9bc68d26a4 format Kconfig and sconscript 2023-01-08 22:52:13 -05:00
Shell 7450ef6c4d
[rt-smart] kernel virtual memory management layer (#6809) 
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes
 2023-01-08 21:08:55 -05:00
flyingcys 98a997c57e
[bsp]add new bsp-bl808 (#6824) 
* add new bsp-bl808

* support ARCH_RISCV_FPU_S && update rtconfig.py
 2023-01-07 02:03:21 -05:00
Yaochenger b99769f686
[libcpu][riscv]移除ch32中的冗余文件,使用common下的文件 (#6813) 
* [libcpu][riscv]移除ch32中的冗余文件,使用common下的文件

* 修正cpuport.h宏定义

* 规范宏定义格式
 2023-01-04 21:06:09 -05:00
Yaochenger f2a66e122f [libcpu][riscv]移除cv32e40p中部分文件，采用common中的文件 2023-01-02 16:42:18 -05:00
Yaochenger 882a0af94e [libcpu][riscv] 添加宏用于区别是否开启FPU，更新ch32v208v-r0 ->ch32v208w-r0，更新注释 2022-12-28 18:47:39 -05:00
Yaochenger b77241935c
[bsp][ch32v208]添加ch32v208BSP,合并libcpu/riscv 中ch系列的port文件 (#6780) 
【1】添加ch32v208-r0 bsp
【2】合并libcpu/riscv 下ch系列mcu的port文件
 2022-12-27 13:24:02 -05:00
linshire c930b4f623
[ch32]对接了rt_hw_context_switch_interrupt接口 (#6749) 
* 对接了rt_hw_context_switch_interruptC(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread)接口

* Update libcpu/risc-v/ch32v1/cpuport.c

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
 2022-12-22 09:34:36 +08:00