fc155f8810
fix cortex-a cahce
2019-06-19 10:40:13 +08:00
043611b98a
add cortex-a fpu support
2019-05-29 08:40:41 +08:00
ec6cb9f260
[BSP][qemu-vexpress-a9] code cleaup for compiling warning.
2019-05-12 15:07:26 +08:00
6cdfb2ac92
fix signal code
2019-05-11 09:34:26 +08:00
d729448f5e
[libcpu][arm/cortex-a] Add correct comments.
2019-05-09 08:48:38 +08:00
1e7bd3d8a1
修改lwp支持中arm cortex-a的swi入口函数处理
2019-04-27 13:54:51 +08:00
61f2a71511
Rename 'platform.h' in 'imx6ul' and 'qemu-vexpress-a9' BSPs.
...
This filename conflicts with the 'mbedtls' package. They are renamed
in the name of the corresponding chips and included in 'board.h'.
Files that rely on this file should include 'board.h' instead.
2019-04-26 10:50:48 +08:00
b10039f396
Disable the data alignment check.
2019-04-01 14:21:59 +08:00
fbd40fc5b8
Add standard rt-thread cache interfaces for arm/cortex-a.
...
Add cache invalidate and clean interfaces.
Adjust the default cache type of memory to 'WriteBach with WriteAllocate'.
2019-03-29 20:22:25 +08:00
2eb1bef773
Make 'qemu-vexpress-a9' and 'imx6ul' use the same libcpu code.
2019-03-25 20:03:49 +08:00
bde47018b8
[libcpu] Add SConscript in libcpu.
2019-01-07 06:09:45 +08:00
cbe07afabe
[libcpu/arm/cortex-a]rt_hw_interrupt_install函数name参数增加const限定
2018-12-05 20:35:34 +08:00
7c425408b4
[license] Change the license of libarm to Apache.
2018-10-15 01:35:07 +08:00
fc7a5abc76
[libcpu]: add 8-byte alignment for arm architecture && optimize code format
2017-12-21 16:37:38 +08:00
f6170a6e5b
[BSP] add i.MX 6UL BSP
2017-11-01 13:30:17 +08:00
ZYH
shaojinchun
Bernard Xiong
qz721
liruncong
SummerGift