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11 Commits

Author SHA1 Message Date
Sparks-Pion accab17fa5
[HUST CSE IoTS&P Lab] [fix] check rt_mutex_create return value (#7169) 2023-04-04 00:33:10 -04:00
shandianchengzi e49140b513
[HUST CSE IoTS&P Lab][bsp] add missing UL suffix to BIT macro to prevent undefined behavior (#7153) 
* [bsp] add missing UL suffix to BIT macro to prevent undefined behavior.

* [bsp] add UL suffix to BIT macro for consistency and readability.

* fix toUppercase.

* fix the abnormal character.

* format the file.
 2023-04-03 23:05:42 +08:00
sion 7a31ab9115 [bsp]Fix Chinese coding errors in annotations. 2023-04-02 08:02:46 -04:00
shandianchengzi dc5123547c [bsp] Fix many abnormal symbols in annotations. 2023-03-31 23:57:17 -04:00
Meco Man 0f461e870c [errno code][-RT_ERROR] fix that use RT_ERROR without - 2023-03-20 00:06:16 -04:00
Meco Man f58d3c5200 rt_device_write/read return data type as rt_ssize_t 
rt_ssize_t can give negative error code, which follows the unix style correctly
 2023-02-07 21:43:57 -05:00
Meco Man ddccef3a64 modify RT_ALIGN_SIZE as 8 by default 2023-01-12 22:47:23 -05:00
Meco Man 9bc68d26a4 format Kconfig and sconscript 2023-01-08 22:52:13 -05:00
guo 68ca9f07a6
[rt-smart] 弱化 RT_USING_LWP，使用 RT_USING_SMART 作为宏配置 (#6740) 
* [dfs] sync cromfs

* [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration

* [format] fix some format issue.
 2022-12-16 18:38:28 +08:00
Man, Jianting (Meco) 99bdf978d7
[rtdef] use lower-case to define attributes (#6728) 
* [rtdef] rename RT_WEAK attribute as rt_weak

* [rtdef] rename RT_USED attribute as rt_used

* [rtdef] rename RT_SECTION attribute as rt_section

* [rtdef] rename ALIGN attribute as rt_align

* [legacy] add RT_USED ALIGN RT_SECTION RT_WEAK as legacy support
 2022-12-11 13:12:03 -05:00
guo ecf2d82159
sync branch rt-smart. (#6641) 
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
 2022-12-03 12:07:44 +08:00