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21 Commits

Author SHA1 Message Date
Shell e25fc8b511
[libcpu/arm64] add C11 atomic ticket spinlock (#8882) 
* [libcpu/arm64] add C11 atomic ticket spinlock

Replace the former implementation of flag-based spinlock which is unfair

Besides, C11 atomic implementation is more readable (it's C anyway),
and maintainable. Cause toolchain can use their builtin optimization and
tune for different micro-architectures. For example armv8.5 introduces a
better instruction. The compiler can help with that when it knows your
target platform in support of it.

Signed-off-by: Shell <smokewood@qq.com>

* fixup: RT_CPUS_NR

---------

Signed-off-by: Shell <smokewood@qq.com>
 2024-05-16 15:45:12 +08:00
Shell 017b2a5a44
[smart] fixup arm64 aspace switch (#8925) 
* [smart] fixup arm64 aspace switch

Signed-off-by: Shell <smokewood@qq.com>

* fixup: arm add arch_kernel_mmu_table_get

---------

Signed-off-by: Shell <smokewood@qq.com>
 2024-05-10 09:17:19 +08:00
zhao maosheng 687eb87a2b fix: code format of serial.c and compile error in aarch64 context_gcc 2024-04-02 08:07:21 -04:00
zms123456 d856f77a55
[components][drivers] fix posix tty, and add more baudrate (#8683) 
* serial-tty fix

* v2
 2024-04-01 21:23:04 +08:00
Shell 751c2ada43
[libcpu/aarch64] improve performance of IRQ dis/en-able (#8687) 
Signed-off-by: Shell <smokewood@qq.com>
 2024-03-28 23:32:05 +08:00
Shell cc157baf23
[kernel] fixup of data racing accessing percpu objects (#8475) 
Signed-off-by: Shell <smokewood@qq.com>
 2024-01-09 23:09:49 +08:00
xqyjlj 3283f54c7a
🎈 perf: perf rt_hw_interrupt_disable/enable (#8042) 
Signed-off-by: Shell <smokewood@qq.com>
Co-authored-by: Shell <smokewood@qq.com>
 2023-10-25 20:31:25 +08:00
Shell b0deb61bc4
[libcpu/aarch64] fix compile error (#8045) 
Signed-off-by: Shell <smokewood@qq.com>
 2023-09-16 11:52:42 +08:00
geniusgogo 4d20416b2f
update components & lwp. (#7888) 2023-08-07 12:22:14 -04:00
Shell acfa74f078
[libcpu/arm] fix race condition with ldrex,strex (#7842) 
Signed-off-by: Shell <smokewood@qq.com>
 2023-07-25 14:07:44 +08:00
wangqinglin 194a2efdf4
AMP-step3: 添加conifg ARCH_ARM_CORTEX_A55， rt_hw_cpu_id_set 适配A55架构, 添加aarch64 rt_… (#7628) 2023-06-11 07:06:16 +08:00
Shell b7554a70d2
[libcpu][component][debug] add debug info for gdb (#7033) 2023-05-14 23:48:16 +08:00
huanghe 50a4e8c662
[bsp][phytium]适配rt-thread5.0.0 版本 (#7441) 
Co-authored-by: 朱耿宇 <zhugengyu@phytium.com.cn>
 2023-05-11 10:25:21 +08:00
Shell 7450ef6c4d
[rt-smart] kernel virtual memory management layer (#6809) 
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes
 2023-01-08 21:08:55 -05:00
Shell e8504c7cf1
[smart/aarch64] code sync (#6750) 
* [smart/aarch64] sync aarch64
 2022-12-20 17:49:37 +08:00
GUI 0a8dd10b0b
[libcpu/aarch64] add gtimer frq set and stack align (#5642) 
* [libcpu/aarch64] add smp support

* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2

* [libcpu/aarch64] disable irq/fiq when switch thread

* [libcpu/aarch64] add gtimer frq set and stack align
 2022-03-07 22:41:56 +08:00
GUI 9b6e75f90b
[libcpu/aarch64] disable irq/fiq when switch thread (#5605) 
* [libcpu/aarch64] add smp support

* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2

* [libcpu/aarch64] disable irq/fiq when switch thread
 2022-02-21 23:24:51 +08:00
Meco Man 563e49890c [asm] 解决tab和空格混用的问题 2022-01-20 20:57:35 +08:00
GuEe-GUI 353f717037 [libcpu/aarch64] add smp support 2022-01-08 18:24:02 +08:00
GuEe-GUI efbdbc2636 fixup .bss size define in link.lds and set spsel=1 in aarch64 2021-11-30 11:14:17 +08:00
bigmagic fb8c7829a8 add raspi4 bsp 2020-04-16 16:44:14 +08:00