If the application defines dozens of global variables,
the speed of clearing the bss segment will be slower.
Because icache can be enabled before the mmu enabled.
Therefore, in order to speed up the process of clearing the BSS segment,
enable icache needs to be put ahead.
* bsp beaglebone: add IAR template files and fix it's build error
ATTENTION:
project.* was generated by scons, so I add it to gitignore.
rtconfig.py *FLAGS located in "PLATFORM == 'iccarm'" are unverified and maybe wrong.
（我只是从STM32里面抄来，然后根据自己的理解改了一下，并没有验证这些参数的正确性，
我也不知道怎么用命令行调用这些参数来编译）
* bsp beaglebone: add beaglebone_ram.icf ROM address from uboot_cmd.txt
am335x_DDR.icf use 0x82000000, different to uboot_cmd.txt & gcc beaglebone_ram.lds,
the difference will easy cause later developer got below error:
=> go 0x80200000
## Starting application at 0x80200000 ...
undefined instruction
pc : [<8200956c>] lr : [<8ff62497>]
reloc pc : [<728a956c>] lr : [<80802497>]
sp : 8df37358 ip : 00000000 fp : 00000002
r10: 8df4d448 r9 : 8df3feb8 r8 : 8ffd30f8
r7 : 8ff78089 r6 : 00000002 r5 : 80200000 r4 : 8df4d44c
r3 : 80200000 r2 : 8df4d44c r1 : 8df4d44c r0 : 00000001
Flags: nzCv IRQs off FIQs on Mode SVC_32
Code: 5dbffcdd bb9bdf7f abf85423 eff1f77f (7ed7daaf)
Resetting CPU ...
resetting ...
* libcpu am335x: context_iar.S rt_hw_context_switch: add thumb mode support
IAR new project defualt Processor mode is Thumb, this will cause user
easy occur the following error:
...
msh />Execption:
r00:0x8800aaa8 r01:0x802080c5 r02:0x00000000 r03:0x88009b4c
r04:0x00001000 r05:0x00000000 r06:0x00001403 r07:0x00100000
r08:0x00000000 r09:0x00000000 r10:0x0000000a
fp :0x0000000a ip :0x65687374
sp :0x00006c6c lr :0x0000008a pc :0x88008be0
cpsr:0x880001bc
software interrupt
shutdown...
(0) assertion failed at function:rt_hw_cpu_shutdown, line number:160
* bsp beaglebone: change IAR template.ewp code use Arm mode
Arm mode bin size will bigger than Thumb mode
* libcpu am335x: IAR: use rt_hw_cpu_dcache_enable instead of rt_cpu_dcache_enable
Reviewer mysterywolf say:
麻烦把rt_cpu_icache_enable 和 rt_cpu_dcache_enable, 统一改成 rt_hw_cpu_icache_enable 和 rt_hw_cpu_dcache_enable
rt_hw_cpu_icache_enable 和 rt_hw_cpu_dcache_enable 是其他bsp也是这么命名的 这是个命名统一的函数
* bsp beaglebone: rerun menuconfg
* bsp beaglebone: add uart0 support
* bsp beaglebone: use uart0 as console
* bsp beaglebone: add heap init
fix rt_application_init() error:
(m != RT_NULL) assertion failed at function:rt_smem_alloc, line number:288
* bsp beaglebone: add mmu & interrupt init
must init mmu, otherwise no interrupt is generated, cause scheduler can't work.
I don't know why need mmu, just seen: bsp/rockchip/rk3568/driver/board.c
* libcpu am335x: reset interrupt controller before init vector
I think reset before init is more better
AM335X_StarterWare_02_00_01_01\system_config\armv7a\am335x\interrupt.c
IntAINTCInit()
* bsp beaglebone: full gpio driver support
* bsp beaglebone: add tftpboot way to uboot_cmd.txt
* bsp beaglebone: optimize am33xx_gpio_hdr, check irqstatus is the last one
Co-authored-by: YangZhongQing <vipox@qq.com>
* Add CANFD support and correct typos
- Added CANFD required fields to can.h
- Fixed typos in can.h and can.c
- Corrected all the projects affected by the typo
- Fixed wrong line-ending in some affected can driver files
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
* update
* bsp: support boards from hpmicro
- Supported HPM6750EVKMINI
- Supported HPM6750EVK
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
Co-authored-by: Meco Man <920369182@qq.com>
* compile_ok
Issues fixed:
(1) update .config: select FINSH_USING_SYMTAB
(2) add rt_size_t in rtconfig_project.h
(3) fix finsh problems of using sym table
(4) update .project to include ipc source codes.
Todo list:
(1) automate the build source selection of ccs and reconcile it with scons
* change compiler
* msh can run now
the key step is to swap the order of rt_interrupt_nest -- and RT_OBJECT_HOOK_CALL(rt_interrupt_leave_hook,()) in irq.c. This is an improvised solution and an issue has been raised.
* Update 2837x_FLASH_lnk_cpu1.cmd
The original one is also fine. Just to make it more rigorous since FSymTab is in data section.
* update readme.md
Complier selection and maintainer update.
Co-authored-by: YuQi <qiyu_sjtu@163.com>
WCH CH569W-R0-1v0 evt board bsp port, first version
dev/test under Ubuntu 20.04
toolchain from MounRiver_Studio_Community_Linux_x64_V120
tested drivers : SysTick, gpio, gpio interrupt, uart1 (RX interrupt, TX polling)
libcpu/risc-v/SConscript :
group includes rtconfig.CPU only if folder exists
libcpu/risc-v/common/cpuport.c/rt_hw_context_switch_interrupt() :
make it RT_WEAK for customization
feat: move MRS demo source to bsp and libraries folder
feat: update Sconscript
feat: modify SConstruct in the bsp
feat: use the rtconfig.py of gd32vf103v-eval bsp to modify
feat: use the MRS's rtconfig.h temoporarily
feat: update Kconfig files
feat: use the MRS's .ld and rename as link.lds
feat: add ch32v1 porting folder
perf: remove board/system_ch32v10x.c
fix: define SOC_ARM_SERIES_CH32V103 in rtconfig.h
fix: add some neccessary macros in rtconfig.h
perf: use the menuconfig to generate rtconfig.h
feat: add readme.md
fix: correct the bad encode in main.c
fix: include board.h in main.c
perf: check and update README.md
perf: remove ch32f10x_port_cn.md
feat: ignore the standard libraries's CI checking
feat: add sdk_dist.py
fix: correct some style errors again
perf: simply the board/kconfig
fix: format ch32v103r-evt
fix: format drvs and libcpu
* [libcpu/aarch64] add smp support
* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2
* [libcpu/aarch64] disable irq/fiq when switch thread
* [libcpu/aarch64] add gtimer frq set and stack align
* [libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568
* [libcpu/aarch64] add smp support
* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2
* [libcpu/aarch64] disable irq/fiq when switch thread
* [libcpu/aarch64] add gtimer frq set and stack align
* [libcpu/aarch64] add smp support
* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2
* [libcpu/aarch64] disable irq/fiq when switch thread
xiaoguang_ma
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