Commit Graph

23 Commits

Author SHA1 Message Date
wusongjie 8aa4366cb2 Drivers: Support Open Firmware API and model of PIC
We support OFW API to replace fdt old API, and add
IRQ, IO, Platform-Bus, CPUs ... OFW node contorl.
To support work with Device Tree or ACPI in drivers
that use IRQ, we make a programmable interrupt
controller driver's model.

Signed-off-by: GuEe-GUI <GuEe-GUI@github.com>
2023-07-05 16:45:16 +08:00
wangqinglin edaa0d9c8a 更新rk3568 bsp 支持PSCI、amp模式 2023-06-11 21:41:37 -04:00
Placebo27 538158bf20
[bsp] fix mismatched function types in rt_pin_ops for all drv_gpio.c (#7457) 2023-05-08 23:35:27 -04:00
yangjie11 95e6b69b8e
sync and update all projects (#7138)
* sync and update
2023-03-31 16:49:48 +08:00
Zxy 4ed9bc11f7
[errno code]fix that use RT_ENOSYS without - (#7084)
* [errno code]fix that use RT_ENOSYS without -

* Update bsp/airm2m/air32f103/libraries/rt_drivers/drv_hwtimer.c

---------

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-03-23 01:54:42 -04:00
Meco Man deb40e8c0c [errno code][-RT_EBUSY] fix that use RT_EBUSY without - 2023-03-22 01:55:18 -04:00
Meco Man dfddd79b24 [errno code][-RT_EINVAL] fix that use RT_EINVAL without - 2023-03-16 20:21:43 -04:00
Bernard Xiong 98e0c58527
Add ADT Kconfig and fix MMU kconfig issue in Cortex-A (#6901)
* Add ADT Kconfig and fix MMU kconfig issue in Cortex-A

* [BSP] enable ADT
2023-02-06 01:11:04 +08:00
Meco Man ddccef3a64 modify RT_ALIGN_SIZE as 8 by default 2023-01-12 22:47:23 -05:00
Meco Man 592284c66c format link scripts 2023-01-08 22:52:13 -05:00
Meco Man 9bc68d26a4 format Kconfig and sconscript 2023-01-08 22:52:13 -05:00
Shell 7450ef6c4d
[rt-smart] kernel virtual memory management layer (#6809)
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes
2023-01-08 21:08:55 -05:00
Shell e8504c7cf1
[smart/aarch64] code sync (#6750)
* [smart/aarch64] sync aarch64
2022-12-20 17:49:37 +08:00
Man, Jianting (Meco) 99bdf978d7
[rtdef] use lower-case to define attributes (#6728)
* [rtdef] rename RT_WEAK attribute as rt_weak

* [rtdef] rename RT_USED attribute as rt_used

* [rtdef] rename RT_SECTION attribute as rt_section

* [rtdef] rename ALIGN attribute as rt_align

* [legacy] add RT_USED ALIGN RT_SECTION RT_WEAK as legacy support
2022-12-11 13:12:03 -05:00
guo ecf2d82159
sync branch rt-smart. (#6641)
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
Meco Man 8b0610fc34 [bsp][readme] 增加scons --exec-path=xxx 命令的使用说明 2022-10-10 09:42:44 +08:00
Man, Jianting (Meco) f7be5fc84b
[bsp][applications][sconscript] 整理统一sconscript格式 (#6481)
* [bsp][sconscript] 整理统一sconscript格式

* update

* update
2022-10-03 10:43:08 -04:00
liuxianliang a4eb64b873 update the project for RT-Thread_V4.1.1 2022-08-16 19:38:48 +08:00
Meco Man dd94198bd6 [gcc][armcc][armclang] rtconfig.CROSS_TOOL->rtconfig.PLATFORM 2022-08-16 09:39:00 +08:00
Steven-LiuSF 8b60b58b51
[bsp][rockchip][rk2108]: add rk2108 base support. (#6040)
* [bsp][rockchip][rk2108]: add rk2108 base support.

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
2022-06-09 14:27:30 +08:00
zhouji 77900ab420 [update] Updated the Cortex-A of linker scripts for the new version of GCC(4.7)。 2022-04-20 17:32:02 +08:00
guozhanxin e353b2d5f1 [bsp] Update all projects. 2022-03-29 19:28:06 +08:00
GUI f587a55bc2
[libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568 (#5722)
* [libcpu/aarch64] add smp support

* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2

* [libcpu/aarch64] disable irq/fiq when switch thread

* [libcpu/aarch64] add gtimer frq set and stack align

* [libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568
2022-03-29 11:08:25 +08:00