add file that forget to submit before
auto change timer mtimercmp register on the base of RT_TICK_PER_SECOND in rtconfig.h
no flashing led
new file： ../../src/idle.c
recover old file
save sp to old thread
clear rt_thread_switch_interrupt_flag
always enable interrupt after rt_hw_context_switch
judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt)
Since the 16 domains are configured as the client domains in
mmu_setttbase(), a Permission fault is generated if the XN bit
(Execute-never) is set in the short-descriptor translation table
(for section and supersection). This leads to the booting failure
when enabling MMU for beagleboard bsp. Here is log:
----------------------------------------------------------------
SD/MMC found on device 0
reading uEnv.txt
117 bytes read in 3 ms (38.1 KiB/s)
Loaded environment from uEnv.txt
Importing environment from mmc ...
Running uenvcmd ...
reading rtthread.bin
162624 bytes read in 24 ms (6.5 MiB/s)
\## Starting application at 0x80200000 ...
----------------------------------------------------------------
This commit removes the XN bit configuration in the section of the
short-descriptor translation table. The OS can be booted successfully
with applying this commit.
1. Combine code for IAR and GCC in file mmu.c and cpuport.c
2. Remove remap code in start_xxx.S. User should config MMU to map vector table to visual address 0x0
2. [bsp][sam9260] Modify SCONS scripts to support IAR tool chain.
3. [bsp][sam9260] Move link strips in to folder link_scripts.
4. [libcpu][arm926] Add copy right to source file and format code.
As the svc stack is the stack of threads, there is no need to allocate a
separate stack for the startup. Reuse the IRQ stack should be OK.
Tested on rm48 board.
for 2013-02-20 aozima commmit "port for gcc", but the commit is
not tested,and the kernel is breakdown in context_gcc.S, the file
is a copy from cortex-m3,but not port for cortex-m0, so i complete
this port for aozima, test it in stm32f0discovery board ,
and it works fine.
You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT
will turn on VFP for all threads and stack all the VFP registers. When
doing lazy stacking, VFP will only be turned on for the thread who
issued VFP instructions.
Currently, if a thread turned on VFP, it cannot be turned off. RTT will
never know what time the thread doesn't need VFP any more. The thread
might could turn off the VFP for it self in proper time.
When saving thread registers in context_switch_interrupt_to, we don't
change them, just move them. So there is no need to always r0-r3 from
stack to the real r0-r3. So just use the intermediate registers and
eliminate 2 MOV.
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
勤为本
zhangjun
zchong-cht
kontais
Bernard Xiong
chinesebear
weety
nongxiaoming
chinesebear
aozima
Adrian Huang
ardafu
Bright Pan
limxuzheng
陈豪
Grissiom
RTsien
Bright Pan
Peng Fan
visitor83
visitor83