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7 Commits

Author SHA1 Message Date
michael a8928c881e MIPS:fix the RT_EXCEPTION_MAX value 
from <see mips run> know that cp0_cause's ExcCode have 5 bit filed and
the max exception is 32.
 2020-09-14 11:10:44 +08:00
bigmagic c66314a8b6 fixed loongson bsp build on windows 2020-09-04 11:57:35 +08:00
bigmagic 1556ba8e7f add ls2k mmu 2020-09-04 10:16:34 +08:00
bigamgic 1ec681a551 fix ls2k libc and irq 2020-06-21 23:28:11 +08:00
bigmagic c024e2e485 add ls2k bsp config 2020-04-07 14:39:20 +08:00
bigmagic 990f731b77 fix mips64 some bug 2020-04-07 14:39:12 +08:00
Jiaxun Yang 7c66501861 [libcpu] Refine MIPS common code 
MIPS common code was highly duplicated, This commit
is a attempt to clean-up and refine these code.

The context and exception handle flow is mostly identical
with Linux, but a notable difference is that when FPU enabled,
we save FP registers in stackframe unconditionally.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
 2019-12-11 15:24:04 +08:00