libs/rt-thread
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4796 Commits

Author SHA1 Message Date
GuEe-GUI
0ede1d6c65 [DM/FIXUP] Fixup NVME build 
1. Fixup Kconfig show order.
2. Fix `RT_DECLARE_IRQ_AFFINITY` to `RT_IRQ_AFFINITY_DECLARE`
3. Remove warning.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-13 10:39:20 +08:00
GuEe-GUI
d248a3a288 [DM/FIXUP] Fixup PCI build 
1. Add PCI include in rtdevice.h
2. Fixup `RT_KEY_ENABLED` loss.
3. remove waring type of `dw_pcie_ep_get_func_from_ep` return.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-13 10:39:20 +08:00
GuEe-GUI
76d3cf3b86 [DM/FIXUP] Fixup bitmap to new type 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-13 10:39:20 +08:00
GuEe-GUI
63bbce1c1f [DM/FIXUP] include name default 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-13 10:39:20 +08:00
zhujiale
ee5b7f1de9 [lwp] fix TTYSUP_CFLAG did not include CBAUD flag 2024-12-12 18:54:30 -05:00
zhujiale
e7b30ed2cc [componets] fix when printf 0 addr by %p will return nil 2024-12-09 19:45:40 -05:00
Supper Thomas
5b75e1c8bf doc(doxyge):fix doxygen path 2024-12-09 17:12:59 -05:00
wycwyhwyq
6876cb6f73
[components] When rtc is not enabled, use other clock sources instead (#9747) 
When rtc is not enabled, use other clock sources instead

Signed-off-by: wycwyhwyq <5f20.6d9b@gmail.com>
 2024-12-06 20:13:03 +08:00
kurisaw
3f1a62cfe3 [libcpu][drivers] cortex-r52 abnormal takeover and software rtc naming change 2024-12-04 10:11:04 +08:00
ligr
1cf97d8565 [components][dfs]add some comments and fix some former comments error for dfs v1. 2024-12-03 19:10:21 -05:00
GuEe-GUI
0de160f418 [DM/THERMAL] Add PWM cool fan 
PWM fan is the most populate cool device.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-02 21:17:24 +08:00
GuEe-GUI
429c0c5257 [DM/FEATURE] Support thermal 
Thermal drivers offer a generic mechanism for thermal management.
Usually it's made up of one or more thermal zones and cooling devices.
Each thermal zone contains its own temperature, trip points, and cooling devices.
All platforms with ACPI or OFW thermal support can use this driver.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-02 21:17:24 +08:00
GuEe-GUI
8c0a6c934b [DM/FEATURE] Support import SoC PIN config 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-02 21:15:17 +08:00
GuEe-GUI
e3340eca34 [DM/FEATURE] Support virtual pin 
1. There is only one GPIO device in System.
2. For Pin API input is pin number
3. Add sets pin debounce time API.

So we need a virtual pin for multi gpio chip.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-02 21:15:17 +08:00
GuEe-GUI
16608279db [DM/FIXUP] Fixup pin propname check 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-02 21:15:17 +08:00
GuEe-GUI
7c59bb01ed [DM/FIXUP] Fixup pin flags get from OFW 
Only check HIGH or LOW

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-02 21:15:17 +08:00
GuEe-GUI
aa30e9804a [DM/FIXUP] Fixup pin depend auto 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-02 21:15:17 +08:00
GuEe-GUI
7b7e4686af [DM/MAILBOX] Fixup platform request will deadlock 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-02 21:14:34 +08:00
GuEe-GUI
72a78a268f [DM/DMA] merge ofw_parse and request_chan 
Work together can make DMA engine device drivers
knows how want a chan easy.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-02 21:14:13 +08:00
GuEe-GUI
8f392779ef [DM/DMA] Use strict mode for device DMA pool 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-12-02 21:14:13 +08:00
ligr
e9452ee98f [documentation][dfs]add some comments to dfs posix APIs for supplement. 2024-11-30 21:09:58 -05:00
GuEe-GUI
88b8310d16 [DM/PCI] Add DesignWare PCIe RC/EP base drivers 
Too many PCI controllers base on DesignWare PCIe.
This is a modules.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-28 09:46:58 +08:00
GuEe-GUI
50982cd970 [DM/PCI] Add memory window pool for EP 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-28 09:46:58 +08:00
GuEe-GUI
0d2e677f07 [DM/LED] Add GPIO LED driver 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-28 09:46:02 +08:00
GuEe-GUI
175a7d26bf [DM/FEATURE] Support LED 
Provides general LED control API and drivers.
It can work on PWM, GPIO and Syscon...

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-28 09:46:02 +08:00
GuEe-GUI
6f68ca7c71 [DM/SPI] Support DM mode in SPI 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-27 18:04:07 +08:00
GuEe-GUI
49d18ec0a9 [DM/REGULATOR] Add populate drivers 
1. Fixed regulator.
2. GPIO regulator.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-27 18:02:23 +08:00
GuEe-GUI
56614a4cb9 [DM/FEATURE] Support regulator 
1. Add the regulator driver framework.
2. Add the generic voltage and current regulator API support
  for drivers.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-27 18:02:23 +08:00
Meco Man
443ade4c29 [sscanf] use rt_sscanf to replace sscanf 2024-11-27 10:59:15 +08:00
ligr
ca1d4e6dea [components][ulog]add some comments to ulog for supplement. 2024-11-26 20:05:09 +08:00
GUI
d025072837
[DM/FEATURE] Support ATA AHCI (#9683) 
Add ACHI drivers to support some old platform
driver such as SATA.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-26 11:22:09 +08:00
GuEe-GUI
71520fa9f1 [DM/FIXUP] Add ms sleep for link status change 
We should wait a while for success or failure
after link status change or will communicate
fail with the endpoint.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-26 11:14:51 +08:00
GuEe-GUI
1ac8044294 [DM/FIXUP] Fixup PCI device ofw private node for MSI 
Some PCI device devicetree is like:
```dts
pcie@fe270000 {
    device_type = "pci";
    msi-map = <0x1000 0x9c 0x1000 0x1000>;

    pcie@10 {
        reg = <0x100000 0x00 0x00 0x00 0x00>;
        #address-cells = <0x03>;
        #size-cells = <0x02>;

        pcie@10,0 {
            reg = <0x00 0x00 0x00 0x00 0x00>;
        };
    };
};
```

that the pcie@10,0 have a private ofw node, it will find
property name `msi-map` or `msi-parent` fail.
We should only find the property in host bridge's ofw node.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-26 11:14:51 +08:00
GUI
1a24ae06f3
[DM/FEATURE] Support reset controller (#9630) 
* [DM/FEATURE] Support reset controller

Reset controllers are central units that control
the reset signals to multiple peripherals.
The reset controller API is split into two parts:
  1. The consumer driver interface, which allows
    peripheral drivers to request control over
    their reset input signals
  2. The reset controller driver interface
which is used by drivers for reset controller devices to
register their reset controls to provide them to the consumers.

* [RESET/SIMPLE] Support simple reset

Currently this driver supports:
 - Altera SoCFPGAs
 - ASPEED BMC SoCs
 - Bitmain BM1880 SoC
 - Realtek SoCs
 - RCC reset controller in STM32 MCUs
 - Allwinner SoCs
 - SiFive FU740 SoCs
 - Sophgo SoCs

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-26 10:02:50 +08:00
GUI
f849afb5ca
[DM/FEATURE] Support hardware mailbox (#9599) 
* [DM/FEATURE] Support hardware mailbox
* [MAILBOX/PIC] Add PIC Mailbox drivers.

The mailbox device(s) may be instantiated in one of three equivalent way:

Device Tree node, eg.:

```dts
interrupt-controller@0 {
	interrupt-controller;
	#interrupt-cells = <1>;
};

pic_mailbox@10000 {
	compatible = "rt-thread,pic-mailbox";
	reg = <0x10000 0x100>;
	position = <0>;
	interrupts = <34>;
	peer-interrupts = <35>;
	uid = <0>;
	#mbox-cells = <1>;
};
```
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-25 11:00:04 +08:00
GUI
c2545cdd7b
[DM/FEATURE] Support PHY (external) (#9597) 
This framework will be of use only to devices that use
external PHY (PHY functionality is not embedded within the controller).

Use in PCIE, USB, HDMI, DP...

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-25 10:23:01 +08:00
PermissionDenied7335
92f26b7ad2 [drivers] fixed a minor typo in the comments of dev_serial_v2.c 2024-11-24 12:48:19 -05:00
GUI
945114fd59
[DM/FEATURE] Support NVME (#9591) 
* [DM/FEATURE] Support NVME

1. Support PRP and SGL (>= NVME v1.1) transport.
2. Support MSI/MSI-X for IO queues.
3. Support NVME on PCI.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-24 13:57:37 +08:00
Meco Man
13e0671f65 [fal] using rt-thread raw API instead of std API 2024-11-24 11:34:30 +08:00
Meco Man
8e10983c9b [klibc] add rt_vsnprintf_std.c and rename RT_KLIBC_USING_VSNPRINTF_LONGLONG 2024-11-24 11:29:28 +08:00
GUI
42a41c696d
[DM/FEATURE] Support SCSI bus (#9592) 
* [DM/FEATURE] Support block for SCSI
1. Support SD and CD-ROM.
2. SD will port to UFS and ATA device.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-22 16:59:37 +08:00
GUI
c055261177
[DM/FEATURE] Support DMA management (#9682) 
1. DMA pool management for platform.
2. DMA engine driver API.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-22 14:11:40 +08:00
ligr
dd709c1cea [components/libc/posix]add comments for thread local storage APIs. 2024-11-21 21:46:47 -05:00
ligr
bb0a1ea453 [components/libc/posix]fix the problem that it doesn't check if barrier still in use and dosen't destory the mutex either. 2024-11-21 19:22:44 -05:00
ligr
0bac8c4f90 [components/libc/posix]fix the errors that assigning an integer to a pointer and always return EINVAL. 2024-11-21 19:22:44 -05:00
ligr
79324c0b4c [components/libc/posix]add comments for barrier APIs. 2024-11-21 19:22:44 -05:00
GUI
f797eccbf1
[DM/FEATURE] Support IIO (Industrial I/O) (#9598) 
[DM/FEATURE] Support IIO (Industrial I/O)

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-21 20:44:25 +08:00
GuEe-GUI
4a3fa385cb [DM/FEATURE] Support import SoC Pinctrl config 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-21 12:44:55 +08:00
GuEe-GUI
b0a5bfe66b [DM/FIXUP] Fixup pinctrl depend auto 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-21 12:44:55 +08:00
GuEe-GUI
0d2c84d89f [DM/FEATURE] make SoC Kconfig import easy 
Open Kconfig will not fail if using osource,
This way can make SoC Kconfig to DM easy.

Link: ecb89b1370ec27be650a0a2fae7c6802b4246933

Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-20 23:52:34 +08:00