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29 Commits

Author SHA1 Message Date
tyustli 49e9d19c82 first version 2019-07-24 17:03:26 +08:00
shaojinchun bcb7fac0d0 fix signals for k210 2019-05-11 09:37:25 +08:00
ZYH fcb88f7034 [libcpu][k210]fix stack frame print 2019-03-28 17:05:52 +08:00
BernardXiong bd8f0d0423 [libcpu] Fix the build directory issue 2019-03-26 13:36:01 +00:00
ZYH c41bf3120f [libcpu][k210]add stack info printf 2019-03-21 15:10:55 +08:00
ZYH 3dd72f956b [libcpu][k210]add description of exception 2019-03-20 12:23:17 +08:00
Bernard Xiong bde47018b8 [libcpu] Add SConscript in libcpu. 2019-01-07 06:09:45 +08:00
shaojinchun 86c76b0e8a add k210 SMP support 2018-12-28 09:41:18 +08:00
Bernard Xiong 597d71cc03 [bsp][k210] Add get_free_heap_size function. 
* Add get_free_heap_size function;
* Increase shell stack for KPU module.
 2018-12-23 14:11:25 +08:00
Bernard Xiong 5e0f8cb3aa [libcpu] Add k210 BSP. 2018-12-18 21:01:03 +08:00
Bernard Xiong 885d99ee9b
[libcpu][risc-v] fix rt_thread_switch_interrupt_flag issue. 2018-12-15 11:47:59 +08:00
Bernard Xiong fd347fdb90
[libcpu][risc-v] fix the rt_thread_switch_interrupt_flag issue 2018-12-15 11:47:10 +08:00
Bernard Xiong 08521ceaa5 [libcpu] Fix the E310 compiling issue. 2018-12-08 17:08:52 +08:00
Bernard Xiong c9576c3e53 [BSP] Add RV32M1_VEGA BSP. 2018-12-08 10:44:56 +08:00
Bernard Xiong 36b194aeb6 [BSP] Update Hifive1 BSP with unified RV porting. 2018-12-08 10:42:40 +08:00
Bernard Xiong 2a7d814f77 [libcpu] Add unified RISC-V libcpu porting. 2018-12-08 10:41:38 +08:00
liang yongxiang 32c5b2515f [libcpu] add risc-v e310 porting 2018-05-31 14:53:26 +08:00
liang yongxiang 5faae3350c [libcpu] remove libcpu/risc-v 2018-05-29 12:59:13 +08:00
Bernard Xiong 2ac493698b [BSP] cleanup for hifive1 bsp. 2017-08-26 11:02:39 +08:00
zhangjun 72cfe9dd68 modify： drivers/cpuusage.c 
modify：     ../../libcpu/risc-v/e310/stack.c
	rmove unused macro definition
modify：     ../../src/idle.c
	Return to the original version
 2017-07-31 12:05:45 +08:00
zhangjun e9f1bdf2da new file： ../../libcpu/risc-v/e310/trap.c 
add file that forget to submit before
	auto change timer mtimercmp register on the base of RT_TICK_PER_SECOND in rtconfig.h
	no flashing led
new file：   ../../src/idle.c
	recover old file
 2017-07-31 11:12:28 +08:00
zhangjun a5305c05df fix bug in context_gcc.s and start_gcc.s: 
save mie into stack
msh  running normaly
 2017-07-31 10:59:59 +08:00
zhangjun b032dff161 fix bug in rt_hw_context_switch_interrupt_do 
save sp to old thread
	clear rt_thread_switch_interrupt_flag
always enable interrupt after rt_hw_context_switch
judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt)
 2017-07-30 19:46:28 +08:00
zhangjun 2d56a27c20 修改： ../../libcpu/risc-v/e310/context_gcc.S 
enable interrupt after return form rt_hw_context_switch
 2017-07-30 15:34:32 +08:00
zhangjun 3c51848d33 fix trap_entry 2017-07-29 15:37:20 +08:00
zhangjun b80f83f360 modified: ../../libcpu/risc-v/e310/context_gcc.S 
fix open timer intrrupt
 2017-07-26 16:27:54 +08:00
zhangjun 98a6896cfa remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable(); 
it will lead to interrupt again in interrupt
 2017-07-26 16:07:01 +08:00
zhangjun b334347a24 deleted: rtthread.s /*just for debug*/ 
modified:   ../../libcpu/risc-v/e310/context_gcc.S
	change  ret to mret and switch to new task with mepc
 2017-07-17 16:55:33 +08:00
zhangjun e01455155a add context_gcc.s 2017-07-17 15:44:00 +08:00