rt-thread

Commit Graph

Author	SHA1	Message	Date
guo	ecf2d82159	sync branch rt-smart. (#6641 ) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>	2022-12-03 12:07:44 +08:00
rewine	53ed031498	[bsp/qemu-virt64-riscv]: dont use sbi in m-mode	2022-06-13 21:26:49 +08:00
rewine	9ebe0f3b47	[bsp] rename qemu-riscv-virt64 to qemu-virt64-riscv	2022-05-25 10:05:23 +08:00

Author

SHA1

Message

Date

guo

ecf2d82159

sync branch rt-smart. (#6641 )

* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>

2022-12-03 12:07:44 +08:00

rewine

53ed031498

[bsp/qemu-virt64-riscv]: dont use sbi in m-mode

2022-06-13 21:26:49 +08:00

rewine

9ebe0f3b47

[bsp] rename qemu-riscv-virt64 to qemu-virt64-riscv

2022-05-25 10:05:23 +08:00

3 Commits