99bdf978d7
[rtdef] use lower-case to define attributes ( #6728 )
...
* [rtdef] rename RT_WEAK attribute as rt_weak
* [rtdef] rename RT_USED attribute as rt_used
* [rtdef] rename RT_SECTION attribute as rt_section
* [rtdef] rename ALIGN attribute as rt_align
* [legacy] add RT_USED ALIGN RT_SECTION RT_WEAK as legacy support
2022-12-11 13:12:03 -05:00
e991be9c51
[smart][risc-v/libcpu] port rv64 cpu code ( #6704 )
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* [risc-v/libcpu] porting Smart & RTOS
* [fix] rv64 plic
* [risc-v/rv64] remove macro in rtdef
2022-12-10 22:16:42 +08:00
ecf2d82159
sync branch rt-smart. ( #6641 )
...
* Synchronize the code of the rt mart branch to the master branch.
* TTY device
* Add lwP code from rt-smart
* Add vnode in DFS, but DFS will be re-write for rt-smart
* There are three libcpu for rt-smart:
* arm/cortex-a, arm/aarch64
* riscv64
Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
8b0610fc34
[bsp][readme] 增加scons --exec-path=xxx 命令的使用说明
2022-10-10 09:42:44 +08:00
a4eb64b873
update the project for RT-Thread_V4.1.1
2022-08-16 19:38:48 +08:00
53ed031498
[bsp/qemu-virt64-riscv]: dont use sbi in m-mode
2022-06-13 21:26:49 +08:00
9ebe0f3b47
[bsp] rename qemu-riscv-virt64 to qemu-virt64-riscv
2022-05-25 10:05:23 +08:00
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