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Convert Libraries format

This commit is contained in:
NU-LL 2021-10-14 19:46:54 +08:00
parent c178d61947
commit ffd8662d7a
33 changed files with 1931 additions and 1931 deletions
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66
bsp/tkm32F499/Libraries/CMSIS_and_startup/sys.c
View File

@ -3,24 +3,24 @@
void RemapVtorTable(void) void RemapVtorTable(void)
{ {
int i; int i;
RCC->AHB1ENR |= 1<<13;//bkp clk,enable sram RCC->AHB1ENR |= 1<<13;//bkp clk,enable sram
//关ROM区中断 //关ROM区中断
for(i = 0;i<90;i++) for(i = 0;i<90;i++)
{ {
NVIC_DisableIRQ((IRQn_Type)i); NVIC_DisableIRQ((IRQn_Type)i);
} }
SCB->VTOR = 0; SCB->VTOR = 0;
SCB->VTOR |= 0x1<<29; SCB->VTOR |= 0x1<<29;
for(i = 0;i < 512;i+=4) for(i = 0;i < 512;i+=4)
*(u32*)(T_SRAM_BASE + i) = *(u32*)(T_SDRAM_BASE+i); *(u32*)(T_SRAM_BASE + i) = *(u32*)(T_SDRAM_BASE+i);
} }
void AI_Responder_enable(void) void AI_Responder_enable(void)
{ {
AI_Responder->ADDR1= 0x70807040; AI_Responder->ADDR1= 0x70807040;
// AI_Responder->ADDR0 = 0x70027080; // AI_Responder->ADDR0 = 0x70027080;
AI_Responder->ADDR1 = 0; AI_Responder->ADDR1 = 0;
AI_Responder->CCR &= ~(0x3<<3); AI_Responder->CCR &= ~(0x3<<3);
AI_Responder->CCR |= 1; AI_Responder->CCR |= 1;
@ -42,14 +42,14 @@ void AI_Responder_disable(void)
//该函数会自动开启对应中断,以及屏蔽线 //该函数会自动开启对应中断,以及屏蔽线
void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM) void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM)
{ {
u8 EXTOFFSET=(BITx%4)*4; u8 EXTOFFSET=(BITx%4)*4;
RCC->APB2ENR|=1<<14; //使能SYSCFG时钟 RCC->APB2ENR|=1<<14; //使能SYSCFG时钟
SYSCFG->EXTICR[BITx/4]&=~(0x000F<<EXTOFFSET);//清除原来设置！！！ SYSCFG->EXTICR[BITx/4]&=~(0x000F<<EXTOFFSET);//清除原来设置！！！
SYSCFG->EXTICR[BITx/4]|=GPIOx<<EXTOFFSET; //EXTI.BITx映射到GPIOx.BITx SYSCFG->EXTICR[BITx/4]|=GPIOx<<EXTOFFSET; //EXTI.BITx映射到GPIOx.BITx
//自动设置 //自动设置
EXTI->IMR|=1<<BITx; //开启line BITx上的中断(如果要禁止中断，则反操作即可) EXTI->IMR|=1<<BITx; //开启line BITx上的中断(如果要禁止中断，则反操作即可)
if(TRIM&0x01)EXTI->FTSR|=1<<BITx; //line BITx事件下降沿触发 if(TRIM&0x01)EXTI->FTSR|=1<<BITx; //line BITx事件下降沿触发
if(TRIM&0x02)EXTI->RTSR|=1<<BITx; //line BITx事件上升沿触发 if(TRIM&0x02)EXTI->RTSR|=1<<BITx; //line BITx事件上升沿触发
} }
@ -57,37 +57,37 @@ void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM)
//采用如下方法实现执行汇编指令WFI //采用如下方法实现执行汇编指令WFI
void WFI_SET(void) void WFI_SET(void)
{ {
__ASM volatile("wfi"); __ASM volatile("wfi");
} }
//关闭所有中断(但是不包括fault和NMI中断) //关闭所有中断(但是不包括fault和NMI中断)
void INTX_DISABLE(void) void INTX_DISABLE(void)
{ {
__ASM volatile("cpsid i"); __ASM volatile("cpsid i");
} }
//开启所有中断 //开启所有中断
void INTX_ENABLE(void) void INTX_ENABLE(void)
{ {
__ASM volatile("cpsie i"); __ASM volatile("cpsie i");
} }
//设置栈顶地址 __set_MSP(0x70002000); //设置栈顶地址 __set_MSP(0x70002000);
//进入待机模式 //进入待机模式
void Sys_Standby(void) void Sys_Standby(void)
{ {
SCB->SCR|=1<<2; //使能SLEEPDEEP位 (SYS->CTRL) SCB->SCR|=1<<2; //使能SLEEPDEEP位 (SYS->CTRL)
RCC->APB1ENR|=1<<28;//使能电源时钟 RCC->APB1ENR|=1<<28;//使能电源时钟
PWR->CSR|=1<<8; //设置WKUP用于唤醒 PWR->CSR|=1<<8; //设置WKUP用于唤醒
PWR->CR|=1<<2; //清除Wake-up 标志 PWR->CR|=1<<2; //清除Wake-up 标志
PWR->CR|=1<<1; //PDDS置位 PWR->CR|=1<<1; //PDDS置位
WFI_SET(); //执行WFI指令,进入待机模式 WFI_SET(); //执行WFI指令,进入待机模式
} }
//系统软复位 //系统软复位
void Sys_Soft_Reset(void) void Sys_Soft_Reset(void)
{ {
SCB->AIRCR =0X05FA0000|(u32)0x04; SCB->AIRCR =0X05FA0000|(u32)0x04;
} }
// TK499_NVIC_Init(2,2,TK80_IRQn,2); // TK499_NVIC_Init(2,2,TK80_IRQn,2);
//设置NVIC //设置NVIC
//NVIC_PreemptionPriority:抢占优先级 //NVIC_PreemptionPriority:抢占优先级
//NVIC_SubPriority :响应优先级 //NVIC_SubPriority :响应优先级
@ -103,13 +103,13 @@ void Sys_Soft_Reset(void)
//NVIC_SubPriority和NVIC_PreemptionPriority的原则是,数值越小,越优先 //NVIC_SubPriority和NVIC_PreemptionPriority的原则是,数值越小,越优先
void TK499_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group) void TK499_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group)
{ {
u32 temp; u32 temp;
NVIC_SetPriorityGrouping(NVIC_Group);//设置分组 NVIC_SetPriorityGrouping(NVIC_Group);//设置分组
temp=NVIC_PreemptionPriority<<(4-NVIC_Group); temp=NVIC_PreemptionPriority<<(4-NVIC_Group);
temp|=NVIC_SubPriority&(0x0f>>NVIC_Group); temp|=NVIC_SubPriority&(0x0f>>NVIC_Group);
temp&=0xf; //取低四位 temp&=0xf; //取低四位
NVIC->ISER[NVIC_Channel/32]|=1<<NVIC_Channel%32;//使能中断位(要清除的话,设置ICER对应位为1即可) NVIC->ISER[NVIC_Channel/32]|=1<<NVIC_Channel%32;//使能中断位(要清除的话,设置ICER对应位为1即可)
NVIC->IP[NVIC_Channel]|=temp<<4; //设置响应优先级和抢断优先级 NVIC->IP[NVIC_Channel]|=temp<<4; //设置响应优先级和抢断优先级
} }
void TK80_IRQHandler(void) void TK80_IRQHandler(void)

10
bsp/tkm32F499/Libraries/CMSIS_and_startup/sys.h
View File

@ -13,16 +13,16 @@ void RemapVtorTable(void);
void AI_Responder_enable(void); void AI_Responder_enable(void);
void AI_Responder_disable(void); void AI_Responder_disable(void);
void Sys_Soft_Reset(void); //系统软复位 void Sys_Soft_Reset(void); //系统软复位
void Sys_Standby(void); //待机模式 void Sys_Standby(void); //待机模式
void TK499_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group); void TK499_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group);
void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM); //外部中断配置函数(只对GPIOA~I) void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM); //外部中断配置函数(只对GPIOA~I)
//以下为汇编函数 //以下为汇编函数
void WFI_SET(void); //执行WFI指令 void WFI_SET(void); //执行WFI指令
void INTX_DISABLE(void);//关闭所有中断 void INTX_DISABLE(void);//关闭所有中断
void INTX_ENABLE(void); //开启所有中断 void INTX_ENABLE(void); //开启所有中断
void TIM3_Config(u16 arr,u16 psc); void TIM3_Config(u16 arr,u16 psc);
#endif #endif

546
bsp/tkm32F499/Libraries/CMSIS_and_startup/tk499.h
View File

@ -21,7 +21,7 @@
****************************************************************************** ******************************************************************************
*/ */
//============== <EFBFBD>汾 EK V1.0 20190818 ==============// //============== 锟芥本 EK V1.0 20190818 ==============//
#define T_SRAM_BASE 0X20000000 #define T_SRAM_BASE 0X20000000
@ -130,10 +130,10 @@ typedef enum IRQn
TIM3_IRQn = 28, /*!< TIM3 global Interrupt */ TIM3_IRQn = 28, /*!< TIM3 global Interrupt */
TIM4_IRQn = 29, /*!< TIM4 global Interrupt */ TIM4_IRQn = 29, /*!< TIM4 global Interrupt */
TIM5_IRQn = 30, /*!< TIM4 global Interrupt */ TIM5_IRQn = 30, /*!< TIM4 global Interrupt */
TIM6_IRQn = 31, /*!< TIM4 global Interrupt */ TIM6_IRQn = 31, /*!< TIM4 global Interrupt */
TIM7_IRQn = 32, /*!< TIM4 global Interrupt */ TIM7_IRQn = 32, /*!< TIM4 global Interrupt */
I2C1_IRQn = 33, /*!< I2C1 Event Interrupt */ I2C1_IRQn = 33, /*!< I2C1 Event Interrupt */
I2C2_IRQn = 34, /*!< I2C2 Event Interrupt */ I2C2_IRQn = 34, /*!< I2C2 Event Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
@ -144,39 +144,39 @@ typedef enum IRQn
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
USBAwake_IRQn = 42, /*!< USB WakeUp from suspend through EXTI Line Interrupt */ USBAwake_IRQn = 42, /*!< USB WakeUp from suspend through EXTI Line Interrupt */
TIM2_BRK_IRQn = 43, /**/ TIM2_BRK_IRQn = 43, /**/
TIM2_UP_IRQn = 44, /**/ TIM2_UP_IRQn = 44, /**/
TIM2_TRG_COM_IRQn = 45, /**/ TIM2_TRG_COM_IRQn = 45, /**/
TIM2_CC_IRQn = 46, /**/ TIM2_CC_IRQn = 46, /**/
DMA1_Channel8_IRQn = 47, /**/ DMA1_Channel8_IRQn = 47, /**/
TK80_IRQn = 48, /**/ TK80_IRQn = 48, /**/
SDIO1_IRQn = 49, /**/ SDIO1_IRQn = 49, /**/
SDIO2_IRQn = 50, /**/ SDIO2_IRQn = 50, /**/
SPI3_IRQn = 51, /**/ SPI3_IRQn = 51, /**/
UART4_IRQn = 52, /**/ UART4_IRQn = 52, /**/
UART5_IRQn = 53, /**/ UART5_IRQn = 53, /**/
TIM8_IRQn = 55, /**/ TIM8_IRQn = 55, /**/
DMA2_Channel1_IRQn = 56, /**/ DMA2_Channel1_IRQn = 56, /**/
DMA2_Channel2_IRQn = 57, /**/ DMA2_Channel2_IRQn = 57, /**/
DMA2_Channel3_IRQn = 58, /**/ DMA2_Channel3_IRQn = 58, /**/
DMA2_Channel4_IRQn = 59, /**/ DMA2_Channel4_IRQn = 59, /**/
DMA2_Channel5_IRQn = 60, /**/ DMA2_Channel5_IRQn = 60, /**/
TIM9_IRQn = 61, /**/ TIM9_IRQn = 61, /**/
TIM10_IRQn = 62, /**/ TIM10_IRQn = 62, /**/
CAN2_IRQn = 63, /**/ CAN2_IRQn = 63, /**/
USB_IRQn = 67, /**/ USB_IRQn = 67, /**/
DMA2_Channel6_IRQn = 68, /**/ DMA2_Channel6_IRQn = 68, /**/
DMA2_Channel7_IRQn = 69, /**/ DMA2_Channel7_IRQn = 69, /**/
DMA2_Channel8_IRQn = 70, /**/ DMA2_Channel8_IRQn = 70, /**/
I2C3_IRQn = 72, /**/ I2C3_IRQn = 72, /**/
I2C4_IRQn = 73, /**/ I2C4_IRQn = 73, /**/
FPU_IRQn = 81, /**/ FPU_IRQn = 81, /**/
SPI4_IRQn = 84, /**/ SPI4_IRQn = 84, /**/
TOUCHPAD_IRQn = 86, TOUCHPAD_IRQn = 86,
QSPI_IRQn = 87, /**/ QSPI_IRQn = 87, /**/
LTDC_IRQn = 88, /**/ LTDC_IRQn = 88, /**/
I2S1_IRQn = 90, /**/ I2S1_IRQn = 90, /**/
} IRQn_Type; } IRQn_Type;
@ -320,38 +320,38 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
__IO uint32_t CR; //0x00 __IO uint32_t CR; //0x00
__IO uint32_t CMR; //0x04 __IO uint32_t CMR; //0x04
__IO uint32_t SR; //0x08 __IO uint32_t SR; //0x08
__IO uint32_t IR; //0x0c __IO uint32_t IR; //0x0c
__IO uint32_t ACR; //0x10 __IO uint32_t ACR; //0x10
__IO uint32_t AMR; //0x14 __IO uint32_t AMR; //0x14
__IO uint32_t BTR0; //0x18 __IO uint32_t BTR0; //0x18
__IO uint32_t BTR1; //0x1C __IO uint32_t BTR1; //0x1C
__IO uint32_t RESERVED0; //0x20 __IO uint32_t RESERVED0; //0x20
uint32_t RESERVED1; //0x24 uint32_t RESERVED1; //0x24
__IO uint32_t TXID0; //0x28 __IO uint32_t TXID0; //0x28
__IO uint32_t TXID1; //0x2c __IO uint32_t TXID1; //0x2c
__IO uint32_t TXDR0; //0x30 __IO uint32_t TXDR0; //0x30
__IO uint32_t TXDR1; //0x34 __IO uint32_t TXDR1; //0x34
__IO uint32_t TXDR2; //0x38 __IO uint32_t TXDR2; //0x38
__IO uint32_t TXDR3; //0x3c __IO uint32_t TXDR3; //0x3c
__IO uint32_t TXDR4; //0x40 __IO uint32_t TXDR4; //0x40
__IO uint32_t TXDR5; //0x44 __IO uint32_t TXDR5; //0x44
__IO uint32_t TXDR6; //0x48 __IO uint32_t TXDR6; //0x48
__IO uint32_t TXDR7; //0x4c __IO uint32_t TXDR7; //0x4c
__IO uint32_t RXID0; //0x50 __IO uint32_t RXID0; //0x50
__IO uint32_t RXID1; //0x54 __IO uint32_t RXID1; //0x54
__IO uint32_t RXDR0; //0x58 __IO uint32_t RXDR0; //0x58
__IO uint32_t RXDR1; //0x5C __IO uint32_t RXDR1; //0x5C
__IO uint32_t RXDR2; //0x60 __IO uint32_t RXDR2; //0x60
__IO uint32_t RXDR3; __IO uint32_t RXDR3;
__IO uint32_t RXDR4; __IO uint32_t RXDR4;
__IO uint32_t RXDR5; //0x6c __IO uint32_t RXDR5; //0x6c
__IO uint32_t RXDR6; //0x70 __IO uint32_t RXDR6; //0x70
__IO uint32_t RXDR7; //0x74 __IO uint32_t RXDR7; //0x74
uint32_t RESERVED2; uint32_t RESERVED2;
__IO uint32_t CDR; //0x7c __IO uint32_t CDR; //0x7c
}CAN_TypeDef; }CAN_TypeDef;
/** /**
@ -359,38 +359,38 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
__IO uint32_t MOD; //00 __IO uint32_t MOD; //00
__IO uint32_t CMR; //04 __IO uint32_t CMR; //04
__IO uint32_t SR; //08 __IO uint32_t SR; //08
__IO uint32_t IR; //0C __IO uint32_t IR; //0C
__IO uint32_t IER; //0x10h __IO uint32_t IER; //0x10h
uint32_t RESERVED0; //14 uint32_t RESERVED0; //14
__IO uint32_t BTR0; //18 __IO uint32_t BTR0; //18
__IO uint32_t BTR1; //1C __IO uint32_t BTR1; //1C
uint32_t RESERVED1; //0x20h uint32_t RESERVED1; //0x20h
uint32_t RESERVED2; //24 uint32_t RESERVED2; //24
uint32_t RESERVED3; //28 uint32_t RESERVED3; //28
__IO uint32_t ALC; //2C __IO uint32_t ALC; //2C
__IO uint32_t ECC; //0x30h __IO uint32_t ECC; //0x30h
__IO uint32_t EWLR; //34 __IO uint32_t EWLR; //34
__IO uint32_t RXERR; //38 __IO uint32_t RXERR; //38
__IO uint32_t TXERR; //3C __IO uint32_t TXERR; //3C
__IO uint32_t FF; //0x40 __IO uint32_t FF; //0x40
__IO uint32_t ID0; //44 __IO uint32_t ID0; //44
__IO uint32_t ID1; //48 __IO uint32_t ID1; //48
__IO uint32_t DATA0; //4C __IO uint32_t DATA0; //4C
__IO uint32_t DATA1; //0x50 __IO uint32_t DATA1; //0x50
__IO uint32_t DATA2; __IO uint32_t DATA2;
__IO uint32_t DATA3; __IO uint32_t DATA3;
__IO uint32_t DATA4; __IO uint32_t DATA4;
__IO uint32_t DATA5; //0x60 __IO uint32_t DATA5; //0x60
__IO uint32_t DATA6; __IO uint32_t DATA6;
__IO uint32_t DATA7; __IO uint32_t DATA7;
__IO uint32_t DATA8; __IO uint32_t DATA8;
__IO uint32_t DATA9; //0x70 __IO uint32_t DATA9; //0x70
__IO uint32_t RMC; __IO uint32_t RMC;
__IO uint32_t RBSA; __IO uint32_t RBSA;
__IO uint32_t CDR; //7C __IO uint32_t CDR; //7C
}CAN_Peli_TypeDef; }CAN_Peli_TypeDef;
@ -558,7 +558,7 @@ typedef struct
typedef struct typedef struct
{ {
__IO uint32_t CFGR; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
__IO uint32_t RESERVED0; __IO uint32_t RESERVED0;
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
} SYSCFG_TypeDef; } SYSCFG_TypeDef;
@ -759,7 +759,7 @@ typedef struct
__IO uint32_t RXDNR; __IO uint32_t RXDNR;
__IO uint32_t SCSR; //30 __IO uint32_t SCSR; //30
__IO uint32_t TXREGBH; __IO uint32_t TXREGBH;
__IO uint32_t TXREGBL; __IO uint32_t TXREGBL;
} SPI_TypeDef; } SPI_TypeDef;
@ -830,13 +830,13 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
__IO uint32_t rTOP; /*! Address offset: 0x00 */ __IO uint32_t rTOP; /*! Address offset: 0x00 */
__IO uint32_t rINT_STATE; /*! Address offset: 0x04 */ __IO uint32_t rINT_STATE; /*! Address offset: 0x04 */
__IO uint32_t rEP_INT_STATE; /*! Address offset: 0x08 */ __IO uint32_t rEP_INT_STATE; /*! Address offset: 0x08 */
__IO uint32_t rEP0_INT_STATE; /*! Address offset: 0x0C */ __IO uint32_t rEP0_INT_STATE; /*! Address offset: 0x0C */
__IO uint32_t rINT_EN; /*! Address offset: 0x10 */ __IO uint32_t rINT_EN; /*! Address offset: 0x10 */
__IO uint32_t rEP_INT_EN; /*! Address offset: 0x14 */ __IO uint32_t rEP_INT_EN; /*! Address offset: 0x14 */
__IO uint32_t rEP0_INT_EN; /*! Address offset: 0x18 */ __IO uint32_t rEP0_INT_EN; /*! Address offset: 0x18 */
__IO uint32_t RESERVED0; __IO uint32_t RESERVED0;
@ -847,137 +847,137 @@ typedef struct
__IO uint32_t rEP3_INT_STATE; /*! Address offset: 0x28 */ __IO uint32_t rEP3_INT_STATE; /*! Address offset: 0x28 */
__IO uint32_t rEP4_INT_STATE; /*! Address offset: 0x2C */ __IO uint32_t rEP4_INT_STATE; /*! Address offset: 0x2C */
__IO uint32_t RESERVED1; /*! Address offset: 0x30 */ __IO uint32_t RESERVED1; /*! Address offset: 0x30 */
__IO uint32_t RESERVED2; /*! Address offset: 0x34 */ __IO uint32_t RESERVED2; /*! Address offset: 0x34 */
__IO uint32_t RESERVED3; /*! Address offset: 0x38 */ __IO uint32_t RESERVED3; /*! Address offset: 0x38 */
__IO uint32_t RESERVED4; /*! Address offset: 0x3C */ __IO uint32_t RESERVED4; /*! Address offset: 0x3C */
__IO uint32_t rEP1_INT_EN; /*! Address offset: 0x40 */ __IO uint32_t rEP1_INT_EN; /*! Address offset: 0x40 */
__IO uint32_t rEP2_INT_EN; /*! Address offset: 0x44 */ __IO uint32_t rEP2_INT_EN; /*! Address offset: 0x44 */
__IO uint32_t rEP3_INT_EN; /*! Address offset: 0x48 */ __IO uint32_t rEP3_INT_EN; /*! Address offset: 0x48 */
__IO uint32_t rEP4_INT_EN; /*! Address offset: 0x4C */ __IO uint32_t rEP4_INT_EN; /*! Address offset: 0x4C */
__IO uint32_t RESERVED5; /*! Address offset: 0x50 */ __IO uint32_t RESERVED5; /*! Address offset: 0x50 */
__IO uint32_t RESERVED6; /*! Address offset: 0x54 */ __IO uint32_t RESERVED6; /*! Address offset: 0x54 */
__IO uint32_t RESERVED7; /*! Address offset: 0x58 */ __IO uint32_t RESERVED7; /*! Address offset: 0x58 */
__IO uint32_t RESERVED8; /*! Address offset: 0x5C */ __IO uint32_t RESERVED8; /*! Address offset: 0x5C */
__IO uint32_t rADDR; /*! Address offset: 0x60 */ __IO uint32_t rADDR; /*! Address offset: 0x60 */
__IO uint32_t rEP_EN; /*! Address offset: 0x64 */ __IO uint32_t rEP_EN; /*! Address offset: 0x64 */
__IO uint32_t RESERVED9; /*! Address offset: 0x68 */ __IO uint32_t RESERVED9; /*! Address offset: 0x68 */
__IO uint32_t RESERVED10; /*! Address offset: 0x6C */ __IO uint32_t RESERVED10; /*! Address offset: 0x6C */
__IO uint32_t RESERVED11; /*! Address offset: 0x70 */ __IO uint32_t RESERVED11; /*! Address offset: 0x70 */
__IO uint32_t RESERVED12; /*! Address offset: 0x74 */ __IO uint32_t RESERVED12; /*! Address offset: 0x74 */
__IO uint32_t rTOG_CTRL1_4; /*! Address offset: 0x78 */ __IO uint32_t rTOG_CTRL1_4; /*! Address offset: 0x78 */
__IO uint32_t RESERVED13; /*! Address offset: 0x7C */ __IO uint32_t RESERVED13; /*! Address offset: 0x7C */
__IO uint32_t rSETUP[8]; /*! Address offset: 0x80 */ __IO uint32_t rSETUP[8]; /*! Address offset: 0x80 */
//__IO uint32_t rSETUP0; /*! Address offset: 0x80 */ //__IO uint32_t rSETUP0; /*! Address offset: 0x80 */
//__IO uint32_t rSETUP1; /*! Address offset: 0x84 */ //__IO uint32_t rSETUP1; /*! Address offset: 0x84 */
//__IO uint32_t rSETUP2; /*! Address offset: 0x88 */ //__IO uint32_t rSETUP2; /*! Address offset: 0x88 */
//__IO uint32_t rSETUP3; /*! Address offset: 0x8C */ //__IO uint32_t rSETUP3; /*! Address offset: 0x8C */
//__IO uint32_t rSETUP4; /*! Address offset: 0x90 */ //__IO uint32_t rSETUP4; /*! Address offset: 0x90 */
//__IO uint32_t rSETUP5; /*! Address offset: 0x94 */ //__IO uint32_t rSETUP5; /*! Address offset: 0x94 */
//__IO uint32_t rSETUP6; /*! Address offset: 0x98 */ //__IO uint32_t rSETUP6; /*! Address offset: 0x98 */
//__IO uint32_t rSETUP7; /*! Address offset: 0x9C */ //__IO uint32_t rSETUP7; /*! Address offset: 0x9C */
__IO uint32_t rPAKET_SIZE0; /*! Address offset: 0xA0 */ __IO uint32_t rPAKET_SIZE0; /*! Address offset: 0xA0 */
__IO uint32_t rPAKET_SIZE1; /*! Address offset: 0xA4 */ __IO uint32_t rPAKET_SIZE1; /*! Address offset: 0xA4 */
__IO uint32_t RESERVED14; /*! Address offset: 0xA8 */ __IO uint32_t RESERVED14; /*! Address offset: 0xA8 */
__IO uint32_t RESERVED15; /*! Address offset: 0xAC */ __IO uint32_t RESERVED15; /*! Address offset: 0xAC */
__IO uint32_t RESERVED16; /*! Address offset: 0xB0 */ __IO uint32_t RESERVED16; /*! Address offset: 0xB0 */
__IO uint32_t RESERVED17; /*! Address offset: 0xB4 */ __IO uint32_t RESERVED17; /*! Address offset: 0xB4 */
__IO uint32_t RESERVED18; /*! Address offset: 0xB8 */ __IO uint32_t RESERVED18; /*! Address offset: 0xB8 */
__IO uint32_t RESERVED19; /*! Address offset: 0xBC */ __IO uint32_t RESERVED19; /*! Address offset: 0xBC */
__IO uint32_t RESERVED20; /*! Address offset: 0xC0 */ __IO uint32_t RESERVED20; /*! Address offset: 0xC0 */
__IO uint32_t RESERVED21; /*! Address offset: 0xC4 */ __IO uint32_t RESERVED21; /*! Address offset: 0xC4 */
__IO uint32_t RESERVED22; /*! Address offset: 0xC8 */ __IO uint32_t RESERVED22; /*! Address offset: 0xC8 */
__IO uint32_t RESERVED23; /*! Address offset: 0xCC */ __IO uint32_t RESERVED23; /*! Address offset: 0xCC */
__IO uint32_t RESERVED24; /*! Address offset: 0xD0 */ __IO uint32_t RESERVED24; /*! Address offset: 0xD0 */
__IO uint32_t RESERVED25; /*! Address offset: 0xD4 */ __IO uint32_t RESERVED25; /*! Address offset: 0xD4 */
__IO uint32_t RESERVED26; /*! Address offset: 0xD8 */ __IO uint32_t RESERVED26; /*! Address offset: 0xD8 */
__IO uint32_t RESERVED27; /*! Address offset: 0xDC */ __IO uint32_t RESERVED27; /*! Address offset: 0xDC */
__IO uint32_t RESERVED28; /*! Address offset: 0xE0 */ __IO uint32_t RESERVED28; /*! Address offset: 0xE0 */
__IO uint32_t RESERVED29; /*! Address offset: 0xE4 */ __IO uint32_t RESERVED29; /*! Address offset: 0xE4 */
__IO uint32_t RESERVED30; /*! Address offset: 0xE8 */ __IO uint32_t RESERVED30; /*! Address offset: 0xE8 */
__IO uint32_t RESERVED31; /*! Address offset: 0xEC */ __IO uint32_t RESERVED31; /*! Address offset: 0xEC */
__IO uint32_t RESERVED32; /*! Address offset: 0xF0 */ __IO uint32_t RESERVED32; /*! Address offset: 0xF0 */
__IO uint32_t RESERVED33; /*! Address offset: 0xF4 */ __IO uint32_t RESERVED33; /*! Address offset: 0xF4 */
__IO uint32_t RESERVED34; /*! Address offset: 0xF8 */ __IO uint32_t RESERVED34; /*! Address offset: 0xF8 */
__IO uint32_t RESERVED35; /*! Address offset: 0xFC */ __IO uint32_t RESERVED35; /*! Address offset: 0xFC */
__IO uint32_t rEP0_AVIL; /*! Address offset: 0x100 */ __IO uint32_t rEP0_AVIL; /*! Address offset: 0x100 */
__IO uint32_t rEP1_AVIL; /*! Address offset: 0x104 */ __IO uint32_t rEP1_AVIL; /*! Address offset: 0x104 */
__IO uint32_t rEP2_AVIL; /*! Address offset: 0x108 */ __IO uint32_t rEP2_AVIL; /*! Address offset: 0x108 */
__IO uint32_t rEP3_AVIL; /*! Address offset: 0x10C */ __IO uint32_t rEP3_AVIL; /*! Address offset: 0x10C */
__IO uint32_t rEP4_AVIL; /*! Address offset: 0x110 */ __IO uint32_t rEP4_AVIL; /*! Address offset: 0x110 */
__IO uint32_t RESERVED36; /*! Address offset: 0x114 */ __IO uint32_t RESERVED36; /*! Address offset: 0x114 */
__IO uint32_t RESERVED37; /*! Address offset: 0x118 */ __IO uint32_t RESERVED37; /*! Address offset: 0x118 */
__IO uint32_t RESERVED38; /*! Address offset: 0x11C */ __IO uint32_t RESERVED38; /*! Address offset: 0x11C */
__IO uint32_t RESERVED39; /*! Address offset: 0x120 */ __IO uint32_t RESERVED39; /*! Address offset: 0x120 */
__IO uint32_t RESERVED40; /*! Address offset: 0x124 */ __IO uint32_t RESERVED40; /*! Address offset: 0x124 */
__IO uint32_t RESERVED41; /*! Address offset: 0x128 */ __IO uint32_t RESERVED41; /*! Address offset: 0x128 */
__IO uint32_t RESERVED42; /*! Address offset: 0x12C */ __IO uint32_t RESERVED42; /*! Address offset: 0x12C */
__IO uint32_t RESERVED43; /*! Address offset: 0x130 */ __IO uint32_t RESERVED43; /*! Address offset: 0x130 */
__IO uint32_t RESERVED44; /*! Address offset: 0x134 */ __IO uint32_t RESERVED44; /*! Address offset: 0x134 */
__IO uint32_t RESERVED45; /*! Address offset: 0x138 */ __IO uint32_t RESERVED45; /*! Address offset: 0x138 */
__IO uint32_t RESERVED46; /*! Address offset: 0x13C */ __IO uint32_t RESERVED46; /*! Address offset: 0x13C */
__IO uint32_t rEP0_CTRL; /*! Address offset: 0x140 */ __IO uint32_t rEP0_CTRL; /*! Address offset: 0x140 */
__IO uint32_t rEP1_CTRL; /*! Address offset: 0x144 */ __IO uint32_t rEP1_CTRL; /*! Address offset: 0x144 */
__IO uint32_t rEP2_CTRL; /*! Address offset: 0x148 */ __IO uint32_t rEP2_CTRL; /*! Address offset: 0x148 */
__IO uint32_t rEP3_CTRL; /*! Address offset: 0x14C */ __IO uint32_t rEP3_CTRL; /*! Address offset: 0x14C */
__IO uint32_t rEP4_CTRL; /*! Address offset: 0x150 */ __IO uint32_t rEP4_CTRL; /*! Address offset: 0x150 */
__IO uint32_t RESERVED47; /*! Address offset: 0x154 */ __IO uint32_t RESERVED47; /*! Address offset: 0x154 */
__IO uint32_t RESERVED48; /*! Address offset: 0x158 */ __IO uint32_t RESERVED48; /*! Address offset: 0x158 */
__IO uint32_t RESERVED49; /*! Address offset: 0x15C */ __IO uint32_t RESERVED49; /*! Address offset: 0x15C */
//__IO uint32_t RESERVED50; /*! Address offset: 0x15C */ //__IO uint32_t RESERVED50; /*! Address offset: 0x15C */
//__IO uint32_t rEPn_FIFO[5]; /*! Address offset: 0x160 */ //__IO uint32_t rEPn_FIFO[5]; /*! Address offset: 0x160 */
__IO uint32_t rEP0_FIFO; /*! Address offset: 0x160 */ __IO uint32_t rEP0_FIFO; /*! Address offset: 0x160 */
__IO uint32_t rEP1_FIFO; /*! Address offset: 0x164 */ __IO uint32_t rEP1_FIFO; /*! Address offset: 0x164 */
__IO uint32_t rEP2_FIFO; /*! Address offset: 0x168 */ __IO uint32_t rEP2_FIFO; /*! Address offset: 0x168 */
__IO uint32_t rEP3_FIFO; /*! Address offset: 0x16C */ __IO uint32_t rEP3_FIFO; /*! Address offset: 0x16C */
__IO uint32_t rEP4_FIFO; /*! Address offset: 0x170 */ __IO uint32_t rEP4_FIFO; /*! Address offset: 0x170 */
__IO uint32_t RESERVED51; /*! Address offset: 0x174 */ __IO uint32_t RESERVED51; /*! Address offset: 0x174 */
__IO uint32_t RESERVED52; /*! Address offset: 0x178 */ __IO uint32_t RESERVED52; /*! Address offset: 0x178 */
__IO uint32_t RESERVED53; /*! Address offset: 0x17C */ __IO uint32_t RESERVED53; /*! Address offset: 0x17C */
__IO uint32_t RESERVED54; /*! Address offset: 0x180 */ __IO uint32_t RESERVED54; /*! Address offset: 0x180 */
__IO uint32_t rEP_DMA; /*! Address offset: 0x184 */ __IO uint32_t rEP_DMA; /*! Address offset: 0x184 */
__IO uint32_t rEP_HALT; /*! Address offset: 0x188 */ __IO uint32_t rEP_HALT; /*! Address offset: 0x188 */
__IO uint32_t RESERVED55; /*! Address offset: 0x18C */ __IO uint32_t RESERVED55; /*! Address offset: 0x18C */
__IO uint32_t RESERVED56; /*! Address offset: 0x190 */ __IO uint32_t RESERVED56; /*! Address offset: 0x190 */
__IO uint32_t RESERVED57; /*! Address offset: 0x194 */ __IO uint32_t RESERVED57; /*! Address offset: 0x194 */
__IO uint32_t RESERVED58; /*! Address offset: 0x198 */ __IO uint32_t RESERVED58; /*! Address offset: 0x198 */
__IO uint32_t RESERVED59; /*! Address offset: 0x19C */ __IO uint32_t RESERVED59; /*! Address offset: 0x19C */
__IO uint32_t RESERVED60; /*! Address offset: 0x1A0 */ __IO uint32_t RESERVED60; /*! Address offset: 0x1A0 */
__IO uint32_t RESERVED61; /*! Address offset: 0x1A4 */ __IO uint32_t RESERVED61; /*! Address offset: 0x1A4 */
__IO uint32_t RESERVED62; /*! Address offset: 0x1A8 */ __IO uint32_t RESERVED62; /*! Address offset: 0x1A8 */
__IO uint32_t RESERVED63; /*! Address offset: 0x1AC */ __IO uint32_t RESERVED63; /*! Address offset: 0x1AC */
__IO uint32_t RESERVED64; /*! Address offset: 0x1B0 */ __IO uint32_t RESERVED64; /*! Address offset: 0x1B0 */
__IO uint32_t RESERVED65; /*! Address offset: 0x1B4 */ __IO uint32_t RESERVED65; /*! Address offset: 0x1B4 */
__IO uint32_t RESERVED66; /*! Address offset: 0x1B8 */ __IO uint32_t RESERVED66; /*! Address offset: 0x1B8 */
__IO uint32_t RESERVED67; /*! Address offset: 0x1BC */ __IO uint32_t RESERVED67; /*! Address offset: 0x1BC */
__IO uint32_t rPOWER; /*! Address offset: 0x1C0 */ __IO uint32_t rPOWER; /*! Address offset: 0x1C0 */
} USB_TypeDef; } USB_TypeDef;
typedef struct typedef struct
@ -1120,9 +1120,9 @@ typedef struct
__IO uint32_t RESERVE0;//1C __IO uint32_t RESERVE0;//1C
__IO uint32_t DOUTR;//20 __IO uint32_t DOUTR;//20
__IO uint32_t BRDR;//24 __IO uint32_t BRDR;//24
__IO uint32_t RESERVE1;//28 __IO uint32_t RESERVE1;//28
__IO uint32_t RESERVE2;//2C __IO uint32_t RESERVE2;//2C
__IO uint32_t CFGR3;//30 __IO uint32_t CFGR3;//30
} TK80_TypeDef; } TK80_TypeDef;
@ -1166,29 +1166,29 @@ typedef struct
typedef struct typedef struct
{ {
__IO uint32_t ADDATA; /*!< ADC status register, Address offset: 0x00 */ __IO uint32_t ADDATA; /*!< ADC status register, Address offset: 0x00 */
__IO uint32_t ADCFG; /*!< ADC control register 1, Address offset: 0x04 */ __IO uint32_t ADCFG; /*!< ADC control register 1, Address offset: 0x04 */
__IO uint32_t ADCR; /*!< ADC control register 2, Address offset: 0x08 */ __IO uint32_t ADCR; /*!< ADC control register 2, Address offset: 0x08 */
__IO uint32_t ADCHS; /*!< ADC sample time register 1, Address offset: 0x0C */ __IO uint32_t ADCHS; /*!< ADC sample time register 1, Address offset: 0x0C */
__IO uint32_t ADCMPR; //10 __IO uint32_t ADCMPR; //10
__IO uint32_t ADSTA; __IO uint32_t ADSTA;
__IO uint32_t ADDR0; //18 __IO uint32_t ADDR0; //18
__IO uint32_t ADDR1; __IO uint32_t ADDR1;
__IO uint32_t ADDR2; //20 __IO uint32_t ADDR2; //20
__IO uint32_t ADDR3; __IO uint32_t ADDR3;
__IO uint32_t ADDR4; __IO uint32_t ADDR4;
__IO uint32_t ADDR5; __IO uint32_t ADDR5;
__IO uint32_t ADDR6; //30 __IO uint32_t ADDR6; //30
__IO uint32_t ADDR7; __IO uint32_t ADDR7;
__IO uint32_t ADDR8; __IO uint32_t ADDR8;
__IO uint32_t ADDR9; __IO uint32_t ADDR9;
__IO uint32_t RESERVED0;//40 __IO uint32_t RESERVED0;//40
__IO uint32_t RESERVED1; __IO uint32_t RESERVED1;
__IO uint32_t TPXDR; __IO uint32_t TPXDR;
__IO uint32_t TPYDR; __IO uint32_t TPYDR;
__IO uint32_t TPCR; __IO uint32_t TPCR;
__IO uint32_t TPFR; __IO uint32_t TPFR;
__IO uint32_t TPCSR; __IO uint32_t TPCSR;
} TOUCHPAD_TypeDef; } TOUCHPAD_TypeDef;
@ -1346,7 +1346,7 @@ typedef struct
#define CAN1_PELI ((CAN_Peli_TypeDef *) CAN1_BASE) #define CAN1_PELI ((CAN_Peli_TypeDef *) CAN1_BASE)
#define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define CAN2_PELI ((CAN_Peli_TypeDef *) CAN2_BASE) #define CAN2_PELI ((CAN_Peli_TypeDef *) CAN2_BASE)
#define USB ((USB_TypeDef*) USB_BASE ) #define USB ((USB_TypeDef*) USB_BASE )
#define PWR ((PWR_TypeDef *) PWR_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE)
#define I2S ((SPI_TypeDef *) I2S_BASE) #define I2S ((SPI_TypeDef *) I2S_BASE)
@ -1377,7 +1377,7 @@ typedef struct
#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) #define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
#define LTDC ((LTDCTypeDef *) LTDC_BASE) #define LTDC ((LTDCTypeDef *) LTDC_BASE)
#define TK80 ((TK80_TypeDef *) TK80_BASE) #define TK80 ((TK80_TypeDef *) TK80_BASE)
#define AI_Responder ((AI_Responder_TypeDef*) AI_Responder_BASE) #define AI_Responder ((AI_Responder_TypeDef*) AI_Responder_BASE)
//#define SDRAM_BANK ((DMA_TypeDef *) SDRAM_BANK_BASE) //#define SDRAM_BANK ((DMA_TypeDef *) SDRAM_BANK_BASE)
@ -1543,18 +1543,18 @@ typedef struct
#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
#define RCC_CR_PLLDN ((uint32_t)0xFC000000) /*!< PLLDN[5:0] bits */ #define RCC_CR_PLLDN ((uint32_t)0xFC000000) /*!< PLLDN[5:0] bits */
#define RCC_CR_PLLDN_0 ((uint32_t)0x04000000) /*!< Bit 0 */ #define RCC_CR_PLLDN_0 ((uint32_t)0x04000000) /*!< Bit 0 */
#define RCC_CR_PLLDN_1 ((uint32_t)0x08000000) /*!< Bit 1 */ #define RCC_CR_PLLDN_1 ((uint32_t)0x08000000) /*!< Bit 1 */
#define RCC_CR_PLLDN_2 ((uint32_t)0x10000000) /*!< Bit 2 */ #define RCC_CR_PLLDN_2 ((uint32_t)0x10000000) /*!< Bit 2 */
#define RCC_CR_PLLDN_3 ((uint32_t)0x20000000) /*!< Bit 3 */ #define RCC_CR_PLLDN_3 ((uint32_t)0x20000000) /*!< Bit 3 */
#define RCC_CR_PLLDN_4 ((uint32_t)0x40000000) /*!< Bit 4 */ #define RCC_CR_PLLDN_4 ((uint32_t)0x40000000) /*!< Bit 4 */
#define RCC_CR_PLLDN_5 ((uint32_t)0x80000000) /*!< Bit 5 */ #define RCC_CR_PLLDN_5 ((uint32_t)0x80000000) /*!< Bit 5 */
#define RCC_CR_PLLDM ((uint32_t)0x00700000) /*!< PLLDM[2:0] bits */ #define RCC_CR_PLLDM ((uint32_t)0x00700000) /*!< PLLDM[2:0] bits */
#define RCC_CR_PLLDM_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define RCC_CR_PLLDM_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define RCC_CR_PLLDM_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define RCC_CR_PLLDM_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define RCC_CR_PLLDM_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define RCC_CR_PLLDM_2 ((uint32_t)0x00400000) /*!< Bit 2 */
/******************* Bit definition for RCC_CFGR register *******************/ /******************* Bit definition for RCC_CFGR register *******************/
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
@ -1629,7 +1629,7 @@ typedef struct
/*!< MCO configuration */ /*!< MCO configuration */
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) // #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) //
#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000)
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected */ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected */
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< Internal 48 MHz RC oscillator clock selected */ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< Internal 48 MHz RC oscillator clock selected */
@ -4480,62 +4480,62 @@ typedef struct
/*!<PeliCAN registers */ /*!<PeliCAN registers */
/******************* Bit definition for CAN_MOD register *******************/ /******************* Bit definition for CAN_MOD register *******************/
#define CAN_MOD_RM ((uint16_t)0x0001) #define CAN_MOD_RM ((uint16_t)0x0001)
#define CAN_MOD_LOM ((uint16_t)0x0002) #define CAN_MOD_LOM ((uint16_t)0x0002)
#define CAN_MOD_STM ((uint16_t)0x0004) #define CAN_MOD_STM ((uint16_t)0x0004)
#define CAN_MOD_AFM ((uint16_t)0x0008) #define CAN_MOD_AFM ((uint16_t)0x0008)
#define CAN_MOD_SM ((uint16_t)0x0010) #define CAN_MOD_SM ((uint16_t)0x0010)
/******************* Bit definition for CAN_IER register *******************/ /******************* Bit definition for CAN_IER register *******************/
#define CAN_IER_RIE ((uint16_t)0x0001) #define CAN_IER_RIE ((uint16_t)0x0001)
#define CAN_IER_TIE ((uint16_t)0x0002) #define CAN_IER_TIE ((uint16_t)0x0002)
#define CAN_IER_EIE ((uint16_t)0x0004) #define CAN_IER_EIE ((uint16_t)0x0004)
#define CAN_IER_DOIE ((uint16_t)0x0008) #define CAN_IER_DOIE ((uint16_t)0x0008)
#define CAN_IER_WUIE ((uint16_t)0x0010) #define CAN_IER_WUIE ((uint16_t)0x0010)
#define CAN_IER_EPIE ((uint16_t)0x0020) #define CAN_IER_EPIE ((uint16_t)0x0020)
#define CAN_IER_ALIE ((uint16_t)0x0040) #define CAN_IER_ALIE ((uint16_t)0x0040)
#define CAN_IER_BEIE ((uint16_t)0x0080) #define CAN_IER_BEIE ((uint16_t)0x0080)
/******************* Bit definition for CAN_ALC register *******************/ /******************* Bit definition for CAN_ALC register *******************/
#define CAN_ALC_BITNO ((uint16_t)0x001F) #define CAN_ALC_BITNO ((uint16_t)0x001F)
#define CAN_ALC_BITNO_0 ((uint16_t)0x0001) #define CAN_ALC_BITNO_0 ((uint16_t)0x0001)
#define CAN_ALC_BITNO_1 ((uint16_t)0x0002) #define CAN_ALC_BITNO_1 ((uint16_t)0x0002)
#define CAN_ALC_BITNO_2 ((uint16_t)0x0004) #define CAN_ALC_BITNO_2 ((uint16_t)0x0004)
#define CAN_ALC_BITNO_3 ((uint16_t)0x0008) #define CAN_ALC_BITNO_3 ((uint16_t)0x0008)
#define CAN_ALC_BITNO_4 ((uint16_t)0x0010) #define CAN_ALC_BITNO_4 ((uint16_t)0x0010)
/******************* Bit definition for CAN_ECC register *******************/ /******************* Bit definition for CAN_ECC register *******************/
#define CAN_ECC_DIR ((uint16_t)0x0020) #define CAN_ECC_DIR ((uint16_t)0x0020)
#define CAN_ECC_SEG ((uint16_t)0x001F) #define CAN_ECC_SEG ((uint16_t)0x001F)
#define CAN_ECC_SEG_0 ((uint16_t)0x0001) #define CAN_ECC_SEG_0 ((uint16_t)0x0001)
#define CAN_ECC_SEG_1 ((uint16_t)0x0002) #define CAN_ECC_SEG_1 ((uint16_t)0x0002)
#define CAN_ECC_SEG_2 ((uint16_t)0x0004) #define CAN_ECC_SEG_2 ((uint16_t)0x0004)
#define CAN_ECC_SEG_3 ((uint16_t)0x0008) #define CAN_ECC_SEG_3 ((uint16_t)0x0008)
#define CAN_ECC_SEG_4 ((uint16_t)0x0010) #define CAN_ECC_SEG_4 ((uint16_t)0x0010)
#define CAN_ECC_ERRC ((uint16_t)0x00C0) #define CAN_ECC_ERRC ((uint16_t)0x00C0)
#define CAN_ECC_ERRC_0 ((uint16_t)0x0040) #define CAN_ECC_ERRC_0 ((uint16_t)0x0040)
#define CAN_ECC_ERRC_1 ((uint16_t)0x0080) #define CAN_ECC_ERRC_1 ((uint16_t)0x0080)
/******************* Bit definition for CAN_EWLR register *******************/ /******************* Bit definition for CAN_EWLR register *******************/
#define CAN_EWLR_EWL ((uint16_t)0x00FF) #define CAN_EWLR_EWL ((uint16_t)0x00FF)
/******************* Bit definition for CAN_RXERR register *******************/ /******************* Bit definition for CAN_RXERR register *******************/
#define CAN_RXERR_RXERR ((uint16_t)0x00FF) #define CAN_RXERR_RXERR ((uint16_t)0x00FF)
/******************* Bit definition for CAN_TXERR register *******************/ /******************* Bit definition for CAN_TXERR register *******************/
#define CAN_TXERR_TXERR ((uint16_t)0x00FF) #define CAN_TXERR_TXERR ((uint16_t)0x00FF)
/******************* Bit definition for CAN_FF register *******************/ /******************* Bit definition for CAN_FF register *******************/
#define CAN_FF_RTR ((uint16_t)0x0040) #define CAN_FF_RTR ((uint16_t)0x0040)
#define CAN_FF_FF ((uint16_t)0x0080) #define CAN_FF_FF ((uint16_t)0x0080)
#define CAN_FF_DLC ((uint16_t)0x000F) #define CAN_FF_DLC ((uint16_t)0x000F)
#define CAN_FF_DLC_0 ((uint16_t)0x0001) #define CAN_FF_DLC_0 ((uint16_t)0x0001)
#define CAN_FF_DLC_1 ((uint16_t)0x0002) #define CAN_FF_DLC_1 ((uint16_t)0x0002)
#define CAN_FF_DLC_2 ((uint16_t)0x0004) #define CAN_FF_DLC_2 ((uint16_t)0x0004)
#define CAN_FF_DLC_3 ((uint16_t)0x0008) #define CAN_FF_DLC_3 ((uint16_t)0x0008)
/******************* Bit definition for CAN_ACR0 register *******************/ /******************* Bit definition for CAN_ACR0 register *******************/
#define CAN_ACR0_AC ((uint16_t)0x00FF) #define CAN_ACR0_AC ((uint16_t)0x00FF)

34
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_adc.h
View File

@ -95,14 +95,14 @@ typedef struct
* @brief for ADC1, ADC2 * @brief for ADC1, ADC2
*/ */
#define ADC_PCLK2_PRESCARE_2 ((uint32_t)0x00000000) #define ADC_PCLK2_PRESCARE_2 ((uint32_t)0x00000000)
#define ADC_PCLK2_PRESCARE_4 ((uint32_t)0x00000010) #define ADC_PCLK2_PRESCARE_4 ((uint32_t)0x00000010)
#define ADC_PCLK2_PRESCARE_6 ((uint32_t)0x00000020) #define ADC_PCLK2_PRESCARE_6 ((uint32_t)0x00000020)
#define ADC_PCLK2_PRESCARE_8 ((uint32_t)0x00000030) #define ADC_PCLK2_PRESCARE_8 ((uint32_t)0x00000030)
#define ADC_PCLK2_PRESCARE_10 ((uint32_t)0x00000040) #define ADC_PCLK2_PRESCARE_10 ((uint32_t)0x00000040)
#define ADC_PCLK2_PRESCARE_12 ((uint32_t)0x00000050) #define ADC_PCLK2_PRESCARE_12 ((uint32_t)0x00000050)
#define ADC_PCLK2_PRESCARE_14 ((uint32_t)0x00000060) #define ADC_PCLK2_PRESCARE_14 ((uint32_t)0x00000060)
#define ADC_PCLK2_PRESCARE_16 ((uint32_t)0x00000070) #define ADC_PCLK2_PRESCARE_16 ((uint32_t)0x00000070)
@ -133,14 +133,14 @@ typedef struct
* @brief for ADC1 * @brief for ADC1
*/ */
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00000010) #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00000010)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00000020) #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00000020)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00000030) #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00000030)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00000040) #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00000040)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x00000050) #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x00000050)
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000060) #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000060)
#define ADC_ExternalTrigConv_EXTI_11 ((uint32_t)0x00000070) #define ADC_ExternalTrigConv_EXTI_11 ((uint32_t)0x00000070)
/** /**
* @brief for ADC2 * @brief for ADC2
@ -202,7 +202,7 @@ typedef struct
#define ADC_Channel_6 ((uint8_t)0x06) #define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07) #define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08) #define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_All ((uint8_t)0x0f) #define ADC_Channel_All ((uint8_t)0x0f)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \

64
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_can.h
View File

@ -66,13 +66,13 @@
*/ */
#define CAN_BASICMode ((uint32_t)0x0) #define CAN_BASICMode ((uint32_t)0x0)
#define CAN_PELIMode ((uint32_t)0x80) #define CAN_PELIMode ((uint32_t)0x80)
#define CAN_WorkMode ((uint32_t)0x80) #define CAN_WorkMode ((uint32_t)0x80)
#define CAN_ResetMode ((uint32_t)0x1) #define CAN_ResetMode ((uint32_t)0x1)
#define CAN_ListenOnlyMode ((uint32_t)0x2) #define CAN_ListenOnlyMode ((uint32_t)0x2)
#define CAN_SeftTestMode ((uint32_t)0x4) #define CAN_SeftTestMode ((uint32_t)0x4)
#define CAN_FilterMode_Singal ((uint32_t)0x8) #define CAN_FilterMode_Singal ((uint32_t)0x8)
#define CAN_FilterMode_Double ((uint32_t)0xf7) #define CAN_FilterMode_Double ((uint32_t)0xf7)
#define CAN_SleepMode ((uint32_t)0x10) #define CAN_SleepMode ((uint32_t)0x10)
/** /**
* @} * @}
@ -81,10 +81,10 @@
/** /**
* @brief parasmeter of BASIC CAN interrupt * @brief parasmeter of BASIC CAN interrupt
*/ */
#define CAN_IT_RIE ((uint32_t)0x2) #define CAN_IT_RIE ((uint32_t)0x2)
#define CAN_IT_TIE ((uint32_t)0x4) #define CAN_IT_TIE ((uint32_t)0x4)
#define CAN_IT_EIE ((uint32_t)0x8) #define CAN_IT_EIE ((uint32_t)0x8)
#define CAN_IT_OIE ((uint32_t)0x10) #define CAN_IT_OIE ((uint32_t)0x10)
/** /**
* @} * @}
@ -93,15 +93,15 @@
/** /**
* @brief parasmeter of PELI CAN interrupt * @brief parasmeter of PELI CAN interrupt
*/ */
#define CAN_IT_RI ((uint32_t)0x1) #define CAN_IT_RI ((uint32_t)0x1)
#define CAN_IT_TI ((uint32_t)0x2) #define CAN_IT_TI ((uint32_t)0x2)
#define CAN_IT_EI ((uint32_t)0x4) #define CAN_IT_EI ((uint32_t)0x4)
#define CAN_IT_DOI ((uint32_t)0x8) #define CAN_IT_DOI ((uint32_t)0x8)
#define CAN_IT_WUI ((uint32_t)0x10) #define CAN_IT_WUI ((uint32_t)0x10)
#define CAN_IT_EPI ((uint32_t)0x20) #define CAN_IT_EPI ((uint32_t)0x20)
#define CAN_IT_ALI ((uint32_t)0x40) #define CAN_IT_ALI ((uint32_t)0x40)
#define CAN_IT_BEI ((uint32_t)0x80) #define CAN_IT_BEI ((uint32_t)0x80)
#define CAN_IT_ALL ((uint32_t)0xff) #define CAN_IT_ALL ((uint32_t)0xff)
/** /**
* @} * @}
@ -110,14 +110,14 @@
/** /**
* @brief parasmeter of CAN Status * @brief parasmeter of CAN Status
*/ */
#define CAN_STATUS_RBS ((uint32_t)0x1) #define CAN_STATUS_RBS ((uint32_t)0x1)
#define CAN_STATUS_DOS ((uint32_t)0x2) #define CAN_STATUS_DOS ((uint32_t)0x2)
#define CAN_STATUS_TBS ((uint32_t)0x4) #define CAN_STATUS_TBS ((uint32_t)0x4)
#define CAN_STATUS_TCS ((uint32_t)0x8) #define CAN_STATUS_TCS ((uint32_t)0x8)
#define CAN_STATUS_RS ((uint32_t)0x10) #define CAN_STATUS_RS ((uint32_t)0x10)
#define CAN_STATUS_TS ((uint32_t)0x20) #define CAN_STATUS_TS ((uint32_t)0x20)
#define CAN_STATUS_ES ((uint32_t)0x40) #define CAN_STATUS_ES ((uint32_t)0x40)
#define CAN_STATUS_BS ((uint32_t)0x80) #define CAN_STATUS_BS ((uint32_t)0x80)
/** /**
* @} * @}
@ -126,10 +126,10 @@
/** /**
* @brief parasmeter of CAN Command register * @brief parasmeter of CAN Command register
*/ */
#define CAN_TR 0x1 #define CAN_TR 0x1
#define CAN_AT 0x2 #define CAN_AT 0x2
#define CAN_RRB 0x4 #define CAN_RRB 0x4
#define CAN_CDO 0x8 #define CAN_CDO 0x8
/** /**
* @} * @}

12
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_gpio.h
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@ -216,16 +216,16 @@ typedef enum
#define GPIO_AF_MCO_SW ((uint8_t)0x00) /* MC0, SWDIO,SWCLK */ #define GPIO_AF_MCO_SW ((uint8_t)0x00) /* MC0, SWDIO,SWCLK */
#define GPIO_AF_TIM_1_2 ((uint8_t)0x01) /* TIM 1/2 */ #define GPIO_AF_TIM_1_2 ((uint8_t)0x01) /* TIM 1/2 */
#define GPIO_AF_TIM_34567 ((uint8_t)0x02) /* TIM 3/4/5/6/7 */ #define GPIO_AF_TIM_34567 ((uint8_t)0x02) /* TIM 3/4/5/6/7 */
#define GPIO_AF_I2S ((uint8_t)0x03) #define GPIO_AF_I2S ((uint8_t)0x03)
#define GPIO_AF_I2C ((uint8_t)0x04) /* I2C 1/2/3 */ #define GPIO_AF_I2C ((uint8_t)0x04) /* I2C 1/2/3 */
#define GPIO_AF_SPI ((uint8_t)0x05) /* SPI 1/2/3/4 */ #define GPIO_AF_SPI ((uint8_t)0x05) /* SPI 1/2/3/4 */
#define GPIO_AF_QSPI ((uint8_t)0x06) #define GPIO_AF_QSPI ((uint8_t)0x06)
#define GPIO_AF_UART_2345 ((uint8_t)0x07) /* UART 2/3/4/5 */ #define GPIO_AF_UART_2345 ((uint8_t)0x07) /* UART 2/3/4/5 */
#define GPIO_AF_UART_1 ((uint8_t)0x08) #define GPIO_AF_UART_1 ((uint8_t)0x08)
#define GPIO_AF_CAN ((uint8_t)0x09) /* CAN 1/2 */ #define GPIO_AF_CAN ((uint8_t)0x09) /* CAN 1/2 */
#define GPIO_AF_USB ((uint8_t)0x0A) #define GPIO_AF_USB ((uint8_t)0x0A)
#define GPIO_AF_GPIO ((uint8_t)0x0B) /* Normal GPIO */ #define GPIO_AF_GPIO ((uint8_t)0x0B) /* Normal GPIO */
#define GPIO_AF_TK80_SDIO ((uint8_t)0x0C) /* TK80 SDIO 1/2 */ #define GPIO_AF_TK80_SDIO ((uint8_t)0x0C) /* TK80 SDIO 1/2 */
#define GPIO_AF_Touchpad ((uint8_t)0x0D) #define GPIO_AF_Touchpad ((uint8_t)0x0D)
#define GPIO_AF_LTDC ((uint8_t)0x0E) /* RGB_LTDC AF */ #define GPIO_AF_LTDC ((uint8_t)0x0E) /* RGB_LTDC AF */

114
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_i2c.h
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@ -75,23 +75,23 @@ typedef struct
* @{ * @{
*/ */
#define TX_EMPTY_CTRL (0x0001<<8) #define TX_EMPTY_CTRL (0x0001<<8)
#define IC_SLAVE_DISABLE (0x0001<<6) #define IC_SLAVE_DISABLE (0x0001<<6)
#define IC_SLAVE_ENABLE (0x0000<<6) #define IC_SLAVE_ENABLE (0x0000<<6)
#define IC_RESTART_EN (0x0001<<5) #define IC_RESTART_EN (0x0001<<5)
#define IC_7BITADDR_MASTER (0x0000<<4) #define IC_7BITADDR_MASTER (0x0000<<4)
#define IC_7BITADDR_SLAVE (0x0000<<3) #define IC_7BITADDR_SLAVE (0x0000<<3)
#define I2C_Speed_STANDARD ((uint16_t)0x0002) #define I2C_Speed_STANDARD ((uint16_t)0x0002)
#define I2C_Speed_FAST ((uint16_t)0x0004) #define I2C_Speed_FAST ((uint16_t)0x0004)
#define I2C_Mode_MASTER ((uint16_t)0x0001) #define I2C_Mode_MASTER ((uint16_t)0x0001)
#define I2C_Mode_SLAVE ((uint16_t)0x0000) #define I2C_Mode_SLAVE ((uint16_t)0x0000)
#define TDMAE_SET ((uint16_t)0x0002) #define TDMAE_SET ((uint16_t)0x0002)
#define RDMAE_SET ((uint16_t)0x0001) #define RDMAE_SET ((uint16_t)0x0001)
#define CMD_READ ((uint16_t)0x0100) #define CMD_READ ((uint16_t)0x0100)
#define CMD_WRITE ((uint16_t)0x0000) #define CMD_WRITE ((uint16_t)0x0000)
@ -144,18 +144,18 @@ typedef struct
* @{ * @{
*/ */
#define I2C_IT_RX_UNDER ((uint16_t)0x0001) #define I2C_IT_RX_UNDER ((uint16_t)0x0001)
#define I2C_IT_RX_OVER ((uint16_t)0x0002) #define I2C_IT_RX_OVER ((uint16_t)0x0002)
#define I2C_IT_RX_FULL ((uint16_t)0x0004) #define I2C_IT_RX_FULL ((uint16_t)0x0004)
#define I2C_IT_TX_OVER ((uint16_t)0x0008) #define I2C_IT_TX_OVER ((uint16_t)0x0008)
#define I2C_IT_TX_EMPTY ((uint16_t)0x0010) #define I2C_IT_TX_EMPTY ((uint16_t)0x0010)
#define I2C_IT_RD_REQ ((uint16_t)0x0020) #define I2C_IT_RD_REQ ((uint16_t)0x0020)
#define I2C_IT_TX_ABRT ((uint16_t)0x0040) #define I2C_IT_TX_ABRT ((uint16_t)0x0040)
#define I2C_IT_RX_DONE ((uint16_t)0x0080) #define I2C_IT_RX_DONE ((uint16_t)0x0080)
#define I2C_IT_ACTIVITY ((uint16_t)0x0100) #define I2C_IT_ACTIVITY ((uint16_t)0x0100)
#define I2C_IT_STOP_DET ((uint16_t)0x0200) #define I2C_IT_STOP_DET ((uint16_t)0x0200)
#define I2C_IT_START_DET ((uint16_t)0x0400) #define I2C_IT_START_DET ((uint16_t)0x0400)
#define I2C_IT_GEN_CALL ((uint16_t)0x0800) #define I2C_IT_GEN_CALL ((uint16_t)0x0800)
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0xF000) == 0x00) && ((IT) != (uint16_t)0x00)) #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0xF000) == 0x00) && ((IT) != (uint16_t)0x00))
@ -175,18 +175,18 @@ typedef struct
#define I2C_FLAG_RX_UNDER ((uint16_t)0x0001) #define I2C_FLAG_RX_UNDER ((uint16_t)0x0001)
#define I2C_FLAG_RX_OVER ((uint16_t)0x0002) #define I2C_FLAG_RX_OVER ((uint16_t)0x0002)
#define I2C_FLAG_RX_FULL ((uint16_t)0x0004) #define I2C_FLAG_RX_FULL ((uint16_t)0x0004)
#define I2C_FLAG_TX_OVER ((uint16_t)0x0008) #define I2C_FLAG_TX_OVER ((uint16_t)0x0008)
#define I2C_FLAG_TX_EMPTY ((uint16_t)0x0010) #define I2C_FLAG_TX_EMPTY ((uint16_t)0x0010)
#define I2C_FLAG_RD_REQ ((uint16_t)0x0020) #define I2C_FLAG_RD_REQ ((uint16_t)0x0020)
#define I2C_FLAG_TX_ABRT ((uint16_t)0x0040) #define I2C_FLAG_TX_ABRT ((uint16_t)0x0040)
#define I2C_FLAG_RX_DONE ((uint16_t)0x0080) #define I2C_FLAG_RX_DONE ((uint16_t)0x0080)
#define I2C_FLAG_ACTIVITY ((uint16_t)0x0100) #define I2C_FLAG_ACTIVITY ((uint16_t)0x0100)
#define I2C_FLAG_STOP_DET ((uint16_t)0x0200) #define I2C_FLAG_STOP_DET ((uint16_t)0x0200)
#define I2C_FLAG_START_DET ((uint16_t)0x0400) #define I2C_FLAG_START_DET ((uint16_t)0x0400)
#define I2C_FLAG_GEN_CALL ((uint16_t)0x0800) #define I2C_FLAG_GEN_CALL ((uint16_t)0x0800)
@ -207,13 +207,13 @@ typedef struct
* @{ * @{
*/ */
#define I2C_STATUS_FLAG_ACTIVITY ((uint16_t)0x0001) #define I2C_STATUS_FLAG_ACTIVITY ((uint16_t)0x0001)
#define I2C_STATUS_FLAG_TFNF ((uint16_t)0x0002) #define I2C_STATUS_FLAG_TFNF ((uint16_t)0x0002)
#define I2C_STATUS_FLAG_TFE ((uint16_t)0x0004) #define I2C_STATUS_FLAG_TFE ((uint16_t)0x0004)
#define I2C_STATUS_FLAG_RFNE ((uint16_t)0x0008) #define I2C_STATUS_FLAG_RFNE ((uint16_t)0x0008)
#define I2C_STATUS_FLAG_RFF ((uint16_t)0x0010) #define I2C_STATUS_FLAG_RFF ((uint16_t)0x0010)
#define I2C_STATUS_FLAG_M_ACTIVITY ((uint16_t)0x0020) #define I2C_STATUS_FLAG_M_ACTIVITY ((uint16_t)0x0020)
#define I2C_STATUS_FLAG_S_ACTIVITY ((uint16_t)0x0040) #define I2C_STATUS_FLAG_S_ACTIVITY ((uint16_t)0x0040)
/** /**
@ -225,18 +225,18 @@ typedef struct
*/ */
#define I2C_EVENT_RX_UNDER ((uint32_t)0x0001) #define I2C_EVENT_RX_UNDER ((uint32_t)0x0001)
#define I2C_EVENT_RX_OVER ((uint32_t)0x0002) #define I2C_EVENT_RX_OVER ((uint32_t)0x0002)
#define I2C_EVENT_RX_FULL ((uint32_t)0x0004) #define I2C_EVENT_RX_FULL ((uint32_t)0x0004)
#define I2C_EVENT_TX_OVER ((uint32_t)0x0008) #define I2C_EVENT_TX_OVER ((uint32_t)0x0008)
#define I2C_EVENT_TX_EMPTY ((uint32_t)0x0010) #define I2C_EVENT_TX_EMPTY ((uint32_t)0x0010)
#define I2C_EVENT_RD_REQ ((uint32_t)0x0020) #define I2C_EVENT_RD_REQ ((uint32_t)0x0020)
#define I2C_EVENT_TX_ABRT ((uint32_t)0x0040) #define I2C_EVENT_TX_ABRT ((uint32_t)0x0040)
#define I2C_EVENT_RX_DONE ((uint32_t)0x0080) #define I2C_EVENT_RX_DONE ((uint32_t)0x0080)
#define I2C_EVENT_ACTIVITY ((uint32_t)0x0100) #define I2C_EVENT_ACTIVITY ((uint32_t)0x0100)
#define I2C_EVENT_STOP_DET ((uint32_t)0x0200) #define I2C_EVENT_STOP_DET ((uint32_t)0x0200)
#define I2C_EVENT_START_DET ((uint32_t)0x0400) #define I2C_EVENT_START_DET ((uint32_t)0x0400)
#define I2C_EVENT_GEN_CALL ((uint32_t)0x0800) #define I2C_EVENT_GEN_CALL ((uint32_t)0x0800)
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_RX_UNDER) || \ #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_RX_UNDER) || \

10
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_spi.h
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@ -209,7 +209,7 @@ typedef struct
* @{ * @{
*/ */
#define SPI_DMAReq_EN ((uint16_t)0x0200) #define SPI_DMAReq_EN ((uint16_t)0x0200)
#define IS_SPI_DMAREQ(DMAREQ) ((DMAREQ) == SPI_DMAReq_EN) #define IS_SPI_DMAREQ(DMAREQ) ((DMAREQ) == SPI_DMAReq_EN)
@ -220,8 +220,8 @@ typedef struct
/** @defgroup SPI TX Fifo and RX Fifo trigger level /** @defgroup SPI TX Fifo and RX Fifo trigger level
* @{ * @{
*/ */
#define SPI_TXTLF ((uint16_t)0x0080) #define SPI_TXTLF ((uint16_t)0x0080)
#define SPI_RXTLF ((uint16_t)0x0020) #define SPI_RXTLF ((uint16_t)0x0020)
#define IS_SPI_FIFOTRIGGER(TRIGGER) (((TRIGGER) == SPI_TXTLF) && ((TRIGGER) == SPI_RXTLF)) #define IS_SPI_FIFOTRIGGER(TRIGGER) (((TRIGGER) == SPI_TXTLF) && ((TRIGGER) == SPI_RXTLF))
@ -261,8 +261,8 @@ typedef struct
#define SPI_Direction_Rx ((uint16_t)0x0010) #define SPI_Direction_Rx ((uint16_t)0x0010)
#define SPI_Direction_Tx ((uint16_t)0x0008) #define SPI_Direction_Tx ((uint16_t)0x0008)
#define SPI_Disable_Tx ((uint16_t)0xfff7) #define SPI_Disable_Tx ((uint16_t)0xfff7)
#define SPI_Disable_Rx ((uint16_t)0xffef) #define SPI_Disable_Rx ((uint16_t)0xffef)
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
((DIRECTION) == SPI_Direction_Tx) || \ ((DIRECTION) == SPI_Direction_Tx) || \
((DIRECTION) == SPI_Disable_Tx) || \ ((DIRECTION) == SPI_Disable_Tx) || \

2
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_tim.h
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@ -203,7 +203,7 @@ typedef struct
((MODE) == TIM_OCMode_Inactive) || \ ((MODE) == TIM_OCMode_Inactive) || \
((MODE) == TIM_OCMode_Toggle)|| \ ((MODE) == TIM_OCMode_Toggle)|| \
((MODE) == TIM_OCMode_PWM1) || \ ((MODE) == TIM_OCMode_PWM1) || \
((MODE) == TIM_OCMode_PWM2) || \ ((MODE) == TIM_OCMode_PWM2) || \
((MODE) == TIM_ForcedAction_Active) || \ ((MODE) == TIM_ForcedAction_Active) || \
((MODE) == TIM_ForcedAction_InActive)) ((MODE) == TIM_ForcedAction_InActive))
/** /**

918
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_can.c
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File diff suppressed because it is too large Load Diff

2
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_dma_bak.c
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@ -480,7 +480,7 @@ ITStatus DMA_GetITStatus(uint32_t DMA_IT)
} }
/** /**
* @brief Clears the DMAy Channelx’s interrupt pending bits. * @brief Clears the DMAy Channelx’s interrupt pending bits.
* @param DMA_IT: specifies the DMA interrupt pending bit to clear. * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of * This parameter can be any combination (for the same DMA) of
* the following values: * the following values:

84
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_gpio.c
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@ -220,10 +220,10 @@ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
} }
GPIOx->CRH = tmpreg; GPIOx->CRH = tmpreg;
} }
/*---------------------------- GPIOE_CRH_EXT Configuration ------------------------*/ /*---------------------------- GPIOE_CRH_EXT Configuration ------------------------*/
if(GPIO_InitStruct->GPIO_Pin>>16) //说明是GPIOE的16~23位 if(GPIO_InitStruct->GPIO_Pin>>16) //说明是GPIOE的16~23位
{ {
GPIO_InitStruct->GPIO_Pin = GPIO_InitStruct->GPIO_Pin>>16; GPIO_InitStruct->GPIO_Pin = GPIO_InitStruct->GPIO_Pin>>16;
tmpreg = GPIOE->CRH_EXT; tmpreg = GPIOE->CRH_EXT;
for (pinpos = 0x00; pinpos < 0x08; pinpos++) for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{ {
@ -362,7 +362,7 @@ void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin)
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN(GPIO_Pin));
if(GPIO_Pin>GPIO_Pin_15)GPIOE->BSRR_EXT=GPIO_Pin>>16; if(GPIO_Pin>GPIO_Pin_15)GPIOE->BSRR_EXT=GPIO_Pin>>16;
else else
GPIOx->BSRR = GPIO_Pin; GPIOx->BSRR = GPIO_Pin;
} }
@ -486,51 +486,51 @@ TIM1 6_CH1, TIM17_CH1
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, uint8_t GPIO_AF) void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, uint8_t GPIO_AF)
{ {
uint32_t temp; uint32_t temp;
unsigned char i; unsigned char i;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
assert_param(IS_GPIO_AF(GPIO_AF)); assert_param(IS_GPIO_AF(GPIO_AF));
if(GPIO_Pin>>16) //说明是GPIOE的16~23位 if(GPIO_Pin>>16) //说明是GPIOE的16~23位
{ {
temp = GPIO_Pin>>16; temp = GPIO_Pin>>16;
for(i=0;i<8;i++) for(i=0;i<8;i++)
{ {
if(temp&0x01) if(temp&0x01)
{ {
GPIOE->AFRH_EXT &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2 GPIOE->AFRH_EXT &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOE->AFRH_EXT |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2))); GPIOE->AFRH_EXT |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
} }
temp = temp>>1; temp = temp>>1;
} }
} }
if(GPIO_Pin&0XFF00) //说明是GPIOE的8~15位 if(GPIO_Pin&0XFF00) //说明是GPIOE的8~15位
{ {
temp = GPIO_Pin>>8; temp = GPIO_Pin>>8;
for(i=0;i<8;i++) for(i=0;i<8;i++)
{ {
if(temp&0x01) if(temp&0x01)
{ {
GPIOx->AFRH &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2 GPIOx->AFRH &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOx->AFRH |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2))); GPIOx->AFRH |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
} }
temp = temp>>1; temp = temp>>1;
} }
} }
if(GPIO_Pin&0XFF) //说明是GPIOE的0~7位 if(GPIO_Pin&0XFF) //说明是GPIOE的0~7位
{ {
for(i=0;i<8;i++) for(i=0;i<8;i++)
{ {
if(temp&0x01) if(temp&0x01)
{ {
GPIOx->AFRL &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2 GPIOx->AFRL &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOx->AFRL |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2))); GPIOx->AFRL |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
} }
temp = temp>>1; temp = temp>>1;
} }
} }
} }
/** /**

100
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_i2c.c
View File

@ -47,7 +47,7 @@
/*I2c Enable disable*/ /*I2c Enable disable*/
#define IC_ENABLE_Reset ((uint16_t)0xFFFE) #define IC_ENABLE_Reset ((uint16_t)0xFFFE)
#define IC_ENABLE_Set ((uint16_t)0x0001) #define IC_ENABLE_Set ((uint16_t)0x0001)
#define IC_CON_RESET ((uint16_t)0xFE8A) #define IC_CON_RESET ((uint16_t)0xFE8A)
#define INTR_MASK ((uint16_t)0xC000) #define INTR_MASK ((uint16_t)0xC000)
/*I2c DMA reset*/ /*I2c DMA reset*/
@ -173,7 +173,7 @@ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
i2cPeriod = 1000000000/I2C_InitStruct->I2C_ClockSpeed; //ns unit i2cPeriod = 1000000000/I2C_InitStruct->I2C_ClockSpeed; //ns unit
tmpreg = 0; tmpreg = 0;
/*Get the I2Cx IC_CON value */ /*Get the I2Cx IC_CON value */
tmpreg = I2Cx->IC_CON; tmpreg = I2Cx->IC_CON;
/*Clear TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/ /*Clear TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/
tmpreg &= IC_CON_RESET; tmpreg &= IC_CON_RESET;
@ -182,16 +182,16 @@ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
if (I2C_InitStruct->I2C_ClockSpeed <= 100000) if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
{ {
minSclLowTime = i2cPeriod/pclk1Period; minSclLowTime = i2cPeriod/pclk1Period;
I2Cx->IC_SS_SCL_LCNT = minSclLowTime/2; I2Cx->IC_SS_SCL_LCNT = minSclLowTime/2;
I2Cx->IC_SS_SCL_HCNT = minSclLowTime - I2Cx->IC_SS_SCL_LCNT; I2Cx->IC_SS_SCL_HCNT = minSclLowTime - I2Cx->IC_SS_SCL_LCNT;
I2C_InitStruct->I2C_Speed = I2C_Speed_STANDARD; I2C_InitStruct->I2C_Speed = I2C_Speed_STANDARD;
} }
else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
{ {
minSclLowTime = i2cPeriod/pclk1Period; minSclLowTime = i2cPeriod/pclk1Period;
I2Cx->IC_FS_SCL_LCNT = minSclLowTime/2; I2Cx->IC_FS_SCL_LCNT = minSclLowTime/2;
I2Cx->IC_FS_SCL_HCNT = minSclLowTime - I2Cx->IC_FS_SCL_LCNT; I2Cx->IC_FS_SCL_HCNT = minSclLowTime - I2Cx->IC_FS_SCL_LCNT;
I2C_InitStruct->I2C_Speed = I2C_Speed_FAST; I2C_InitStruct->I2C_Speed = I2C_Speed_FAST;
} }
@ -261,10 +261,10 @@ void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
/** /**
* @brief Enables or disables the specified I2C DMA requests. * @brief Enables or disables the specified I2C DMA requests.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param DMA_Direcction : TDMAE_SET,RDMAE_SET * @param DMA_Direcction : TDMAE_SET,RDMAE_SET
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg TDMAE_SET :DMA TX set * @arg TDMAE_SET :DMA TX set
* @arg RDMAE_SET :DMA RX set * @arg RDMAE_SET :DMA RX set
* @param NewState: new state of the I2C DMA transfer. * @param NewState: new state of the I2C DMA transfer.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
* @retval : None * @retval : None
@ -424,14 +424,14 @@ void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt mask * @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt mask
* @arg I2C_IT_RX_FULL : Rx buffer full interrupt mask * @arg I2C_IT_RX_FULL : Rx buffer full interrupt mask
* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt mask * @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt mask
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt mask * @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt mask
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt mask * @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt mask
* @arg I2C_IT_TX_ABRT : TX error interrupt mask(Master mode) * @arg I2C_IT_TX_ABRT : TX error interrupt mask(Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt mask(slave mode) * @arg I2C_IT_RX_DONE : Master not ack interrupt mask(slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt mask * @arg I2C_IT_ACTIVITY : I2C activity interrupt mask
* @arg I2C_IT_STOP_DET : stop condition interrupt mask * @arg I2C_IT_STOP_DET : stop condition interrupt mask
* @arg I2C_IT_START_DET : start condition interrupt mask * @arg I2C_IT_START_DET : start condition interrupt mask
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt mask * @arg I2C_IT_GEN_CALL : a general call address and ack interrupt mask
* @param NewState: new state of the specified I2C interrupts. * @param NewState: new state of the specified I2C interrupts.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
* @retval : None * @retval : None
@ -566,14 +566,14 @@ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
* @arg I2C_EVENT_RX_OVER : RX Buffer Overrun event * @arg I2C_EVENT_RX_OVER : RX Buffer Overrun event
* @arg I2C_EVENTT_RX_FULL : Rx buffer full event * @arg I2C_EVENTT_RX_FULL : Rx buffer full event
* @arg I2C_EVENT_TX_OVER : TX Buffer Overrun event * @arg I2C_EVENT_TX_OVER : TX Buffer Overrun event
* @arg I2C_EVENT_TX_EMPTY : TX_FIFO empty event * @arg I2C_EVENT_TX_EMPTY : TX_FIFO empty event
* @arg I2C_EVENT_RD_REQ : I2C work as slave or master event * @arg I2C_EVENT_RD_REQ : I2C work as slave or master event
* @arg I2C_EVENT_TX_ABRT : TX error event(Master mode) * @arg I2C_EVENT_TX_ABRT : TX error event(Master mode)
* @arg I2C_EVENT_RX_DONE : Master not ack event(slave mode) * @arg I2C_EVENT_RX_DONE : Master not ack event(slave mode)
* @arg I2C_EVENT_ACTIVITY : I2C activity event * @arg I2C_EVENT_ACTIVITY : I2C activity event
* @arg I2C_EVENT_STOP_DET : stop condition event * @arg I2C_EVENT_STOP_DET : stop condition event
* @arg I2C_EVENT_START_DET : start condition event * @arg I2C_EVENT_START_DET : start condition event
* @arg I2C_EVENT_GEN_CALL : a general call address and ack event * @arg I2C_EVENT_GEN_CALL : a general call address and ack event
* - SUCCESS: Last event is equal to the I2C_EVENT * - SUCCESS: Last event is equal to the I2C_EVENT
* - ERROR: Last event is different from the I2C_EVENT * - ERROR: Last event is different from the I2C_EVENT
*/ */
@ -624,9 +624,9 @@ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
* @arg I2C_FLAG_RX_FULL : Rx buffer full flag * @arg I2C_FLAG_RX_FULL : Rx buffer full flag
* @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag * @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag
* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag * @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag
* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag * @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode) * @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode) * @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
* @arg I2C_FLAG_ACTIVITY: I2C activity flag * @arg I2C_FLAG_ACTIVITY: I2C activity flag
* @arg I2C_FLAG_STOP_DET: stop condition flag * @arg I2C_FLAG_STOP_DET: stop condition flag
* @arg I2C_FLAG_START_DET: start condition flag * @arg I2C_FLAG_START_DET: start condition flag
@ -673,9 +673,9 @@ FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
* @arg I2C_FLAG_RX_FULL : Rx buffer full flag * @arg I2C_FLAG_RX_FULL : Rx buffer full flag
* @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag * @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag
* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag * @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag
* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag * @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode) * @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode) * @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
* @arg I2C_FLAG_ACTIVITY: I2C activity flag * @arg I2C_FLAG_ACTIVITY: I2C activity flag
* @arg I2C_FLAG_STOP_DET: stop condition flag * @arg I2C_FLAG_STOP_DET: stop condition flag
* @arg I2C_FLAG_START_DET: start condition flag * @arg I2C_FLAG_START_DET: start condition flag
@ -772,14 +772,14 @@ void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt * @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt
* @arg I2C_IT_RX_FULL : Rx buffer full interrupt * @arg I2C_IT_RX_FULL : Rx buffer full interrupt
* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt * @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt * @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt * @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode) * @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode) * @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt * @arg I2C_IT_ACTIVITY : I2C activity interrupt
* @arg I2C_IT_STOP_DET : stop condition interrupt * @arg I2C_IT_STOP_DET : stop condition interrupt
* @arg I2C_IT_START_DET : start condition interrupt * @arg I2C_IT_START_DET : start condition interrupt
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt * @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
* @retval : The new state of I2C_IT (SET or RESET). * @retval : The new state of I2C_IT (SET or RESET).
*/ */
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
@ -814,14 +814,14 @@ ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt * @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt
* @arg I2C_IT_RX_FULL : Rx buffer full interrupt * @arg I2C_IT_RX_FULL : Rx buffer full interrupt
* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt * @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt * @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt * @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode) * @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode) * @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt * @arg I2C_IT_ACTIVITY : I2C activity interrupt
* @arg I2C_IT_STOP_DET : stop condition interrupt * @arg I2C_IT_STOP_DET : stop condition interrupt
* @arg I2C_IT_START_DET : start condition interrupt * @arg I2C_IT_START_DET : start condition interrupt
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt * @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
* @retval : None * @retval : None
*/ */
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)

170
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_rcc.c
View File

@ -174,22 +174,22 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
*/ */
void SystemClk_HSEInit(uint32_t PLL_DN) void SystemClk_HSEInit(uint32_t PLL_DN)
{ {
RCC_DeInit(); RCC_DeInit();
//HSE on //HSE on
//CR寄存器BIT16位（HSEON位）置1，作用是连接外部时钟HSE作为系统时钟 //CR寄存器BIT16位（HSEON位）置1，作用是连接外部时钟HSE作为系统时钟
RCC_HSEConfig(RCC_HSE_ON); RCC_HSEConfig(RCC_HSE_ON);
while(1) while(1)
{ {
if(RCC_WaitForHSEStartUp()!=0) if(RCC_WaitForHSEStartUp()!=0)
{ {
break; break;
} }
} }
RCC_PLLCmd(DISABLE); RCC_PLLCmd(DISABLE);
RCC_PLLConfig(RCC_PLLSource_HSE_Div1,PLL_DN); RCC_PLLConfig(RCC_PLLSource_HSE_Div1,PLL_DN);
RCC_PLLCmd(ENABLE); RCC_PLLCmd(ENABLE);
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);//选择外部时钟作为系统时钟 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);//选择外部时钟作为系统时钟
} }
/** /**
* @brief Resets the RCC clock configuration to the default reset state. * @brief Resets the RCC clock configuration to the default reset state.
@ -350,24 +350,24 @@ void RCC_PLLDMDNConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLDN,uint32_t RCC_P
assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
if(RCC_PLLSource == 0) if(RCC_PLLSource == 0)
{ {
tmpreg0 &= ~(1<<22); tmpreg0 &= ~(1<<22);
} }
else else
{ {
TK499_PLL_FACTOR |= 0x10000; TK499_PLL_FACTOR |= 0x10000;
tmpreg0 |= (1<<22); tmpreg0 |= (1<<22);
} }
RCC_PLLDN &= 0x7f; RCC_PLLDN &= 0x7f;
RCC_PLLDP &= 0x3; RCC_PLLDP &= 0x3;
RCC_PLLDM &= 0xf; RCC_PLLDM &= 0xf;
/* Set the PLL configuration bits */ /* Set the PLL configuration bits */
tmpreg0 |= (u32)((u32)(RCC_PLLDN<<6))|((u32)(RCC_PLLDP<<4))|((u32)RCC_PLLDM); tmpreg0 |= (u32)((u32)(RCC_PLLDN<<6))|((u32)(RCC_PLLDP<<4))|((u32)RCC_PLLDM);
RCC->PLLCFGR = tmpreg0; RCC->PLLCFGR = tmpreg0;
// RCC->PLLCFGR = 0x4004d1; // RCC->PLLCFGR = 0x4004d1;
} }
@ -402,137 +402,137 @@ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
if(RCC_PLLMul==RCC_PLLMul_2) if(RCC_PLLMul==RCC_PLLMul_2)
{ {
TK499_PLL_FACTOR = 2; TK499_PLL_FACTOR = 2;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000001, 0x00000000,0x00000000); //Frclk*8/4 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000001, 0x00000000,0x00000000); //Frclk*8/4
} }
if(RCC_PLLMul==RCC_PLLMul_3) if(RCC_PLLMul==RCC_PLLMul_3)
{ {
TK499_PLL_FACTOR = 3; TK499_PLL_FACTOR = 3;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000002, 0x00000000,0x00000000);//Frclk*6/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000002, 0x00000000,0x00000000);//Frclk*6/2
} }
if(RCC_PLLMul==RCC_PLLMul_4) if(RCC_PLLMul==RCC_PLLMul_4)
{ {
TK499_PLL_FACTOR = 4; TK499_PLL_FACTOR = 4;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000003, 0x00000000,0x00000000);//Frclk*8/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000003, 0x00000000,0x00000000);//Frclk*8/2
} }
if(RCC_PLLMul==RCC_PLLMul_5) if(RCC_PLLMul==RCC_PLLMul_5)
{ {
TK499_PLL_FACTOR = 5; TK499_PLL_FACTOR = 5;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000001,0x00000001);//Frclk*10/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000001,0x00000001);//Frclk*10/2
} }
if(RCC_PLLMul==RCC_PLLMul_6) if(RCC_PLLMul==RCC_PLLMul_6)
{ {
TK499_PLL_FACTOR = 6; TK499_PLL_FACTOR = 6;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000005, 0x00000000,0x00000000);//Frclk*12/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000005, 0x00000000,0x00000000);//Frclk*12/2
} }
if(RCC_PLLMul==RCC_PLLMul_7) if(RCC_PLLMul==RCC_PLLMul_7)
{ {
TK499_PLL_FACTOR = 7; TK499_PLL_FACTOR = 7;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000006, 0x00000000,0x00000000);//Frclk*14/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000006, 0x00000000,0x00000000);//Frclk*14/2
} }
if(RCC_PLLMul==RCC_PLLMul_8) if(RCC_PLLMul==RCC_PLLMul_8)
{ {
TK499_PLL_FACTOR = 8; TK499_PLL_FACTOR = 8;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000007, 0x00000000,0x00000000);//Frclk*16/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000007, 0x00000000,0x00000000);//Frclk*16/2
} }
if(RCC_PLLMul==RCC_PLLMul_9) if(RCC_PLLMul==RCC_PLLMul_9)
{ {
TK499_PLL_FACTOR = 9; TK499_PLL_FACTOR = 9;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000008, 0x00000000,0x00000000);//Frclk*18/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000008, 0x00000000,0x00000000);//Frclk*18/2
} }
if(RCC_PLLMul==RCC_PLLMul_10) if(RCC_PLLMul==RCC_PLLMul_10)
{ {
TK499_PLL_FACTOR = 10; TK499_PLL_FACTOR = 10;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000009, 0x00000000,0x00000000);//Frclk*20/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000009, 0x00000000,0x00000000);//Frclk*20/2
} }
if(RCC_PLLMul==RCC_PLLMul_11) if(RCC_PLLMul==RCC_PLLMul_11)
{ {
TK499_PLL_FACTOR = 11; TK499_PLL_FACTOR = 11;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000a, 0x00000000,0x00000000);//Frclk*22/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000a, 0x00000000,0x00000000);//Frclk*22/2
} }
if(RCC_PLLMul==RCC_PLLMul_12) if(RCC_PLLMul==RCC_PLLMul_12)
{ {
TK499_PLL_FACTOR = 12; TK499_PLL_FACTOR = 12;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000b, 0x00000000,0x00000000);//Frclk*24/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000b, 0x00000000,0x00000000);//Frclk*24/2
} }
if(RCC_PLLMul==RCC_PLLMul_13) if(RCC_PLLMul==RCC_PLLMul_13)
{ {
TK499_PLL_FACTOR = 13; TK499_PLL_FACTOR = 13;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000c, 0x00000000,0x00000000);//Frclk*26/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000c, 0x00000000,0x00000000);//Frclk*26/2
} }
if(RCC_PLLMul==RCC_PLLMul_14) if(RCC_PLLMul==RCC_PLLMul_14)
{ {
TK499_PLL_FACTOR = 14; TK499_PLL_FACTOR = 14;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000d, 0x00000000,0x00000000);//Frclk*28/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000d, 0x00000000,0x00000000);//Frclk*28/2
} }
if(RCC_PLLMul==RCC_PLLMul_15) if(RCC_PLLMul==RCC_PLLMul_15)
{ {
TK499_PLL_FACTOR = 15; TK499_PLL_FACTOR = 15;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000e, 0x00000000,0x00000000);//Frclk*30/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000e, 0x00000000,0x00000000);//Frclk*30/2
} }
if(RCC_PLLMul==RCC_PLLMul_16) if(RCC_PLLMul==RCC_PLLMul_16)
{ {
TK499_PLL_FACTOR = 16; TK499_PLL_FACTOR = 16;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000f, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000f, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_17) if(RCC_PLLMul==RCC_PLLMul_17)
{ {
TK499_PLL_FACTOR = 17; TK499_PLL_FACTOR = 17;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000010, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000010, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_18) if(RCC_PLLMul==RCC_PLLMul_18)
{ {
TK499_PLL_FACTOR = 18; TK499_PLL_FACTOR = 18;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000011, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000011, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_19) if(RCC_PLLMul==RCC_PLLMul_19)
{ {
TK499_PLL_FACTOR = 19; TK499_PLL_FACTOR = 19;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000012, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000012, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_20) if(RCC_PLLMul==RCC_PLLMul_20)
{ {
TK499_PLL_FACTOR = 20; TK499_PLL_FACTOR = 20;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_21) if(RCC_PLLMul==RCC_PLLMul_21)
{ {
TK499_PLL_FACTOR = 21; TK499_PLL_FACTOR = 21;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000014, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000014, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_22) if(RCC_PLLMul==RCC_PLLMul_22)
{ {
TK499_PLL_FACTOR = 22; TK499_PLL_FACTOR = 22;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000015, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000015, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_23) if(RCC_PLLMul==RCC_PLLMul_23)
{ {
TK499_PLL_FACTOR = 23; TK499_PLL_FACTOR = 23;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000016, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000016, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_24) if(RCC_PLLMul==RCC_PLLMul_24)
{ {
TK499_PLL_FACTOR = 24; TK499_PLL_FACTOR = 24;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000017, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000017, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_25) if(RCC_PLLMul==RCC_PLLMul_25)
{ {
TK499_PLL_FACTOR = 25; TK499_PLL_FACTOR = 25;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000018, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000018, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_26) if(RCC_PLLMul==RCC_PLLMul_26)
{ {
TK499_PLL_FACTOR = 26; TK499_PLL_FACTOR = 26;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000019, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000019, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_27) if(RCC_PLLMul==RCC_PLLMul_27)
{ {
TK499_PLL_FACTOR = 27; TK499_PLL_FACTOR = 27;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000020, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000020, 0x00000000,0x00000000);//Frclk*32/2
} }
if(RCC_PLLMul==RCC_PLLMul_28) if(RCC_PLLMul==RCC_PLLMul_28)
{ {
TK499_PLL_FACTOR = 28; TK499_PLL_FACTOR = 28;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000021, 0x00000000,0x00000000);//Frclk*32/2 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000021, 0x00000000,0x00000000);//Frclk*32/2
} }
} }
@ -581,25 +581,25 @@ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
tmpreg |= RCC_SYSCLKSource; tmpreg |= RCC_SYSCLKSource;
/* Store the new value */ /* Store the new value */
RCC->CFGR = tmpreg; RCC->CFGR = tmpreg;
if(RCC_SYSCLKSource == RCC_SYSCLKSource_PLLCLK) if(RCC_SYSCLKSource == RCC_SYSCLKSource_PLLCLK)
{ {
if(TK499_PLL_FACTOR&0x10000)//hse as pll src if(TK499_PLL_FACTOR&0x10000)//hse as pll src
{ {
TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSE_VALUE; TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSE_VALUE;
} }
else else
{ {
TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSI_Value_Pll_ON; TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSI_Value_Pll_ON;
} }
} }
else if(RCC_SYSCLKSource == RCC_SYSCLKSource_HSE) else if(RCC_SYSCLKSource == RCC_SYSCLKSource_HSE)
{ {
TK499_SYS_CLK = HSE_VALUE; TK499_SYS_CLK = HSE_VALUE;
} }
else else
{ {
TK499_SYS_CLK = HSI_Value_Pll_OFF; TK499_SYS_CLK = HSI_Value_Pll_OFF;
} }
} }
/** /**

2
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_spi.c
View File

@ -150,7 +150,7 @@ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
tmpreg |= (uint32_t)((uint32_t) SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_NSS | tmpreg |= (uint32_t)((uint32_t) SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_NSS |
SPI_InitStruct->SPI_Mode ); SPI_InitStruct->SPI_Mode );
/* Write to SPIx GCTL */ /* Write to SPIx GCTL */
// if(SPI_InitStruct->SPI_DataSize==SPI_DataSize_8b) tmpreg |= 0x1000; // if(SPI_InitStruct->SPI_DataSize==SPI_DataSize_8b) tmpreg |= 0x1000;
SPIx->GCTL = tmpreg; SPIx->GCTL = tmpreg;
/*---------------------------- SPIx CCTL Configuration ------------------------*/ /*---------------------------- SPIx CCTL Configuration ------------------------*/
tmpreg = SPIx->CCTL; tmpreg = SPIx->CCTL;

8
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_uart.c
View File

@ -49,8 +49,8 @@
#define GCR_UE_Set ((uint16_t)0x0001) /* UART Enable Mask */ #define GCR_UE_Set ((uint16_t)0x0001) /* UART Enable Mask */
#define GCR_UE_Reset ((uint16_t)0xFFFE) /* UART Disable Mask */ #define GCR_UE_Reset ((uint16_t)0xFFFE) /* UART Disable Mask */
#define CCR_CLEAR_Mask ((uint32_t)0xFFFFFF30) /* UART CCR Mask */ #define CCR_CLEAR_Mask ((uint32_t)0xFFFFFF30) /* UART CCR Mask */
#define GCR_CLEAR_Mask ((uint32_t)0xFFFFFFE0) /* UART GCR Mask */ #define GCR_CLEAR_Mask ((uint32_t)0xFFFFFFE0) /* UART GCR Mask */
/** /**
* @} * @}
*/ */
@ -159,8 +159,8 @@ void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct)
/* Determine the UART_baud*/ /* Determine the UART_baud*/
tmpreg = ((RCC_ClocksStatus.PCLK1_Frequency)/(UART_InitStruct->UART_BaudRate)/16) ; tmpreg = ((RCC_ClocksStatus.PCLK1_Frequency)/(UART_InitStruct->UART_BaudRate)/16) ;
/* Write to UART BRR */ /* Write to UART BRR */
UARTx->BRR = tmpreg; UARTx->BRR = tmpreg;
} }
/** /**

4
bsp/tkm32F499/drivers/board.c
View File

@ -26,8 +26,8 @@ MSH_CMD_EXPORT(reboot, Reboot System);
static void bsp_clock_config(void) static void bsp_clock_config(void)
{ {
RemapVtorTable(); RemapVtorTable();
SystemClk_HSEInit(RCC_PLLMul_20);//启动PLL时钟，12MHz*20=240MHz SystemClk_HSEInit(RCC_PLLMul_20);//启动PLL时钟，12MHz*20=240MHz
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//2：2，全局性函数，仅需设置一次 NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//2：2，全局性函数，仅需设置一次
uint32_t sysclk = 0; uint32_t sysclk = 0;
getSystemClock(&sysclk); getSystemClock(&sysclk);

2
bsp/tkm32F499/drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *