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This commit is contained in:
NU-LL 2021-10-14 19:46:54 +08:00
parent c178d61947
commit ffd8662d7a
33 changed files with 1931 additions and 1931 deletions
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66
bsp/tkm32F499/Libraries/CMSIS_and_startup/sys.c
View File

@ -3,24 +3,24 @@
void RemapVtorTable(void)
{
int i;
int i;
RCC->AHB1ENR |= 1<<13;//bkp clk,enable sram
//关ROM区中断
//关ROM区中断
for(i = 0;i<90;i++)
{
NVIC_DisableIRQ((IRQn_Type)i);
}
SCB->VTOR = 0;
SCB->VTOR |= 0x1<<29;
for(i = 0;i < 512;i+=4)
*(u32*)(T_SRAM_BASE + i) = *(u32*)(T_SDRAM_BASE+i);
SCB->VTOR = 0;
SCB->VTOR |= 0x1<<29;
for(i = 0;i < 512;i+=4)
*(u32*)(T_SRAM_BASE + i) = *(u32*)(T_SDRAM_BASE+i);
}
void AI_Responder_enable(void)
{
AI_Responder->ADDR1= 0x70807040;
// AI_Responder->ADDR0 = 0x70027080;
// AI_Responder->ADDR0 = 0x70027080;
AI_Responder->ADDR1 = 0;
AI_Responder->CCR &= ~(0x3<<3);
AI_Responder->CCR |= 1;
@ -42,14 +42,14 @@ void AI_Responder_disable(void)
//该函数会自动开启对应中断,以及屏蔽线
void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM)
{
u8 EXTOFFSET=(BITx%4)*4;
RCC->APB2ENR|=1<<14; //使能SYSCFG时钟
SYSCFG->EXTICR[BITx/4]&=~(0x000F<<EXTOFFSET);//清除原来设置！！！
SYSCFG->EXTICR[BITx/4]|=GPIOx<<EXTOFFSET; //EXTI.BITx映射到GPIOx.BITx
//自动设置
EXTI->IMR|=1<<BITx; //开启line BITx上的中断(如果要禁止中断，则反操作即可)
if(TRIM&0x01)EXTI->FTSR|=1<<BITx; //line BITx事件下降沿触发
if(TRIM&0x02)EXTI->RTSR|=1<<BITx; //line BITx事件上升沿触发
u8 EXTOFFSET=(BITx%4)*4;
RCC->APB2ENR|=1<<14; //使能SYSCFG时钟
SYSCFG->EXTICR[BITx/4]&=~(0x000F<<EXTOFFSET);//清除原来设置！！！
SYSCFG->EXTICR[BITx/4]|=GPIOx<<EXTOFFSET; //EXTI.BITx映射到GPIOx.BITx
//自动设置
EXTI->IMR|=1<<BITx; //开启line BITx上的中断(如果要禁止中断，则反操作即可)
if(TRIM&0x01)EXTI->FTSR|=1<<BITx; //line BITx事件下降沿触发
if(TRIM&0x02)EXTI->RTSR|=1<<BITx; //line BITx事件上升沿触发
}
@ -57,37 +57,37 @@ void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM)
//采用如下方法实现执行汇编指令WFI
void WFI_SET(void)
{
__ASM volatile("wfi");
__ASM volatile("wfi");
}
//关闭所有中断(但是不包括fault和NMI中断)
void INTX_DISABLE(void)
{
__ASM volatile("cpsid i");
__ASM volatile("cpsid i");
}
//开启所有中断
void INTX_ENABLE(void)
{
__ASM volatile("cpsie i");
__ASM volatile("cpsie i");
}
//设置栈顶地址 __set_MSP(0x70002000);
//进入待机模式
void Sys_Standby(void)
{
SCB->SCR|=1<<2; //使能SLEEPDEEP位 (SYS->CTRL)
RCC->APB1ENR|=1<<28;//使能电源时钟
PWR->CSR|=1<<8; //设置WKUP用于唤醒
PWR->CR|=1<<2; //清除Wake-up 标志
PWR->CR|=1<<1; //PDDS置位
WFI_SET(); //执行WFI指令,进入待机模式
SCB->SCR|=1<<2; //使能SLEEPDEEP位 (SYS->CTRL)
RCC->APB1ENR|=1<<28;//使能电源时钟
PWR->CSR|=1<<8; //设置WKUP用于唤醒
PWR->CR|=1<<2; //清除Wake-up 标志
PWR->CR|=1<<1; //PDDS置位
WFI_SET(); //执行WFI指令,进入待机模式
}
//系统软复位
void Sys_Soft_Reset(void)
{
SCB->AIRCR =0X05FA0000|(u32)0x04;
SCB->AIRCR =0X05FA0000|(u32)0x04;
}
// TK499_NVIC_Init(2,2,TK80_IRQn,2);
// TK499_NVIC_Init(2,2,TK80_IRQn,2);
//设置NVIC
//NVIC_PreemptionPriority:抢占优先级
//NVIC_SubPriority :响应优先级
@ -103,13 +103,13 @@ void Sys_Soft_Reset(void)
//NVIC_SubPriority和NVIC_PreemptionPriority的原则是,数值越小,越优先
void TK499_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group)
{
u32 temp;
NVIC_SetPriorityGrouping(NVIC_Group);//设置分组
temp=NVIC_PreemptionPriority<<(4-NVIC_Group);
temp|=NVIC_SubPriority&(0x0f>>NVIC_Group);
temp&=0xf; //取低四位
NVIC->ISER[NVIC_Channel/32]|=1<<NVIC_Channel%32;//使能中断位(要清除的话,设置ICER对应位为1即可)
NVIC->IP[NVIC_Channel]|=temp<<4; //设置响应优先级和抢断优先级
u32 temp;
NVIC_SetPriorityGrouping(NVIC_Group);//设置分组
temp=NVIC_PreemptionPriority<<(4-NVIC_Group);
temp|=NVIC_SubPriority&(0x0f>>NVIC_Group);
temp&=0xf; //取低四位
NVIC->ISER[NVIC_Channel/32]|=1<<NVIC_Channel%32;//使能中断位(要清除的话,设置ICER对应位为1即可)
NVIC->IP[NVIC_Channel]|=temp<<4; //设置响应优先级和抢断优先级
}
void TK80_IRQHandler(void)

10
bsp/tkm32F499/Libraries/CMSIS_and_startup/sys.h
View File

@ -13,16 +13,16 @@ void RemapVtorTable(void);
void AI_Responder_enable(void);
void AI_Responder_disable(void);
void Sys_Soft_Reset(void); //系统软复位
void Sys_Standby(void); //待机模式
void Sys_Soft_Reset(void); //系统软复位
void Sys_Standby(void); //待机模式
void TK499_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group);
void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM); //外部中断配置函数(只对GPIOA~I)
void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM); //外部中断配置函数(只对GPIOA~I)
//以下为汇编函数
void WFI_SET(void); //执行WFI指令
void WFI_SET(void); //执行WFI指令
void INTX_DISABLE(void);//关闭所有中断
void INTX_ENABLE(void); //开启所有中断
void INTX_ENABLE(void); //开启所有中断
void TIM3_Config(u16 arr,u16 psc);
#endif

546
bsp/tkm32F499/Libraries/CMSIS_and_startup/tk499.h
View File

@ -21,7 +21,7 @@
******************************************************************************
*/
//============== <EFBFBD>汾 EK V1.0 20190818 ==============//
//============== 锟芥本 EK V1.0 20190818 ==============//
#define T_SRAM_BASE 0X20000000
@ -130,10 +130,10 @@ typedef enum IRQn
TIM3_IRQn = 28, /*!< TIM3 global Interrupt */
TIM4_IRQn = 29, /*!< TIM4 global Interrupt */
TIM5_IRQn = 30, /*!< TIM4 global Interrupt */
TIM6_IRQn = 31, /*!< TIM4 global Interrupt */
TIM7_IRQn = 32, /*!< TIM4 global Interrupt */
TIM6_IRQn = 31, /*!< TIM4 global Interrupt */
TIM7_IRQn = 32, /*!< TIM4 global Interrupt */
I2C1_IRQn = 33, /*!< I2C1 Event Interrupt */
I2C1_IRQn = 33, /*!< I2C1 Event Interrupt */
I2C2_IRQn = 34, /*!< I2C2 Event Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
@ -144,39 +144,39 @@ typedef enum IRQn
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
USBAwake_IRQn = 42, /*!< USB WakeUp from suspend through EXTI Line Interrupt */
TIM2_BRK_IRQn = 43, /**/
TIM2_UP_IRQn = 44, /**/
TIM2_TRG_COM_IRQn = 45, /**/
TIM2_CC_IRQn = 46, /**/
DMA1_Channel8_IRQn = 47, /**/
TK80_IRQn = 48, /**/
TIM2_BRK_IRQn = 43, /**/
TIM2_UP_IRQn = 44, /**/
TIM2_TRG_COM_IRQn = 45, /**/
TIM2_CC_IRQn = 46, /**/
DMA1_Channel8_IRQn = 47, /**/
TK80_IRQn = 48, /**/
SDIO1_IRQn = 49, /**/
SDIO2_IRQn = 50, /**/
SPI3_IRQn = 51, /**/
UART4_IRQn = 52, /**/
UART5_IRQn = 53, /**/
TIM8_IRQn = 55, /**/
DMA2_Channel1_IRQn = 56, /**/
DMA2_Channel2_IRQn = 57, /**/
DMA2_Channel3_IRQn = 58, /**/
DMA2_Channel4_IRQn = 59, /**/
DMA2_Channel5_IRQn = 60, /**/
TIM9_IRQn = 61, /**/
TIM10_IRQn = 62, /**/
CAN2_IRQn = 63, /**/
USB_IRQn = 67, /**/
DMA2_Channel6_IRQn = 68, /**/
DMA2_Channel7_IRQn = 69, /**/
DMA2_Channel8_IRQn = 70, /**/
I2C3_IRQn = 72, /**/
I2C4_IRQn = 73, /**/
FPU_IRQn = 81, /**/
SPI4_IRQn = 84, /**/
TOUCHPAD_IRQn = 86,
QSPI_IRQn = 87, /**/
LTDC_IRQn = 88, /**/
I2S1_IRQn = 90, /**/
SDIO1_IRQn = 49, /**/
SDIO2_IRQn = 50, /**/
SPI3_IRQn = 51, /**/
UART4_IRQn = 52, /**/
UART5_IRQn = 53, /**/
TIM8_IRQn = 55, /**/
DMA2_Channel1_IRQn = 56, /**/
DMA2_Channel2_IRQn = 57, /**/
DMA2_Channel3_IRQn = 58, /**/
DMA2_Channel4_IRQn = 59, /**/
DMA2_Channel5_IRQn = 60, /**/
TIM9_IRQn = 61, /**/
TIM10_IRQn = 62, /**/
CAN2_IRQn = 63, /**/
USB_IRQn = 67, /**/
DMA2_Channel6_IRQn = 68, /**/
DMA2_Channel7_IRQn = 69, /**/
DMA2_Channel8_IRQn = 70, /**/
I2C3_IRQn = 72, /**/
I2C4_IRQn = 73, /**/
FPU_IRQn = 81, /**/
SPI4_IRQn = 84, /**/
TOUCHPAD_IRQn = 86,
QSPI_IRQn = 87, /**/
LTDC_IRQn = 88, /**/
I2S1_IRQn = 90, /**/
} IRQn_Type;
@ -320,38 +320,38 @@ typedef struct
*/
typedef struct
{
__IO uint32_t CR; //0x00
__IO uint32_t CMR; //0x04
__IO uint32_t SR; //0x08
__IO uint32_t IR; //0x0c
__IO uint32_t ACR; //0x10
__IO uint32_t AMR; //0x14
__IO uint32_t BTR0; //0x18
__IO uint32_t BTR1; //0x1C
__IO uint32_t RESERVED0; //0x20
uint32_t RESERVED1; //0x24
__IO uint32_t TXID0; //0x28
__IO uint32_t TXID1; //0x2c
__IO uint32_t TXDR0; //0x30
__IO uint32_t TXDR1; //0x34
__IO uint32_t TXDR2; //0x38
__IO uint32_t TXDR3; //0x3c
__IO uint32_t TXDR4; //0x40
__IO uint32_t TXDR5; //0x44
__IO uint32_t TXDR6; //0x48
__IO uint32_t TXDR7; //0x4c
__IO uint32_t RXID0; //0x50
__IO uint32_t RXID1; //0x54
__IO uint32_t RXDR0; //0x58
__IO uint32_t RXDR1; //0x5C
__IO uint32_t RXDR2; //0x60
__IO uint32_t CR; //0x00
__IO uint32_t CMR; //0x04
__IO uint32_t SR; //0x08
__IO uint32_t IR; //0x0c
__IO uint32_t ACR; //0x10
__IO uint32_t AMR; //0x14
__IO uint32_t BTR0; //0x18
__IO uint32_t BTR1; //0x1C
__IO uint32_t RESERVED0; //0x20
uint32_t RESERVED1; //0x24
__IO uint32_t TXID0; //0x28
__IO uint32_t TXID1; //0x2c
__IO uint32_t TXDR0; //0x30
__IO uint32_t TXDR1; //0x34
__IO uint32_t TXDR2; //0x38
__IO uint32_t TXDR3; //0x3c
__IO uint32_t TXDR4; //0x40
__IO uint32_t TXDR5; //0x44
__IO uint32_t TXDR6; //0x48
__IO uint32_t TXDR7; //0x4c
__IO uint32_t RXID0; //0x50
__IO uint32_t RXID1; //0x54
__IO uint32_t RXDR0; //0x58
__IO uint32_t RXDR1; //0x5C
__IO uint32_t RXDR2; //0x60
__IO uint32_t RXDR3;
__IO uint32_t RXDR4;
__IO uint32_t RXDR5; //0x6c
__IO uint32_t RXDR6; //0x70
__IO uint32_t RXDR7; //0x74
__IO uint32_t RXDR5; //0x6c
__IO uint32_t RXDR6; //0x70
__IO uint32_t RXDR7; //0x74
uint32_t RESERVED2;
__IO uint32_t CDR; //0x7c
__IO uint32_t CDR; //0x7c
}CAN_TypeDef;
/**
@ -359,38 +359,38 @@ typedef struct
*/
typedef struct
{
__IO uint32_t MOD; //00
__IO uint32_t CMR; //04
__IO uint32_t SR; //08
__IO uint32_t IR; //0C
__IO uint32_t IER; //0x10h
uint32_t RESERVED0; //14
__IO uint32_t BTR0; //18
__IO uint32_t BTR1; //1C
uint32_t RESERVED1; //0x20h
uint32_t RESERVED2; //24
uint32_t RESERVED3; //28
__IO uint32_t ALC; //2C
__IO uint32_t ECC; //0x30h
__IO uint32_t EWLR; //34
__IO uint32_t RXERR; //38
__IO uint32_t TXERR; //3C
__IO uint32_t FF; //0x40
__IO uint32_t ID0; //44
__IO uint32_t ID1; //48
__IO uint32_t DATA0; //4C
__IO uint32_t DATA1; //0x50
__IO uint32_t MOD; //00
__IO uint32_t CMR; //04
__IO uint32_t SR; //08
__IO uint32_t IR; //0C
__IO uint32_t IER; //0x10h
uint32_t RESERVED0; //14
__IO uint32_t BTR0; //18
__IO uint32_t BTR1; //1C
uint32_t RESERVED1; //0x20h
uint32_t RESERVED2; //24
uint32_t RESERVED3; //28
__IO uint32_t ALC; //2C
__IO uint32_t ECC; //0x30h
__IO uint32_t EWLR; //34
__IO uint32_t RXERR; //38
__IO uint32_t TXERR; //3C
__IO uint32_t FF; //0x40
__IO uint32_t ID0; //44
__IO uint32_t ID1; //48
__IO uint32_t DATA0; //4C
__IO uint32_t DATA1; //0x50
__IO uint32_t DATA2;
__IO uint32_t DATA3;
__IO uint32_t DATA4;
__IO uint32_t DATA5; //0x60
__IO uint32_t DATA5; //0x60
__IO uint32_t DATA6;
__IO uint32_t DATA7;
__IO uint32_t DATA8;
__IO uint32_t DATA9; //0x70
__IO uint32_t DATA9; //0x70
__IO uint32_t RMC;
__IO uint32_t RBSA;
__IO uint32_t CDR; //7C
__IO uint32_t CDR; //7C
}CAN_Peli_TypeDef;
@ -558,7 +558,7 @@ typedef struct
typedef struct
{
__IO uint32_t CFGR; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
__IO uint32_t RESERVED0;
__IO uint32_t RESERVED0;
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
} SYSCFG_TypeDef;
@ -759,7 +759,7 @@ typedef struct
__IO uint32_t RXDNR;
__IO uint32_t SCSR; //30
__IO uint32_t TXREGBH;
__IO uint32_t TXREGBL;
__IO uint32_t TXREGBL;
} SPI_TypeDef;
@ -830,13 +830,13 @@ typedef struct
*/
typedef struct
{
__IO uint32_t rTOP; /*! Address offset: 0x00 */
__IO uint32_t rINT_STATE; /*! Address offset: 0x04 */
__IO uint32_t rEP_INT_STATE; /*! Address offset: 0x08 */
__IO uint32_t rEP0_INT_STATE; /*! Address offset: 0x0C */
__IO uint32_t rINT_EN; /*! Address offset: 0x10 */
__IO uint32_t rEP_INT_EN; /*! Address offset: 0x14 */
__IO uint32_t rEP0_INT_EN; /*! Address offset: 0x18 */
__IO uint32_t rTOP; /*! Address offset: 0x00 */
__IO uint32_t rINT_STATE; /*! Address offset: 0x04 */
__IO uint32_t rEP_INT_STATE; /*! Address offset: 0x08 */
__IO uint32_t rEP0_INT_STATE; /*! Address offset: 0x0C */
__IO uint32_t rINT_EN; /*! Address offset: 0x10 */
__IO uint32_t rEP_INT_EN; /*! Address offset: 0x14 */
__IO uint32_t rEP0_INT_EN; /*! Address offset: 0x18 */
__IO uint32_t RESERVED0;
@ -847,137 +847,137 @@ typedef struct
__IO uint32_t rEP3_INT_STATE; /*! Address offset: 0x28 */
__IO uint32_t rEP4_INT_STATE; /*! Address offset: 0x2C */
__IO uint32_t RESERVED1; /*! Address offset: 0x30 */
__IO uint32_t RESERVED2; /*! Address offset: 0x34 */
__IO uint32_t RESERVED3; /*! Address offset: 0x38 */
__IO uint32_t RESERVED4; /*! Address offset: 0x3C */
__IO uint32_t RESERVED1; /*! Address offset: 0x30 */
__IO uint32_t RESERVED2; /*! Address offset: 0x34 */
__IO uint32_t RESERVED3; /*! Address offset: 0x38 */
__IO uint32_t RESERVED4; /*! Address offset: 0x3C */
__IO uint32_t rEP1_INT_EN; /*! Address offset: 0x40 */
__IO uint32_t rEP2_INT_EN; /*! Address offset: 0x44 */
__IO uint32_t rEP3_INT_EN; /*! Address offset: 0x48 */
__IO uint32_t rEP4_INT_EN; /*! Address offset: 0x4C */
__IO uint32_t rEP1_INT_EN; /*! Address offset: 0x40 */
__IO uint32_t rEP2_INT_EN; /*! Address offset: 0x44 */
__IO uint32_t rEP3_INT_EN; /*! Address offset: 0x48 */
__IO uint32_t rEP4_INT_EN; /*! Address offset: 0x4C */
__IO uint32_t RESERVED5; /*! Address offset: 0x50 */
__IO uint32_t RESERVED6; /*! Address offset: 0x54 */
__IO uint32_t RESERVED7; /*! Address offset: 0x58 */
__IO uint32_t RESERVED8; /*! Address offset: 0x5C */
__IO uint32_t RESERVED5; /*! Address offset: 0x50 */
__IO uint32_t RESERVED6; /*! Address offset: 0x54 */
__IO uint32_t RESERVED7; /*! Address offset: 0x58 */
__IO uint32_t RESERVED8; /*! Address offset: 0x5C */
__IO uint32_t rADDR; /*! Address offset: 0x60 */
__IO uint32_t rEP_EN; /*! Address offset: 0x64 */
__IO uint32_t rADDR; /*! Address offset: 0x60 */
__IO uint32_t rEP_EN; /*! Address offset: 0x64 */
__IO uint32_t RESERVED9; /*! Address offset: 0x68 */
__IO uint32_t RESERVED10; /*! Address offset: 0x6C */
__IO uint32_t RESERVED11; /*! Address offset: 0x70 */
__IO uint32_t RESERVED12; /*! Address offset: 0x74 */
__IO uint32_t RESERVED9; /*! Address offset: 0x68 */
__IO uint32_t RESERVED10; /*! Address offset: 0x6C */
__IO uint32_t RESERVED11; /*! Address offset: 0x70 */
__IO uint32_t RESERVED12; /*! Address offset: 0x74 */
__IO uint32_t rTOG_CTRL1_4; /*! Address offset: 0x78 */
__IO uint32_t RESERVED13; /*! Address offset: 0x7C */
__IO uint32_t RESERVED13; /*! Address offset: 0x7C */
__IO uint32_t rSETUP[8]; /*! Address offset: 0x80 */
//__IO uint32_t rSETUP0; /*! Address offset: 0x80 */
//__IO uint32_t rSETUP1; /*! Address offset: 0x84 */
//__IO uint32_t rSETUP2; /*! Address offset: 0x88 */
//__IO uint32_t rSETUP3; /*! Address offset: 0x8C */
//__IO uint32_t rSETUP4; /*! Address offset: 0x90 */
//__IO uint32_t rSETUP5; /*! Address offset: 0x94 */
//__IO uint32_t rSETUP6; /*! Address offset: 0x98 */
//__IO uint32_t rSETUP7; /*! Address offset: 0x9C */
__IO uint32_t rPAKET_SIZE0; /*! Address offset: 0xA0 */
__IO uint32_t rPAKET_SIZE1; /*! Address offset: 0xA4 */
__IO uint32_t rSETUP[8]; /*! Address offset: 0x80 */
//__IO uint32_t rSETUP0; /*! Address offset: 0x80 */
//__IO uint32_t rSETUP1; /*! Address offset: 0x84 */
//__IO uint32_t rSETUP2; /*! Address offset: 0x88 */
//__IO uint32_t rSETUP3; /*! Address offset: 0x8C */
//__IO uint32_t rSETUP4; /*! Address offset: 0x90 */
//__IO uint32_t rSETUP5; /*! Address offset: 0x94 */
//__IO uint32_t rSETUP6; /*! Address offset: 0x98 */
//__IO uint32_t rSETUP7; /*! Address offset: 0x9C */
__IO uint32_t rPAKET_SIZE0; /*! Address offset: 0xA0 */
__IO uint32_t rPAKET_SIZE1; /*! Address offset: 0xA4 */
__IO uint32_t RESERVED14; /*! Address offset: 0xA8 */
__IO uint32_t RESERVED15; /*! Address offset: 0xAC */
__IO uint32_t RESERVED14; /*! Address offset: 0xA8 */
__IO uint32_t RESERVED15; /*! Address offset: 0xAC */
__IO uint32_t RESERVED16; /*! Address offset: 0xB0 */
__IO uint32_t RESERVED17; /*! Address offset: 0xB4 */
__IO uint32_t RESERVED18; /*! Address offset: 0xB8 */
__IO uint32_t RESERVED19; /*! Address offset: 0xBC */
__IO uint32_t RESERVED16; /*! Address offset: 0xB0 */
__IO uint32_t RESERVED17; /*! Address offset: 0xB4 */
__IO uint32_t RESERVED18; /*! Address offset: 0xB8 */
__IO uint32_t RESERVED19; /*! Address offset: 0xBC */
__IO uint32_t RESERVED20; /*! Address offset: 0xC0 */
__IO uint32_t RESERVED21; /*! Address offset: 0xC4 */
__IO uint32_t RESERVED22; /*! Address offset: 0xC8 */
__IO uint32_t RESERVED23; /*! Address offset: 0xCC */
__IO uint32_t RESERVED20; /*! Address offset: 0xC0 */
__IO uint32_t RESERVED21; /*! Address offset: 0xC4 */
__IO uint32_t RESERVED22; /*! Address offset: 0xC8 */
__IO uint32_t RESERVED23; /*! Address offset: 0xCC */
__IO uint32_t RESERVED24; /*! Address offset: 0xD0 */
__IO uint32_t RESERVED25; /*! Address offset: 0xD4 */
__IO uint32_t RESERVED26; /*! Address offset: 0xD8 */
__IO uint32_t RESERVED27; /*! Address offset: 0xDC */
__IO uint32_t RESERVED24; /*! Address offset: 0xD0 */
__IO uint32_t RESERVED25; /*! Address offset: 0xD4 */
__IO uint32_t RESERVED26; /*! Address offset: 0xD8 */
__IO uint32_t RESERVED27; /*! Address offset: 0xDC */
__IO uint32_t RESERVED28; /*! Address offset: 0xE0 */
__IO uint32_t RESERVED29; /*! Address offset: 0xE4 */
__IO uint32_t RESERVED30; /*! Address offset: 0xE8 */
__IO uint32_t RESERVED31; /*! Address offset: 0xEC */
__IO uint32_t RESERVED28; /*! Address offset: 0xE0 */
__IO uint32_t RESERVED29; /*! Address offset: 0xE4 */
__IO uint32_t RESERVED30; /*! Address offset: 0xE8 */
__IO uint32_t RESERVED31; /*! Address offset: 0xEC */
__IO uint32_t RESERVED32; /*! Address offset: 0xF0 */
__IO uint32_t RESERVED33; /*! Address offset: 0xF4 */
__IO uint32_t RESERVED34; /*! Address offset: 0xF8 */
__IO uint32_t RESERVED35; /*! Address offset: 0xFC */
__IO uint32_t RESERVED32; /*! Address offset: 0xF0 */
__IO uint32_t RESERVED33; /*! Address offset: 0xF4 */
__IO uint32_t RESERVED34; /*! Address offset: 0xF8 */
__IO uint32_t RESERVED35; /*! Address offset: 0xFC */
__IO uint32_t rEP0_AVIL; /*! Address offset: 0x100 */
__IO uint32_t rEP1_AVIL; /*! Address offset: 0x104 */
__IO uint32_t rEP2_AVIL; /*! Address offset: 0x108 */
__IO uint32_t rEP3_AVIL; /*! Address offset: 0x10C */
__IO uint32_t rEP4_AVIL; /*! Address offset: 0x110 */
__IO uint32_t rEP0_AVIL; /*! Address offset: 0x100 */
__IO uint32_t rEP1_AVIL; /*! Address offset: 0x104 */
__IO uint32_t rEP2_AVIL; /*! Address offset: 0x108 */
__IO uint32_t rEP3_AVIL; /*! Address offset: 0x10C */
__IO uint32_t rEP4_AVIL; /*! Address offset: 0x110 */
__IO uint32_t RESERVED36; /*! Address offset: 0x114 */
__IO uint32_t RESERVED37; /*! Address offset: 0x118 */
__IO uint32_t RESERVED38; /*! Address offset: 0x11C */
__IO uint32_t RESERVED39; /*! Address offset: 0x120 */
__IO uint32_t RESERVED36; /*! Address offset: 0x114 */
__IO uint32_t RESERVED37; /*! Address offset: 0x118 */
__IO uint32_t RESERVED38; /*! Address offset: 0x11C */
__IO uint32_t RESERVED39; /*! Address offset: 0x120 */
__IO uint32_t RESERVED40; /*! Address offset: 0x124 */
__IO uint32_t RESERVED41; /*! Address offset: 0x128 */
__IO uint32_t RESERVED42; /*! Address offset: 0x12C */
__IO uint32_t RESERVED43; /*! Address offset: 0x130 */
__IO uint32_t RESERVED40; /*! Address offset: 0x124 */
__IO uint32_t RESERVED41; /*! Address offset: 0x128 */
__IO uint32_t RESERVED42; /*! Address offset: 0x12C */
__IO uint32_t RESERVED43; /*! Address offset: 0x130 */
__IO uint32_t RESERVED44; /*! Address offset: 0x134 */
__IO uint32_t RESERVED45; /*! Address offset: 0x138 */
__IO uint32_t RESERVED46; /*! Address offset: 0x13C */
__IO uint32_t RESERVED44; /*! Address offset: 0x134 */
__IO uint32_t RESERVED45; /*! Address offset: 0x138 */
__IO uint32_t RESERVED46; /*! Address offset: 0x13C */
__IO uint32_t rEP0_CTRL; /*! Address offset: 0x140 */
__IO uint32_t rEP1_CTRL; /*! Address offset: 0x144 */
__IO uint32_t rEP2_CTRL; /*! Address offset: 0x148 */
__IO uint32_t rEP3_CTRL; /*! Address offset: 0x14C */
__IO uint32_t rEP4_CTRL; /*! Address offset: 0x150 */
__IO uint32_t rEP0_CTRL; /*! Address offset: 0x140 */
__IO uint32_t rEP1_CTRL; /*! Address offset: 0x144 */
__IO uint32_t rEP2_CTRL; /*! Address offset: 0x148 */
__IO uint32_t rEP3_CTRL; /*! Address offset: 0x14C */
__IO uint32_t rEP4_CTRL; /*! Address offset: 0x150 */
__IO uint32_t RESERVED47; /*! Address offset: 0x154 */
__IO uint32_t RESERVED48; /*! Address offset: 0x158 */
__IO uint32_t RESERVED49; /*! Address offset: 0x15C */
//__IO uint32_t RESERVED50; /*! Address offset: 0x15C */
__IO uint32_t RESERVED47; /*! Address offset: 0x154 */
__IO uint32_t RESERVED48; /*! Address offset: 0x158 */
__IO uint32_t RESERVED49; /*! Address offset: 0x15C */
//__IO uint32_t RESERVED50; /*! Address offset: 0x15C */
//__IO uint32_t rEPn_FIFO[5]; /*! Address offset: 0x160 */
//__IO uint32_t rEPn_FIFO[5]; /*! Address offset: 0x160 */
__IO uint32_t rEP0_FIFO; /*! Address offset: 0x160 */
__IO uint32_t rEP1_FIFO; /*! Address offset: 0x164 */
__IO uint32_t rEP2_FIFO; /*! Address offset: 0x168 */
__IO uint32_t rEP3_FIFO; /*! Address offset: 0x16C */
__IO uint32_t rEP4_FIFO; /*! Address offset: 0x170 */
__IO uint32_t rEP0_FIFO; /*! Address offset: 0x160 */
__IO uint32_t rEP1_FIFO; /*! Address offset: 0x164 */
__IO uint32_t rEP2_FIFO; /*! Address offset: 0x168 */
__IO uint32_t rEP3_FIFO; /*! Address offset: 0x16C */
__IO uint32_t rEP4_FIFO; /*! Address offset: 0x170 */
__IO uint32_t RESERVED51; /*! Address offset: 0x174 */
__IO uint32_t RESERVED52; /*! Address offset: 0x178 */
__IO uint32_t RESERVED53; /*! Address offset: 0x17C */
__IO uint32_t RESERVED51; /*! Address offset: 0x174 */
__IO uint32_t RESERVED52; /*! Address offset: 0x178 */
__IO uint32_t RESERVED53; /*! Address offset: 0x17C */
__IO uint32_t RESERVED54; /*! Address offset: 0x180 */
__IO uint32_t RESERVED54; /*! Address offset: 0x180 */
__IO uint32_t rEP_DMA; /*! Address offset: 0x184 */
__IO uint32_t rEP_HALT; /*! Address offset: 0x188 */
__IO uint32_t RESERVED55; /*! Address offset: 0x18C */
__IO uint32_t rEP_DMA; /*! Address offset: 0x184 */
__IO uint32_t rEP_HALT; /*! Address offset: 0x188 */
__IO uint32_t RESERVED55; /*! Address offset: 0x18C */
__IO uint32_t RESERVED56; /*! Address offset: 0x190 */
__IO uint32_t RESERVED57; /*! Address offset: 0x194 */
__IO uint32_t RESERVED58; /*! Address offset: 0x198 */
__IO uint32_t RESERVED59; /*! Address offset: 0x19C */
__IO uint32_t RESERVED56; /*! Address offset: 0x190 */
__IO uint32_t RESERVED57; /*! Address offset: 0x194 */
__IO uint32_t RESERVED58; /*! Address offset: 0x198 */
__IO uint32_t RESERVED59; /*! Address offset: 0x19C */
__IO uint32_t RESERVED60; /*! Address offset: 0x1A0 */
__IO uint32_t RESERVED61; /*! Address offset: 0x1A4 */
__IO uint32_t RESERVED62; /*! Address offset: 0x1A8 */
__IO uint32_t RESERVED63; /*! Address offset: 0x1AC */
__IO uint32_t RESERVED60; /*! Address offset: 0x1A0 */
__IO uint32_t RESERVED61; /*! Address offset: 0x1A4 */
__IO uint32_t RESERVED62; /*! Address offset: 0x1A8 */
__IO uint32_t RESERVED63; /*! Address offset: 0x1AC */
__IO uint32_t RESERVED64; /*! Address offset: 0x1B0 */
__IO uint32_t RESERVED65; /*! Address offset: 0x1B4 */
__IO uint32_t RESERVED66; /*! Address offset: 0x1B8 */
__IO uint32_t RESERVED67; /*! Address offset: 0x1BC */
__IO uint32_t rPOWER; /*! Address offset: 0x1C0 */
__IO uint32_t RESERVED64; /*! Address offset: 0x1B0 */
__IO uint32_t RESERVED65; /*! Address offset: 0x1B4 */
__IO uint32_t RESERVED66; /*! Address offset: 0x1B8 */
__IO uint32_t RESERVED67; /*! Address offset: 0x1BC */
__IO uint32_t rPOWER; /*! Address offset: 0x1C0 */
} USB_TypeDef;
typedef struct
@ -1120,9 +1120,9 @@ typedef struct
__IO uint32_t RESERVE0;//1C
__IO uint32_t DOUTR;//20
__IO uint32_t BRDR;//24
__IO uint32_t RESERVE1;//28
__IO uint32_t RESERVE2;//2C
__IO uint32_t CFGR3;//30
__IO uint32_t RESERVE1;//28
__IO uint32_t RESERVE2;//2C
__IO uint32_t CFGR3;//30
} TK80_TypeDef;
@ -1166,29 +1166,29 @@ typedef struct
typedef struct
{
__IO uint32_t ADDATA; /*!< ADC status register, Address offset: 0x00 */
__IO uint32_t ADDATA; /*!< ADC status register, Address offset: 0x00 */
__IO uint32_t ADCFG; /*!< ADC control register 1, Address offset: 0x04 */
__IO uint32_t ADCR; /*!< ADC control register 2, Address offset: 0x08 */
__IO uint32_t ADCHS; /*!< ADC sample time register 1, Address offset: 0x0C */
__IO uint32_t ADCMPR; //10
__IO uint32_t ADCMPR; //10
__IO uint32_t ADSTA;
__IO uint32_t ADDR0; //18
__IO uint32_t ADDR1;
__IO uint32_t ADDR2; //20
__IO uint32_t ADDR3;
__IO uint32_t ADDR4;
__IO uint32_t ADDR5;
__IO uint32_t ADDR6; //30
__IO uint32_t ADDR7;
__IO uint32_t ADDR8;
__IO uint32_t ADDR9;
__IO uint32_t RESERVED0;//40
__IO uint32_t RESERVED1;
__IO uint32_t ADDR0; //18
__IO uint32_t ADDR1;
__IO uint32_t ADDR2; //20
__IO uint32_t ADDR3;
__IO uint32_t ADDR4;
__IO uint32_t ADDR5;
__IO uint32_t ADDR6; //30
__IO uint32_t ADDR7;
__IO uint32_t ADDR8;
__IO uint32_t ADDR9;
__IO uint32_t RESERVED0;//40
__IO uint32_t RESERVED1;
__IO uint32_t TPXDR;
__IO uint32_t TPYDR;
__IO uint32_t TPCR;
__IO uint32_t TPFR;
__IO uint32_t TPCSR;
__IO uint32_t TPFR;
__IO uint32_t TPCSR;
} TOUCHPAD_TypeDef;
@ -1346,7 +1346,7 @@ typedef struct
#define CAN1_PELI ((CAN_Peli_TypeDef *) CAN1_BASE)
#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define CAN2_PELI ((CAN_Peli_TypeDef *) CAN2_BASE)
#define USB ((USB_TypeDef*) USB_BASE )
#define USB ((USB_TypeDef*) USB_BASE )
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define I2S ((SPI_TypeDef *) I2S_BASE)
@ -1377,7 +1377,7 @@ typedef struct
#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
#define LTDC ((LTDCTypeDef *) LTDC_BASE)
#define LTDC ((LTDCTypeDef *) LTDC_BASE)
#define TK80 ((TK80_TypeDef *) TK80_BASE)
#define AI_Responder ((AI_Responder_TypeDef*) AI_Responder_BASE)
//#define SDRAM_BANK ((DMA_TypeDef *) SDRAM_BANK_BASE)
@ -1543,18 +1543,18 @@ typedef struct
#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
#define RCC_CR_PLLDN ((uint32_t)0xFC000000) /*!< PLLDN[5:0] bits */
#define RCC_CR_PLLDN_0 ((uint32_t)0x04000000) /*!< Bit 0 */
#define RCC_CR_PLLDN_1 ((uint32_t)0x08000000) /*!< Bit 1 */
#define RCC_CR_PLLDN_2 ((uint32_t)0x10000000) /*!< Bit 2 */
#define RCC_CR_PLLDN_3 ((uint32_t)0x20000000) /*!< Bit 3 */
#define RCC_CR_PLLDN_4 ((uint32_t)0x40000000) /*!< Bit 4 */
#define RCC_CR_PLLDN_5 ((uint32_t)0x80000000) /*!< Bit 5 */
#define RCC_CR_PLLDN ((uint32_t)0xFC000000) /*!< PLLDN[5:0] bits */
#define RCC_CR_PLLDN_0 ((uint32_t)0x04000000) /*!< Bit 0 */
#define RCC_CR_PLLDN_1 ((uint32_t)0x08000000) /*!< Bit 1 */
#define RCC_CR_PLLDN_2 ((uint32_t)0x10000000) /*!< Bit 2 */
#define RCC_CR_PLLDN_3 ((uint32_t)0x20000000) /*!< Bit 3 */
#define RCC_CR_PLLDN_4 ((uint32_t)0x40000000) /*!< Bit 4 */
#define RCC_CR_PLLDN_5 ((uint32_t)0x80000000) /*!< Bit 5 */
#define RCC_CR_PLLDM ((uint32_t)0x00700000) /*!< PLLDM[2:0] bits */
#define RCC_CR_PLLDM_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define RCC_CR_PLLDM_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define RCC_CR_PLLDM_2 ((uint32_t)0x00400000) /*!< Bit 2 */
#define RCC_CR_PLLDM ((uint32_t)0x00700000) /*!< PLLDM[2:0] bits */
#define RCC_CR_PLLDM_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define RCC_CR_PLLDM_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define RCC_CR_PLLDM_2 ((uint32_t)0x00400000) /*!< Bit 2 */
/******************* Bit definition for RCC_CFGR register *******************/
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
@ -1629,7 +1629,7 @@ typedef struct
/*!< MCO configuration */
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) //
#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) //
#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000)
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected */
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< Internal 48 MHz RC oscillator clock selected */
@ -4480,62 +4480,62 @@ typedef struct
/*!<PeliCAN registers */
/******************* Bit definition for CAN_MOD register *******************/
#define CAN_MOD_RM ((uint16_t)0x0001)
#define CAN_MOD_LOM ((uint16_t)0x0002)
#define CAN_MOD_STM ((uint16_t)0x0004)
#define CAN_MOD_AFM ((uint16_t)0x0008)
#define CAN_MOD_SM ((uint16_t)0x0010)
#define CAN_MOD_RM ((uint16_t)0x0001)
#define CAN_MOD_LOM ((uint16_t)0x0002)
#define CAN_MOD_STM ((uint16_t)0x0004)
#define CAN_MOD_AFM ((uint16_t)0x0008)
#define CAN_MOD_SM ((uint16_t)0x0010)
/******************* Bit definition for CAN_IER register *******************/
#define CAN_IER_RIE ((uint16_t)0x0001)
#define CAN_IER_TIE ((uint16_t)0x0002)
#define CAN_IER_EIE ((uint16_t)0x0004)
#define CAN_IER_DOIE ((uint16_t)0x0008)
#define CAN_IER_WUIE ((uint16_t)0x0010)
#define CAN_IER_EPIE ((uint16_t)0x0020)
#define CAN_IER_ALIE ((uint16_t)0x0040)
#define CAN_IER_BEIE ((uint16_t)0x0080)
#define CAN_IER_RIE ((uint16_t)0x0001)
#define CAN_IER_TIE ((uint16_t)0x0002)
#define CAN_IER_EIE ((uint16_t)0x0004)
#define CAN_IER_DOIE ((uint16_t)0x0008)
#define CAN_IER_WUIE ((uint16_t)0x0010)
#define CAN_IER_EPIE ((uint16_t)0x0020)
#define CAN_IER_ALIE ((uint16_t)0x0040)
#define CAN_IER_BEIE ((uint16_t)0x0080)
/******************* Bit definition for CAN_ALC register *******************/
#define CAN_ALC_BITNO ((uint16_t)0x001F)
#define CAN_ALC_BITNO_0 ((uint16_t)0x0001)
#define CAN_ALC_BITNO_1 ((uint16_t)0x0002)
#define CAN_ALC_BITNO_2 ((uint16_t)0x0004)
#define CAN_ALC_BITNO_3 ((uint16_t)0x0008)
#define CAN_ALC_BITNO_4 ((uint16_t)0x0010)
#define CAN_ALC_BITNO ((uint16_t)0x001F)
#define CAN_ALC_BITNO_0 ((uint16_t)0x0001)
#define CAN_ALC_BITNO_1 ((uint16_t)0x0002)
#define CAN_ALC_BITNO_2 ((uint16_t)0x0004)
#define CAN_ALC_BITNO_3 ((uint16_t)0x0008)
#define CAN_ALC_BITNO_4 ((uint16_t)0x0010)
/******************* Bit definition for CAN_ECC register *******************/
#define CAN_ECC_DIR ((uint16_t)0x0020)
#define CAN_ECC_DIR ((uint16_t)0x0020)
#define CAN_ECC_SEG ((uint16_t)0x001F)
#define CAN_ECC_SEG_0 ((uint16_t)0x0001)
#define CAN_ECC_SEG_1 ((uint16_t)0x0002)
#define CAN_ECC_SEG_2 ((uint16_t)0x0004)
#define CAN_ECC_SEG_3 ((uint16_t)0x0008)
#define CAN_ECC_SEG_4 ((uint16_t)0x0010)
#define CAN_ECC_SEG ((uint16_t)0x001F)
#define CAN_ECC_SEG_0 ((uint16_t)0x0001)
#define CAN_ECC_SEG_1 ((uint16_t)0x0002)
#define CAN_ECC_SEG_2 ((uint16_t)0x0004)
#define CAN_ECC_SEG_3 ((uint16_t)0x0008)
#define CAN_ECC_SEG_4 ((uint16_t)0x0010)
#define CAN_ECC_ERRC ((uint16_t)0x00C0)
#define CAN_ECC_ERRC_0 ((uint16_t)0x0040)
#define CAN_ECC_ERRC_1 ((uint16_t)0x0080)
#define CAN_ECC_ERRC ((uint16_t)0x00C0)
#define CAN_ECC_ERRC_0 ((uint16_t)0x0040)
#define CAN_ECC_ERRC_1 ((uint16_t)0x0080)
/******************* Bit definition for CAN_EWLR register *******************/
#define CAN_EWLR_EWL ((uint16_t)0x00FF)
#define CAN_EWLR_EWL ((uint16_t)0x00FF)
/******************* Bit definition for CAN_RXERR register *******************/
#define CAN_RXERR_RXERR ((uint16_t)0x00FF)
#define CAN_RXERR_RXERR ((uint16_t)0x00FF)
/******************* Bit definition for CAN_TXERR register *******************/
#define CAN_TXERR_TXERR ((uint16_t)0x00FF)
#define CAN_TXERR_TXERR ((uint16_t)0x00FF)
/******************* Bit definition for CAN_FF register *******************/
#define CAN_FF_RTR ((uint16_t)0x0040)
#define CAN_FF_FF ((uint16_t)0x0080)
#define CAN_FF_RTR ((uint16_t)0x0040)
#define CAN_FF_FF ((uint16_t)0x0080)
#define CAN_FF_DLC ((uint16_t)0x000F)
#define CAN_FF_DLC_0 ((uint16_t)0x0001)
#define CAN_FF_DLC_1 ((uint16_t)0x0002)
#define CAN_FF_DLC_2 ((uint16_t)0x0004)
#define CAN_FF_DLC_3 ((uint16_t)0x0008)
#define CAN_FF_DLC ((uint16_t)0x000F)
#define CAN_FF_DLC_0 ((uint16_t)0x0001)
#define CAN_FF_DLC_1 ((uint16_t)0x0002)
#define CAN_FF_DLC_2 ((uint16_t)0x0004)
#define CAN_FF_DLC_3 ((uint16_t)0x0008)
/******************* Bit definition for CAN_ACR0 register *******************/
#define CAN_ACR0_AC ((uint16_t)0x00FF)

34
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_adc.h
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@ -95,14 +95,14 @@ typedef struct
* @brief for ADC1, ADC2
*/
#define ADC_PCLK2_PRESCARE_2 ((uint32_t)0x00000000)
#define ADC_PCLK2_PRESCARE_4 ((uint32_t)0x00000010)
#define ADC_PCLK2_PRESCARE_6 ((uint32_t)0x00000020)
#define ADC_PCLK2_PRESCARE_8 ((uint32_t)0x00000030)
#define ADC_PCLK2_PRESCARE_10 ((uint32_t)0x00000040)
#define ADC_PCLK2_PRESCARE_12 ((uint32_t)0x00000050)
#define ADC_PCLK2_PRESCARE_14 ((uint32_t)0x00000060)
#define ADC_PCLK2_PRESCARE_16 ((uint32_t)0x00000070)
#define ADC_PCLK2_PRESCARE_2 ((uint32_t)0x00000000)
#define ADC_PCLK2_PRESCARE_4 ((uint32_t)0x00000010)
#define ADC_PCLK2_PRESCARE_6 ((uint32_t)0x00000020)
#define ADC_PCLK2_PRESCARE_8 ((uint32_t)0x00000030)
#define ADC_PCLK2_PRESCARE_10 ((uint32_t)0x00000040)
#define ADC_PCLK2_PRESCARE_12 ((uint32_t)0x00000050)
#define ADC_PCLK2_PRESCARE_14 ((uint32_t)0x00000060)
#define ADC_PCLK2_PRESCARE_16 ((uint32_t)0x00000070)
@ -133,14 +133,14 @@ typedef struct
* @brief for ADC1
*/
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00000010)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00000020)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00000030)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00000040)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x00000050)
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000060)
#define ADC_ExternalTrigConv_EXTI_11 ((uint32_t)0x00000070)
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00000010)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00000020)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00000030)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00000040)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x00000050)
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000060)
#define ADC_ExternalTrigConv_EXTI_11 ((uint32_t)0x00000070)
/**
* @brief for ADC2
@ -202,7 +202,7 @@ typedef struct
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_All ((uint8_t)0x0f)
#define ADC_Channel_All ((uint8_t)0x0f)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \

66
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_can.h
View File

@ -16,7 +16,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_CAN_H
#define __HAL_CAN_H
@ -66,13 +66,13 @@
*/
#define CAN_BASICMode ((uint32_t)0x0)
#define CAN_PELIMode ((uint32_t)0x80)
#define CAN_WorkMode ((uint32_t)0x80)
#define CAN_ResetMode ((uint32_t)0x1)
#define CAN_ListenOnlyMode ((uint32_t)0x2)
#define CAN_SeftTestMode ((uint32_t)0x4)
#define CAN_FilterMode_Singal ((uint32_t)0x8)
#define CAN_FilterMode_Double ((uint32_t)0xf7)
#define CAN_SleepMode ((uint32_t)0x10)
#define CAN_WorkMode ((uint32_t)0x80)
#define CAN_ResetMode ((uint32_t)0x1)
#define CAN_ListenOnlyMode ((uint32_t)0x2)
#define CAN_SeftTestMode ((uint32_t)0x4)
#define CAN_FilterMode_Singal ((uint32_t)0x8)
#define CAN_FilterMode_Double ((uint32_t)0xf7)
#define CAN_SleepMode ((uint32_t)0x10)
/**
* @}
@ -81,10 +81,10 @@
/**
* @brief parasmeter of BASIC CAN interrupt
*/
#define CAN_IT_RIE ((uint32_t)0x2)
#define CAN_IT_TIE ((uint32_t)0x4)
#define CAN_IT_EIE ((uint32_t)0x8)
#define CAN_IT_OIE ((uint32_t)0x10)
#define CAN_IT_RIE ((uint32_t)0x2)
#define CAN_IT_TIE ((uint32_t)0x4)
#define CAN_IT_EIE ((uint32_t)0x8)
#define CAN_IT_OIE ((uint32_t)0x10)
/**
* @}
@ -93,15 +93,15 @@
/**
* @brief parasmeter of PELI CAN interrupt
*/
#define CAN_IT_RI ((uint32_t)0x1)
#define CAN_IT_TI ((uint32_t)0x2)
#define CAN_IT_EI ((uint32_t)0x4)
#define CAN_IT_DOI ((uint32_t)0x8)
#define CAN_IT_WUI ((uint32_t)0x10)
#define CAN_IT_EPI ((uint32_t)0x20)
#define CAN_IT_ALI ((uint32_t)0x40)
#define CAN_IT_BEI ((uint32_t)0x80)
#define CAN_IT_ALL ((uint32_t)0xff)
#define CAN_IT_RI ((uint32_t)0x1)
#define CAN_IT_TI ((uint32_t)0x2)
#define CAN_IT_EI ((uint32_t)0x4)
#define CAN_IT_DOI ((uint32_t)0x8)
#define CAN_IT_WUI ((uint32_t)0x10)
#define CAN_IT_EPI ((uint32_t)0x20)
#define CAN_IT_ALI ((uint32_t)0x40)
#define CAN_IT_BEI ((uint32_t)0x80)
#define CAN_IT_ALL ((uint32_t)0xff)
/**
* @}
@ -110,14 +110,14 @@
/**
* @brief parasmeter of CAN Status
*/
#define CAN_STATUS_RBS ((uint32_t)0x1)
#define CAN_STATUS_DOS ((uint32_t)0x2)
#define CAN_STATUS_TBS ((uint32_t)0x4)
#define CAN_STATUS_TCS ((uint32_t)0x8)
#define CAN_STATUS_RS ((uint32_t)0x10)
#define CAN_STATUS_TS ((uint32_t)0x20)
#define CAN_STATUS_ES ((uint32_t)0x40)
#define CAN_STATUS_BS ((uint32_t)0x80)
#define CAN_STATUS_RBS ((uint32_t)0x1)
#define CAN_STATUS_DOS ((uint32_t)0x2)
#define CAN_STATUS_TBS ((uint32_t)0x4)
#define CAN_STATUS_TCS ((uint32_t)0x8)
#define CAN_STATUS_RS ((uint32_t)0x10)
#define CAN_STATUS_TS ((uint32_t)0x20)
#define CAN_STATUS_ES ((uint32_t)0x40)
#define CAN_STATUS_BS ((uint32_t)0x80)
/**
* @}
@ -126,10 +126,10 @@
/**
* @brief parasmeter of CAN Command register
*/
#define CAN_TR 0x1
#define CAN_AT 0x2
#define CAN_RRB 0x4
#define CAN_CDO 0x8
#define CAN_TR 0x1
#define CAN_AT 0x2
#define CAN_RRB 0x4
#define CAN_CDO 0x8
/**
* @}

38
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_dma.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the DMA firmware
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_DMA_H
@ -38,7 +38,7 @@
* @{
*/
/**
/**
* @brief DMA Init structure definition
*/
@ -71,9 +71,9 @@ typedef struct
((*(uint32_t*)&(PERIPH)) == DMA1_Channel4_BASE) || \
((*(uint32_t*)&(PERIPH)) == DMA1_Channel5_BASE))
/** @defgroup DMA_data_transfer_direction
/** @defgroup DMA_data_transfer_direction
* @{
*/
@ -85,7 +85,7 @@ typedef struct
* @}
*/
/** @defgroup DMA_peripheral_incremented_mode
/** @defgroup DMA_peripheral_incremented_mode
* @{
*/
@ -97,7 +97,7 @@ typedef struct
* @}
*/
/** @defgroup DMA_memory_incremented_mode
/** @defgroup DMA_memory_incremented_mode
* @{
*/
@ -109,7 +109,7 @@ typedef struct
* @}
*/
/** @defgroup DMA_peripheral_data_size
/** @defgroup DMA_peripheral_data_size
* @{
*/
@ -123,7 +123,7 @@ typedef struct
* @}
*/
/** @defgroup DMA_memory_data_size
/** @defgroup DMA_memory_data_size
* @{
*/
@ -137,7 +137,7 @@ typedef struct
* @}
*/
/** @defgroup DMA_circular_normal_mode
/** @defgroup DMA_circular_normal_mode
* @{
*/
@ -148,7 +148,7 @@ typedef struct
* @}
*/
/** @defgroup DMA_priority_level
/** @defgroup DMA_priority_level
* @{
*/
@ -164,7 +164,7 @@ typedef struct
* @}
*/
/** @defgroup DMA_memory_to_memory
/** @defgroup DMA_memory_to_memory
* @{
*/
@ -176,7 +176,7 @@ typedef struct
* @}
*/
/** @defgroup DMA_interrupts_definition
/** @defgroup DMA_interrupts_definition
* @{
*/
@ -185,7 +185,7 @@ typedef struct
#define DMA_IT_TE ((uint32_t)0x00000008)
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
/**
/**
* @brief For DMA1
*/
@ -262,11 +262,11 @@ typedef struct
* @}
*/
/** @defgroup DMA_flags_definition
/** @defgroup DMA_flags_definition
* @{
*/
/**
/**
* @brief For DMA1
*/
@ -352,13 +352,13 @@ typedef struct
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5))
/**
* @}
*/
/** @defgroup DMA_Buffer_Size
/** @defgroup DMA_Buffer_Size
* @{
*/

26
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_exti.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the EXTI
* @brief This file contains all the functions prototypes for the EXTI
* firmware library.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_EXTI_H
@ -38,8 +38,8 @@
* @{
*/
/**
* @brief EXTI mode enumeration
/**
* @brief EXTI mode enumeration
*/
typedef enum
@ -50,22 +50,22 @@ typedef enum
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
/**
* @brief EXTI Trigger enumeration
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
}EXTITrigger_TypeDef;
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling) || \
((TRIGGER) == EXTI_Trigger_Rising_Falling))
/**
* @brief EXTI Init Structure definition
/**
* @brief EXTI Init Structure definition
*/
typedef struct
@ -84,7 +84,7 @@ typedef struct
* @{
*/
/** @defgroup EXTI_Lines
/** @defgroup EXTI_Lines
* @{
*/
@ -106,10 +106,10 @@ typedef struct
#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16
Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17
#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17
Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18
Connected to the USB Wakeup from
#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18
Connected to the USB Wakeup from
suspend event */
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF80000) == 0x00) && ((LINE) != (uint16_t)0x00))

32
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_flash.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the FLASH
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_FLASH_H
@ -38,12 +38,12 @@
* @{
*/
/**
* @brief FLASH Status
/**
* @brief FLASH Status
*/
typedef enum
{
{
FLASH_BUSY = 1,
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
@ -59,7 +59,7 @@ typedef enum
* @{
*/
/** @defgroup Flash_Latency
/** @defgroup Flash_Latency
* @{
*/
@ -75,31 +75,31 @@ typedef enum
* @}
*/
/** @defgroup Half_Cycle_Enable_Disable
/** @defgroup Half_Cycle_Enable_Disable
* @{
*/
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
((STATE) == FLASH_HalfCycleAccess_Disable))
((STATE) == FLASH_HalfCycleAccess_Disable))
/**
* @}
*/
/** @defgroup Prefetch_Buffer_Enable_Disable
/** @defgroup Prefetch_Buffer_Enable_Disable
* @{
*/
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
((STATE) == FLASH_PrefetchBuffer_Disable))
((STATE) == FLASH_PrefetchBuffer_Disable))
/**
* @}
*/
/** @defgroup Option_Bytes_Write_Protection
/** @defgroup Option_Bytes_Write_Protection
* @{
*/
@ -184,7 +184,7 @@ ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
* @}
*/
/** @defgroup Option_Bytes_IWatchdog
/** @defgroup Option_Bytes_IWatchdog
* @{
*/
@ -196,7 +196,7 @@ ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
* @}
*/
/** @defgroup Option_Bytes_nRST_STOP
/** @defgroup Option_Bytes_nRST_STOP
* @{
*/
@ -208,7 +208,7 @@ ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
* @}
*/
/** @defgroup Option_Bytes_nRST_STDBY
/** @defgroup Option_Bytes_nRST_STDBY
* @{
*/
@ -220,7 +220,7 @@ ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
* @}
*/
/** @defgroup FLASH_Interrupts
/** @defgroup FLASH_Interrupts
* @{
*/
@ -232,7 +232,7 @@ ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
* @}
*/
/** @defgroup FLASH_Flags
/** @defgroup FLASH_Flags
* @{
*/

12
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_gpio.h
View File

@ -216,16 +216,16 @@ typedef enum
#define GPIO_AF_MCO_SW ((uint8_t)0x00) /* MC0, SWDIO,SWCLK */
#define GPIO_AF_TIM_1_2 ((uint8_t)0x01) /* TIM 1/2 */
#define GPIO_AF_TIM_34567 ((uint8_t)0x02) /* TIM 3/4/5/6/7 */
#define GPIO_AF_TIM_34567 ((uint8_t)0x02) /* TIM 3/4/5/6/7 */
#define GPIO_AF_I2S ((uint8_t)0x03)
#define GPIO_AF_I2C ((uint8_t)0x04) /* I2C 1/2/3 */
#define GPIO_AF_SPI ((uint8_t)0x05) /* SPI 1/2/3/4 */
#define GPIO_AF_QSPI ((uint8_t)0x06)
#define GPIO_AF_QSPI ((uint8_t)0x06)
#define GPIO_AF_UART_2345 ((uint8_t)0x07) /* UART 2/3/4/5 */
#define GPIO_AF_UART_1 ((uint8_t)0x08)
#define GPIO_AF_CAN ((uint8_t)0x09) /* CAN 1/2 */
#define GPIO_AF_USB ((uint8_t)0x0A)
#define GPIO_AF_GPIO ((uint8_t)0x0B) /* Normal GPIO */
#define GPIO_AF_UART_1 ((uint8_t)0x08)
#define GPIO_AF_CAN ((uint8_t)0x09) /* CAN 1/2 */
#define GPIO_AF_USB ((uint8_t)0x0A)
#define GPIO_AF_GPIO ((uint8_t)0x0B) /* Normal GPIO */
#define GPIO_AF_TK80_SDIO ((uint8_t)0x0C) /* TK80 SDIO 1/2 */
#define GPIO_AF_Touchpad ((uint8_t)0x0D)
#define GPIO_AF_LTDC ((uint8_t)0x0E) /* RGB_LTDC AF */

154
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_i2c.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the I2C firmware
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_I2C_H
@ -38,8 +38,8 @@
* @{
*/
/**
* @brief I2C Init structure definition
/**
* @brief I2C Init structure definition
*/
/*
typedef struct
@ -62,7 +62,7 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup I2C_Exported_Constants
@ -71,27 +71,27 @@ typedef struct
#define IS_I2C_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == I2C1_BASE) || \
((*(uint32_t*)&(PERIPH)) == I2C2_BASE))
/** @defgroup I2C_modes
/** @defgroup I2C_modes
* @{
*/
#define TX_EMPTY_CTRL (0x0001<<8)
#define IC_SLAVE_DISABLE (0x0001<<6)
#define IC_SLAVE_ENABLE (0x0000<<6)
#define IC_RESTART_EN (0x0001<<5)
#define IC_7BITADDR_MASTER (0x0000<<4)
#define IC_7BITADDR_SLAVE (0x0000<<3)
#define TX_EMPTY_CTRL (0x0001<<8)
#define IC_SLAVE_DISABLE (0x0001<<6)
#define IC_SLAVE_ENABLE (0x0000<<6)
#define IC_RESTART_EN (0x0001<<5)
#define IC_7BITADDR_MASTER (0x0000<<4)
#define IC_7BITADDR_SLAVE (0x0000<<3)
#define I2C_Speed_STANDARD ((uint16_t)0x0002)
#define I2C_Speed_FAST ((uint16_t)0x0004)
#define I2C_Mode_MASTER ((uint16_t)0x0001)
#define I2C_Mode_SLAVE ((uint16_t)0x0000)
#define I2C_Speed_STANDARD ((uint16_t)0x0002)
#define I2C_Speed_FAST ((uint16_t)0x0004)
#define I2C_Mode_MASTER ((uint16_t)0x0001)
#define I2C_Mode_SLAVE ((uint16_t)0x0000)
#define TDMAE_SET ((uint16_t)0x0002)
#define RDMAE_SET ((uint16_t)0x0001)
#define TDMAE_SET ((uint16_t)0x0002)
#define RDMAE_SET ((uint16_t)0x0001)
#define CMD_READ ((uint16_t)0x0100)
#define CMD_WRITE ((uint16_t)0x0000)
#define CMD_READ ((uint16_t)0x0100)
#define CMD_WRITE ((uint16_t)0x0000)
@ -105,7 +105,7 @@ typedef struct
*/
/** @defgroup I2C_transfer_direction
/** @defgroup I2C_transfer_direction
* @{
*/
@ -117,7 +117,7 @@ typedef struct
* @}
*/
/** @defgroup I2C_acknowledged_address_defines
/** @defgroup I2C_acknowledged_address_defines
* @{
*/
@ -128,9 +128,9 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup I2C_interrupts_definition
/** @defgroup I2C_interrupts_definition
* @{
*/
@ -138,24 +138,24 @@ typedef struct
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
*/
/** @defgroup I2C_interrupts_definition
/** @defgroup I2C_interrupts_definition
* @{
*/
#define I2C_IT_RX_UNDER ((uint16_t)0x0001)
#define I2C_IT_RX_OVER ((uint16_t)0x0002)
#define I2C_IT_RX_FULL ((uint16_t)0x0004)
#define I2C_IT_TX_OVER ((uint16_t)0x0008)
#define I2C_IT_TX_EMPTY ((uint16_t)0x0010)
#define I2C_IT_RD_REQ ((uint16_t)0x0020)
#define I2C_IT_TX_ABRT ((uint16_t)0x0040)
#define I2C_IT_RX_DONE ((uint16_t)0x0080)
#define I2C_IT_ACTIVITY ((uint16_t)0x0100)
#define I2C_IT_STOP_DET ((uint16_t)0x0200)
#define I2C_IT_START_DET ((uint16_t)0x0400)
#define I2C_IT_GEN_CALL ((uint16_t)0x0800)
#define I2C_IT_RX_UNDER ((uint16_t)0x0001)
#define I2C_IT_RX_OVER ((uint16_t)0x0002)
#define I2C_IT_RX_FULL ((uint16_t)0x0004)
#define I2C_IT_TX_OVER ((uint16_t)0x0008)
#define I2C_IT_TX_EMPTY ((uint16_t)0x0010)
#define I2C_IT_RD_REQ ((uint16_t)0x0020)
#define I2C_IT_TX_ABRT ((uint16_t)0x0040)
#define I2C_IT_RX_DONE ((uint16_t)0x0080)
#define I2C_IT_ACTIVITY ((uint16_t)0x0100)
#define I2C_IT_STOP_DET ((uint16_t)0x0200)
#define I2C_IT_START_DET ((uint16_t)0x0400)
#define I2C_IT_GEN_CALL ((uint16_t)0x0800)
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0xF000) == 0x00) && ((IT) != (uint16_t)0x00))
@ -169,24 +169,24 @@ typedef struct
* @}
*/
/** @defgroup I2C_flags_definition
/** @defgroup I2C_flags_definition
* @{
*/
#define I2C_FLAG_RX_UNDER ((uint16_t)0x0001)
#define I2C_FLAG_RX_OVER ((uint16_t)0x0002)
#define I2C_FLAG_RX_FULL ((uint16_t)0x0004)
#define I2C_FLAG_TX_OVER ((uint16_t)0x0008)
#define I2C_FLAG_TX_EMPTY ((uint16_t)0x0010)
#define I2C_FLAG_RD_REQ ((uint16_t)0x0020)
#define I2C_FLAG_TX_ABRT ((uint16_t)0x0040)
#define I2C_FLAG_RX_DONE ((uint16_t)0x0080)
#define I2C_FLAG_ACTIVITY ((uint16_t)0x0100)
#define I2C_FLAG_STOP_DET ((uint16_t)0x0200)
#define I2C_FLAG_START_DET ((uint16_t)0x0400)
#define I2C_FLAG_GEN_CALL ((uint16_t)0x0800)
#define I2C_FLAG_RX_UNDER ((uint16_t)0x0001)
#define I2C_FLAG_RX_OVER ((uint16_t)0x0002)
#define I2C_FLAG_RX_FULL ((uint16_t)0x0004)
#define I2C_FLAG_TX_OVER ((uint16_t)0x0008)
#define I2C_FLAG_TX_EMPTY ((uint16_t)0x0010)
#define I2C_FLAG_RD_REQ ((uint16_t)0x0020)
#define I2C_FLAG_TX_ABRT ((uint16_t)0x0040)
#define I2C_FLAG_RX_DONE ((uint16_t)0x0080)
#define I2C_FLAG_ACTIVITY ((uint16_t)0x0100)
#define I2C_FLAG_STOP_DET ((uint16_t)0x0200)
#define I2C_FLAG_START_DET ((uint16_t)0x0400)
#define I2C_FLAG_GEN_CALL ((uint16_t)0x0800)
@ -203,40 +203,40 @@ typedef struct
((FLAG) == I2C_FLAG_START_DET) || ((FLAG) == I2C_FLAG_GEN_CALL))
/** @defgroup I2C_Statusflags_definition
/** @defgroup I2C_Statusflags_definition
* @{
*/
#define I2C_STATUS_FLAG_ACTIVITY ((uint16_t)0x0001)
#define I2C_STATUS_FLAG_TFNF ((uint16_t)0x0002)
#define I2C_STATUS_FLAG_TFE ((uint16_t)0x0004)
#define I2C_STATUS_FLAG_RFNE ((uint16_t)0x0008)
#define I2C_STATUS_FLAG_RFF ((uint16_t)0x0010)
#define I2C_STATUS_FLAG_M_ACTIVITY ((uint16_t)0x0020)
#define I2C_STATUS_FLAG_S_ACTIVITY ((uint16_t)0x0040)
#define I2C_STATUS_FLAG_ACTIVITY ((uint16_t)0x0001)
#define I2C_STATUS_FLAG_TFNF ((uint16_t)0x0002)
#define I2C_STATUS_FLAG_TFE ((uint16_t)0x0004)
#define I2C_STATUS_FLAG_RFNE ((uint16_t)0x0008)
#define I2C_STATUS_FLAG_RFF ((uint16_t)0x0010)
#define I2C_STATUS_FLAG_M_ACTIVITY ((uint16_t)0x0020)
#define I2C_STATUS_FLAG_S_ACTIVITY ((uint16_t)0x0040)
/**
* @}
*/
/** @defgroup I2C_Events
/** @defgroup I2C_Events
* @{
*/
#define I2C_EVENT_RX_UNDER ((uint32_t)0x0001)
#define I2C_EVENT_RX_OVER ((uint32_t)0x0002)
#define I2C_EVENT_RX_FULL ((uint32_t)0x0004)
#define I2C_EVENT_TX_OVER ((uint32_t)0x0008)
#define I2C_EVENT_TX_EMPTY ((uint32_t)0x0010)
#define I2C_EVENT_RD_REQ ((uint32_t)0x0020)
#define I2C_EVENT_TX_ABRT ((uint32_t)0x0040)
#define I2C_EVENT_RX_DONE ((uint32_t)0x0080)
#define I2C_EVENT_ACTIVITY ((uint32_t)0x0100)
#define I2C_EVENT_STOP_DET ((uint32_t)0x0200)
#define I2C_EVENT_START_DET ((uint32_t)0x0400)
#define I2C_EVENT_GEN_CALL ((uint32_t)0x0800)
#define I2C_EVENT_RX_UNDER ((uint32_t)0x0001)
#define I2C_EVENT_RX_OVER ((uint32_t)0x0002)
#define I2C_EVENT_RX_FULL ((uint32_t)0x0004)
#define I2C_EVENT_TX_OVER ((uint32_t)0x0008)
#define I2C_EVENT_TX_EMPTY ((uint32_t)0x0010)
#define I2C_EVENT_RD_REQ ((uint32_t)0x0020)
#define I2C_EVENT_TX_ABRT ((uint32_t)0x0040)
#define I2C_EVENT_RX_DONE ((uint32_t)0x0080)
#define I2C_EVENT_ACTIVITY ((uint32_t)0x0100)
#define I2C_EVENT_STOP_DET ((uint32_t)0x0200)
#define I2C_EVENT_START_DET ((uint32_t)0x0400)
#define I2C_EVENT_GEN_CALL ((uint32_t)0x0800)
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_RX_UNDER) || \
@ -253,7 +253,7 @@ typedef struct
* @}
*/
/** @defgroup I2C_own_address1
/** @defgroup I2C_own_address1
* @{
*/
@ -262,7 +262,7 @@ typedef struct
* @}
*/
/** @defgroup I2C_clock_speed
/** @defgroup I2C_clock_speed
* @{
*/
@ -317,14 +317,14 @@ void I2C_ReadCmd(I2C_TypeDef* I2Cx);
#endif /*__HAL_I2C_H */
/**
* @}
*/
*/
/**
* @}
*/
*/
/**
* @}
*/
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

10
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_iwdg.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the IWDG
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_IWDG_H
@ -46,7 +46,7 @@
* @{
*/
/** @defgroup Write_access_to_IWDG_PR_and_IWDG_RLR_registers
/** @defgroup Write_access_to_IWDG_PR_and_IWDG_RLR_registers
* @{
*/
@ -58,7 +58,7 @@
* @}
*/
/** @defgroup IWDG_prescaler
/** @defgroup IWDG_prescaler
* @{
*/
@ -80,7 +80,7 @@
* @}
*/
/** @defgroup IWDG_Flag
/** @defgroup IWDG_Flag
* @{
*/

16
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_misc.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the
* @brief This file contains all the functions prototypes for the
* miscellaneous firmware library functions.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MISC_H
@ -38,8 +38,8 @@
* @{
*/
/**
* @brief NVIC Init Structure definition
/**
* @brief NVIC Init Structure definition
*/
typedef struct
@ -58,7 +58,7 @@ typedef struct
* @{
*/
/** @defgroup Vector_Table_Base
/** @defgroup Vector_Table_Base
* @{
*/
@ -70,7 +70,7 @@ typedef struct
* @}
*/
/** @defgroup System_Low_Power
/** @defgroup System_Low_Power
* @{
*/
@ -84,7 +84,7 @@ typedef struct
* @}
*/
/** @defgroup Preemption_Priority_Group
/** @defgroup Preemption_Priority_Group
* @{
*/
@ -115,7 +115,7 @@ typedef struct
* @}
*/
/** @defgroup SysTick_clock_source
/** @defgroup SysTick_clock_source
* @{
*/

22
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_pwr.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the PWR firmware
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_PWR_H
@ -32,23 +32,23 @@
/** @addtogroup PWR
* @{
*/
*/
/** @defgroup PWR_Exported_Types
* @{
*/
*/
/**
* @}
*/
*/
/** @defgroup PWR_Exported_Constants
* @{
*/
*/
/** @defgroup PVD_detection_level
/** @defgroup PVD_detection_level
* @{
*/
*/
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000000)
#define PWR_PVDLevel_2V8 ((uint32_t)0x00000200)
@ -71,7 +71,7 @@
* @}
*/
/** @defgroup Regulator_state_is_STOP_mode
/** @defgroup Regulator_state_is_STOP_mode
* @{
*/
@ -83,7 +83,7 @@
* @}
*/
/** @defgroup STOP_mode_entry
/** @defgroup STOP_mode_entry
* @{
*/
@ -95,7 +95,7 @@
* @}
*/
/** @defgroup PWR_Flag
/** @defgroup PWR_Flag
* @{
*/

50
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_rcc.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the RCC firmware
* @brief This file contains all the functions prototypes for the RCC firmware
* library.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_RCC_H
@ -55,7 +55,7 @@ typedef struct
* @{
*/
/** @defgroup HSE_configuration
/** @defgroup HSE_configuration
* @{
*/
@ -67,9 +67,9 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup PLL_entry_clock_source
/** @defgroup PLL_entry_clock_source
* @{
*/
@ -81,10 +81,10 @@ typedef struct
((SOURCE) == RCC_PLLSource_HSE_Div2))
/**
* @}
*/
*/
/** @defgroup System_clock_source
/** @defgroup System_clock_source
* @{
*/
@ -98,7 +98,7 @@ typedef struct
* @}
*/
/** @defgroup AHB_clock_source
/** @defgroup AHB_clock_source
* @{
*/
@ -118,9 +118,9 @@ typedef struct
((HCLK) == RCC_SYSCLK_Div512))
/**
* @}
*/
*/
/** @defgroup APB1_APB2_clock_source
/** @defgroup APB1_APB2_clock_source
* @{
*/
@ -135,9 +135,9 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup PLL_multiplication_factor
/** @defgroup PLL_multiplication_factor
* @{
*/
@ -178,14 +178,14 @@ typedef struct
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
((MUL) == RCC_PLLMul_16))
((MUL) == RCC_PLLMul_16))
/**
* @}
*/
/** @defgroup RCC_Interrupt_source
/** @defgroup RCC_Interrupt_source
* @{
*/
@ -205,7 +205,7 @@ typedef struct
* @}
*/
/** @defgroup USB_clock_source
/** @defgroup USB_clock_source
* @{
*/
@ -217,7 +217,7 @@ typedef struct
* @}
*/
/** @defgroup ADC_clock_source
/** @defgroup ADC_clock_source
* @{
*/
@ -231,7 +231,7 @@ typedef struct
* @}
*/
/** @defgroup LSE_configuration
/** @defgroup LSE_configuration
* @{
*/
@ -244,7 +244,7 @@ typedef struct
* @}
*/
/** @defgroup RTC_clock_source
/** @defgroup RTC_clock_source
* @{
*/
@ -258,7 +258,7 @@ typedef struct
* @}
*/
/** @defgroup AHB_peripheral
/** @defgroup AHB_peripheral
* @{
*/
@ -282,7 +282,7 @@ typedef struct
* @}
*/
/** @defgroup APB2_peripheral
/** @defgroup APB2_peripheral
* @{
*/
@ -313,9 +313,9 @@ typedef struct
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFC0002) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
*/
/** @defgroup APB1_peripheral
/** @defgroup APB1_peripheral
* @{
*/
@ -356,7 +356,7 @@ typedef struct
* @}
*/
/** @defgroup Clock_source_to_output_on_MCO_pin
/** @defgroup Clock_source_to_output_on_MCO_pin
* @{
*/
@ -375,7 +375,7 @@ typedef struct
* @}
*/
/** @defgroup RCC_Flag
/** @defgroup RCC_Flag
* @{
*/
@ -462,6 +462,6 @@ void getSystemClock(u32 *sysclk);
/**
* @}
*/
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

58
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_spi.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the SPI firmware
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_SPI_H
@ -32,14 +32,14 @@
/** @addtogroup SPI
* @{
*/
*/
/** @defgroup SPI_Exported_Types
* @{
*/
/**
* @brief SPI Init structure definition
/**
* @brief SPI Init structure definition
*/
typedef struct
@ -51,7 +51,7 @@ typedef struct
uint16_t SPI_CPHA;
uint16_t SPI_NSS;
uint16_t SPI_BaudRatePrescaler;
uint16_t SPI_FirstBit;
uint16_t SPI_FirstBit;
}SPI_InitTypeDef;
@ -73,7 +73,7 @@ typedef struct
* @}
*/
/** @defgroup SPI_master_slave_mode
/** @defgroup SPI_master_slave_mode
* @{
*/
@ -85,7 +85,7 @@ typedef struct
* @}
*/
/** @defgroup SPI_data_size
/** @defgroup SPI_data_size
* @{
*/
@ -99,7 +99,7 @@ typedef struct
*/
/** @defgroup SPI_7bit_8bit data width
/** @defgroup SPI_7bit_8bit data width
* @{
*/
@ -112,7 +112,7 @@ typedef struct
*/
/** @defgroup SPI_Clock_Polarity
/** @defgroup SPI_Clock_Polarity
* @{
*/
@ -124,7 +124,7 @@ typedef struct
* @}
*/
/** @defgroup SPI_Clock_Phase
/** @defgroup SPI_Clock_Phase
* @{
*/
@ -136,7 +136,7 @@ typedef struct
* @}
*/
/** @defgroup SPI_Slave_Select_management
/** @defgroup SPI_Slave_Select_management
* @{
*/
@ -150,7 +150,7 @@ typedef struct
* @}
*/
/** @defgroup SPI_NSS_internal_software_mangement
/** @defgroup SPI_NSS_internal_software_mangement
* @{
*/
@ -164,9 +164,9 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup SPI_BaudRate_Prescaler_
/** @defgroup SPI_BaudRate_Prescaler_
* @{
*/
@ -189,9 +189,9 @@ typedef struct
((PRESCALER) == SPI_BaudRatePrescaler_256))
/**
* @}
*/
*/
/** @defgroup SPI_MSB_LSB_transmission
/** @defgroup SPI_MSB_LSB_transmission
* @{
*/
@ -205,11 +205,11 @@ typedef struct
* @}
*/
/** @defgroup SPI_DMA_transfer_requests
/** @defgroup SPI_DMA_transfer_requests
* @{
*/
#define SPI_DMAReq_EN ((uint16_t)0x0200)
#define SPI_DMAReq_EN ((uint16_t)0x0200)
#define IS_SPI_DMAREQ(DMAREQ) ((DMAREQ) == SPI_DMAReq_EN)
@ -217,11 +217,11 @@ typedef struct
* @}
*/
/** @defgroup SPI TX Fifo and RX Fifo trigger level
/** @defgroup SPI TX Fifo and RX Fifo trigger level
* @{
*/
#define SPI_TXTLF ((uint16_t)0x0080)
#define SPI_RXTLF ((uint16_t)0x0020)
#define SPI_TXTLF ((uint16_t)0x0080)
#define SPI_RXTLF ((uint16_t)0x0020)
#define IS_SPI_FIFOTRIGGER(TRIGGER) (((TRIGGER) == SPI_TXTLF) && ((TRIGGER) == SPI_RXTLF))
@ -234,7 +234,7 @@ typedef struct
* @}
*/
/** @defgroup SPI_NSS_internal_software_mangement
/** @defgroup SPI_NSS_internal_software_mangement
* @{
*/
@ -255,14 +255,14 @@ typedef struct
*/
/** @defgroup SPI_direction_transmit_receive
/** @defgroup SPI_direction_transmit_receive
* @{
*/
#define SPI_Direction_Rx ((uint16_t)0x0010)
#define SPI_Direction_Tx ((uint16_t)0x0008)
#define SPI_Disable_Tx ((uint16_t)0xfff7)
#define SPI_Disable_Rx ((uint16_t)0xffef)
#define SPI_Disable_Tx ((uint16_t)0xfff7)
#define SPI_Disable_Rx ((uint16_t)0xffef)
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
((DIRECTION) == SPI_Direction_Tx) || \
((DIRECTION) == SPI_Disable_Tx) || \
@ -271,7 +271,7 @@ typedef struct
* @}
*/
/** @defgroup SPI_interrupts_definition
/** @defgroup SPI_interrupts_definition
* @{
*/
#define SPI_INT_EN ((uint16_t)0x0002)
@ -296,7 +296,7 @@ typedef struct
* @}
*/
/** @defgroup SPI_flags_definition
/** @defgroup SPI_flags_definition
* @{
*/
@ -311,7 +311,7 @@ typedef struct
* @}
*/
/** @defgroup SPI mode tx data transmit phase adjust set
/** @defgroup SPI mode tx data transmit phase adjust set
*in slave mode according to txedge bit of CCTL register
* @{
*/

44
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_syscfg.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the SYSCFG firmware
* @brief This file contains all the functions prototypes for the SYSCFG firmware
* library.
******************************************************************************
* @attention
@ -20,47 +20,47 @@
#ifdef __cplusplus
extern "C" {
#endif
/*!< Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup SYSCFG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSCFG_Exported_Constants
* @{
*/
/** @defgroup SYSCFG_EXTI_Port_Sources
*/
/** @defgroup SYSCFG_EXTI_Port_Sources
* @{
*/
*/
#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
((PORTSOURCE) == EXTI_PortSourceGPIOF))
((PORTSOURCE) == EXTI_PortSourceGPIOF))
/**
* @}
*/
/** @defgroup SYSCFG_EXTI_Pin_sources
/** @defgroup SYSCFG_EXTI_Pin_sources
* @{
*/
*/
#define EXTI_PinSource0 ((uint8_t)0x00)
#define EXTI_PinSource1 ((uint8_t)0x01)
#define EXTI_PinSource2 ((uint8_t)0x02)
@ -98,9 +98,9 @@ extern "C" {
* @}
*/
/** @defgroup SYSCFG_Memory_Remap_Config
/** @defgroup SYSCFG_Memory_Remap_Config
* @{
*/
*/
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
@ -114,9 +114,9 @@ extern "C" {
* @}
*/
/** @defgroup SYSCFG_DMA_Remap_Config
/** @defgroup SYSCFG_DMA_Remap_Config
* @{
*/
*/
#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */
#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */
#define SYSCFG_DMARemap_UART1Rx SYSCFG_CFGR1_UART1RX_DMA_RMP /* Remap UART1 Rx DMA requests from channel3 to channel5 */
@ -152,7 +152,7 @@ extern "C" {
/* Function used to set the SYSCFG configuration to the default reset state **/
void SYSCFG_DeInit(void);
/* SYSCFG configuration functions *********************************************/
/* SYSCFG configuration functions *********************************************/
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
@ -171,10 +171,10 @@ void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
/**
* @}
*/
*/
/**
* @}
*/
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

246
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_tim.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the TIM firmware
* @brief This file contains all the functions prototypes for the TIM firmware
* library.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_TIM_H
@ -26,62 +26,62 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup TIM
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/**
/**
* @brief TIM Time Base Init structure definition
* @note This sturcture is used with all TIMx.
*/
typedef struct
{
uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
This parameter can be a value of @ref TIM_Counter_Mode */
uint32_t TIM_Period;
/*!< Auto-Reload Register at the next update event.
This parameter must be a number between 0x0000 and 0xFFFF. */
This parameter must be a number between 0x0000 and 0xFFFF. */
uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_Clock_Division_CKD */
uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
This parameter must be a number between 0x00 and 0xFF.
@note This parameter is valid only for TIM1. */
} TIM_TimeBaseInitTypeDef;
/**
* @brief TIM Output Compare Init structure definition
} TIM_TimeBaseInitTypeDef;
/**
* @brief TIM Output Compare Init structure definition
*/
typedef struct
{
uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_state */
uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_N_state
@note This parameter is valid only for TIM1. */
@ -93,8 +93,8 @@ extern "C" {
uint16_t TIM_OCNIdleState;
} TIM_OCInitTypeDef;
/**
* @brief TIM Input Capture Init structure definition
/**
* @brief TIM Input Capture Init structure definition
*/
typedef struct
@ -106,22 +106,22 @@ typedef struct
uint16_t TIM_ICFilter;
} TIM_ICInitTypeDef;
/**
* @brief BDTR structure definition
/**
* @brief BDTR structure definition
*/
typedef struct
{
uint16_t TIM_OSSRState;
uint16_t TIM_OSSIState;
uint16_t TIM_LOCKLevel;
uint16_t TIM_LOCKLevel;
uint16_t TIM_DeadTime;
uint16_t TIM_Break;
uint16_t TIM_BreakPolarity;
uint16_t TIM_AutomaticOutput;
} TIM_BDTRInitTypeDef;
/** @defgroup TIM_Exported_constants
/** @defgroup TIM_Exported_constants
* @{
*/
@ -180,9 +180,9 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup TIM_Output_Compare_and_PWM_modes
/** @defgroup TIM_Output_Compare_and_PWM_modes
* @{
*/
@ -203,14 +203,14 @@ typedef struct
((MODE) == TIM_OCMode_Inactive) || \
((MODE) == TIM_OCMode_Toggle)|| \
((MODE) == TIM_OCMode_PWM1) || \
((MODE) == TIM_OCMode_PWM2) || \
((MODE) == TIM_OCMode_PWM2) || \
((MODE) == TIM_ForcedAction_Active) || \
((MODE) == TIM_ForcedAction_InActive))
/**
* @}
*/
/** @defgroup TIM_One_Pulse_Mode
/** @defgroup TIM_One_Pulse_Mode
* @{
*/
@ -220,9 +220,9 @@ typedef struct
((MODE) == TIM_OPMode_Repetitive))
/**
* @}
*/
*/
/** @defgroup TIM_Channel
/** @defgroup TIM_Channel
* @{
*/
@ -243,9 +243,9 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup TIM_Clock_Division_CKD
/** @defgroup TIM_Clock_Division_CKD
* @{
*/
@ -259,7 +259,7 @@ typedef struct
* @}
*/
/** @defgroup TIM_Counter_Mode
/** @defgroup TIM_Counter_Mode
* @{
*/
@ -275,9 +275,9 @@ typedef struct
((MODE) == TIM_CounterMode_CenterAligned3))
/**
* @}
*/
*/
/** @defgroup TIM_Output_Compare_Polarity
/** @defgroup TIM_Output_Compare_Polarity
* @{
*/
@ -289,7 +289,7 @@ typedef struct
* @}
*/
/** @defgroup TIM_Output_Compare_N_Polarity
/** @defgroup TIM_Output_Compare_N_Polarity
* @{
*/
@ -311,9 +311,9 @@ typedef struct
((STATE) == TIM_OutputState_Enable))
/**
* @}
*/
*/
/** @defgroup TIM_Output_Compare_N_state
/** @defgroup TIM_Output_Compare_N_state
* @{
*/
@ -323,9 +323,9 @@ typedef struct
((STATE) == TIM_OutputNState_Enable))
/**
* @}
*/
*/
/** @defgroup TIM_Capture_Compare_state
/** @defgroup TIM_Capture_Compare_state
* @{
*/
@ -335,9 +335,9 @@ typedef struct
((CCX) == TIM_CCx_Disable))
/**
* @}
*/
*/
/** @defgroup TIM_Capture_Compare_N_state
/** @defgroup TIM_Capture_Compare_N_state
* @{
*/
@ -347,9 +347,9 @@ typedef struct
((CCXN) == TIM_CCxN_Disable))
/**
* @}
*/
*/
/** @defgroup TIM_Break_Input_enable_disable
/** @defgroup TIM_Break_Input_enable_disable
* @{
*/
@ -359,9 +359,9 @@ typedef struct
((STATE) == TIM_Break_Disable))
/**
* @}
*/
*/
/** @defgroup TIM_Break_Polarity
/** @defgroup TIM_Break_Polarity
* @{
*/
@ -371,9 +371,9 @@ typedef struct
((POLARITY) == TIM_BreakPolarity_High))
/**
* @}
*/
*/
/** @defgroup TIM_AOE_Bit_Set_Reset
/** @defgroup TIM_AOE_Bit_Set_Reset
* @{
*/
@ -383,9 +383,9 @@ typedef struct
((STATE) == TIM_AutomaticOutput_Disable))
/**
* @}
*/
*/
/** @defgroup TIM_Lock_level
/** @defgroup TIM_Lock_level
* @{
*/
@ -399,9 +399,9 @@ typedef struct
((LEVEL) == TIM_LOCKLevel_3))
/**
* @}
*/
*/
/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
* @{
*/
@ -413,7 +413,7 @@ typedef struct
* @}
*/
/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
* @{
*/
@ -423,9 +423,9 @@ typedef struct
((STATE) == TIM_OSSRState_Disable))
/**
* @}
*/
*/
/** @defgroup TIM_Output_Compare_Idle_State
/** @defgroup TIM_Output_Compare_Idle_State
* @{
*/
@ -435,9 +435,9 @@ typedef struct
((STATE) == TIM_OCIdleState_Reset))
/**
* @}
*/
*/
/** @defgroup TIM_Output_Compare_N_Idle_State
/** @defgroup TIM_Output_Compare_N_Idle_State
* @{
*/
@ -447,9 +447,9 @@ typedef struct
((STATE) == TIM_OCNIdleState_Reset))
/**
* @}
*/
*/
/** @defgroup TIM_Input_Capture_Polarity
/** @defgroup TIM_Input_Capture_Polarity
* @{
*/
@ -458,16 +458,16 @@ typedef struct
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
((POLARITY) == TIM_ICPolarity_Falling)|| \
((POLARITY) == TIM_ICPolarity_BothEdge))
((POLARITY) == TIM_ICPolarity_BothEdge))
/**
* @}
*/
*/
/** @defgroup TIM_Input_Capture_Selection
/** @defgroup TIM_Input_Capture_Selection
* @{
*/
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC2, IC1, IC4 or IC3, respectively. */
@ -477,9 +477,9 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
((SELECTION) == TIM_ICSelection_TRC))
/**
* @}
*/
*/
/** @defgroup TIM_Input_Capture_Prescaler
/** @defgroup TIM_Input_Capture_Prescaler
* @{
*/
@ -493,9 +493,9 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
((PRESCALER) == TIM_ICPSC_DIV8))
/**
* @}
*/
*/
/** @defgroup TIM_interrupt_sources
/** @defgroup TIM_interrupt_sources
* @{
*/
@ -519,9 +519,9 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
((IT) == TIM_IT_Break))
/**
* @}
*/
*/
/** @defgroup TIM_DMA_Base_address
/** @defgroup TIM_DMA_Base_address
* @{
*/
@ -567,10 +567,10 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
((BASE) == TIM_DMABase_OR))
/**
* @}
*/
*/
/** @defgroup TIM_DMA_Burst_Length
/** @defgroup TIM_DMA_Burst_Length
* @{
*/
@ -612,9 +612,9 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
((LENGTH) == TIM_DMABurstLength_18Transfers))
/**
* @}
*/
*/
/** @defgroup TIM_DMA_sources
/** @defgroup TIM_DMA_sources
* @{
*/
@ -629,9 +629,9 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
/**
* @}
*/
*/
/** @defgroup TIM_External_Trigger_Prescaler
/** @defgroup TIM_External_Trigger_Prescaler
* @{
*/
@ -645,9 +645,9 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
((PRESCALER) == TIM_ExtTRGPSC_DIV8))
/**
* @}
*/
*/
/** @defgroup TIM_Internal_Trigger_Selection
/** @defgroup TIM_Internal_Trigger_Selection
* @{
*/
@ -673,9 +673,9 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
((SELECTION) == TIM_TS_ITR3))
/**
* @}
*/
*/
/** @defgroup TIM_TIx_External_Clock_Source
/** @defgroup TIM_TIx_External_Clock_Source
* @{
*/
@ -685,11 +685,11 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
/**
* @}
*/
*/
/** @defgroup TIM_External_Trigger_Polarity
/** @defgroup TIM_External_Trigger_Polarity
* @{
*/
*/
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
@ -698,7 +698,7 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
* @}
*/
/** @defgroup TIM_Prescaler_Reload_Mode
/** @defgroup TIM_Prescaler_Reload_Mode
* @{
*/
@ -708,9 +708,9 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
((RELOAD) == TIM_PSCReloadMode_Immediate))
/**
* @}
*/
*/
/** @defgroup TIM_Forced_Action
/** @defgroup TIM_Forced_Action
* @{
*/
@ -720,9 +720,9 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
((ACTION) == TIM_ForcedAction_InActive))
/**
* @}
*/
*/
/** @defgroup TIM_Encoder_Mode
/** @defgroup TIM_Encoder_Mode
* @{
*/
@ -734,10 +734,10 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
((MODE) == TIM_EncoderMode_TI12))
/**
* @}
*/
*/
/** @defgroup TIM_Event_Source
/** @defgroup TIM_Event_Source
* @{
*/
@ -753,9 +753,9 @@ connected to IC2, IC1, IC4 or IC3, respectively. */
/**
* @}
*/
*/
/** @defgroup TIM_Update_Source
/** @defgroup TIM_Update_Source
* @{
*/
@ -767,9 +767,9 @@ through the slave mode controller. */
((SOURCE) == TIM_UpdateSource_Regular))
/**
* @}
*/
*/
/** @defgroup TIM_Output_Compare_Preload_State
/** @defgroup TIM_Output_Compare_Preload_State
* @{
*/
@ -779,9 +779,9 @@ through the slave mode controller. */
((STATE) == TIM_OCPreload_Disable))
/**
* @}
*/
*/
/** @defgroup TIM_Output_Compare_Fast_State
/** @defgroup TIM_Output_Compare_Fast_State
* @{
*/
@ -792,9 +792,9 @@ through the slave mode controller. */
/**
* @}
*/
*/
/** @defgroup TIM_Output_Compare_Clear_State
/** @defgroup TIM_Output_Compare_Clear_State
* @{
*/
@ -804,9 +804,9 @@ through the slave mode controller. */
((STATE) == TIM_OCClear_Disable))
/**
* @}
*/
*/
/** @defgroup TIM_Trigger_Output_Source
/** @defgroup TIM_Trigger_Output_Source
* @{
*/
@ -828,9 +828,9 @@ through the slave mode controller. */
((SOURCE) == TIM_TRGOSource_OC4Ref))
/**
* @}
*/
*/
/** @defgroup TIM_Slave_Mode
/** @defgroup TIM_Slave_Mode
* @{
*/
@ -844,9 +844,9 @@ through the slave mode controller. */
((MODE) == TIM_SlaveMode_External1))
/**
* @}
*/
*/
/** @defgroup TIM_Master_Slave_Mode
/** @defgroup TIM_Master_Slave_Mode
* @{
*/
@ -856,9 +856,9 @@ through the slave mode controller. */
((STATE) == TIM_MasterSlaveMode_Disable))
/**
* @}
*/
*/
/** @defgroup TIM_Flags
/** @defgroup TIM_Flags
* @{
*/
@ -891,19 +891,19 @@ through the slave mode controller. */
#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
/**
* @}
*/
*/
/** @defgroup TIM_Input_Capture_Filer_Value
/** @defgroup TIM_Input_Capture_Filer_Value
* @{
*/
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
/**
* @}
*/
*/
/** @defgroup TIM_External_Trigger_Filter
/** @defgroup TIM_External_Trigger_Filter
* @{
*/
@ -912,18 +912,18 @@ through the slave mode controller. */
* @}
*/
/** @defgroup TIM_OCReferenceClear
/** @defgroup TIM_OCReferenceClear
* @{
*/
#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
/**
* @}
*/
/** @defgroup TIM_Remap
/** @defgroup TIM_Remap
* @{
*/
#define TIM14_GPIO ((uint16_t)0x0000)
@ -939,7 +939,7 @@ through the slave mode controller. */
* @}
*/
/** @defgroup TIM_Legacy
/** @defgroup TIM_Legacy
* @{
*/
@ -970,7 +970,7 @@ through the slave mode controller. */
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Exported functions ------------------------------------------------------- */
/* TimeBase management ********************************************************/
void TIM_DeInit(TIM_TypeDef* TIMx);
@ -1065,7 +1065,7 @@ void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSo
uint16_t TIM_ICPolarity, uint16_t ICFilter);
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter);
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
@ -1077,7 +1077,7 @@ void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter);
/* Specific interface management **********************************************/
/* Specific interface management **********************************************/
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
@ -1094,7 +1094,7 @@ void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
/**
* @}
*/
*/
/**
* @}

74
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_uart.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the UART
* @brief This file contains all the functions prototypes for the UART
* firmware library.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_UART_H
@ -32,15 +32,15 @@
/** @addtogroup UART
* @{
*/
*/
/** @defgroup UART_Exported_Types
* @{
*/
*/
/**
* @brief UART Init Structure definition
*/
/**
* @brief UART Init Structure definition
*/
typedef struct
{
@ -49,17 +49,17 @@ typedef struct
uint16_t UART_StopBits;
uint16_t UART_Parity;
uint16_t UART_Mode;
uint16_t UART_HardwareFlowControl;
uint16_t UART_HardwareFlowControl;
} UART_InitTypeDef;
/**
* @}
*/
*/
/** @defgroup UART_Exported_Constants
* @{
*/
*/
#define IS_UART_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == UART1_BASE) || \
((*(uint32_t*)&(PERIPH)) == UART2_BASE) || \
@ -68,9 +68,9 @@ typedef struct
((*(uint32_t*)&(PERIPH)) == UART2_BASE) || \
((*(uint32_t*)&(PERIPH)) == UART3_BASE))
/** @defgroup UART_Word_Length
/** @defgroup UART_Word_Length
* @{
*/
*/
#define UART_WordLength_5b ((uint16_t)0x0000)
#define UART_WordLength_6b ((uint16_t)0x0010)
@ -84,39 +84,39 @@ typedef struct
((LENGTH) == UART_WordLength_8b))
/**
* @}
*/
*/
/** @defgroup UART_Stop_Bits
/** @defgroup UART_Stop_Bits
* @{
*/
*/
#define UART_StopBits_1 ((uint16_t)0x0000)
#define UART_StopBits_2 ((uint16_t)0x0004)
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \
((STOPBITS) == UART_StopBits_2))
((STOPBITS) == UART_StopBits_2))
/**
* @}
*/
*/
/** @defgroup UART_Parity
/** @defgroup UART_Parity
* @{
*/
*/
#define UART_Parity_No ((uint16_t)0x0000)
#define UART_Parity_Even ((uint16_t)0x0003)
#define UART_Parity_Odd ((uint16_t)0x0001)
#define UART_Parity_Odd ((uint16_t)0x0001)
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \
((PARITY) == UART_Parity_Even) || \
((PARITY) == UART_Parity_Odd))
/**
* @}
*/
*/
/** @defgroup UART_Mode
/** @defgroup UART_Mode
* @{
*/
*/
#define UART_Mode_Rx ((uint16_t)0x0008)
#define UART_Mode_Tx ((uint16_t)0x0010)
@ -126,11 +126,11 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup UART_Hardware_Flow_Control
/** @defgroup UART_Hardware_Flow_Control
* @{
*/
*/
#define UART_HardwareFlowControl_None ((uint16_t)0x0000)
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
@ -139,7 +139,7 @@ typedef struct
((CONTROL) == UART_HardwareFlowControl_CTS) || \
((CONTROL) == UART_HardwareFlowControl_RTS_CTS))
/** @defgroup UART_Interrupt_definition
/** @defgroup UART_Interrupt_definition
* @{
*/
@ -165,7 +165,7 @@ typedef struct
* @}
*/
/** @defgroup UART_DMA_Requests
/** @defgroup UART_DMA_Requests
* @{
*/
#define UART_DMAReq_EN ((uint16_t)0x0002)
@ -174,10 +174,10 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup UART_Flags
/** @defgroup UART_Flags
* @{
*/
@ -200,19 +200,19 @@ typedef struct
/**
* @}
*/
*/
/**
* @}
*/
*/
/** @defgroup UART_Exported_Macros
* @{
*/
*/
/**
* @}
*/
*/
/** @defgroup UART_Exported_Functions
* @{
@ -233,14 +233,14 @@ void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT);
#endif /* __HAL_UART_H */
/**
* @}
*/
*/
/**
* @}
*/
*/
/**
* @}
*/
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

32
bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_wwdg.h
View File

@ -4,7 +4,7 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the WWDG
* @brief This file contains all the functions prototypes for the WWDG
* firmware library.
******************************************************************************
* @copy
@ -17,7 +17,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_WWDG_H
@ -32,23 +32,23 @@
/** @addtogroup WWDG
* @{
*/
*/
/** @defgroup WWDG_Exported_Types
* @{
*/
*/
/**
* @}
*/
*/
/** @defgroup WWDG_Exported_Constants
* @{
*/
*/
/** @defgroup WWDG_Prescaler
/** @defgroup WWDG_Prescaler
* @{
*/
*/
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
@ -63,22 +63,22 @@
/**
* @}
*/
*/
/**
* @}
*/
*/
/** @defgroup WWDG_Exported_Macros
* @{
*/
*/
/**
* @}
*/
*/
/** @defgroup WWDG_Exported_Functions
* @{
*/
*/
void WWDG_DeInit(void);
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
@ -93,14 +93,14 @@ void WWDG_ClearFlag(void);
/**
* @}
*/
*/
/**
* @}
*/
*/
/**
* @}
*/
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

918
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_can.c
View File

File diff suppressed because it is too large Load Diff

50
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_dma.c
View File

@ -27,14 +27,14 @@
* @{
*/
/** @defgroup DMA
/** @defgroup DMA
* @brief DMA driver modules
* @{
*/
*/
/** @defgroup DMA_Private_TypesDefinitions
* @{
*/
*/
/**
* @}
*/
@ -109,22 +109,22 @@ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
/* Reset DMAy Channelx control register */
DMAy_Channelx->CCR = 0;
/* Reset DMAy Channelx remaining bytes register */
DMAy_Channelx->CNDTR = 0;
/* Reset DMAy Channelx peripheral address register */
DMAy_Channelx->CPAR = 0;
/* Reset DMAy Channelx memory address register */
DMAy_Channelx->CMAR = 0;
if (DMAy_Channelx == DMA1_Channel1)
{
/* Reset interrupt pending bits for DMA1 Channel1 */
@ -181,7 +181,7 @@ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
DMA2->IFCR |= DMA2_Channel4_IT_Mask;
}
else
{
{
if (DMAy_Channelx == DMA2_Channel5)
{
/* Reset interrupt pending bits for DMA2 Channel5 */
@ -193,7 +193,7 @@ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
/**
* @brief Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
* contains the configuration information for the specified DMA Channel.
@ -208,7 +208,7 @@ void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruc
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
@ -285,9 +285,9 @@ void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
/**
* @brief Enables or disables the specified DMAy Channelx.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param NewState: new state of the DMAy Channelx.
* @param NewState: new state of the DMAy Channelx.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
@ -311,10 +311,10 @@ void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
/**
* @brief Enables or disables the specified DMAy Channelx interrupts.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
* or disabled.
* or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer interrupt mask
@ -343,27 +343,27 @@ void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, Functiona
/**
* @brief Sets the number of data units in the current DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DataNumber: The number of data units in the current DMAy Channelx
* transfer.
* @note This function can only be used when the DMAy_Channelx is disabled.
* transfer.
* @note This function can only be used when the DMAy_Channelx is disabled.
* @retval None.
*/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DataNumber;
DMAy_Channelx->CNDTR = DataNumber;
}
/**
* @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @retval The number of remaining data units in the current DMAy Channelx
* transfer.
@ -434,7 +434,7 @@ FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
@ -461,7 +461,7 @@ FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
/* DMAy_FLAG is reset */
bitstatus = RESET;
}
/* Return the DMAy_FLAG status */
return bitstatus;
}
@ -540,7 +540,7 @@ void DMA_ClearFlag(uint32_t DMAy_FLAG)
/**
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
* @param DMAy_IT: specifies the DMAy interrupt source to check.
* @param DMAy_IT: specifies the DMAy interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.

2
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_dma_bak.c
View File

@ -480,7 +480,7 @@ ITStatus DMA_GetITStatus(uint32_t DMA_IT)
}
/**
* @brief Clears the DMAy Channelx’s interrupt pending bits.
* @brief Clears the DMAy Channelx’s interrupt pending bits.
* @param DMA_IT: specifies the DMA interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of
* the following values:

84
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_gpio.c
View File

@ -220,10 +220,10 @@ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
}
GPIOx->CRH = tmpreg;
}
/*---------------------------- GPIOE_CRH_EXT Configuration ------------------------*/
/*---------------------------- GPIOE_CRH_EXT Configuration ------------------------*/
if(GPIO_InitStruct->GPIO_Pin>>16) //说明是GPIOE的16~23位
{
GPIO_InitStruct->GPIO_Pin = GPIO_InitStruct->GPIO_Pin>>16;
GPIO_InitStruct->GPIO_Pin = GPIO_InitStruct->GPIO_Pin>>16;
tmpreg = GPIOE->CRH_EXT;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
@ -362,7 +362,7 @@ void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin)
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
if(GPIO_Pin>GPIO_Pin_15)GPIOE->BSRR_EXT=GPIO_Pin>>16;
else
else
GPIOx->BSRR = GPIO_Pin;
}
@ -486,51 +486,51 @@ TIM1 6_CH1, TIM17_CH1
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, uint8_t GPIO_AF)
{
uint32_t temp;
unsigned char i;
unsigned char i;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
assert_param(IS_GPIO_AF(GPIO_AF));
if(GPIO_Pin>>16) //说明是GPIOE的16~23位
{
temp = GPIO_Pin>>16;
for(i=0;i<8;i++)
{
if(temp&0x01)
{
GPIOE->AFRH_EXT &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOE->AFRH_EXT |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
}
temp = temp>>1;
}
}
if(GPIO_Pin&0XFF00) //说明是GPIOE的8~15位
{
temp = GPIO_Pin>>8;
for(i=0;i<8;i++)
{
if(temp&0x01)
{
GPIOx->AFRH &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOx->AFRH |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
}
temp = temp>>1;
}
}
if(GPIO_Pin&0XFF) //说明是GPIOE的0~7位
{
for(i=0;i<8;i++)
{
if(temp&0x01)
{
GPIOx->AFRL &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOx->AFRL |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
}
temp = temp>>1;
}
}
if(GPIO_Pin>>16) //说明是GPIOE的16~23位
{
temp = GPIO_Pin>>16;
for(i=0;i<8;i++)
{
if(temp&0x01)
{
GPIOE->AFRH_EXT &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOE->AFRH_EXT |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
}
temp = temp>>1;
}
}
if(GPIO_Pin&0XFF00) //说明是GPIOE的8~15位
{
temp = GPIO_Pin>>8;
for(i=0;i<8;i++)
{
if(temp&0x01)
{
GPIOx->AFRH &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOx->AFRH |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
}
temp = temp>>1;
}
}
if(GPIO_Pin&0XFF) //说明是GPIOE的0~7位
{
for(i=0;i<8;i++)
{
if(temp&0x01)
{
GPIOx->AFRL &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOx->AFRL |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
}
temp = temp>>1;
}
}
}
/**

100
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_i2c.c
View File

@ -47,7 +47,7 @@
/*I2c Enable disable*/
#define IC_ENABLE_Reset ((uint16_t)0xFFFE)
#define IC_ENABLE_Set ((uint16_t)0x0001)
#define IC_CON_RESET ((uint16_t)0xFE8A)
#define IC_CON_RESET ((uint16_t)0xFE8A)
#define INTR_MASK ((uint16_t)0xC000)
/*I2c DMA reset*/
@ -173,7 +173,7 @@ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
i2cPeriod = 1000000000/I2C_InitStruct->I2C_ClockSpeed; //ns unit
tmpreg = 0;
/*Get the I2Cx IC_CON value */
/*Get the I2Cx IC_CON value */
tmpreg = I2Cx->IC_CON;
/*Clear TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/
tmpreg &= IC_CON_RESET;
@ -182,16 +182,16 @@ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
{
minSclLowTime = i2cPeriod/pclk1Period;
I2Cx->IC_SS_SCL_LCNT = minSclLowTime/2;
I2Cx->IC_SS_SCL_HCNT = minSclLowTime - I2Cx->IC_SS_SCL_LCNT;
I2C_InitStruct->I2C_Speed = I2C_Speed_STANDARD;
I2Cx->IC_SS_SCL_LCNT = minSclLowTime/2;
I2Cx->IC_SS_SCL_HCNT = minSclLowTime - I2Cx->IC_SS_SCL_LCNT;
I2C_InitStruct->I2C_Speed = I2C_Speed_STANDARD;
}
else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
{
minSclLowTime = i2cPeriod/pclk1Period;
I2Cx->IC_FS_SCL_LCNT = minSclLowTime/2;
I2Cx->IC_FS_SCL_HCNT = minSclLowTime - I2Cx->IC_FS_SCL_LCNT;
I2C_InitStruct->I2C_Speed = I2C_Speed_FAST;
minSclLowTime = i2cPeriod/pclk1Period;
I2Cx->IC_FS_SCL_LCNT = minSclLowTime/2;
I2Cx->IC_FS_SCL_HCNT = minSclLowTime - I2Cx->IC_FS_SCL_LCNT;
I2C_InitStruct->I2C_Speed = I2C_Speed_FAST;
}
@ -261,10 +261,10 @@ void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
/**
* @brief Enables or disables the specified I2C DMA requests.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param DMA_Direcction : TDMAE_SET,RDMAE_SET
* @param DMA_Direcction : TDMAE_SET,RDMAE_SET
* This parameter can be any combination of the following values:
* @arg TDMAE_SET :DMA TX set
* @arg RDMAE_SET :DMA RX set
* @arg TDMAE_SET :DMA TX set
* @arg RDMAE_SET :DMA RX set
* @param NewState: new state of the I2C DMA transfer.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
@ -424,14 +424,14 @@ void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt mask
* @arg I2C_IT_RX_FULL : Rx buffer full interrupt mask
* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt mask
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt mask
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt mask
* @arg I2C_IT_TX_ABRT : TX error interrupt mask(Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt mask(slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt mask
* @arg I2C_IT_STOP_DET : stop condition interrupt mask
* @arg I2C_IT_START_DET : start condition interrupt mask
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt mask
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt mask
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt mask
* @arg I2C_IT_TX_ABRT : TX error interrupt mask(Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt mask(slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt mask
* @arg I2C_IT_STOP_DET : stop condition interrupt mask
* @arg I2C_IT_START_DET : start condition interrupt mask
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt mask
* @param NewState: new state of the specified I2C interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
@ -566,14 +566,14 @@ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
* @arg I2C_EVENT_RX_OVER : RX Buffer Overrun event
* @arg I2C_EVENTT_RX_FULL : Rx buffer full event
* @arg I2C_EVENT_TX_OVER : TX Buffer Overrun event
* @arg I2C_EVENT_TX_EMPTY : TX_FIFO empty event
* @arg I2C_EVENT_RD_REQ : I2C work as slave or master event
* @arg I2C_EVENT_TX_ABRT : TX error event(Master mode)
* @arg I2C_EVENT_RX_DONE : Master not ack event(slave mode)
* @arg I2C_EVENT_ACTIVITY : I2C activity event
* @arg I2C_EVENT_STOP_DET : stop condition event
* @arg I2C_EVENT_START_DET : start condition event
* @arg I2C_EVENT_GEN_CALL : a general call address and ack event
* @arg I2C_EVENT_TX_EMPTY : TX_FIFO empty event
* @arg I2C_EVENT_RD_REQ : I2C work as slave or master event
* @arg I2C_EVENT_TX_ABRT : TX error event(Master mode)
* @arg I2C_EVENT_RX_DONE : Master not ack event(slave mode)
* @arg I2C_EVENT_ACTIVITY : I2C activity event
* @arg I2C_EVENT_STOP_DET : stop condition event
* @arg I2C_EVENT_START_DET : start condition event
* @arg I2C_EVENT_GEN_CALL : a general call address and ack event
* - SUCCESS: Last event is equal to the I2C_EVENT
* - ERROR: Last event is different from the I2C_EVENT
*/
@ -624,9 +624,9 @@ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
* @arg I2C_FLAG_RX_FULL : Rx buffer full flag
* @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag
* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag
* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
* @arg I2C_FLAG_ACTIVITY: I2C activity flag
* @arg I2C_FLAG_STOP_DET: stop condition flag
* @arg I2C_FLAG_START_DET: start condition flag
@ -673,9 +673,9 @@ FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
* @arg I2C_FLAG_RX_FULL : Rx buffer full flag
* @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag
* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag
* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
* @arg I2C_FLAG_ACTIVITY: I2C activity flag
* @arg I2C_FLAG_STOP_DET: stop condition flag
* @arg I2C_FLAG_START_DET: start condition flag
@ -772,14 +772,14 @@ void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt
* @arg I2C_IT_RX_FULL : Rx buffer full interrupt
* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt
* @arg I2C_IT_STOP_DET : stop condition interrupt
* @arg I2C_IT_START_DET : start condition interrupt
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt
* @arg I2C_IT_STOP_DET : stop condition interrupt
* @arg I2C_IT_START_DET : start condition interrupt
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
* @retval : The new state of I2C_IT (SET or RESET).
*/
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
@ -814,14 +814,14 @@ ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt
* @arg I2C_IT_RX_FULL : Rx buffer full interrupt
* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt
* @arg I2C_IT_STOP_DET : stop condition interrupt
* @arg I2C_IT_START_DET : start condition interrupt
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt
* @arg I2C_IT_STOP_DET : stop condition interrupt
* @arg I2C_IT_START_DET : start condition interrupt
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
* @retval : None
*/
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)

46
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_misc.c
View File

@ -27,7 +27,7 @@
* @{
*/
/** @defgroup MISC
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
@ -38,7 +38,7 @@
/**
* @}
*/
*/
/** @defgroup MISC_Private_Defines
* @{
@ -79,7 +79,7 @@
/**
* @brief Configures the priority grouping: pre-emption priority and subpriority.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 4 bits for subpriority
@ -95,18 +95,18 @@
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
//void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
//{
//{
// /* Check the parameters */
// assert_param(IS_TIM_ALL_PERIPH(TIMx));
// assert_param(IS_TIM_IT(TIM_IT));
// assert_param(IS_FUNCTIONAL_STATE(NewState));
//
//
// if (NewState != DISABLE)
// {
// /* Enable the Interrupt sources */
@ -124,7 +124,7 @@ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
// /* Check the parameters */
// assert_param(IS_TIM_ALL_PERIPH(TIMx));
// assert_param(IS_FUNCTIONAL_STATE(NewState));
//
//
// if (NewState != DISABLE)
// {
// /* Enable the TIM Counter */
@ -147,22 +147,22 @@ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority --------------------------------*/
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
tmppriority = tmppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
/* Enable the Selected IRQ Channels --------------------------------------*/
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
@ -173,7 +173,7 @@ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
tmppre = NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05];
//printf("NVIC->ISER = 0x%x\r\n",tmppre);
}
@ -184,14 +184,14 @@ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
* This parameter can be one of the following values:
* @arg NVIC_VectTab_RAM
* @arg NVIC_VectTab_FLASH
* @param Offset: Vector Table base offset field. This value must be a multiple
* @param Offset: Vector Table base offset field. This value must be a multiple
* of 0x200.
* @retval None
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
{
{
//SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
@ -207,8 +207,8 @@ void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
*/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
{
if (NewState != DISABLE)
{
SCB->SCR |= LowPowerMode;
@ -230,7 +230,7 @@ void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
{
/* Check the parameters */
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;

38
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_pwr.c
View File

@ -16,7 +16,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_pwr.h"
@ -26,10 +26,10 @@
* @{
*/
/** @defgroup PWR
/** @defgroup PWR
* @brief PWR driver modules
* @{
*/
*/
/** @defgroup PWR_Private_TypesDefinitions
* @{
@ -136,13 +136,13 @@ void PWR_BackupAccessCmd(FunctionalState NewState)
//*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
if(NewState!=DISABLE)
{
PWR->CR |= 0x00000100;
PWR->CR |= 0x00000100;
}
else
{
PWR->CR &= 0xfffffeff;
PWR->CR &= 0xfffffeff;
}
}
/**
@ -155,7 +155,7 @@ void PWR_PVDCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if(NewState==ENABLE)
{
PWR->CR |= 0x00000010;
@ -164,7 +164,7 @@ void PWR_PVDCmd(FunctionalState NewState)
{
PWR->CR &= 0xffffffef;
}
}
/**
@ -209,14 +209,14 @@ void PWR_WakeUpPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if(NewState!=DISABLE)
{
PWR->CSR |= 0x00000100;
PWR->CSR |= 0x00000100;
}
else
{
PWR->CSR &= 0xfffffeff;
PWR->CSR &= 0xfffffeff;
}
}
@ -227,7 +227,7 @@ void PWR_WakeUpPinCmd(FunctionalState NewState)
* @arg PWR_Regulator_ON: STOP mode with regulator ON
* @arg PWR_Regulator_LowPower: STOP mode with
* regulator in low power mode
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or
* WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
@ -240,7 +240,7 @@ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
@ -250,12 +250,12 @@ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SysCtrl_SLEEPDEEP_Set;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
{
/* Request Wait For Interrupt */
__WFI();
}
@ -278,7 +278,7 @@ void PWR_EnterSTANDBYMode(void)
/* Select STANDBY mode */
PWR->CR |= CR_PDDS_Set;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SysCtrl_SLEEPDEEP_Set;
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM )
@ -302,7 +302,7 @@ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
@ -327,7 +327,7 @@ void PWR_ClearFlag(uint32_t PWR_FLAG)
{
/* Check the parameters */
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
PWR->CR |= PWR_FLAG << 2;
}

170
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_rcc.c
View File

@ -174,22 +174,22 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
*/
void SystemClk_HSEInit(uint32_t PLL_DN)
{
RCC_DeInit();
//HSE on
//CR寄存器BIT16位（HSEON位）置1，作用是连接外部时钟HSE作为系统时钟
RCC_HSEConfig(RCC_HSE_ON);
RCC_DeInit();
//HSE on
//CR寄存器BIT16位（HSEON位）置1，作用是连接外部时钟HSE作为系统时钟
RCC_HSEConfig(RCC_HSE_ON);
while(1)
{
if(RCC_WaitForHSEStartUp()!=0)
{
break;
}
}
RCC_PLLCmd(DISABLE);
RCC_PLLConfig(RCC_PLLSource_HSE_Div1,PLL_DN);
RCC_PLLCmd(ENABLE);
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);//选择外部时钟作为系统时钟
while(1)
{
if(RCC_WaitForHSEStartUp()!=0)
{
break;
}
}
RCC_PLLCmd(DISABLE);
RCC_PLLConfig(RCC_PLLSource_HSE_Div1,PLL_DN);
RCC_PLLCmd(ENABLE);
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);//选择外部时钟作为系统时钟
}
/**
* @brief Resets the RCC clock configuration to the default reset state.
@ -350,24 +350,24 @@ void RCC_PLLDMDNConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLDN,uint32_t RCC_P
assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
if(RCC_PLLSource == 0)
{
tmpreg0 &= ~(1<<22);
}
else
{
TK499_PLL_FACTOR |= 0x10000;
tmpreg0 |= (1<<22);
}
if(RCC_PLLSource == 0)
{
tmpreg0 &= ~(1<<22);
}
else
{
TK499_PLL_FACTOR |= 0x10000;
tmpreg0 |= (1<<22);
}
RCC_PLLDN &= 0x7f;
RCC_PLLDP &= 0x3;
RCC_PLLDM &= 0xf;
RCC_PLLDP &= 0x3;
RCC_PLLDM &= 0xf;
/* Set the PLL configuration bits */
tmpreg0 |= (u32)((u32)(RCC_PLLDN<<6))|((u32)(RCC_PLLDP<<4))|((u32)RCC_PLLDM);
RCC->PLLCFGR = tmpreg0;
// RCC->PLLCFGR = 0x4004d1;
// RCC->PLLCFGR = 0x4004d1;
}
@ -402,137 +402,137 @@ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
if(RCC_PLLMul==RCC_PLLMul_2)
{
TK499_PLL_FACTOR = 2;
TK499_PLL_FACTOR = 2;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000001, 0x00000000,0x00000000); //Frclk*8/4
}
if(RCC_PLLMul==RCC_PLLMul_3)
{
TK499_PLL_FACTOR = 3;
TK499_PLL_FACTOR = 3;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000002, 0x00000000,0x00000000);//Frclk*6/2
}
if(RCC_PLLMul==RCC_PLLMul_4)
{
TK499_PLL_FACTOR = 4;
TK499_PLL_FACTOR = 4;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000003, 0x00000000,0x00000000);//Frclk*8/2
}
if(RCC_PLLMul==RCC_PLLMul_5)
{
TK499_PLL_FACTOR = 5;
TK499_PLL_FACTOR = 5;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000001,0x00000001);//Frclk*10/2
}
if(RCC_PLLMul==RCC_PLLMul_6)
{
TK499_PLL_FACTOR = 6;
TK499_PLL_FACTOR = 6;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000005, 0x00000000,0x00000000);//Frclk*12/2
}
if(RCC_PLLMul==RCC_PLLMul_7)
{
TK499_PLL_FACTOR = 7;
TK499_PLL_FACTOR = 7;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000006, 0x00000000,0x00000000);//Frclk*14/2
}
if(RCC_PLLMul==RCC_PLLMul_8)
{
TK499_PLL_FACTOR = 8;
TK499_PLL_FACTOR = 8;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000007, 0x00000000,0x00000000);//Frclk*16/2
}
if(RCC_PLLMul==RCC_PLLMul_9)
{
TK499_PLL_FACTOR = 9;
TK499_PLL_FACTOR = 9;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000008, 0x00000000,0x00000000);//Frclk*18/2
}
if(RCC_PLLMul==RCC_PLLMul_10)
{
TK499_PLL_FACTOR = 10;
TK499_PLL_FACTOR = 10;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000009, 0x00000000,0x00000000);//Frclk*20/2
}
if(RCC_PLLMul==RCC_PLLMul_11)
{
TK499_PLL_FACTOR = 11;
TK499_PLL_FACTOR = 11;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000a, 0x00000000,0x00000000);//Frclk*22/2
}
if(RCC_PLLMul==RCC_PLLMul_12)
{
TK499_PLL_FACTOR = 12;
TK499_PLL_FACTOR = 12;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000b, 0x00000000,0x00000000);//Frclk*24/2
}
if(RCC_PLLMul==RCC_PLLMul_13)
{
TK499_PLL_FACTOR = 13;
TK499_PLL_FACTOR = 13;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000c, 0x00000000,0x00000000);//Frclk*26/2
}
if(RCC_PLLMul==RCC_PLLMul_14)
{
TK499_PLL_FACTOR = 14;
TK499_PLL_FACTOR = 14;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000d, 0x00000000,0x00000000);//Frclk*28/2
}
if(RCC_PLLMul==RCC_PLLMul_15)
{
TK499_PLL_FACTOR = 15;
TK499_PLL_FACTOR = 15;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000e, 0x00000000,0x00000000);//Frclk*30/2
}
if(RCC_PLLMul==RCC_PLLMul_16)
{
TK499_PLL_FACTOR = 16;
TK499_PLL_FACTOR = 16;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000f, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_17)
if(RCC_PLLMul==RCC_PLLMul_17)
{
TK499_PLL_FACTOR = 17;
TK499_PLL_FACTOR = 17;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000010, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_18)
if(RCC_PLLMul==RCC_PLLMul_18)
{
TK499_PLL_FACTOR = 18;
TK499_PLL_FACTOR = 18;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000011, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_19)
if(RCC_PLLMul==RCC_PLLMul_19)
{
TK499_PLL_FACTOR = 19;
TK499_PLL_FACTOR = 19;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000012, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_20)
if(RCC_PLLMul==RCC_PLLMul_20)
{
TK499_PLL_FACTOR = 20;
TK499_PLL_FACTOR = 20;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_21)
if(RCC_PLLMul==RCC_PLLMul_21)
{
TK499_PLL_FACTOR = 21;
TK499_PLL_FACTOR = 21;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000014, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_22)
if(RCC_PLLMul==RCC_PLLMul_22)
{
TK499_PLL_FACTOR = 22;
TK499_PLL_FACTOR = 22;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000015, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_23)
if(RCC_PLLMul==RCC_PLLMul_23)
{
TK499_PLL_FACTOR = 23;
TK499_PLL_FACTOR = 23;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000016, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_24)
if(RCC_PLLMul==RCC_PLLMul_24)
{
TK499_PLL_FACTOR = 24;
TK499_PLL_FACTOR = 24;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000017, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_25)
if(RCC_PLLMul==RCC_PLLMul_25)
{
TK499_PLL_FACTOR = 25;
TK499_PLL_FACTOR = 25;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000018, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_26)
if(RCC_PLLMul==RCC_PLLMul_26)
{
TK499_PLL_FACTOR = 26;
TK499_PLL_FACTOR = 26;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000019, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_27)
if(RCC_PLLMul==RCC_PLLMul_27)
{
TK499_PLL_FACTOR = 27;
TK499_PLL_FACTOR = 27;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000020, 0x00000000,0x00000000);//Frclk*32/2
}
if(RCC_PLLMul==RCC_PLLMul_28)
if(RCC_PLLMul==RCC_PLLMul_28)
{
TK499_PLL_FACTOR = 28;
TK499_PLL_FACTOR = 28;
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000021, 0x00000000,0x00000000);//Frclk*32/2
}
}
@ -581,25 +581,25 @@ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
tmpreg |= RCC_SYSCLKSource;
/* Store the new value */
RCC->CFGR = tmpreg;
if(RCC_SYSCLKSource == RCC_SYSCLKSource_PLLCLK)
{
if(TK499_PLL_FACTOR&0x10000)//hse as pll src
{
TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSE_VALUE;
}
else
{
TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSI_Value_Pll_ON;
}
}
else if(RCC_SYSCLKSource == RCC_SYSCLKSource_HSE)
{
TK499_SYS_CLK = HSE_VALUE;
}
else
{
TK499_SYS_CLK = HSI_Value_Pll_OFF;
}
if(RCC_SYSCLKSource == RCC_SYSCLKSource_PLLCLK)
{
if(TK499_PLL_FACTOR&0x10000)//hse as pll src
{
TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSE_VALUE;
}
else
{
TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSI_Value_Pll_ON;
}
}
else if(RCC_SYSCLKSource == RCC_SYSCLKSource_HSE)
{
TK499_SYS_CLK = HSE_VALUE;
}
else
{
TK499_SYS_CLK = HSI_Value_Pll_OFF;
}
}
/**

160
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_spi.c
View File

@ -16,7 +16,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_spi.h"
@ -26,10 +26,10 @@
* @{
*/
/** @defgroup SPI
/** @defgroup SPI
* @brief SPI driver modules
* @{
*/
*/
/** @defgroup SPI_Private_TypesDefinitions
* @{
@ -37,7 +37,7 @@
/**
* @}
*/
*/
/** @defgroup SPI_Private_Defines
@ -96,7 +96,7 @@ void SPI_DeInit(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
switch (*(uint32_t*)&SPIx)
{
case SPI1_BASE:
@ -111,7 +111,7 @@ void SPI_DeInit(SPI_TypeDef* SPIx)
}
/**
* @brief Initializes the SPIx peripheral according to the specified
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the SPI_InitStruct.
* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
@ -122,10 +122,10 @@ void SPI_DeInit(SPI_TypeDef* SPIx)
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
{
uint32_t tmpreg = 0;
/* check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Check the SPI parameters */
assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
@ -147,12 +147,12 @@ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
/* Set dat_sel bits according to SPI_DataSize value */
/* Set csn and csn_sel bits according to SPI_NSS value */
/* Set mm bit according to SPI_Mode value */
tmpreg |= (uint32_t)((uint32_t) SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_NSS |
tmpreg |= (uint32_t)((uint32_t) SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_NSS |
SPI_InitStruct->SPI_Mode );
/* Write to SPIx GCTL */
// if(SPI_InitStruct->SPI_DataSize==SPI_DataSize_8b) tmpreg |= 0x1000;
// if(SPI_InitStruct->SPI_DataSize==SPI_DataSize_8b) tmpreg |= 0x1000;
SPIx->GCTL = tmpreg;
/*---------------------------- SPIx CCTL Configuration ------------------------*/
/*---------------------------- SPIx CCTL Configuration ------------------------*/
tmpreg = SPIx->CCTL;
/* Clear spilen, lsbfe, CPOL, CPHA bits */
tmpreg &= CCTL_CLEAR_Mask;
@ -160,21 +160,21 @@ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
/* Set LSBFirst bit according to SPI_FirstBit value */
/* Set CPOL bit according to SPI_CPOL value */
/* Set CPHA bit according to SPI_CPHA value */
tmpreg |= (uint16_t)((uint16_t) SPI_InitStruct->SPI_DataWidth | SPI_InitStruct->SPI_FirstBit | SPI_InitStruct->SPI_CPOL |
tmpreg |= (uint16_t)((uint16_t) SPI_InitStruct->SPI_DataWidth | SPI_InitStruct->SPI_FirstBit | SPI_InitStruct->SPI_CPOL |
SPI_InitStruct->SPI_CPHA );
/* Write to SPIx CCTL */
SPIx->CCTL = tmpreg;
/*---------------------------- SPIx SPBRG Configuration ------------------------*/
/*---------------------------- SPIx SPBRG Configuration ------------------------*/
tmpreg = SPIx->SPBRG;
/* Clear spbrg bits */
tmpreg &= (uint16_t)SPBRG_CLEAR_Mask;
tmpreg &= (uint16_t)SPBRG_CLEAR_Mask;
/* Set BR bits according to SPI_BaudRatePrescaler value */
tmpreg |= (uint16_t) SPI_InitStruct->SPI_BaudRatePrescaler;
/* Write to SPIx SPBRG */
SPIx->SPBRG = tmpreg;
}
/**
@ -186,7 +186,7 @@ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
{
/*--------------- Reset SPI init structure parameters values -----------------*/
/* initialize the SPI_Mode member */
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
/* initialize the SPI_DataSize member */
@ -203,14 +203,14 @@ void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
/* Initialize the SPI_FirstBit member */
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
}
/**
* @brief Enables or disables the specified SPI peripheral.
* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
* @param NewState: new state of the SPIx peripheral.
* @param NewState: new state of the SPIx peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
@ -235,17 +235,17 @@ void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
/**
* @brief Enables or disables the specified SPIinterrupts.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param SPI_IT: specifies the SPI interrupt source to be
* enabled or disabled.
* 0, 1 in SPI mode
* @param SPI_IT: specifies the SPI interrupt source to be
* enabled or disabled.
* This parameter can be one of the following values:
* @arg SPI_IT_TX: Tx buffer empty interrupt mask
* @arg SPI_IT_RX: Rx buffer interrupt mask
* @arg SPI_IT_UNDERRUN: under Error interrupt mask in slave mode
* @arg SPI_IT_RXOVER: RX OVER Error interrupt mask
* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt mask
* @arg SPI_IT_RXFULL: Rx buffer full interrupt mask
* @arg SPI_IT_TXEPT: Tx buffer empty interrupt mask
* @arg SPI_IT_RXOVER: RX OVER Error interrupt mask
* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt mask
* @arg SPI_IT_RXFULL: Rx buffer full interrupt mask
* @arg SPI_IT_TXEPT: Tx buffer empty interrupt mask
* @param NewState: new state of the specified SPI interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
@ -256,7 +256,7 @@ void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState)
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_SPI_CONFIG_IT(SPI_IT));
if (NewState != DISABLE)
{
/* Enable the selected SPI Global interrupt */
@ -271,18 +271,18 @@ void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState)
/* Disable the selected SPI Global interrupt */
SPIx->GCTL &= (uint16_t)~SPI_INT_EN;
}
}
/**
* @brief Enables or disables the SPIx DMA interface.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param SPI_DMAReq: specifies the SPI DMA transfer request
* to be enabled or disabled.
* 0, 1 in SPI mode
* @param SPI_DMAReq: specifies the SPI DMA transfer request
* to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg SPI_DMAReq_EN: DMA transfer request enable
* @param NewState: new state of the selected SPI DMA transfer
* @param NewState: new state of the selected SPI DMA transfer
* request.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
@ -308,12 +308,12 @@ void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState
/**
* @brief configure tn Fifo trigger level bit.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param SPI_FifoTriggerValue: specifies the Fifo trigger level
* 0, 1 in SPI mode
* @param SPI_FifoTriggerValue: specifies the Fifo trigger level
* This parameter can be any combination of the following values:
* SPI_TXTLF : SPI TX FIFO Trigger value set
* SPI_RXTLF : SPI RX FIFO Trigger value set
* @param NewState: new state of the selected SPI DMA transfer
* @param NewState: new state of the selected SPI DMA transfer
* request.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
@ -324,7 +324,7 @@ void SPI_FifoTrigger(SPI_TypeDef* SPIx, uint16_t SPI_FifoTriggerValue, Functiona
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_SPI_FIFOTRIGGER(SPI_FifoTriggerValue));
if (NewState != DISABLE)
{
/* Enable the selected SPI DMA requests */
@ -340,7 +340,7 @@ void SPI_FifoTrigger(SPI_TypeDef* SPIx, uint16_t SPI_FifoTriggerValue, Functiona
/**
* @brief Transmits a Data through the SPIx peripheral.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* 0, 1 in SPI mode
* @param Data : Data to be transmitted..
* @retval : None
*/
@ -348,40 +348,40 @@ void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Write in the TXREG register the data to be sent */
SPIx->TXREG = Data;
}
/**
* @brief Returns the most recent received data by the SPIx peripheral.
* @brief Returns the most recent received data by the SPIx peripheral.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* 0, 1 in SPI mode
* @retval : The value of the received data.
*/
uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Return the data in the RXREG register */
return SPIx->RXREG;
}
/**
* @brief Slave chip csn single by selected
* @brief Slave chip csn single by selected
* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
* @param SPI_CSInternalSelected: specifies the SPI CS internal selected.
* This parameter can be one of the following values:
* @arg SPI_CS_BIT0: cs bit 0 selected
* @arg SPI_CS_BIT1: cs bit 1 selected
* @arg SPI_CS_BIT2: cs bit 2 selected
* @arg SPI_CS_BIT3: cs bit 3 selected
* @arg SPI_CS_BIT4: cs bit 4 selected
* @arg SPI_CS_BIT5: cs bit 5 selected
* @arg SPI_CS_BIT6: cs bit 6 selected
* @arg SPI_CS_BIT7: cs bit 7 selected
* @param NewState: new state of the selected SPI CS pin
* This parameter can be one of the following values:
* @arg SPI_CS_BIT0: cs bit 0 selected
* @arg SPI_CS_BIT1: cs bit 1 selected
* @arg SPI_CS_BIT2: cs bit 2 selected
* @arg SPI_CS_BIT3: cs bit 3 selected
* @arg SPI_CS_BIT4: cs bit 4 selected
* @arg SPI_CS_BIT5: cs bit 5 selected
* @arg SPI_CS_BIT6: cs bit 6 selected
* @arg SPI_CS_BIT7: cs bit 7 selected
* @param NewState: new state of the selected SPI CS pin
* request.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
@ -392,8 +392,8 @@ void SPI_CSInternalSelected(SPI_TypeDef* SPIx, uint16_t SPI_CSInternalSelected,F
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_CS(SPI_CSInternalSelected));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* selected cs pin according SCSR Value */
@ -434,7 +434,7 @@ void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
* for the specified SPI.
* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
* @param SPI_Direction: specifies the data transfer direction in
* bi-directional mode.
* bi-directional mode.
* This parameter can be one of the following values:
* @arg SPI_Direction_Tx: Selects Tx transmission direction
* @arg SPI_Direction_Rx: Selects Rx receive direction
@ -447,7 +447,7 @@ void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_DIRECTION(SPI_Direction));
/* Set the Tx only mode */
if(SPI_Direction==SPI_Direction_Tx)
{
@ -473,8 +473,8 @@ void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
/**
* @brief Checks whether the specified SPI flag is set or not.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param SPI_FLAG: specifies the SPI flag to check.
* 0, 1 in SPI mode
* @param SPI_FLAG: specifies the SPI flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXAVL: Rx buffer has bytes flag
* @arg SPI_FLAG_TXEPT: Tx buffer and tx shifter empty flag
@ -504,22 +504,22 @@ FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG)
/**
* @brief Checks whether the specified SPI interrupt has occurred or not.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param SPI_IT: specifies the SPI interrupt source to check.
* 0, 1 in SPI mode
* @param SPI_IT: specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TX: Tx buffer empty interrupt
* @arg SPI_IT_RX: Rx buffer interrupt
* @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode
* @arg SPI_IT_RXOVER: RX OVER Error interrupt
* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt
* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt
* @arg SPI_IT_RXFULL: Rx buffer full interrupt
* @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt
* @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt
* @retval : The new state of SPI_IT (SET or RESET).
*/
ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_GET_IT(SPI_IT));
@ -541,25 +541,25 @@ ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT)
/**
* @brief Clears the SPIx Error interrupt pending bit.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* 0, 1 in SPI mode
* @param SPI_IT: specifies the SPI interrupt pending bit to clear.
* @arg SPI_IT_TX: Tx buffer empty interrupt
* @arg SPI_IT_RX: Rx buffer interrupt
* @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode
* @arg SPI_IT_RXOVER: RX OVER Error interrupt
* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt
* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt
* @arg SPI_IT_RXFULL: Rx buffer full interrupt
* @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt
* This function clears only ERR intetrrupt pending bit.
* @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt
* This function clears only ERR intetrrupt pending bit.
* @retval : None
*/
void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_CLEAR_IT(SPI_IT));
/* Clear the selected SPI IT INTERRUPT */
SPIx->INTCLR |= (uint16_t)SPI_IT;
}
@ -567,10 +567,10 @@ void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT)
/**
* @brief SPI Hole a count Received bytes in next receive process.
* @param SPIx: where x can be 0, 1 in SPI mode
* @param SPIx: where x can be 0, 1 in SPI mode
* @param Number: specifies the SPI receive Number.
* This parament can be 1-65535.
* This function can use only in SPI master single receive mode.
* This parament can be 1-65535.
* This function can use only in SPI master single receive mode.
* @retval : None
*/
void SPI_RxBytes(SPI_TypeDef* SPIx, uint16_t Number)
@ -583,12 +583,12 @@ void SPI_RxBytes(SPI_TypeDef* SPIx, uint16_t Number)
/**
* @brief slave mode tx data transmit phase adjust set.
* @param SPIx: where x can be 0, 1 in SPI mode
* @param SPIx: where x can be 0, 1 in SPI mode
* @param AdjustValue: specifies the SPI receive Number.
* This parament can be :
* This parament can be :
* SPI_SlaveAdjust_FAST: fast speed use
* SPI_SlaveAdjust_LOW: low speed use
* This function can use only in SPI master single receive mode.
* This function can use only in SPI master single receive mode.
* @retval : None
*/
void SPI_SlaveAdjust(SPI_TypeDef* SPIx, uint16_t AdjustValue)
@ -603,14 +603,14 @@ void SPI_SlaveAdjust(SPI_TypeDef* SPIx, uint16_t AdjustValue)
/**
* @}
*/
*/
/**
* @}
*/
*/
/**
* @}
*/
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

52
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_syscfg.c
View File

@ -4,21 +4,21 @@
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides firmware functions to manage the following
* @brief This file provides firmware functions to manage the following
* functionalities of the SYSCFG peripheral:
* + Remapping the memory mapped at 0x00000000
* + Remapping the memory mapped at 0x00000000
* + Remapping the DMA channels
* + Enabling I2C fast mode plus driving capability for I2C pins
* + Enabling I2C fast mode plus driving capability for I2C pins
* + Configuring the EXTI lines connection to the GPIO port
* + Configuring the CFGR2 features (Connecting some internal signal
* to the break input of TIM1)
*
*
* @verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The SYSCFG registers can be accessed only when the SYSCFG
[..]
The SYSCFG registers can be accessed only when the SYSCFG
interface APB clock is enabled.
To enable SYSCFG APB clock use:
RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
@ -38,10 +38,10 @@ RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
* @{
*/
/** @defgroup SYSCFG
/** @defgroup SYSCFG
* @brief SYSCFG driver modules
* @{
*/
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@ -52,10 +52,10 @@ RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
/** @defgroup SYSCFG_Private_Functions
* @{
*/
*/
/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
* @brief SYSCFG Initialization and Configuration functions
* @brief SYSCFG Initialization and Configuration functions
*
@verbatim
===============================================================================
@ -85,14 +85,14 @@ void SYSCFG_DeInit(void)
SYSCFG->EXTICR[1] = 0;
SYSCFG->EXTICR[2] = 0;
SYSCFG->EXTICR[3] = 0;
}
/**
* @brief Configures the memory mapping at address 0x00000000.
* @param SYSCFG_MemoryRemap: selects the memory remapping.
* This parameter can be one of the following values:
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
* @retval None
@ -100,19 +100,19 @@ void SYSCFG_DeInit(void)
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
{
uint32_t tmpctrl = 0;
/* Check the parameter */
assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
/* Get CFGR1 register value */
tmpctrl = SYSCFG->CFGR;
/* Clear MEM_MODE bits */
tmpctrl &= (uint32_t) (~SYSCFG_CFGR_MEM_MODE);
/* Set the new MEM_MODE bits value */
tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
/* Set CFGR1 register with the new memory remap configuration */
SYSCFG->CFGR = tmpctrl;
}
@ -126,11 +126,11 @@ void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
* @arg SYSCFG_DMARemap_UART1Rx: Remap UART1 Rx DMA requests from channel3 to channel5
* @arg SYSCFG_DMARemap_UART1Tx: Remap UART1 Tx DMA requests from channel2 to channel4
* @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
* @param NewState: new state of the DMA channel remapping.
* @param NewState: new state of the DMA channel remapping.
* This parameter can be: ENABLE or DISABLE.
* @note When enabled, DMA channel of the selected peripheral is remapped
* @note When disabled, Default DMA channel is mapped to the selected peripheral
* @note By default TIM17 DMA requests is mapped to channel 1,
* @note By default TIM17 DMA requests is mapped to channel 1,
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
* TIM17 DMA requests to channel 2 and use
* SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
@ -142,7 +142,7 @@ void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewS
/* Check the parameters */
assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Remap the DMA channel */
@ -159,7 +159,7 @@ void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewS
/**
* @brief Selects the GPIO pin used as EXTI Line.
* @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source
* @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source
* for EXTI lines where x can be (A, B, C, D, E or F).
* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
* @note This parameter can be EXTI_PinSourcex where x can be:
@ -169,11 +169,11 @@ void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewS
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
{
uint32_t tmp = 0x00;
/* Check the parameters */
assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
@ -187,13 +187,13 @@ void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex
/**
* @}
*/
*/
/**
* @}
*/
*/
/**
* @}
*/
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

692
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_tim.c
View File

File diff suppressed because it is too large Load Diff

8
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_uart.c
View File

@ -49,8 +49,8 @@
#define GCR_UE_Set ((uint16_t)0x0001) /* UART Enable Mask */
#define GCR_UE_Reset ((uint16_t)0xFFFE) /* UART Disable Mask */
#define CCR_CLEAR_Mask ((uint32_t)0xFFFFFF30) /* UART CCR Mask */
#define GCR_CLEAR_Mask ((uint32_t)0xFFFFFFE0) /* UART GCR Mask */
#define CCR_CLEAR_Mask ((uint32_t)0xFFFFFF30) /* UART CCR Mask */
#define GCR_CLEAR_Mask ((uint32_t)0xFFFFFFE0) /* UART GCR Mask */
/**
* @}
*/
@ -159,8 +159,8 @@ void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct)
/* Determine the UART_baud*/
tmpreg = ((RCC_ClocksStatus.PCLK1_Frequency)/(UART_InitStruct->UART_BaudRate)/16) ;
/* Write to UART BRR */
UARTx->BRR = tmpreg;
/* Write to UART BRR */
UARTx->BRR = tmpreg;
}
/**

4
bsp/tkm32F499/drivers/board.c
View File

@ -26,8 +26,8 @@ MSH_CMD_EXPORT(reboot, Reboot System);
static void bsp_clock_config(void)
{
RemapVtorTable();
SystemClk_HSEInit(RCC_PLLMul_20);//启动PLL时钟，12MHz*20=240MHz
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//2：2，全局性函数，仅需设置一次
SystemClk_HSEInit(RCC_PLLMul_20);//启动PLL时钟，12MHz*20=240MHz
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//2：2，全局性函数，仅需设置一次
uint32_t sysclk = 0;
getSystemClock(&sysclk);

2
bsp/tkm32F499/drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*